CN118245266B - Watchdog circuit and control method thereof - Google Patents
Watchdog circuit and control method thereof Download PDFInfo
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- CN118245266B CN118245266B CN202410627973.1A CN202410627973A CN118245266B CN 118245266 B CN118245266 B CN 118245266B CN 202410627973 A CN202410627973 A CN 202410627973A CN 118245266 B CN118245266 B CN 118245266B
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- 230000009467 reduction Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 4
- 239000013072 incoming material Substances 0.000 description 3
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- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
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Abstract
The invention discloses a watchdog circuit and a control method thereof, and belongs to the technical field of electronic circuits. The watchdog circuit comprises a watchdog chip; the watchdog chip comprises a first pin, a second pin and a third pin; the first pin is connected with the dog feeding signal output end of the main control unit and is used for receiving a dog feeding signal sent by the main control unit; the second pin is connected with the reset end of the main control unit; the watchdog chip is used for controlling the second pin to send a first reset signal to the reset end of the main control unit when the first pin does not receive the watchdog feeding signal within a first preset time under the condition that the watchdog function is started, so that the main control unit is reset; the third pin is connected with a control signal, and the watchdog chip is further used for determining whether to close the watchdog function according to the control signal. The watchdog circuit provided by the embodiment of the invention has the advantages of simple structure, simple and easy-to-use control logic, simple function realization and great reduction of occupied circuit resources and cost.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronic circuits, in particular to a watchdog circuit and a control method thereof.
Background
In a computer control system, interference from external electromagnetic fields often results in running of programs in the computer control system and thus in dead loops. In consideration of real-time monitoring of the running state of the main control system in the computer, a chip specially used for monitoring the running state of the main control system program is generated and commonly called a watchdog.
The watchdog can automatically reset the main control system and restart and normally work under the condition that the system or the circuit is interfered, so that the normal operation of the system is recovered from software and hardware errors, and the abnormal operation of the system is prevented. However, in the prior art, the watchdog circuit has more pins, complicated circuit realization, complex function realization, more circuit resources occupied by the watchdog circuit and higher cost.
Disclosure of Invention
The invention provides a watchdog circuit and a control method thereof, which are used for simplifying the structure of the watchdog circuit, so that the control logic of the watchdog circuit is simple and easy to use, and the circuit resource and the cost are greatly reduced.
In a first aspect, an embodiment of the present invention provides a watchdog circuit, including a watchdog chip; the watchdog chip comprises a first pin, a second pin and a third pin;
The first pin is connected with the dog feeding signal output end of the main control unit and is used for receiving a dog feeding signal sent by the main control unit;
The second pin is connected with the reset end of the main control unit; the watchdog chip is used for controlling the second pin to send a first reset signal to the reset end of the main control unit when the first pin does not receive the watchdog feeding signal within a first preset time under the condition that the watchdog function is started, so that the main control unit is reset; the watchdog chip is used for controlling the second pin to stop outputting the first reset signal under the condition that the watchdog function is closed;
The third pin is connected with a control signal, and the watchdog chip is further used for determining whether to close the watchdog function according to the control signal.
Further, the watchdog circuit further comprises: a voltage control unit; the first input end of the voltage control unit is connected with a first power supply signal, the second input end of the voltage control unit is connected with a second power supply signal, and the output end of the voltage control unit is connected with the third pin; the voltage control unit is used for outputting the first power supply signal or the second power supply signal as the control signal; the first power supply signal and the second power supply signal have different voltages;
the watchdog chip is used for starting the watchdog function when the third pin receives the first power signal, and closing the watchdog function when the third pin receives the second power signal.
Further, the voltage control unit includes: jump cap and first resistor;
The first end of the first resistor is connected with the first input end of the voltage control unit, the first end of the jump cap is connected with the second input end of the voltage control unit, and the second end of the jump cap is respectively connected with the second end of the first resistor and the output end of the voltage control unit.
Further, the third pin is also connected with a signal receiving end of the main control unit;
The watchdog chip is further used for controlling the third pin to send a square wave signal to a signal receiving end of the main control unit when detecting that the control signal received by the third pin continues for a third preset time to be the second power signal after being electrified; and the main control unit is used for judging that a watchdog program in the watchdog chip is normal when the square wave signal is received, and the watchdog chip can execute the watchdog function.
Further, the watchdog chip further comprises a fourth pin;
the fourth pin is connected with the control end of the power supply control unit, and the power supply control unit is used for supplying power to the main control unit; the watchdog chip is further configured to send a restart control signal to the power control unit through the fourth pin when the first pin is detected to not receive the watchdog feeding signal within a second preset time after the second pin sends the first reset signal to the main control unit at least twice under the condition that the watchdog function is turned on, so that the power control unit controls the main control unit to power off and restart according to the restart control signal; wherein the second preset time is longer than the first preset time.
Further, the watchdog circuit further comprises a third resistor, a first end of the third resistor is connected with the reset end of the main control unit, and a second end of the third resistor is connected with a first power supply signal.
Further, the watchdog circuit further comprises a reset chip;
The power supply end of the reset chip is connected with a first power supply signal, the grounding end of the reset chip is grounded, and the output end of the reset chip is connected with the reset end of the main control unit; the reset chip is used for sending a second reset signal to the reset end of the main control unit when the reset chip is electrified, so that the main control unit is reset.
Further, the watchdog circuit further comprises: a watchdog circuit power supply for providing the first power signal;
The watchdog chip further comprises a fifth pin and a sixth pin, wherein the fifth pin is connected with the first power signal, and the sixth pin is grounded.
In a second aspect, an embodiment of the present invention further provides a watchdog circuit control method, which is applied to the watchdog circuit described in any embodiment of the present invention, and executed by the watchdog chip, where the watchdog circuit control method includes:
judging whether to close the watchdog function of the watchdog circuit according to the control signal;
under the condition that the watchdog function is started, when the first pin does not receive a watchdog feeding signal within a first preset time, the second pin is controlled to send a first reset signal to a reset end of the main control unit, so that the main control unit is reset.
Further, the watchdog chip further comprises a fourth pin; the watchdog circuit control method further comprises the following steps:
Under the condition that the watchdog function is started, after the second pin sends the first reset signal to the main control unit at least twice, when the first pin still does not receive the watchdog feeding signal in a second preset time, a restarting control signal is sent to a power control unit through the fourth pin, so that the power control unit controls the main control unit to be powered off and restarted according to the restarting control signal; wherein the second preset time is longer than the first preset time;
The sending the restart control signal to the power control unit through the fourth pin includes:
Controlling the output voltage of the fourth pin to be the first voltage and jumping to be the second voltage after lasting for a fourth preset time, so that the power supply control unit controls the main control unit to be powered off and shut down;
After a fifth preset time, controlling the output voltage of the fourth pin to be the first voltage, and jumping to the second voltage after lasting a sixth preset time, so that the power control unit controls the main control unit to be electrified and started; wherein the sixth preset time is less than the fourth preset time.
The invention provides a watchdog circuit and a control method thereof, wherein the watchdog circuit comprises a watchdog chip; the watchdog chip comprises a first pin, a second pin and a third pin; based on the control signal received by the third pin, the watchdog chip can control whether the watchdog function of the watchdog circuit is started or not, if necessary, for example, when the main control unit burns firmware, the watchdog function is closed, so that the main control unit can be effectively prevented from being restarted by mistake, and the working states such as firmware burning and the like can be ensured to be normally and smoothly carried out. Under the condition that the watchdog function is started, when the first pin does not receive the watchdog feeding signal in the first preset time, the second pin is controlled to send a first reset signal to the reset end of the main control unit, so that the main control unit is reset, and the reset function of the watchdog circuit can be simply and conveniently realized. Therefore, the watchdog circuit provided by the embodiment of the invention can normally realize the watchdog function only by occupying a limited number of pins of the watchdog chip and controls the opening or closing of the watchdog function. Compared with the prior art, the watchdog circuit provided by the embodiment of the invention has the advantages of simple structure, simple and easy-to-use control logic, simple function realization and great reduction of occupied circuit resources and cost.
Drawings
Fig. 1 is a schematic diagram of a watchdog circuit according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a watchdog chip according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of another watchdog circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of another watchdog circuit provided by an embodiment of the present invention.
Fig. 5 is a schematic circuit diagram of a watchdog circuit power supply according to an embodiment of the present invention.
Fig. 6 is a flowchart of a watchdog circuit control method according to an embodiment of the present invention.
Fig. 7 is a flowchart of sending a restart control signal to a power control unit according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The embodiment of the invention provides a watchdog circuit. Fig. 1 is a schematic diagram of a watchdog circuit according to an embodiment of the present invention, and fig. 2 is a schematic diagram of a watchdog chip according to an embodiment of the present invention, where, as shown in fig. 1 and fig. 2, the watchdog circuit includes a watchdog chip 110; the watchdog chip 110 includes a first pin IOB1, a second pin IOB2, and a third pin IOB3. The first pin IOB1 is connected to the dog feeding signal output end WDI of the main control unit 210, and the first pin IOB1 is configured to receive a dog feeding signal W1 sent by the main control unit 210; the second pin IOB2 is connected to the RESET end RESET of the main control unit 210; the watchdog chip 110 is configured to, when the watchdog function is turned on and the first pin IOB1 does not receive the watchdog feeding signal W1 within a first preset time, control the second pin IOB2 to send a first RESET signal S1 to a RESET end RESET of the main control unit 210, so as to RESET the main control unit 210; and, the watchdog chip 110 is configured to control the second pin IOB2 to stop outputting the first reset signal S1 when the watchdog function is turned off; the third pin IOB3 is connected to the control signal C1, and the watchdog chip 110 is further configured to determine whether to turn off the watchdog function according to the control signal C1.
The watchdog chip 110 may be a single chip microcomputer with a watchdog program, for example, a microcontroller (Micro Controller Unit, MCU); the first pin IOB1, the second pin IOB2 and the third pin IOB3 are all pins on the singlechip. The master control unit 210 may be a master control system of a computer control system, for example comprising a microprocessor (ADVANCED RISC MACHINE, ARM). Illustratively, the master control unit 210 is a light emitting diode industry transmit card system. The control signal C1 may be a high level signal or a low level signal, and may be sent by associated control hardware in the watchdog circuit. The feeding signal W1 may be a 1Hz square wave. The first preset time may be set according to a time interval of the main control unit 210 sending the feeding dog signal W1, and optionally, the first preset time is greater than a time interval of the main control unit 210 sending the feeding dog signal W1 twice, and the first preset time is, for example, 90s, which is not limited in the present application.
Specifically, referring to fig. 1 and 2, the watchdog chip 110 may receive a watchdog signal W1 sent by the main control unit 210 and send a first reset signal S1 to the main control unit 210. When the watchdog function is started, the first pin IOB1 of the watchdog chip 110 receives the watchdog feeding signal W1 sent by the main control unit 210, and when the watchdog chip 110 does not receive the watchdog feeding signal W1 within a first preset time, the second pin IOB2 is controlled to send a first RESET signal S1 to the RESET end RESET of the main control unit 210, so that the main control unit 210 is RESET, and the program of the main control unit 210 is prevented from running. It will be appreciated that the watchdog chip 110 clears the previous timing and restarts the timing each time the watchdog signal W1 is received. The watchdog chip 110 starts timing from the time of receiving the first feeding signal W1, and after the first preset time, the next feeding signal W1 is not received yet, so that it can be determined that the internal program of the main control unit 210 has a problem, and the feeding signal W1 cannot be regularly sent at a specified time interval, and in this case, the main control unit 210 is controlled to reset, so that the program of the main control unit 210 can be effectively prevented from running.
The watchdog chip 110 may also receive a control signal C1 from the third pin IOB3, and determine whether to turn off the watchdog function according to the control signal C1. Specifically, when the control signal C1 received by the third pin IOB3 of the watchdog chip 110 is at the second level, the watchdog chip 110 turns off the watchdog function, and controls the second pin IOB2 to stop sending the first reset signal S1, and the second level is, illustratively, a low level. When the third pin IOB3 is at a low level, the watchdog chip 110 turns off the watchdog function, and the second pin IOB2 does not transmit the first reset signal S1 even if the first pin IOB1 does not receive the watchdog feeding signal W1 within the first preset time. For example, when the master control unit 210 performs debugging, firmware burning, or other operation states that may not be able to send the watchdog feeding signal W1 in time but need to be maintained for a longer time, the watchdog function of the watchdog chip 110 may be turned off, so as to prevent the master control unit 210 from being reset by the watchdog chip 110 in the above operation states. The watchdog chip 110 can realize the watchdog function and control the opening or closing of the watchdog function only by the first pin IOB1, the second pin IOB2 and the third pin IOB3, and the control logic is simple, so that the occupied singlechip resource is greatly reduced.
The technical scheme of the embodiment of the invention provides a watchdog circuit, which comprises a watchdog chip 110; the watchdog chip comprises a first pin IOB1, a second pin IOB2 and a third pin IOB3; based on the control signal C1 received by the third pin IOB3, the watchdog chip 110 may control whether the watchdog function of the watchdog circuit is enabled, if necessary, for example, when the main control unit 210 performs firmware burning, closing the watchdog function may effectively prevent the main control unit 210 from being restarted by mistake, so as to ensure that the working states such as firmware burning can be performed normally and smoothly. Under the condition that the watchdog function is turned on, when the first pin IOB1 does not receive the watchdog feeding signal W1 within a first preset time, the second pin IOB2 is controlled to send a first RESET signal S1 to the RESET end RESET of the main control unit 210, so that the main control unit 210 is RESET, and the RESET function of the watchdog circuit can be simply realized. Therefore, the watchdog circuit provided by the embodiment of the invention can normally realize the watchdog function only by occupying a limited number of pins of the watchdog chip 110 and controls the opening or closing of the watchdog function. Compared with the prior art, the watchdog circuit provided by the embodiment of the invention has the advantages of simple structure, simple and easy-to-use control logic, simple function realization and great reduction of occupied circuit resources and cost.
The embodiment of the invention also provides another watchdog circuit, which is improved based on the embodiment, and fig. 3 is a schematic structural diagram of the other watchdog circuit provided by the embodiment of the invention, as shown in fig. 3, the watchdog circuit further includes: a voltage control unit 120; a first input end of the voltage control unit 120 is connected with a first power supply signal, a second input end of the voltage control unit 120 is connected with a second power supply signal, and an output end of the voltage control unit 120 is connected with a third pin IOB3; the voltage control unit 120 is configured to output the first power signal or the second power signal as a control signal C1; the first power supply signal and the second power supply signal have different voltages; the watchdog chip 110 is configured to turn on a watchdog function when the third pin IOB3 receives the first power signal, and turn off the watchdog function when the third pin IOB3 receives the second power signal.
The voltages of the first power supply signal and the second power supply signal are different, the first power supply signal can be a high level signal, as shown in fig. 3, and the first power supply signal can be a 3.3V power supply; the second power signal is a low level signal, and the first power signal may be provided by a power supply of the watchdog chip 110, and is obtained through the second input terminal of the voltage control unit 120 to the ground. Alternatively, the first power signal may be a low-level signal, and the second power signal may be a high-level signal.
Specifically, when the first input terminal and the output terminal of the voltage control unit 120 are connected, the third pin IOB3 receives the first power signal, and the watchdog chip 110 starts the watchdog function. When the second input terminal and the output terminal of the voltage control unit 120 are communicated, the third pin IOB3 receives the second power signal, and the watchdog chip 110 turns off the watchdog function. The voltage control unit 120 controls the watchdog chip 110 to open or close the watchdog function by controlling the third pin IOB3 to be at a high level or a low level, so as to realize active control of the watchdog function of the watchdog chip 110 through one pin of the watchdog chip 110, and control logic is simple.
Further, as shown in fig. 3, the voltage control unit 120 includes: jump cap 1201 and first resistor R1; the first end of the first resistor R1 is connected with the first input end of the voltage control unit 120, the first end of the jump cap 1201 is connected with the second input end of the voltage control unit 120, and the second end of the jump cap 1201 is respectively connected with the second end of the first resistor R1 and the output end of the voltage control unit 120.
The first end of the jump cap 1201 is connected to the second input end of the voltage control unit 120, and the second input end of the voltage control unit 120 is connected to the second power signal, i.e. the first end of the jump cap 1201 is connected to the second power signal. Alternatively, as shown in fig. 3, the first terminal of the jump cap 1201 is grounded, and the second power signal is a low level signal. A second end of the jump cap 1201 is connected to the third pin IOB3. Note that, when the jump cap 1201 is shorted, the jump cap 1201 may serve as a wire to conduct the first end and the second end of the jump cap 1201, so that the third pin IOB3 receives the second power signal. A first end of the first resistor R1 is connected to a first power signal through a first input end of the voltage control unit 120, and optionally, the first power signal is a high level signal; then, the first resistor corresponds to a pull-up resistor, and when the jump cap is not shorted, the third pin IOB3 can be pulled to a high level through the first resistor.
Specifically, when the first end and the second end of the jump cap 1201 are in the off state, the third pin IOB3 receives the first power signal, the watchdog function is in the on state, and the watchdog chip 110 operates normally. When the jump cap 1201 is shorted, the third pin IOB3 may receive the second power signal, and turn off the watchdog function of the watchdog chip 110. The active control of the watchdog chip 110 to close the watchdog function can be realized by controlling the short circuit of the jump cap 1201, the control logic is simple, and the cost of circuit hardware is lower.
Fig. 4 is a schematic diagram of another watchdog circuit according to an embodiment of the present invention, further, with reference to fig. 3 and fig. 4, the third pin IOB3 is further connected to the signal receiving terminal wd_ctl of the main control unit 210; the watchdog chip 110 is further configured to, after power-on, control the third pin IOB3 to send a square wave signal WD1 to a signal receiving end wd_ctl of the main control unit 210 when detecting that the control signal C1 received by the third pin IOB3 continues for a third preset time to be the second power signal; the main control unit 210 is configured to determine that a watchdog program in the watchdog chip 110 is normal when receiving the square wave signal WD1, and the watchdog chip 110 is capable of executing a watchdog function.
Specifically, the watchdog chip 110 may not only turn on the watchdog function when the third pin IOB3 receives the first power signal, but also turn off the watchdog function when the third pin IOB3 receives the second power signal, and further may send a signal to the signal receiving terminal wd_ctl to enable the main control unit 210 to determine whether the watchdog program in the watchdog chip 110 is normal. The judgment principle is as follows: the following functions may be configured in the gatekeeper: after powering up, if it is detected that the control signal C1 received by the third pin IOB3 continues for a third preset time to be the second power signal, the watchdog chip 110 sends a square wave signal WD1 to the main control unit 210 through the third pin IOB 3. Under the condition that the watchdog chip 110 normally burns the watchdog program, if the control signal C1 received by the third pin IOB3 after the watchdog chip 110 is powered on meets the above specification, the watchdog chip 110 sends the square wave signal WD1 to the signal receiving terminal wd_ctl of the main control unit 210 through the third pin IOB 3. When receiving the square wave signal WD1, the main control unit 210 determines that the watchdog program in the watchdog chip 110 is normal, that is, the watchdog program has been burned in the watchdog chip 110, and the watchdog chip 110 can perform the watchdog function; if the main control unit 210 does not receive the square wave signal WD1, it determines that the watchdog program in the watchdog chip 110 is abnormal or that the watchdog program is not burned in the watchdog chip 110.
In addition, the jump cap 1201 is shorted before the watchdog chip 110 is powered on, so that the control signal C1 received by the third pin IOB3 may be kept for a third preset time to be the second power signal, i.e. the third pin IOB3 may be kept for a third preset time to be a low level. The third pin IOB3 of the watchdog chip 110 realizes the function of detecting the incoming material burning program function of the watchdog circuit by sending a signal to the signal receiving terminal wd_ctl of the main control unit 210. Optionally, the square wave signal WD1 is a 1Hz square wave, and the third preset time may be set according to the usage scenario, and, for example, in order to determine whether the watchdog program is burned in the watchdog chip 110 as soon as possible, the third preset time may be set to 10s, which is not limited herein. For example, the watchdog chip 110 only needs to determine whether to output the square wave signal WD1 through the third pin IOB3 once when power is on, and after power is on, if the condition that the third pin IOB3 is continuously pulled down occurs in the middle of the system operation, only the watchdog function needs to be adaptively turned off, and no 1Hz square wave needs to be output.
Optionally, as shown in fig. 3 and fig. 4, the watchdog chip 110 further includes a fourth pin IOB4; the fourth pin IOB4 is connected to a control end PWRON of the power control unit 220, and the power control unit 220 is configured to supply power to the main control unit 210; the watchdog chip 110 is further configured to, when the watchdog function is turned on and after the second pin IOB2 sends the first reset signal S1 to the main control unit 210 at least twice, send a restart control signal PW1 to the power control unit 220 through the fourth pin IOB4 after detecting that the first pin IOB1 has not received the watchdog feeding signal W1 within a second preset time, so that the power control unit 220 controls the main control unit 210 to power off and restart according to the restart control signal PW 1; wherein the second preset time is longer than the first preset time.
The power control unit 220 may supply power to the main control unit 210, and when the power control unit 220 shuts down or cuts off the power supply path to the main control unit 210, the power supply to the main control unit 210 is stopped, so that the main control unit 210 is powered off; when the power control unit 220 is turned on or turns on the power supply path to the main control unit 210, power is supplied to the main control unit 210, so that the main control unit 210 is powered on. The first preset time is an interval time for the main control unit 210 to send the feeding signal W1, and the second preset time is set to be longer than the first preset time, so that the second pin IOB2 is guaranteed to have enough interval time to receive the feeding signal W1 after sending the first reset signal S1 to the main control unit 210 at least twice.
Specifically, under the condition that the watchdog function is turned on, after the second pin IOB2 sends the first reset signal S1 to the main control unit 210 at least twice, when it is detected that the first pin IOB1 still does not receive the watchdog feeding signal W1 within the second preset time, it indicates that the main control unit 210 still fails to reset after receiving the first reset signal S1 at least twice, and further indicates that the main control unit 210 has run out or crashed, so that the main control unit 210 still does not send the watchdog feeding signal W1 to the first pin IOB1 after the second preset time, and at this time, the main control unit 210 may be forced to be powered off and restarted, so that the main control unit 210 is reset. Illustratively, when the watchdog chip 110 detects that the first pin IOB1 has not received the watchdog feeding signal W1 within the second preset time, the process of sending the restart control signal PW1 includes: transmitting a low level signal to the power control unit 220 through the fourth pin IOB4, pulling the level of the control terminal PWRON of the power control unit 220 low for a fourth preset time, turning off the power control unit 220, and stopping supplying power to the main control unit 210; after the fifth preset time, the level of the control end PWRON of the power control unit 220 is pulled down for a sixth preset time, so that the power control unit 220 is started, the control end PWRON of the power control unit 220 recovers to be at a high level, and the power control unit 220 supplies power to the main control unit 210, thereby realizing the process of powering off and restarting the main control unit 210 and realizing the forced reset of the main control unit 210. The power control unit 220 is, for example, a power management unit (Power Management Unit, PMU).
It should be noted that, the fourth preset time, the fifth preset time and the sixth preset time are set according to the power-on/off program of the power control unit 220, and by way of example, when the power control unit 220 is turned off, it needs to be turned off for 8 seconds, when the power control unit is turned on, it needs to be turned on for 600ms, and the interval between the power off and the power on is greater than 500ms, the fourth preset time is set to 8 seconds, the fifth preset time is 500ms and the sixth preset time is 600ms, so that the power control unit 220 is restarted by satisfying the power-off program of the power control unit 220.
Based on the above embodiments, optionally, as shown in fig. 3, the watchdog circuit further includes: and a first end of the third resistor R3 is connected with the reset end of the main control unit 210, and a second end of the third resistor R3 is connected with a first power supply signal. For example, the first RESET signal S1 may be a low level signal, and when the first pin IOB1 of the watchdog chip 110 does not receive the feeding signal W1 within a first preset time, the second pin IOB2 is controlled to send the first RESET signal S1 to the RESET end RESET of the main control unit 210, and pull down the level of the RESET end RESET of the main control unit 210 for the preset RESET time, so that the main control unit 210 is RESET. The third resistor R3 corresponds to a pull-up resistor of the RESET terminal RESET, and when the first RESET signal S1 is not output from the second pin IOB2, the potential of the RESET terminal RESET can be pulled up by the third resistor R3. The preset reset time may be set according to a reset mechanism of the main control unit 210, for example, 500ms.
With continued reference to fig. 3, optionally, when the watchdog chip 110 is debugged, a second resistor R2 may also be set, specifically, the second pin IOB2 is connected to a first end of the second resistor R2, a second end of the second resistor R2 is respectively connected to the RESET end RESET of the main control unit 210 and a first end of the third resistor R3, and a second end of the third resistor R3 is connected to the first power signal. The second resistor R2 may be a 0 ohm resistor, a jumper, or a dial switch.
Optionally, as shown in fig. 3 and 4, the watchdog circuit further includes a reset chip 130; the power end VCC of the RESET chip 130 is connected with a first power signal, the ground end GND2 of the RESET chip 130 is grounded, and the output end of the RESET chip 130 is connected with the RESET end RESET of the main control unit 210; the RESET chip 130 is configured to send a second RESET signal S2 to the RESET terminal RESET of the main control unit 210 when the RESET chip 130 is powered on, so as to RESET the main control unit 210.
The power supply terminal VCC of the reset chip 130 is connected to the same first power supply signal as the fifth pin VDD of the watchdog chip 110, and the power supplies of the reset chip 130 and the watchdog chip 110 are the same. The power supply of the reset chip 130 and the power supply control unit 220 are powered by the same general power supply, and when the main control unit 210 is powered on, the reset chip 130 is powered on, so that the reset chip 130 performs a reset operation on the main control unit 210 when the main control unit is powered on. The types of the second reset signal S2 and the first reset signal S1 may be the same, and optionally, the second reset signal S2 and the first reset signal S1 are both low level signals, and the duration of the low level signals is a preset reset time, where the preset reset time may be set according to a reset mechanism of the main control unit 210.
Specifically, the RESET chip 130 sends the second RESET signal S2 to the RESET terminal RESET of the main control unit 210 only when the RESET chip 130 is powered up, so that the main control unit 210 is RESET when the main control unit 210 is powered up, and the main control unit 210 is RESET to be initialized when the main control unit 210 is powered up, so that the main control unit 210 can normally send the watchdog signal W1 to the watchdog chip 110 during the power-up period. After the RESET chip 130 sends the second RESET signal S2 to the RESET terminal RESET of the main control unit 210 once after power is on, the RESET chip 130 does not send the second RESET signal S2 to the RESET terminal RESET of the main control unit 210 any more, and during the power on period of the main control unit 210, the main control unit 210 is RESET through the watchdog chip 110.
Based on the above embodiments, optionally, as shown in fig. 3 and fig. 4, the watchdog circuit further includes: a watchdog circuit power supply 140, the watchdog circuit power supply 140 for providing a first power signal; the watchdog chip 110 further includes a fifth pin VDD and a sixth pin GND1, wherein the fifth pin VDD is connected to the first power signal, and the sixth pin GND1 is grounded.
As shown in fig. 3 and 4, the watchdog circuit power 140 may provide the first power signal to the corresponding pins of the watchdog chip 110, the voltage control unit 120 and the reset chip 130, so that the corresponding pins of the watchdog chip 110, the voltage control unit 120 and the reset chip 130 maintain a high level, and the watchdog circuit power 140 may supply power to the watchdog chip 110 and the reset chip 130 as a power source. The watchdog circuit power supply 140 and the power supply control unit 220 are powered by the same general power supply of the system in which they are located, and when the watchdog chip 110, the voltage control unit 120 and the reset chip 130 are powered up, the main control unit 210 is also powered up.
Specifically, fig. 5 is a circuit schematic diagram of a watchdog circuit power supply according to an embodiment of the present invention, as shown in fig. 5, an input end VIN of a voltage conversion chip U1 of a watchdog circuit power supply 140 may be connected to a voltage of 5.5V, a ground of the voltage conversion chip U1 is grounded, a capacitor C1 is disposed between the input end VIN and the ground of the voltage conversion chip U1, a capacitor C2 and a capacitor C3 are disposed between an output end VOUT and the ground of the voltage conversion chip U1, filtering and voltage stabilization are performed through the capacitor C1, the capacitor C2 and the capacitor C3, and the voltage conversion chip U1 converts the voltage of 5.5V into the voltage of 3.3V as a first power signal to be output from the output end VOUT of the voltage conversion chip U1, so as to supply power to the watchdog chip 110 and the reset chip 130, and provide the corresponding pins of the watchdog chip 110, the voltage control unit 120 and the reset chip 130 with the first power signal. Alternatively, the capacitance value of the capacitor C1 is 10uF, the capacitance value of the capacitor C2 is 10uF, and the capacitance value of the capacitor C3 is 0.1uF. The voltage conversion chip U1 may be a low dropout regulator (Low dropout regulator, LDO).
It should be noted that, the watchdog chip 110 in the embodiment of the present invention has only 6 pins, and may use a singlechip with 6 pins to implement the watchdog function in the embodiment of the present invention, so that the circuit resource and the cost are greatly reduced, the software control logic is simple and easy to use, a reset master control mechanism is provided, the reset chip 130 is additionally added to ensure sufficient master control reset time, and the function of detecting the incoming material burning program function is provided.
The technical scheme of the embodiment of the invention provides a simple watchdog circuit, when a first pin IOB1 of a watchdog chip 110 does not receive a watchdog feeding signal W1 within a first preset time, a second pin IOB2 is controlled to send a first RESET signal S1 to a RESET end RESET of a main control unit 210, so that the main control unit 210 is RESET, and a RESET function of the watchdog circuit is realized; the watchdog chip 110 controls the second pin IOB2 to stop outputting the first reset signal S1 in the case that the watchdog function is turned off; the third pin IOB3 is connected with the control signal C1, and the watchdog chip 110 determines whether to close the watchdog function according to the control signal C1, so that the watchdog circuit controls the closing and opening of the watchdog function according to the control signal C1, and realizes the function of detecting the feed burning program function of the watchdog circuit through the third pin IOB 3; the fourth pin of the watchdog chip 110 controls the main control unit 210 to be powered off and restarted, so that the forced reset of the main control unit 210 is realized. The watchdog circuit can adopt the singlechip with 6 pins to realize the watchdog function in the embodiment of the invention, the control logic is simple and easy to use, the function is realized simply, and the occupied singlechip resource is greatly reduced, thereby reducing the circuit resource and the cost.
The embodiment of the invention also provides a watchdog circuit control method, which is applied to the watchdog circuit in any embodiment of the invention, and is executed by the watchdog chip in any embodiment of the invention, and fig. 6 is a flowchart of the watchdog circuit control method provided by the embodiment of the invention, and referring to fig. 6, the watchdog circuit control method includes:
S110, judging whether to close the watchdog function of the watchdog circuit according to the control signal.
Specifically, referring to fig. 2, the third pin IOB3 of the watchdog chip 110 may receive the control signal C1, and the watchdog chip 110 determines whether to turn off the watchdog function according to the control signal C1, when the watchdog chip 110 receives the second level of the control signal C1, the watchdog chip 110 turns off the watchdog function, and controls the second pin IOB2 to stop sending the first reset signal S1, and, illustratively, when the third pin IOB3 is at a low level, the watchdog chip 110 turns off the watchdog function, and even if the first pin IOB1 does not receive the watchdog signal W1 within the first preset time, the second pin IOB2 does not send the first reset signal S1, so as to control the watchdog function of the watchdog chip 110, so that when the master unit 210 performs a debug or other operating states, the watchdog function of the watchdog chip 110 may be turned off, and the watchdog chip 110 is prevented from being reset by mistake when the master unit 210 performs a debug.
And S120, under the condition that the watchdog function is started, when the first pin does not receive the watchdog feeding signal within a first preset time, the second pin is controlled to send a first reset signal to a reset end of the main control unit, so that the main control unit is reset.
Specifically, referring to fig. 2, in the case that the watchdog function of the watchdog chip 110 is turned on, the watchdog chip 110 may receive the watchdog signal W1 sent by the main control unit 210 and send a first RESET signal S1 to the main control unit 210, the first pin IOB1 of the watchdog chip 110 receives the watchdog signal W1 sent by the main control unit 210, and when the watchdog chip 110 does not receive the watchdog signal W1 within a first preset time, the second pin IOB2 is controlled to send the first RESET signal S1 to the RESET end RESET of the main control unit 210, so that the main control unit 210 is RESET, and the program of the main control unit 210 is prevented from running.
The technical scheme of the embodiment of the invention provides a watchdog circuit control method, which comprises the steps of judging whether to close a watchdog function of a watchdog circuit according to a control signal, so that the watchdog circuit controls the closing and opening of the watchdog function according to the control signal; under the condition that the watchdog function is started, when the first pin does not receive the watchdog feeding signal in a first preset time, the second pin is controlled to send a first reset signal to a reset end of the main control unit, so that the main control unit is reset, and the reset function of the watchdog circuit is realized. The watchdog circuit control method is simple and easy to use, has simple function realization, and greatly reduces occupied resources.
Optionally, in another embodiment of the present invention, referring to fig. 3, the watchdog chip 110 further includes a fourth pin IOB4; the watchdog circuit control method further comprises the following steps: under the condition that the watchdog function is started, after the second pin IOB2 sends the first reset signal S1 to the main control unit 210 at least twice, when the first pin IOB1 is detected to still not receive the watchdog feeding signal W1 within the second preset time, a restart control signal PW1 is sent to the power control unit 220 through the fourth pin IOB4, so that the power control unit 220 controls the main control unit 210 to be powered off and restarted according to the restart control signal PW 1; wherein the second preset time is longer than the first preset time.
Specifically, under the condition that the watchdog function is turned on, after the second pin IOB2 sends the first reset signal S1 to the main control unit 210 at least twice, when it is detected that the first pin IOB1 still does not receive the watchdog feeding signal in the second preset time, it indicates that the main control unit 210 still does not successfully reset after receiving the first reset signal S1 at least twice, and the main control unit 210 has run out or crashed a program, so that the main control unit 210 still does not send the watchdog feeding signal to the first pin IOB1 in the second preset time, and at this time, the main control unit 210 can be forced to be powered off and restarted, so that the main control unit 210 is reset.
Optionally, fig. 7 is a flowchart of sending a restart control signal to the power control unit according to an embodiment of the present invention, with continued reference to fig. 3 and fig. 7, sending the restart control signal to the power control unit 220 through the fourth pin IOB4, including:
s210, the output voltage of the fourth pin IOB4 is controlled to be the first voltage and is hopped to be the second voltage after lasting for a fourth preset time, so that the power control unit 220 controls the main control unit 210 to be powered off and shut down.
The first voltage is low level, and the second voltage is high level.
S220, after a fifth preset time, controlling the output voltage of the fourth pin IOB4 to be the first voltage, and jumping to be the second voltage after lasting the sixth preset time, so that the power control unit 220 controls the main control unit 210 to be electrified and started; wherein the sixth preset time is less than the fourth preset time.
Specifically, when the watchdog chip 110 detects that the first pin IOB1 still does not receive the dog feeding signal W1 within the second preset time, the fourth pin IOB4 is controlled to send a low level to the power control unit 220, and the fourth preset time of the level of the control end PWRON of the first power control unit 220 is pulled down, so that the power control unit 220 controls the main control unit 210 to be powered off, which is equivalent to the long-press power-off effect; after the fifth preset time, the level of the control terminal PWRON of the power control unit 220 is pulled down for a sixth preset time, so that the power control unit 220 is turned on, the control terminal PWRON of the power control unit 220 recovers to a high level, and the power control unit 220 controls the main control unit 210 to be powered on and turned on, which is equivalent to a short press power-on effect. Based on this, a process of powering off and restarting the control main control unit 210 can be implemented, and forced reset of the main control unit 210 can be implemented.
It should be noted that, the fourth preset time, the fifth preset time, and the sixth preset time are set according to the power-on/off program of the power control unit 220, and in order to satisfy the power-on/off process of the power control unit 220, the sixth preset time may be set to be less than the fourth preset time. For example, when the power control unit 220 is turned off, it needs to be turned off for 8 seconds, when the power control unit is turned on, it needs to be turned off for 600ms, and the interval between the power off and the power on is greater than 500ms, the fourth preset time is set to 8 seconds, the fifth preset time is set to 500ms, and the sixth preset time is set to 600ms, so that the power control unit 220 is restarted due to the power off procedure of the power control unit 220.
The watchdog circuit control method provided by the technical scheme of the embodiment of the invention can realize the reset control function of the watchdog circuit, can actively control the watchdog function of closing the watchdog circuit, has the function of detecting whether the incoming material burning program of the watchdog circuit is good or not, has the function of forcedly resetting the main control unit, is simple and easy to use, has simple function realization, and can greatly reduce circuit resources and cost.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (5)
1. The watchdog circuit is characterized by comprising a watchdog chip and a voltage control unit; the watchdog chip comprises a first pin, a second pin and a third pin;
The first pin is connected with the dog feeding signal output end of the main control unit and is used for receiving a dog feeding signal sent by the main control unit;
The second pin is connected with the reset end of the main control unit; the watchdog chip is used for controlling the second pin to send a first reset signal to the reset end of the main control unit when the first pin does not receive the watchdog feeding signal within a first preset time under the condition that the watchdog function is started, so that the main control unit is reset; the watchdog chip is used for controlling the second pin to stop outputting the first reset signal under the condition that the watchdog function is closed;
The third pin is connected with a control signal, and the watchdog chip is further used for determining whether to close the watchdog function according to the control signal; the first input end of the voltage control unit is connected with a first power supply signal, the second input end of the voltage control unit is connected with a second power supply signal, and the output end of the voltage control unit is connected with the third pin; the voltage control unit is used for outputting the first power supply signal or the second power supply signal as the control signal; the first power supply signal and the second power supply signal have different voltages; the voltage control unit is further used for outputting the second power supply signal to the third pin before the watchdog chip is powered on;
The watchdog chip is used for starting the watchdog function when the third pin receives the first power supply signal and closing the watchdog function when the third pin receives the second power supply signal;
The third pin is also connected with a signal receiving end of the main control unit;
The watchdog chip is further used for controlling the third pin to send a square wave signal to a signal receiving end of the main control unit when detecting that the control signal received by the third pin continues for a third preset time to be the second power signal after being electrified; the watchdog chip only judges whether the square wave signal is output through the third pin once when being electrified; the main control unit is used for judging that a watchdog program in the watchdog chip is normal when the square wave signal is received, namely the watchdog program is burnt in the watchdog chip, and the watchdog chip can execute the watchdog function; the main control unit is also used for judging that the watchdog program in the watchdog chip is abnormal or the watchdog program in the watchdog chip is not burnt if the square wave signal is not received;
The voltage control unit includes: jump cap and first resistor;
the first end of the first resistor is connected with the first input end of the voltage control unit, the first end of the jump cap is connected with the second input end of the voltage control unit, and the second end of the jump cap is respectively connected with the second end of the first resistor and the output end of the voltage control unit;
When the jump cap is in short circuit, the first end and the second end of the jump cap are conducted, so that the third pin receives the second power signal, and the watchdog function of the watchdog chip is closed; when the first end and the second end of the jump cap are in an off state, the third pin receives the first power signal, and the watchdog function of the watchdog chip is in an on state;
The watchdog chip further comprises a fourth pin;
The fourth pin is connected with the control end of the power supply control unit, and the power supply control unit is used for supplying power to the main control unit; the watchdog chip is further configured to send a restart control signal to the power control unit through the fourth pin when the first pin is detected to not receive the watchdog feeding signal within a second preset time after the second pin sends the first reset signal to the main control unit at least twice under the condition that the watchdog function is turned on, so that the power control unit controls the main control unit to power off and restart according to the restart control signal; wherein the second preset time is longer than the first preset time;
The sending a restart control signal to the power control unit through the fourth pin includes: controlling the output voltage of the fourth pin to be the first voltage and jumping to be the second voltage after lasting for a fourth preset time, so that the power supply control unit controls the main control unit to be powered off and shut down; after a fifth preset time, controlling the output voltage of the fourth pin to be the first voltage, and jumping to the second voltage after lasting a sixth preset time, so that the power control unit controls the main control unit to be electrified and started; wherein the sixth preset time is less than the fourth preset time.
2. The watchdog circuit of claim 1, further comprising a third resistor, a first end of the third resistor connected to the reset end of the main control unit, and a second end of the third resistor connected to the first power signal.
3. The watchdog circuit of claim 1, further comprising a reset chip;
The power supply end of the reset chip is connected with a first power supply signal, the grounding end of the reset chip is grounded, and the output end of the reset chip is connected with the reset end of the main control unit; the reset chip is used for sending a second reset signal to the reset end of the main control unit when the reset chip is electrified, so that the main control unit is reset.
4. A watchdog circuit according to claim 2 or 3, further comprising: a watchdog circuit power supply for providing the first power signal;
The watchdog chip further comprises a fifth pin and a sixth pin, wherein the fifth pin is connected with the first power signal, and the sixth pin is grounded.
5. A watchdog circuit control method, characterized in that it is applied to the watchdog circuit of any one of claims 1 to 4, executed by the watchdog chip, and comprises:
judging whether to close the watchdog function of the watchdog circuit according to the control signal;
under the condition that the watchdog function is started, when the first pin does not receive a watchdog feeding signal within a first preset time, the second pin is controlled to send a first reset signal to a reset end of the main control unit, so that the main control unit is reset.
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| CN114610514A (en) * | 2022-02-10 | 2022-06-10 | 深圳数影科技有限公司 | Watchdog control circuit and equipment |
| CN217386347U (en) * | 2022-05-30 | 2022-09-06 | 西安中车永电捷通电气有限公司 | Watchdog system |
| CN117234537A (en) * | 2023-08-15 | 2023-12-15 | 江苏安科瑞电器制造有限公司 | Burning interface circuit and working method thereof |
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| US6839792B2 (en) * | 2000-12-15 | 2005-01-04 | Innovative Concepts, Inc. | Data modem |
| CN214376409U (en) * | 2021-03-08 | 2021-10-08 | 苏州摩卡智行信息科技有限公司 | External watchdog control circuit for preventing program burning |
| CN215376257U (en) * | 2021-06-30 | 2021-12-31 | 八方电气(苏州)股份有限公司 | Reset control circuit of hardware watchdog |
| CN220651243U (en) * | 2023-09-01 | 2024-03-22 | 纵目科技（上海）股份有限公司 | Watchdog chip control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102214124A (en) * | 2011-06-08 | 2011-10-12 | 深圳市理邦精密仪器股份有限公司 | Watchdog reset control system |
| CN114610514A (en) * | 2022-02-10 | 2022-06-10 | 深圳数影科技有限公司 | Watchdog control circuit and equipment |
| CN217386347U (en) * | 2022-05-30 | 2022-09-06 | 西安中车永电捷通电气有限公司 | Watchdog system |
| CN117234537A (en) * | 2023-08-15 | 2023-12-15 | 江苏安科瑞电器制造有限公司 | Burning interface circuit and working method thereof |
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