CN118201469A - Planar Josephson junction, preparation method thereof and Josephson junction array - Google Patents
Planar Josephson junction, preparation method thereof and Josephson junction array Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
- H10N60/805—Constructional details for Josephson-effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
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Abstract
The invention provides a planar Josephson junction and a preparation method thereof, a Josephson junction array, wherein the planar Josephson junction is formed on one surface of a substrate, the surface is provided with a first part and a second part, the first part extends upwards to form a boss, the included angle between the side surface of the boss and the second part is more than 0 DEG and less than or equal to 90 DEG, and the planar Josephson junction comprises: the first superconducting layer is arranged on the boss; and a second superconducting layer disposed on the second portion; and a gap is formed between the first superconducting layer and the second superconducting layer, and the length of the gap in the vertical direction is smaller than the superconducting coherence length of the superconducting materials adopted by the first superconducting layer and the second superconducting layer. When the first superconducting layer and the second superconducting layer are below the superconducting transition temperature, current is introduced into the first superconducting layer or the second superconducting layer, so that quantum tunneling effect is generated by the Cookies in the superconducting layers introduced with the current, the Cookies penetrate through the gap and enter the other superconducting layer, and Josephson current is formed.
Description
Technical Field
The invention relates to the technical field of superconducting electronics, in particular to a planar Josephson junction, a preparation method thereof and a Josephson junction array.
Background
The commonly used Josephson junction is a vertical structure Josephson junction, and the vertical structure Josephson junction has the advantage of simple preparation, but large-scale integration requires extremely complex circuit support, which prevents large-scale application. And the planar Josephson junction can be directly used for circuit connection in the plane without introducing an external complex circuit structure. Therefore, the exploration of the planar Josephson junction technology is urgent, the size of the intermediate barrier layer is difficult to control because the planar Josephson junction technology is very complex, high-precision micro-nano processing equipment and means are required to be introduced, and the prepared device is unstable and easy to break down, so that the application prospect of the planar Josephson junction is limited.
Disclosure of Invention
In view of the above, the present invention provides a planar josephson junction, a method for fabricating the same, and a josephson junction array, which can control the size of the intermediate barrier layer and improve the stability of the planar josephson junction.
As one aspect of the invention, a planar josephson junction is provided, formed on a surface of a substrate, the surface having a first portion and a second portion, the first portion extending upwardly to form a ledge, the side of the ledge being at an angle of greater than 0 ° and less than or equal to 90 ° to the second portion, the planar josephson junction comprising a first superconducting layer and a second superconducting layer. The first superconductive layer is disposed on the boss and the second superconductive layer is disposed on the second portion of the surface. And a gap is formed between the first superconducting layer and the second superconducting layer, and the length of the gap in the vertical direction is smaller than the superconducting coherence length of the superconducting materials adopted by the first superconducting layer and the second superconducting layer.
According to an embodiment of the present invention, the surface roughness of the first superconducting layer and the second superconducting layer is smaller than the control accuracy of the gap.
According to an embodiment of the present invention, the first superconducting layer and the second superconducting layer are made of a metal or nonmetal material having superconducting properties.
According to an embodiment of the present invention, the first superconducting layer and the second superconducting layer are made of niobium, lead, aluminum, copper oxide, an iron-based superconductor, or an organic superconductor.
According to an embodiment of the invention, the filling of the gap is vacuum, solid, liquid or gas.
As another aspect of an embodiment of the invention, there is provided a method of preparing a planar josephson junction of any of the above, the method comprising:
Depositing a mask over a first portion of a substrate;
Etching downwards from the second part of the substrate by adopting dry etching or wet etching, so that the first part forms a boss higher than the second part;
removing the mask;
and simultaneously growing a first superconducting layer and a second superconducting layer on the boss and the second part of the substrate, and forming a gap between the first superconducting layer and the second superconducting layer to form a planar Josephson junction.
According to an embodiment of the present invention, the method of growing the first superconducting layer and the second superconducting layer includes one of electron beam evaporation, magnetron sputtering, and pulsed laser deposition.
According to an embodiment of the invention, depositing a mask on a first portion of a substrate includes:
Patterning a first portion on a substrate;
depositing a mask material in the exposed areas;
The substrate with the deposited masking material is placed in a first solution, and the masking material on the second portion of the substrate is stripped off, leaving the masking material on the first portion as a mask.
According to an embodiment of the present invention, etching downward from the second portion of the substrate using wet etching includes:
And etching the second part of the substrate by adopting a second solution.
According to an embodiment of the invention, before patterning the first portion on the substrate, further comprises: and placing the substrate into an organic solvent for ultrasonic cleaning.
As a further aspect of an embodiment of the invention there is provided an array of josephson junctions comprising a plurality of planar josephson junctions of any of the above.
According to the planar Josephson junction provided by the embodiment of the invention, the boss is formed on the first part of the substrate, the height difference is formed with the second part of the substrate, the first superconducting layer and the second superconducting layer are respectively arranged on the first part and the second part of the substrate, the first superconducting layer and the second superconducting layer form a gap in the height direction, the gap is adopted as a barrier layer of the planar Josephson junction, and when the first superconducting layer and the second superconducting layer are below the superconducting transition temperature, the current is introduced into the first superconducting layer or the second superconducting layer, so that the Cooper pair in the superconducting layer introduced with the current generates quantum tunneling effect, passes through the gap and enters the other superconducting layer to form the Josephson current. Compared with the traditional alumina material adopted by the barrier layer of the Josephson junction, the air seam is used as the barrier layer between superconducting materials, so that the barrier layer has more stable property and smaller leakage current, and the stability of the planar Josephson junction is improved.
According to the preparation method of the planar Josephson junction, the step structure with the first part higher than the second part is formed on the substrate by etching, superconducting materials are simultaneously grown on the first part and the second part, and a gap is formed between the first superconducting layer and the second superconducting layer in the vertical direction to serve as a barrier layer of the planar Josephson junction, so that the planar Josephson junction with high stability and high consistency can be prepared in a large scale without using a complex high-precision instrument. The method for preparing the Josephson junction is simplified, and a gap within 1 nanometer (nm) can be realized by using the method provided by the invention, so that a way is provided for preparing the Josephson junction with high superconductive property.
According to the Josephson junction array provided by the embodiment of the invention, the property of each plane Josephson junction is stable and uniform, and compared with a vertical Josephson junction, the Josephson junction array is simple in circuit design, does not need to introduce a complex external circuit, and is easier to integrate into a high-density array.
Drawings
Fig. 1 shows a cross-sectional view of a planar josephson junction according to an embodiment of the invention;
Fig. 2 shows a first cross-sectional view of a planar josephson junction according to an embodiment of the invention;
Fig. 3 shows a flow chart of a method of fabricating a planar josephson junction according to an embodiment of the invention;
Fig. 4a-4d show schematic structural variations of planar josephson junction preparation according to an embodiment of the invention;
FIG. 5 shows a topography of a substrate according to an embodiment of the invention;
Fig. 6 shows a topography of a planar josephson junction according to an embodiment of the invention;
Fig. 7 shows a schematic diagram of a planar josephson junction according to an embodiment of the invention;
FIG. 8 shows a graph of planar Josephson junction resistance temperature dependence of superconductive layers at different deposition times in accordance with an embodiment of the present invention;
Fig. 9 shows a josephson junction array according to an embodiment of the invention;
fig. 10 shows a top view of a quantum chip according to an embodiment of the invention; and
FIG. 11 shows a cross-sectional view of section A-A shown in FIG. 10.
Reference numerals illustrate:
1-a substrate;
11-boss;
2-a first superconductive layer;
3-a second superconductive layer;
4-gap;
5-masking;
a 6-bias layer;
7-an excitation layer;
8-an output assembly;
81-a resonant cavity;
82-a detection layer;
83-a first electrode;
84-a second electrode;
9-biasing electrodes;
10-exciting the electrode;
101-superconducting qubits.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
Fig. 1 shows a first cross-sectional view of a planar josephson junction according to an embodiment of the invention, and fig. 2 shows a second cross-sectional view of a planar josephson junction according to an embodiment of the invention.
As an aspect of the embodiments of the invention, there is provided a planar josephson junction formed on a surface of a substrate 1, the surface of the substrate 1 having a first portion and a second portion, as shown in fig. 1 and 2. The first part extends upwards to form a boss 11 higher than the second part, the side of the boss 11 adjacent to the second part and the top surface of the second part having an angle alpha in the range of (0 DEG, 90 DEG), i.e. the angle alpha between the side of the boss 11 and the second part is greater than 0 DEG and less than or equal to 90 DEG, preferably alpha is greater than or equal to 45 DEG and less than or equal to 90 DEG the planar Josephson junction comprises a first superconducting layer 2 and a second superconducting layer 3, the first superconducting layer 2 being arranged on the boss 11 and the second superconducting layer 3 being arranged on the second part of the surface, wherein a gap 4 is formed between the first superconducting layer 2 and the second superconducting layer 3, the length h of the gap 4 in the vertical direction being smaller than the superconducting coherence length of the superconducting materials used by the first superconducting layer 2 and the second superconducting layer 3, such that the first superconducting layer 2 and the second superconducting layer 3 and the gap 4 form a planar Josephson junction.
According to the planar Josephson junction provided by the embodiment of the invention, the boss is formed on the first part of the substrate, the height difference is formed with the second part of the substrate, the first superconducting layer and the second superconducting layer are respectively arranged on the first part and the second part of the substrate, the first superconducting layer and the second superconducting layer form a gap in the height direction, the gap is adopted as a barrier layer of the planar Josephson junction, and when the first superconducting layer and the second superconducting layer are below the superconducting transition temperature, the current is introduced into the first superconducting layer or the second superconducting layer, so that the Cooper pair in the superconducting layer introduced with the current generates quantum tunneling effect, passes through the gap and enters the other superconducting layer to form the Josephson current.
In some exemplary embodiments, the included angle α may be any one of 1 °, 5 °, 10 °,20 °, 30 °, 40 °, 50 °, 60 °, 70 °, 75 °, 80 °, 85 °, 90 °, and the like by employing a dry etching or wet etching method.
According to an embodiment of the present invention, the gap filling material may include a conductive material, an insulator material, or a semiconductor material. It is understood that the filler material may be a vacuum, a solid, a liquid, or a gas.
In an exemplary embodiment, the gap filling material may include an insulating gas or air, etc. Compared with the traditional alumina material adopted by the barrier layer of the Josephson junction, the barrier layer between superconducting materials is made of gas, has more stable property and smaller leakage current, and improves the stability of the planar Josephson junction.
According to an embodiment of the invention, the substrate is an insulating substrate. Further, the substrate is one of silicon wafer with an oxide layer, aluminum oxide, magnesium oxide and intrinsic silicon.
According to an embodiment of the present invention, the first superconducting layer and the second superconducting layer are metallic or non-metallic materials having superconducting properties.
According to embodiments of the invention, the first superconducting layer and the second superconducting layer may be made of the same superconducting material, so as to facilitate preparation and improve stability of the josephson junction. It will be appreciated that the superconducting material used for the first superconducting layer may also be different from the superconducting material used for the second superconducting layer.
In an exemplary embodiment, the superconducting material used for the first superconducting layer and the second superconducting layer may be niobium (Nb), lead (Pb), aluminum (Al), tin (Sn), magnesium (Mg), niobium-titanium alloy (NbTi), or niobium-trisin (Nb 3 Sn).
In another exemplary embodiment, the superconducting material used for the first superconducting layer and the second superconducting layer may be any one of copper oxide, an iron-based superconductor, an organic superconductor, and the like.
According to an embodiment of the invention, the resistivity of some substances suddenly changes to zero when the temperature is below a certain value (Tc), this state being called superconducting state, such substances being called superconductors, tc being called transition temperature of the superconductors. The transition temperatures of different superconducting materials are also different. For example, niobium (Nb) has a superconducting transition temperature of 9.25 kelvin (K), i.e., -263.9 degrees celsius (°c); the superconducting transition temperature of lead (Pb) is 7.193K.
According to the embodiment of the present invention, the surface roughness of the first superconducting layer and the second superconducting layer is smaller than the control accuracy of the gap and smaller than the superconducting coherence length of the superconducting material employed by the first superconducting layer 2 and the second superconducting layer 3.
Fig. 3 shows a flow chart of a method of fabricating a planar josephson junction according to an embodiment of the invention, fig. 4a-4d show schematic structural variations of the fabrication of a planar josephson junction according to an embodiment of the invention, fig. 5 shows a topography of a substrate according to an embodiment of the invention, and fig. 6 shows a topography of a planar josephson junction according to an embodiment of the invention. Wherein the scale of the microscope in FIG. 5 is 2 μm and the scale of the microscope in FIG. 6 is 200nm.
As another aspect of an embodiment of the invention, there is provided a method of preparing a planar josephson junction of any of the above, as shown in fig. 3, fig. 4a-4d and fig. 5 and 6, the method comprising operations S310-S340.
In operation S310, as shown in fig. 4a, a mask 5 is deposited on a first portion of a substrate 1.
In operation S320, as shown in fig. 4b, the second portion of the substrate is etched downward by dry etching or wet etching, so that the first portion forms a boss 11 higher than the second portion, and as shown in fig. 5, the difference in height between the first portion and the second portion of the substrate is D, and the difference in height D is greater than the superconducting coherence length of the superconducting material used for the first superconducting layer and the second superconducting layer.
In operation S330, as shown in fig. 4c, the mask 5 is removed, and for example, the mask may be etched away using a hydrochloric acid (HCl) solution.
In operation S340, as shown in fig. 4d, 5 and 6, a first superconductive layer 2 and a second superconductive layer 3 are grown simultaneously on the boss 11 and the second portion of the substrate 1 in the direction indicated by the arrow in fig. 5, and a gap 4 is formed between the first superconductive layer 2 and the second superconductive layer 3 to form a planar josephson junction. The materials of the first superconducting layer 2 and the second superconducting layer 3 may be niobium (Nb), and it is understood that the materials of the first superconducting layer 2 and the second superconducting layer 3 may also be other superconducting materials, such as aluminum.
According to the embodiment of the present invention, the length h of the gap 4 in the vertical direction can be controlled so that h is smaller than the superconducting coherence length of the superconducting materials employed for the first superconducting layer 2 and the second superconducting layer 3 by controlling the thicknesses of the grown first superconducting layer and second superconducting layer.
In fig. 6, the gap 4 formed between the first superconducting layer 2 and the second superconducting layer 3 is undersized (less than 50 nm) in the drawing, and is 200 nm-sized in fig. 6, and is therefore not shown.
Fig. 7 shows a schematic diagram of a planar josephson junction according to an embodiment of the invention.
As shown in fig. 7, the material of the first superconducting layer 2 and the second superconducting layer 3 is niobium (Nb), and when the planar josephson junction is below the superconducting transition temperature of the niobium material, that is, below 9.25K (-263.9 ℃), the cooper pair (Cooper pairs) in one superconducting layer generates a quantum tunneling effect, passes through the gap, and enters the other superconducting layer to form a josephson current.
According to the preparation method of the planar Josephson junction, the step structure with the first part higher than the second part is formed on the substrate by etching, superconducting materials are grown on the first part and the second part, and a gap is formed between the first superconducting layer and the second superconducting layer in the vertical direction to serve as a barrier layer of the planar Josephson junction, so that the planar Josephson junction with high stability and high consistency can be prepared in a large scale without using a complex high-precision instrument. The method for preparing the Josephson junction is simplified, and the method provided by the invention can realize the gap length with the height smaller than the superconducting coherence length of the superconducting materials adopted by the first superconducting layer and the second superconducting layer, thereby providing a way for preparing the high-temperature superconducting Josephson junction.
Methods of growing the first and second superconducting layers according to embodiments of the present invention include chemical vapor deposition, deposition processes of physical vapor deposition (e.g., evaporation or sputtering), epitaxial techniques, and other deposition processes of sol-gel methods (so 1-ge 1). Physical vapor deposition includes Ion Beam Assisted Deposition (IBAD), electron beam vapor deposition (Evaporation), pulsed Laser Deposition (PLD), magnetron Sputtering (Magnetron Sputtering). The epitaxy method is Molecular Beam Epitaxy (MBE). A kind of electronic device with a high-pressure air-conditioning system. Preferably, the method comprises one of electron beam evaporation, magnetron sputtering and pulse laser deposition.
According to an embodiment of the present invention, before operation S310, further comprising: the substrate is pretreated.
According to an embodiment of the present invention, preprocessing a substrate includes: the substrate is cleaned, the substrate is put into an organic solvent for ultrasonic cleaning, and the ultrasonic cleaning time can be set according to actual needs, for example, 20 minutes (min), 30min, 35min or 40min. And fishing out after ultrasonic cleaning is finished, and drying the cleaned substrate by using inert gas (such as any one or more of nitrogen, argon and the like). And patterning the cleaned substrate into a required pattern (namely, an area needing mask protection) by micro-nano processing.
In an exemplary embodiment, the substrate is a silicon substrate, and the silicon substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment for 30min, and then is fished out and dried by nitrogen.
According to an embodiment of the present invention, patterning is one of lithography, electron beam exposure, and a stencil method.
According to an embodiment of the invention, the mask is made of a material that is resistant to etching and is chemically stable in the liquids (which may be, for example, acetone solution and sodium hydroxide solution) that are used for subsequent metal stripping and etching of the substrate.
According to the embodiment of the invention, the mask material can be selected according to actual needs, and comprises a metal material and a nonmetal material. For example, the mask material includes any one of nickel (Ni), chromium (Cr), titanium (Ti), and the like.
According to an embodiment of the invention, depositing a mask on a first portion of a substrate includes: patterning a first portion on a substrate, depositing a metal layer on the exposed area, placing the substrate with the deposited metal layer in a first solution, stripping the metal on a second portion of the substrate, and using the metal layer on the first portion as a mask.
According to an embodiment of the invention, etching down from the second portion of the substrate using wet etching comprises: a second portion of the substrate is etched using a second solution.
According to an embodiment of the invention, the first solution is an organic solvent, an acid or a base. For example, in the case of dissolving polymethyl methacrylate (PMMA), the first solution may be an acetone solution.
According to an embodiment of the invention, the second solution is a solution capable of chemically reacting with the substrate. For example, in the case where the substrate is a silicon substrate, the second solution may be a sodium hydroxide solution.
Fig. 8 shows a graph of planar josephson junction resistance temperature dependence of superconductive layers at different deposition times in accordance with an embodiment of the present invention.
In an exemplary embodiment, as shown in fig. 8, the abscissa represents the temperature T (K), and the ordinate represents the resistance R (Ω). The first superconducting layer and the second superconducting layer are deposited simultaneously with superconducting materials, and the curves of fig. 8 respectively show the temperature dependence of the josephson junction resistance at different times of deposition of the superconducting materials. Wherein the curve in fig. 8 (seen from the right side of fig. 8) increases in sequence from the time of depositing superconducting material from top down. As can be seen from fig. 8, the resistances increase sequentially from the bottom (the time to deposit superconducting material is longest) to the top (the time to deposit superconducting material is shortest) of the curve, and by adjusting the deposition time of superconducting material, the junction labeled as superconducting State (SC), transitional state (AM), josephson Junction (JJs) and Insulator (INS) which are representative in fig. 8 can be prepared. In fig. 8, the curves between the superconducting State (SC) and the Josephson Junction (JJs) are both transition states (AM) and the curves above the Josephson Junction (JJs) are both Insulators (INS) so that a suitable planar josephson junction can be prepared by adjusting the time for depositing superconducting material.
Fig. 9 shows a josephson junction array according to an embodiment of the invention.
As a further aspect of an embodiment of the invention there is provided an array of josephson junctions, as shown in fig. 9, comprising a plurality of any of the planar josephson junctions described above.
According to the Josephson junction array provided by the embodiment of the invention, the property of each plane Josephson junction is stable and uniform, and compared with a vertical Josephson junction, the Josephson junction array is simple in circuit design, does not need to introduce a complex external circuit, and is easier to integrate into a high-density array.
In an exemplary embodiment, as shown in fig. 9, a josephson array is formed on the substrate 1, comprising a plurality of any of the planar josephson junctions described above.
According to embodiments of the invention, a plurality of planar josephson junctions in the array of josephson junctions may be one or more of connected in series, in parallel, and disconnected at the time of fabrication, as desired.
According to an embodiment of the invention, a plurality of planar josephson junctions in the array of josephson junctions may be used in series in a voltage reference circuit and a multi-planar josephson junction device may be made without connection.
The technical scheme of the invention is described in detail through specific examples. It should be noted that the following specific embodiments are only examples and are not intended to limit the present invention.
Example 1
In this embodiment, silicon dioxide or silicon (SiO 2/Si) with a thickness of 300 nm is selected as the substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment of 30 and min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and nickel (Ni) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etching is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution) to form a stepped structure, i.e., the first portion of the substrate forms a higher boss than the second portion, as shown in fig. 4 c.
As shown in fig. 4d, a substrate with a stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness (roughness less than the control accuracy of the air gap and less than the superconducting coherence length of the niobium material), the niobium film at the first and second parts of the substrate, respectively, and the air gap therebetween forming a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 2
In the embodiment, aluminum oxide with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment for 30: 30min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and nickel (Ni) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness, and the niobium films respectively located in the first and second parts of the substrate and the air gap between them form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 3
In the embodiment, magnesium oxide with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment for 30: 30min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and nickel (Ni) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness, and the niobium films respectively located in the first and second parts of the substrate and the air gap between them form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 4
In the embodiment, intrinsic silicon with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment for 30: 30min, fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and nickel (Ni) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness, and the niobium films respectively located in the first and second parts of the substrate and the air gap between them form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 5
In the embodiment, siO 2/Si with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment of 30 and min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, the electron beam exposure is used to pattern the region to be protected of the hard mask on the substrate, and then the photolithography method is used to deposit nickel (Ni) as the hard mask for the later wet etching in the exposed region.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness, and the niobium films respectively located in the first and second parts of the substrate and the air gap between them form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 6
In the embodiment, siO 2/Si with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment of 30 and min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and aluminum (Al) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness, and the niobium films respectively located in the first and second parts of the substrate and the air gap between them form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 7
In the embodiment, siO 2/Si with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment of 30 and min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and titanium (Ti) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness, and the niobium films respectively located in the first and second parts of the substrate and the air gap between them form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 8
In the embodiment, siO 2/Si with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment of 30 and min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and nickel (Ni) is deposited on the exposed region as a hard mask for post dry etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched using a dry etching method.
After the surface layer silicon etching is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution) to form a stepped structure, i.e., the first portion of the substrate forms a higher boss than the second portion, as shown in fig. 4 c. As shown in fig. 4d, the substrate with the stepped structure is placed in a magnetron sputtering chamber to grow a niobium film with low roughness, and the niobium films respectively located in the first and second parts of the substrate and the air gap between them form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 9
In the embodiment, siO 2/Si with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment of 30 and min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and nickel (Ni) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is grown into a niobium film with low roughness by an electron beam evaporation method, and the niobium films respectively located at the first part and the second part of the substrate and an air gap between the niobium films form a plane josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
Example 10
In the embodiment, siO 2/Si with the thickness of 300 nm is selected as a substrate, the substrate is cleaned, and the substrate is respectively put into acetone, alcohol and deionized water for ultrasonic treatment of 30 and min, and then is fished out and dried by nitrogen.
As shown in fig. 4a, a hard mask protection region is patterned on a substrate by using electron beam exposure, and nickel (Ni) is deposited on the exposed region as a hard mask for a post wet etching by using a metal deposition method of electron beam evaporation.
As shown in fig. 4b, the metal-plated sample is peeled off in an acetone solution, and then fished out, and the substrate (i.e., the second portion of the substrate) protected by the hard mask is etched by using a sodium hydroxide (NaOH) solution with a certain concentration.
After the surface layer silicon etch is completed, the hard mask is etched away using a solution (which may be a hydrochloric acid solution), as shown in fig. 4 c. A stepped structure is formed, i.e. the first portion of the substrate forms a higher boss than the second portion.
As shown in fig. 4d, the substrate with the stepped structure is grown with a pulse laser method to form a low roughness niobium film, and the niobium films respectively located at the first and second parts of the substrate and the air gap therebetween form a planar josephson junction.
A plurality of planar josephson junctions are interconnected to form an array of josephson junctions.
The same preparation process as in example 1 was used for examples 2,3, 4, the choice of insulating substrate being different. The aluminum oxide and magnesium oxide mentioned in examples 2,3 are relatively difficult to etch with respect to silicon. For example 4 where the substrate is intrinsic silicon, the intrinsic silicon has no stop layer and the etch depth is not easily controlled.
In example 5, exposure using photolithography, the pattern edge was rough compared to example 1, which affects the uniformity and stability of the device.
The material selection in the hard mask was different for examples 6, 7 as in the preparation process in example 1. The aluminum (Al) and titanium (Ti) mentioned in examples 6 and 7 have a high corrosion rate in wet etching, and do not exert a good protective effect.
For the dry etching used in example 8, the air gap verticality obtained by the dry etching is poor, resulting in poor device stability.
For examples 9 and 10, niobium films were prepared by electron beam evaporation and pulsed laser deposition. Niobium films prepared using electron beam evaporation have poor crystallinity compared to example 1, and it is difficult to achieve superconductivity; the niobium film prepared using pulsed laser deposition resulted in larger roughness of the large particles compared to example 1, resulting in uneven and unstable device.
Fig. 10 shows a top view of a quantum chip according to an embodiment of the invention.
As a further aspect of an embodiment of the present invention, there is provided a quantum chip, as shown in fig. 10, comprising a quantum chip including a substrate 1, superconducting qubits 101, a bias layer 6 and an excitation layer 7. Superconducting qubit 101 is disposed on substrate 1, superconducting qubit 101 comprising two parallel-connected planar josephson junctions of any of the above. The bias layer 6 is disposed on the substrate 1 and coupled to the superconducting qubit 101, and is adapted to transmit a magnetic flux bias voltage from the outside, where the magnetic flux bias voltage is adapted to regulate the frequency of the superconducting qubit 101, so that the superconducting qubit 101 is at an operating frequency. The excitation layer 7 is arranged on the substrate 1 and coupled with the superconducting qubit 101, and is suitable for microwave pulse transmitted from the outside, and the microwave pulse is suitable for driving the superconducting qubit 101 under the working frequency, so that the energy level of the superconducting qubit 101 is transited, and the quantum state of the superconducting qubit 101 is regulated and controlled to read and write information.
According to the quantum chip provided by the embodiment of the invention, two parallel Josephson junctions are arranged on the substrate to form superconducting quantum bits, and the superconducting quantum bits are regulated and controlled by transmitting magnetic flux bias voltage through the excitation layer, so that the superconducting quantum bits are in working frequency, the magnetic flux bias voltage can also reduce decoherence of the quantum bits, and the coherence time of the quantum bits is improved, so that the accuracy of quantum calculation is improved. Furthermore, microwave pulses are transmitted through the excitation layer to drive the superconducting quantum bits, so that the energy level of the superconducting quantum bits is transited, the quantum states of the superconducting quantum bits are regulated, and information reading and writing are realized. By using air as the barrier layer of the Josephson junction, the decoherence time, stability and gate fidelity of the superconducting qubit are improved.
Compared with the traditional computer, the quantum computer can be in a coherent superposition state of 0 and 1, and the capability is called coherence, and a high-quality quantum computing chip needs a large number of logic gates and long decoherence time.
In an exemplary embodiment, the scale of the microscope is 200 μm in fig. 10, and in practice, the scale may be sized according to actual needs.
According to an embodiment of the present invention, the frequency of superconducting qubit 101 generally refers to the frequency corresponding to the energy difference between its quantum states. This frequency is related to the capacitance and inductance of the josephson junction, and these parameters determine the Hamiltonian (Hamiltonian) of the qubit and thus its energy level structure.
According to an embodiment of the invention, the quantum chip further comprises two bias electrodes 9, as shown in fig. 10. The two bias layers 6 are respectively coupled with the two josephson junctions of the superconducting qubit 101 through capacitance, and the two bias electrodes 9 are respectively arranged at one ends of the two bias layers far away from the two josephson junctions and are used for receiving magnetic flux bias voltages from the outside so that the superconducting qubit 101 is at the working frequency.
According to an embodiment of the invention, the quantum chip further comprises two excitation electrodes 10, as shown in fig. 10. The two excitation layers 7 are respectively coupled with the two josephson junctions of the superconducting qubit 101 through capacitance, and the two excitation electrodes 10 are respectively arranged at one ends of the two excitation layers far away from the two josephson junctions and are used for receiving microwave pulses from the outside so as to drive the superconducting qubit 101 to enable the energy level of the superconducting qubit 101 to transit through the microwave pulses under the working frequency of the superconducting qubit 101 and regulate the quantum state of the superconducting qubit 101.
According to an embodiment of the present invention, the quantum chip further comprises an output component 8, wherein the output component 8 is disposed on the substrate and coupled with the superconducting qubit 101, and is adapted to convert a quantum state where the superconducting qubit 101 is located into an electrical signal and output the electrical signal.
According to the embodiment of the invention, the quantum state of the superconducting quantum bit 101 is indirectly obtained by arranging the output component coupled with the superconducting quantum bit 101 and reading the electric signal output by the output component, so that the nondestructive measurement of the superconducting quantum bit 101 is realized.
According to an embodiment of the invention, the output assembly 8 comprises a resonator 81 and a detection layer 82. The resonant cavity 81 is coupled with the superconducting qubit 101 to obtain a quantum state where the superconducting qubit 101 is located and convert the quantum state into an electrical signal, and the detection layer 82 is coupled with the resonant cavity 81. Wherein a voltage signal input from a first end of the detection layer 82 is influenced by the electric signal, and a response signal is output from a second end of the detection layer 82 to calculate a quantum state of the superconducting qubit 101 based on the voltage signal and the response signal.
According to the embodiment of the present invention, by calculating the transmission coefficients of the voltage signal input from the first end and the response signal output from the second end of the detection layer 82, the quality factor of the resonator 81 can be calculated, and further the decay rate of the photons of the resonator 81 can be calculated from the quality factor, the smaller the decay rate, the higher the discrimination of the quantum state of the readout quantum bit.
According to the embodiment of the invention, the resonant cavity 81 and the superconducting qubit 101 are coupled through capacitance, the detection layer 82 and the resonant cavity 81 are coupled through capacitance, so that a voltage signal input from the first end of the detection layer 82 can be influenced by an electric signal of the resonant cavity 81, and a response signal is output from the second end of the detection layer 82, so that the quantum state of the superconducting qubit 101 is indirectly obtained based on the voltage signal and the response signal, and nondestructive measurement of the superconducting qubit 101 is realized.
According to an embodiment of the present invention, as shown in fig. 10, the quantum chip further includes a first electrode 83 and a second electrode 84. The detection layer 82 and the resonant cavity 81 are coupled by capacitance, and a first electrode 83 and a second electrode 84 are respectively disposed at a first end and a second end of the detection layer 82, for respectively receiving a voltage signal from the outside and outputting a response signal.
Figure 11 shows a cross-sectional view of A-A shown in figure 10.
As can be seen from fig. 11, the area of the substrate 1 for preparing the circuit structures of the bias layer, the excitation layer, etc. is also a step structure, having a first surface located at an upper portion of the step structure and a second surface located at a lower portion of the step structure, the first surface being higher than the second surface. The superconducting material is deposited on the first surface, which forms the circuit structure of the quantum chip (e.g., the bias layer, the excitation layer, the output component, the bias electrode, and the excitation electrode), and on the second surface, which acts as a peripheral circuit of the quantum chip. The height difference L between the superconducting materials on the first surface and the second surface is larger than the superconducting coherence length of the adopted superconducting materials, so that the circuit structure of the quantum chip can be electrically insulated from the peripheral circuit.
It will be appreciated that the planar josephson junction provided by the present invention may also be applied to other devices, such as travelling wave parametric amplifiers and the like.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.
Claims (10)
1. A planar josephson junction formed on a surface of a substrate, the surface having a first portion and a second portion, the first portion extending upwardly to form a ledge, the side of the ledge being at an angle of greater than 0 ° and less than or equal to 90 ° to the second portion, the planar josephson junction comprising:
The first superconducting layer is arranged on the boss; and
A second superconductive layer disposed on a second portion of the surface;
And a gap is formed between the first superconducting layer and the second superconducting layer, and the length of the gap in the vertical direction is smaller than the superconducting coherence length of the superconducting materials adopted by the first superconducting layer and the second superconducting layer.
2. The planar josephson junction of claim 1, wherein the surface roughness of the first and second superconducting layers is less than the control accuracy of the gap.
3. The planar josephson junction of claim 1, wherein the first superconducting layer and the second superconducting layer are metallic or non-metallic materials having superconducting properties.
4. The planar josephson junction of claim 3, wherein the first superconducting layer and the second superconducting layer are made of any one of niobium, lead, aluminum, copper oxide, an iron-based superconductor, and an organic superconductor.
5. The planar josephson junction of claim 1, wherein the filling of the gap is any one of vacuum, solid, liquid and gas.
6. A method of preparing the planar josephson junction of any of claims 1 to 5, comprising:
Depositing a mask over a first portion of a substrate;
Etching downwards from the second part of the substrate by adopting dry etching or wet etching, so that the first part forms a boss higher than the second part;
removing the mask;
first and second superconducting layers are grown simultaneously on the boss and the second portion of the substrate, with a gap being formed between the first and second superconducting layers to form a planar josephson junction.
7. The method of claim 6, wherein the method of growing the first and second superconducting layers comprises any one of electron beam evaporation, magnetron sputtering, pulsed laser deposition.
8. The method of claim 6, wherein depositing a mask over the first portion of the substrate comprises:
Patterning a first portion on a substrate;
depositing a mask material in the exposed areas;
The substrate with the deposited masking material is placed in a first solution, and the masking material on the second portion of the substrate is stripped off, leaving the masking material on the first portion as a mask.
9. The method of claim 6, wherein etching down from the second portion of the substrate using wet etching comprises:
and etching the second part of the substrate by adopting a second solution.
10. An array of josephson junctions comprising a plurality of planar josephson junctions according to any of claims 1 to 5.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4454522A (en) * | 1981-11-05 | 1984-06-12 | The Board Of Trustees Of The Leland Stanford Junior University | Microbridge superconducting device having support with stepped parallel surfaces |
| JPH0730159A (en) * | 1993-07-15 | 1995-01-31 | Sumitomo Electric Ind Ltd | Josephson junction element and its manufacture |
| JPH07193285A (en) * | 1993-12-27 | 1995-07-28 | Sharp Corp | Josephson junction element |
| CN114512594A (en) * | 2020-10-27 | 2022-05-17 | 阿里巴巴集团控股有限公司 | Superconducting quantum bit and preparation method thereof, quantum memory and quantum computer |
| CN117915757A (en) * | 2023-11-15 | 2024-04-19 | 本源量子计算科技（合肥）股份有限公司 | Josephson junction device and superconducting quantum chip |
-
2024
- 2024-05-20 CN CN202410621048.8A patent/CN118201469B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4454522A (en) * | 1981-11-05 | 1984-06-12 | The Board Of Trustees Of The Leland Stanford Junior University | Microbridge superconducting device having support with stepped parallel surfaces |
| JPH0730159A (en) * | 1993-07-15 | 1995-01-31 | Sumitomo Electric Ind Ltd | Josephson junction element and its manufacture |
| JPH07193285A (en) * | 1993-12-27 | 1995-07-28 | Sharp Corp | Josephson junction element |
| CN114512594A (en) * | 2020-10-27 | 2022-05-17 | 阿里巴巴集团控股有限公司 | Superconducting quantum bit and preparation method thereof, quantum memory and quantum computer |
| CN117915757A (en) * | 2023-11-15 | 2024-04-19 | 本源量子计算科技（合肥）股份有限公司 | Josephson junction device and superconducting quantum chip |
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