CN118135955A

CN118135955A - Level conversion circuit and display device

Info

Publication number: CN118135955A
Application number: CN202410437400.2A
Authority: CN
Inventors: 王明良; 叶利丹
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Priority date: 2024-04-11
Filing date: 2024-04-11
Publication date: 2024-06-04

Abstract

The embodiment of the application discloses a level conversion circuit and a display device. The level conversion circuit is used for receiving an initial clock signal and correspondingly outputting an adjusted clock signal and comprises a control unit, an adjusting unit and a clock signal output unit, wherein the control unit is used for receiving the initial clock signal and correspondingly outputting a clock adjusting signal, the adjusting unit is connected with the control unit and outputs a speed regulating control signal to the clock signal output unit according to the clock adjusting signal, the clock signal output unit is connected with the adjusting unit, a first conductive end and a second conductive end, the first conductive end is used for providing a first voltage, the second conductive end is used for providing a second voltage, the first conductive end and the second conductive end are alternately selected according to the speed regulating control signal received by the self-adjusting unit and are connected with the clock signal output end, the first voltage and the second voltage form the clock signal, and the speed regulating control signal is used for regulating the speed of the clock signal output unit to output the clock signal.

Description

Level conversion circuit and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

The display device includes a display panel, and a data driving circuit and a scan driving circuit for driving the display panel. The data driving circuit provides data driving signals for the data lines of the display panel, and the scanning driving circuit provides scanning signals for the scanning lines of the display panel respectively. At present, the scan driving circuit outputs a scan signal according to a received clock signal, wherein the clock signal is provided by the timing controller, but the scan driving circuit outputs the clock signal with a larger driving capability due to different refresh rates and loads. Thus, the level shift unit is usually also provided for the clock signal supplied from the timing control circuit.

In the prior art, a level conversion circuit performs level conversion according to an initial clock signal provided by a timing control circuit to generate a high-level VGH and a low-level VGL clock signal, and then a scan driving circuit outputs a scan signal according to the clock signal. However, the scan signals output by the scan driving circuit often cannot meet the requirements of different loads, so that images cannot be accurately displayed.

Disclosure of Invention

In view of the foregoing technical problems, the present application provides a level shifter circuit and a display device with accurate output clock signals.

In a first aspect, an embodiment of the present application discloses a level conversion circuit, configured to receive an initial clock signal and output an adjusted clock signal correspondingly, where the level conversion circuit includes a control unit, an adjusting unit, and a clock signal output unit, where the control unit is configured to receive the initial clock signal and output a clock adjustment signal correspondingly, the adjusting unit is connected to the control unit and output a speed adjustment control signal to the clock signal output unit according to the clock adjustment signal, the clock signal output unit is connected to the adjusting unit, a first conductive end and a second conductive end, the first conductive end is configured to provide a first voltage, the second conductive end is configured to provide a second voltage, and the first conductive end and the second conductive end are alternately selected according to the speed adjustment control signal received from the adjusting unit and connected to the clock signal output end, where the first voltage and the second voltage form a clock signal, and the speed adjustment control signal is configured to adjust a speed of the clock signal output by the clock signal output unit.

In an embodiment of the present application, the adjusting unit includes a power unit, a first switch output unit and a second switch output unit; the power unit is connected with the control unit and outputs the speed regulation control signals with different powers according to the clock regulation signals; the first switch output unit is connected with the power unit and the clock signal output unit, and transmits the speed regulation control signal to the clock signal output unit under the control of a first potential of the initial clock signal; the second switch output unit is connected with the power unit and the clock signal output unit, receives the initial clock signal and transmits the speed regulation control signal to the clock signal output unit under the control of a second potential of the initial clock signal; the initial clock signal is a plurality of periodic pulse width signals, and each period comprises the first voltage and the second potential.

In an embodiment of the application, the power unit includes a power control end, a first power output end and a second power output end, wherein the power control end is connected with the control unit and receives the clock adjustment signal, and the power unit outputs the clock adjustment signal from the first power output end and the second power output end under the control of the clock adjustment signal.

In an embodiment of the present application, the power unit includes a current source, where the current source is configured to output different currents from the first power output terminal and the second power output terminal as the clock adjustment signal according to the clock adjustment signal; the first switch output unit comprises a first switch which is conducted under the control of a first potential of the initial clock signal, and the clock adjustment signal is transmitted to the clock signal output unit from the first switch conducting end and the second switch conducting end. The second switch output unit comprises a second switch and a first switch tube, the first switch tube is conducted under the control of a second potential of the initial clock signal, the starting voltage output by the starting voltage end is transmitted to the second switch and is controlled to be conducted, and the clock adjustment signal is transmitted to the clock signal output unit through the second switch.

In an embodiment of the application, the clock signal output unit includes a first voltage output subunit and a second voltage output subunit, where the first voltage output subunit is connected to the adjusting unit and the first voltage end, and is configured to receive the speed regulation control signal from the adjusting unit, and transmit, according to the speed regulation control signal, a first voltage provided by the first voltage end to the clock signal output end according to a corresponding speed; the second voltage output subunit is connected with the adjusting unit and the second voltage end, and is used for receiving the speed regulation control signal from the speed searching adjusting unit, transmitting the second voltage provided by the second voltage end to the clock signal output end according to the speed regulation control signal at a corresponding speed, and the first voltage and the second voltage form a pulse width signal of the clock signal in one period.

In an embodiment of the application, the first voltage output subunit includes a first output switch tube, where the first output switch tube includes a first output control end, a first output conductive end and a second output conductive end, the first output control end is electrically connected to the adjusting unit and receives a speed regulation control signal, the first output conductive end is connected to the first conductive end, the second output conductive end is connected to a clock signal output end, the first output switch is in a conducting state according to a corresponding speed under the control of the speed regulation control signal, and a first voltage output by the first conductive end is transmitted to the clock signal output end through the first output conductive end and the second output conductive end.

In an embodiment of the application, the second voltage output subunit includes a second output switch tube and a third output switch tube, where the second output switch tube includes a second output control end, a third output conductive end and a fourth output conductive end, the second output control end is electrically connected to the adjusting unit and receives the speed regulation control signal, the third output conductive end is connected to the first voltage end, and the fourth output conductive end is connected to the third switch tube. The third output switch tube comprises a third output control end, a fifth output conductive end and a sixth output conductive end, wherein the third output control end is electrically connected with the fourth output conductive end and is used for receiving the speed regulation control signal from the second output switch tube, the fifth output conductive end is connected with the second conductive end, and the sixth output conductive end is connected with the clock signal output end; the second output switch is in a conducting state according to the corresponding speed under the control of the speed regulation control signal, the first voltage output by the first conducting end is transmitted to the third output switch tube through the third output conducting end and the fourth output conducting end, the first voltage correspondingly controls the third output switch tube to be conducted, and the second voltage output by the second conducting end is transmitted to the clock signal output end through the second output switch tube.

In the embodiment of the application, the first switch comprises a first switch control end, a first switch conducting end and a second switch conducting end, wherein the first switch control end receives the initial clock signal, the first switch conducting end is connected with the first power output end, the second switch conducting end is connected with the clock signal output unit, the first switch is conducted or cut off under the control of the initial clock signal, and when the first switch is conducted under the control of a first potential of the initial clock signal, the clock adjustment signal is transmitted to the clock signal output unit from the first switch conducting end and the second switch conducting end.

The first switch tube comprises a first conductive control end, a first conductive end and a second conductive end, wherein the first conductive control end receives the initial clock signal, the first conductive end is connected with a starting voltage end, and the second conductive end is connected with the second switch; the second switch comprises a second switch control end, a third switch conducting end and a fourth switch Guan Daodian end, wherein the second switch control end is connected with the second conducting end of the first switch tube, the third switch conducting end is connected with the second power output end, and the fourth switch conducting end is connected with the clock signal output unit; the first switch tube is in on or off under the control of the initial clock signal, when the first switch is in on under the control of the second potential of the initial clock signal, the starting voltage output by the starting voltage end controls the second switch to be in on, and the clock adjustment signal is transmitted to the clock signal output unit from the third switch conducting end and the fourth switch conducting end.

In an embodiment of the application, the level conversion circuit further includes a comparison unit, the comparison unit is connected to the control unit and the clock signal output unit, and is configured to detect the clock signal output by the clock signal output unit and obtain a detection signal, compare the detection signal with a reference clock signal to obtain a first comparison result, and transmit the first comparison result to the control unit, where the control unit outputs different clock adjustment signals according to the first comparison result, so as to adjust a speed of outputting the clock signal by the clock signal output unit.

In an embodiment of the application, the level conversion circuit further includes a temperature detection unit, the temperature detection unit is connected to the control unit, the temperature detection unit is configured to detect a temperature of the level conversion circuit, output a temperature adjustment signal to the control unit according to the detected temperature, and the control unit outputs different clock adjustment signals according to the temperature adjustment signal, so as to adjust a speed of outputting the clock signal as the clock signal output unit.

In a second aspect, an embodiment of the present application further provides a display device, including a display panel and the foregoing level conversion circuit, where a display area of the display panel includes a plurality of sub-pixels arranged in a matrix, and further includes a plurality of scan lines extending along a first direction and a plurality of data lines extending along a second direction, where the first direction is perpendicular to the second direction, the sub-pixels are located at a position where the scan lines intersect the data lines, and the display panel includes a data driving circuit, a scan driving circuit, and a timing control circuit, where the timing control circuit is configured to output an initial clock signal to the level conversion circuit, the level conversion circuit outputs a scan signal to the scan driving circuit according to the initial clock signal, and the timing control circuit is further configured to output the data signal to the data driving circuit, where the scan signal is configured to control the sub-pixels to receive the data signal from the data driving circuit to perform image display.

Compared with the prior art, in the embodiment of the application, the clock signal actually output by the clock signal output end is influenced due to load change, the waveform of the adjusting clock signal can be adjusted and changed by the control unit by adjusting the current output by the current source, and the difference value between the adjusting clock signal and the standard reference clock signal is adjusted as much as possible, so that the accurate output of the clock signal is ensured, and the accurate display of the image is ensured.

When the clock signal actually output by the clock signal output end is influenced due to load change, the corresponding detection signal and the reference clock signal have a difference value, namely the scanning driving circuit which is used as a load and is connected with the scanning signal in the display panel outputs what scanning signal, or the scanning signal which is used as a load is light and heavy, the level conversion circuit can timely adjust the clock signal, namely the waveform of the adjusting clock signal can be adjusted and changed by utilizing the control unit to adjust the current output by the power unit, and the difference value between the adjusting clock signal and the reference clock signal is adjusted to the greatest extent, so that the difference value between the adjusting clock signal and the reference clock signal is within a preset range, and the clock signal can be accurately output. Further, when the level conversion circuit is applied to the display device, the scanning signal can also meet the image display requirement of the sub-pixels, so that the image display effect is better.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the application;

FIG. 2 is a schematic diagram of a functional module of the display device shown in FIG. 1;

FIG. 3 is a schematic plan layout structure of the display panel shown in FIG. 2;

FIG. 4 is a schematic diagram of an equivalent circuit of any one of the sub-pixels shown in FIG. 3 according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an equivalent circuit of any one of the sub-pixels shown in FIG. 3 according to another embodiment of the present application;

FIG. 6 is a schematic diagram showing the connection of circuit functional units in the second circuit board;

FIG. 7 is a schematic diagram of the circuit structure of the level shifter shown in FIG. 6;

FIG. 8 is a schematic diagram of waveforms of the detection signal and the reference clock signal corresponding to the clock signal before adjustment in the present embodiment;

FIG. 9 is a schematic diagram of waveforms of the detection signal and the reference clock signal corresponding to the clock signal after adjustment in the present embodiment;

Fig. 10 is a schematic diagram of the adjusting unit shown in fig. 6 for adjusting the clock signal.

Reference numerals illustrate:

Display device-1, display panel-10, frame-30, first circuit board-31, second circuit board-32, display area-10 a, non-display area-10 b, data lines-D1-Dm, scan lines-G1-Gn, first direction-F1, second direction-F2, timing control circuit-11, data driving circuit-12, scan driving circuit-13, sub-pixel-P, ith scan line-Gi, jth data line-Sj, storage capacitor-C1, driving switch tube-M1, control switch tube-M2, first control end-M20, first conductive end-M21, second conductive end-M22, second control end-M12, third conductive end-M13, fourth conductive end-M14, driving node-N1, light emitting element-OLED drive current-Ids, ground-GND, power supply-VDD, display capacitor-C1, storage capacitor-C2, transistor-T, pixel electrode-IT, power management circuit-300, level shift circuit-100, clock signal-CK, CK 1-CKN, control unit-101, trigger enable signal-STV, initial clock signal-CK 0, clock adjustment signal-CKc, adjustment unit-102, speed regulation control signal-CH, power unit-SC, power control terminal-SC 0, first power output terminal-SC 1, second power output terminal-SC 2, current source-1020, first switch output unit-ST 1, first switch-1021, first switch control terminal-K10, first switch conductive terminal-K11, the temperature detection circuit comprises a second switch conducting terminal-K12, a second switch output unit-ST 2, a second switch-1022, a first switch tube-1023, a first conducting control terminal-M10, a first conducting terminal-M11, a second conducting terminal-M12, a second switch control terminal-K20, a third switch conducting terminal-K23, a fourth switch Guan Daodian terminal-K24, a clock signal output unit-103, a first voltage output subunit-1031, a second voltage output subunit-1032, a clock signal output terminal-CKout, a first output switch tube-S1, a first output control terminal-S10, a first output conducting terminal-S11, a second output conducting terminal-S12, a second output switch tube-S2, a second output control terminal-S20, a third output conducting terminal-S23, a fourth output conducting terminal-S24, a third output switch tube-S3, a third output control terminal-S30, a fifth output conducting terminal-S35, a sixth output conducting terminal-S36, a detection unit-104, a comparison unit-TH, a detection result of the temperature detection unit-RF signal of which is equal to or higher than the temperature of the temperature detection unit-T2.

Detailed Description

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device according to an embodiment of the application.

As shown in fig. 1, the display device 1 includes a display panel 10 and a frame 30, wherein the display panel 10 is fixed in the frame 30, and the frame 30 provides fixing and supporting functions for the display panel 10. In other embodiments of the present application, when the display device 1 is a portable electronic device, such as a mobile phone, a tablet computer, etc.

Referring to fig. 2, fig. 2 is a schematic diagram of a functional module of the display device 1 shown in fig. 1. As shown in fig. 2, the display device 1 includes a display panel 10, a first circuit board 31, and a second circuit board 32. The first circuit board 31 is electrically connected to the display panel 10 and the second circuit board 32. The first circuit board 31 and the display panel 10 may be connected by a flexible conductive wire or a flexible conductive film, so that the first circuit board 31 can rotate or rotate relative to the display panel 10 and be fixed on the display panel 10, and correspondingly, the first circuit board 31 and the second circuit board 32 are also connected by a flexible conductive wire, so that the second circuit board 32 can rotate the first circuit board 31 and be fixed on the display panel 10.

In the present embodiment, the first circuit board 31 is a driving circuit board (X-board), and the second circuit board 32 is a control circuit board (C-board). The first circuit board 31 and the second circuit board 32 may be a driving circuit board (X-board) or a control circuit board (C-board) alone, or may be an integrated driving circuit board (X-board) and a control circuit board (C-board).

The second circuit board 32 is used as a control circuit board (C-board), and mainly includes a power management circuit 300 (PMIC), a timing control circuit 11 (TCON), etc., and the second circuit board 32 is mainly used for receiving an externally provided display signal for displaying an image and correspondingly outputting a data signal, a control signal, and a power signal.

The first circuit board 31 is used as a driving circuit board (X-board) and is mainly used for receiving data signals and control signals provided by the first circuit board 31 and transmitting the data signals and control signals to a plurality of data driving chips (data driving circuits). In this embodiment, the first circuit board 31 includes a memory (not shown), and the first circuit board 31 is connected to the display panel 10 through a Chip On Flex (COF), and a data driving Chip is disposed On the Chip On Flex. The data driving chip is connected with the sub-pixel P (fig. 3) through a data line (fig. 3) to transmit a data signal to the sub-pixel P for image display.

Please refer to fig. 3, which is a schematic plan layout of the display panel 10 shown in fig. 2. As shown in fig. 3, the display area 10a of the display panel 10 includes a plurality of m×n sub-pixels P, m data lines D1 to Dm and n scan lines G1 to Gn arranged in a matrix, where m and n are natural numbers greater than 1.

The n scan lines G1 to Gn extend along a first direction F1 and are mutually insulated and arranged in parallel along a second direction F2, and the m data lines D1 to Dm extend along the second direction F2 and are mutually insulated and arranged in parallel along the first direction F1, wherein the first direction F1 and the second direction F2 are mutually perpendicular.

The display device 1 further includes a timing control circuit 11 for driving the sub-pixels P to display an image, a data driving circuit 12, and a scan driving circuit 13 provided in the display panel 10, corresponding to the non-display region 10b of the display panel 10.

The timing control circuit 11 is electrically connected to the Data driving circuit 12 and the scan driving circuit 13, and is used for controlling the working timings of the Data driving circuit 12 and the scan driving circuit 13, i.e. outputting corresponding timing control signals to the Data driving circuit 12 and the scan driving circuit 13, so as to control when the scan driving circuit 13 outputs corresponding scan signals and when the Data driving circuit 12 outputs corresponding Data signals (Data).

The Data driving circuit 12 is electrically connected to the m Data lines D1 to Dm, and is configured to transmit the Data signal (Data) for display to the plurality of sub-pixels P in the form of Data voltages through the m Data lines D1 to Dm.

The Scan driving circuit 13 is electrically connected to the n Scan lines G1 to Gn, and is configured to output a Scan signal Scan to the sub-pixel P through the n Scan lines G1 to Gn, so as to control when the sub-pixel P receives the Data signal Data. The Scan driving circuit 13 sequentially outputs the Scan signal Scan from the n Scan lines G1 to Gn in the position arrangement order from the Scan lines G1, G2, … …, gn in the scanning period.

Referring to fig. 4, fig. 4 is an equivalent circuit diagram of any one of the sub-pixels shown in fig. 3 according to an embodiment of the application. As shown in fig. 4, any one of the sub-pixels arranged in an array in the sub-pixel P array substrate 10C includes a driving switching transistor M1, a control switching transistor M2, and a storage capacitor C1.

The control switch tube M2 includes a first control end M20, a first conductive end M21 and a second conductive end M22, wherein the first control end M20 is connected to the ith scanning line Gi, the first conductive end M21 is connected to the jth data line Dj, and the second conductive end M22 is connected to the driving node N1. The voltage received by the first control terminal M20 is used to control the on or off of the control switch tube M2.

In this embodiment, the control switch M2 is a thin film transistor (Thin Film Transistor, TFT), wherein the gate of the transistor is used as the first control terminal M20, or the gate of the transistor is directly connected to the first control terminal M20, the source of the transistor is used as the first conductive terminal M21, or the source of the transistor is directly connected to the first conductive terminal M21, the drain of the transistor is used as the second conductive terminal M22, or the drain of the transistor is directly connected to the second conductive terminal M22. The on control switch M2 receives the data signal from the data line Dj and transmits the data signal to the driving node N1 under the control of the scan signal output by the scan line Gi.

The driving switch tube M1 includes a second control terminal M12, a third conductive terminal M13, and a fourth conductive terminal M14, wherein the second control terminal M12 is connected to the driving node N1, the third conductive terminal M13 is connected to the power supply terminal VDD, and the fourth conductive terminal M14 is connected to the anode of the light emitting element OLED. The voltage received by the second control terminal M12 is used to control the on or off of the driving switch tube M1. In this embodiment, the driving switch M1 is controlled to be turned on or off according to the voltage of the driving node N1. In this embodiment, the cathode of the light emitting element OLED is connected to the ground GND.

In this embodiment, the driving switch transistor M1 is a thin film transistor TFT, and the gate of the transistor is used as the second control terminal M12, or the gate of the transistor is directly connected to the second control terminal M12; the drain of the transistor is used as the third conductive terminal M13, or the drain of the transistor is directly connected to the third conductive terminal M13, and the source of the transistor is used as the fourth conductive terminal M14, or the source of the transistor is directly connected to the fourth conductive terminal M14. The on-state driving switch M1 is in an on-state or an off-state under the voltage control of the driving node N1, and the on-state driving switch M1 outputs a corresponding driving current Ids to the light emitting element OLED according to the power supply voltage provided by the power supply terminal VDD under the control of the driving node N1. It will be appreciated that the drive current Ids is also the source-drain current flowing through the drive switch tube M1.

The storage capacitor C1 is connected between the driving node N1 and the power supply terminal VDD, and is configured to store a data voltage corresponding to a data signal transmitted from the control switch M2 to the driving node N1, and maintain the data voltage to support controlling the on state of the driving switch M1 and simultaneously controlling the driving current Ids provided by the driving switch M1 for the light emitting element OLED.

In this embodiment, the driving switch transistor M1 and the control switch transistor M2 are P-type thin film transistors, and of course, in other embodiments of the present application, the driving transistor M1 and the control transistor M2 may be N-type TFTs.

In this embodiment, the sub-pixel P displays an image by the light emitting element OLED, that is, in this embodiment, the display medium in the sub-pixel P is an organic light emitting material.

Referring to fig. 5, fig. 5 is an equivalent circuit diagram of any one of the sub-pixels shown in fig. 3 according to another embodiment of the application. As shown in fig. 5, the sub-pixel P includes a transistor T, a display capacitor Ca, and a storage capacitor Cb. The gate of the transistor T is connected to the ith scan line Gi for controlling the transistor T to be turned on or off. The source of the transistor T is connected to the jth data line Dj, and the drain of the transistor T is connected to the pixel electrode IT, for receiving a data signal from the jth data line Dj and transmitting the data signal to the pixel electrode IT under the control of the ith scan line Gi.

IT can be understood that the display capacitor Ca is formed of the pixel electrode IT, the liquid crystal molecules as the display medium layer, and the common electrode, wherein the display capacitor Ca and the storage capacitor Cb are connected in parallel, and an electric field of the display capacitor Ca between the pixel electrode IT and the common electrode is maintained by the storage capacitor Cb before the next data signal is loaded.

In this embodiment, the sub-pixel P displays an image through the display capacitor Ca, that is, in this embodiment, the display medium in the sub-pixel P is a liquid crystal material.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating connection of circuit functional units in the second circuit board 32 shown in fig. 3. As shown in fig. 6, the power management circuit 300 and the timing control circuit 11 are respectively electrically connected to the level shift circuit 100, wherein the power management circuit 300 outputs a power signal to the level shift circuit, and the timing control circuit 11 outputs at least one initial clock signal CK0 to the level shift circuit 100. The level shift circuit 100 generates a plurality of driving clock signals CK1 to CKN according to a power supply signal and an initial clock signal CK 0.

The initial clock signal CK0 includes a plurality of pulse width signals arranged periodically, and the pulse width signals in each period include a first potential that lasts for a first preset period and a second potential that lasts for a second preset period. The first position and the second potential are opposite in magnitude, and specific voltage values of the first position and the second potential can be set according to actual requirements, and the first position and the second potential are not limited to the above examples. The specific duration of the first preset time period and the second preset time period can also be set according to actual requirements.

The power signal includes a first Voltage (VGH) at a high Voltage (VGH) and a second Voltage (VGL) at a low Voltage (VGL), for example, 3.5 volts (V) at a second voltage (0V). It is understood that the magnitudes of the first voltage and the second voltage are opposite, and specific voltage values of the first voltage and the second voltage can be set according to actual requirements, and are not limited to the above examples.

It is understood that the clock signals CK1 to CKN are used for being provided to the scan driving circuit 13 to output corresponding scan signals in cooperation with the scan driving circuit 13. When the load of the scan driving circuit 13 is heavy due to the refresh rate and resolution of the scan lines G1 to Gn, the clock signals CK1 to CKN deviate from the standard (ideal) clock signals, and thus the scan signals cannot be accurately output, and the image cannot be accurately displayed.

Specifically, please refer to fig. 7, which is a schematic circuit diagram of the level shifter circuit 100 shown in fig. 5, and as shown in fig. 7, the level shifter circuit 100 includes a control unit 101, an adjusting unit 102, a clock signal output unit 103, a comparing unit 104, and a temperature detecting unit 105.

The control unit 101 receives the trigger enable signal STV and the initial clock signal CK0, starts operation under the trigger of the trigger enable signal STV, and outputs the clock adjustment signal CKc according to the initial clock signal CK 0.

The adjusting unit 102 is connected to the control unit 101 and the clock signal output unit 103, and is configured to control a speed at which the clock signal output unit 103 outputs a clock signal according to the clock adjusting signal CKc. In this embodiment, the adjusting unit 102 outputs a speed adjusting control signal CH to the clock signal output unit 103 according to the clock adjusting signal CKc, where the speed adjusting control signal CH controls the speed at which the clock signal output unit 103 outputs the clock signal CK.

In this embodiment, the clock adjustment signal CKc may be a pulse width modulation signal (PWM signal) having different duty cycles. In other embodiments of the present application, the clock adjustment signal CKc may be a voltage signal with different voltage values or a current signal with different current values, which is not limited to this example.

The clock signal output unit 103 is connected to the adjustment unit 102, the power management circuit 300, and the scan driving circuit 13. The clock signal output unit 103 receives the initial voltage signal from the power management circuit 300 and outputs the clock signal CK to the scan driving circuit 13 at a predetermined speed under the control of the speed regulation control signal CH. In this embodiment, the clock signal output unit 103 outputs a pulse width signal composed of a first voltage and a second voltage alternately according to a preset speed under the control of the speed regulation control signal CH and the initial clock signal CK0 output by the adjustment unit 102, and it is understood that the first voltage and the second voltage compose two different high potentials of the pulse width signal, and the pulse width signal may have a preset frequency and a duty ratio, but different phases, and the pulse width signal is the clock signal CK.

In this embodiment, the clock signal output unit 103 includes a first conductive terminal VGH and a second conductive terminal VGL, and a clock signal output terminal CKout, where the first conductive terminal VGH is configured to output a first voltage, the second conductive terminal VGL outputs a second voltage, and the clock signal output unit 103 alternately selects the first conductive terminal VGH and the second conductive terminal VGL to connect the clock signal output terminal CKout according to the timing control signal CH received by the self-adjusting unit 102, so that the first voltage and the second voltage are alternately output from the clock signal output terminal CKout and form the clock signal CK. Wherein, the speed regulation control signal CH is used for regulating the speed of the clock signal output unit 103 outputting the clock signal CK.

It is understood that the clock signal CK may be plural, for example, N clock signals CK 1-CKN. Thus, the corresponding control unit 101, the adjusting unit 102, the clock signal output unit 103, and the comparing unit 104 may be plural, that is, one clock signal output unit 103 outputs one clock signal CK, and the control unit 101, the adjusting unit 102, and the comparing unit 104 may be plural to cooperate with the same. The clock signals CK1 to CKN have a certain phase difference, and the phase difference may be the same, for example, 60 degrees, 90 degrees, or the like. In this embodiment, the pulse width signal is transmitted to the scan driving circuit 13 through the clock signal output terminal CKo between the clock signal output unit 103 and the scan driving circuit 13.

The comparing unit 104 is connected to the control unit 101 and the clock signal output unit 103, and is configured to detect the pulse width signal output by the clock signal output unit 103 to obtain a detection signal TH, compare the detection signal TH with a reference clock signal RF to obtain a first comparison result TC, and transmit the first comparison result TC to the control unit 101, where the control unit 101 outputs different clock adjustment signals CKc according to the first comparison result TC, so as to adjust the speed at which the clock signal output unit 103 outputs the clock signal CK, more specifically, adjust the rising speed of the pulse width signal as the clock signals CK1 to CKN from low potential to high potential or the falling speed of the high potential to low potential.

Please refer to fig. 8, which is a schematic diagram of waveforms of the detection signal and the reference clock signal RF corresponding to the clock signal before adjustment in the present embodiment, as shown in fig. 8, the reference clock signal RF in the present embodiment is a standard clock signal, and the detection signal TH is a signal corresponding to the clock signal output by the clock signal output unit 103. In fig. 8, the voltage difference Δv between the detection signal TH and the reference clock signal RF is greater than 0 corresponding to the same time t1, in other words, it is explained that the voltage of the clock signal CK actually output by the clock signal output unit 103 is smaller than the standard clock signal or the ideal clock signal in the reference clock signal RF at the same time t1, or that the voltage of the clock signal CK actually output by the clock signal output unit 103 needs to be reached at a time t2 later than the time Δt of t1 for the same voltage value.

Fig. 9 is a schematic diagram of waveforms of the detection signal and the reference clock signal of the adjusted corresponding clock signal in the present embodiment, as shown in fig. 9, the control unit 101 outputs different clock adjustment signals CKc according to the first comparison result TC, and the difference Δv between the clock signal and the reference clock signal is within a threshold range through adjustment of the adjustment unit 102. In this embodiment, the adjusted clock signal is substantially the same as the reference clock signal, that is, the difference Δv between the clock signal and the reference clock signal is close to 0.

The temperature detecting unit 105 is configured to detect a temperature of the level shifter 100, output a temperature adjustment signal TT to the control unit 101 according to the detected temperature, and the control unit 101 outputs clock adjustment signals CKc with different voltages according to the temperature adjustment signal TT, and may correspondingly adjust a rising speed or a falling speed of the pulse width signals as the clock signals CK1 to CKN.

More specifically, referring to fig. 7, the control unit 101 is a logic array integrated circuit formed by logic devices, and is configured to start operating under the triggering of the trigger enable signal STV, and output the clock adjustment signal CKc according to the initial clock signal CK 0. Of course, it is understood that the control unit 101 may also receive other clock signals having a phase difference with the initial clock signal CK0, and the control unit 101 may output a corresponding clock adjustment signal CKc corresponding to each clock signal. The number of clock signals specifically received by the control unit 101 can be set according to actual requirements, which is not limited to this example.

The adjusting unit 102 includes a power unit SC, a first switching output unit ST1, and a second switching output unit ST2.

The power unit SC is connected to the control unit 101 and receives a clock adjustment signal CKc for outputting currents of different power levels under the control of the clock adjustment signal CKc. In this embodiment, the power unit SC includes a power control end SC0, a first power output end SC1 and a second power output end SC2, the power control end SC0 is connected to the control unit 101 and receives a clock adjustment signal CKc, and the power unit SC outputs currents with different power levels from the first power output end SC1 and the second power output end SC2 under the control of the clock adjustment signal CKc, which can be understood that the first power output end SC1 and the second power output end SC2 output currents with different power levels as the speed regulation control signal CH.

The first switch output unit ST1 and the second switch output unit ST2 are respectively connected to the first power output end SC1 and the second power output end SC2, in this embodiment, the first switch output unit ST1 is connected to the first power output end SC1, and the second switch output unit ST2 is connected to the second power output end SC2. The first switch output unit ST1 is configured to transmit the speed regulation control signal CH output by the first power output terminal SC1 to the clock signal output unit 103 under the control of the initial clock signal CK0 in a first preset period, and similarly, the second switch output unit ST2 is configured to transmit the speed regulation control signal CH output by the second power output terminal SC2 to the clock signal output unit 103 under the control of the initial clock signal CK0 in a second preset period.

It should be noted that the first preset period and the second preset period respectively correspond to the duration periods of two different potentials in the initial clock signal CK0, for example, the first preset period may be a period in which the initial clock signal CK0 is at a high potential, and the second preset period may be a period in which the initial clock signal CK0 is at a low potential.

Specifically, in the present embodiment, the power unit SC includes a current source 1020, the first switching output unit ST1 includes at least one first switch 1021, and the second switching output unit ST2 includes at least one second switch 1022 and a first switching tube 1023.

The current source 1020 is connected to the control unit 101 and receives the clock adjustment signal CKc, and is configured to output currents with different power levels under the control of the clock adjustment signal CKc. In this embodiment, the current source 1020 receives the clock adjustment signal CKc outputted from the control unit 101 from the power control terminal SC0, and the current source 1020 outputs currents with different power levels from the first power output terminal SC1 and the second power output terminal SC2 as the speed regulation control signal CH under the control of the clock adjustment signal CKc.

The first switch 1021 is connected to the first power output end SC1 of the current source 1020 and the clock signal output unit 103, the first switch 1021 receives the initial clock signal CK0 and is in an on state or an off state under the control of the initial clock signal CK0, when the first switch 1021 is in the on state, the first power output end SC1 of the current source 1020 is electrically connected to the clock signal output unit 103, and the magnitude of the current output by the first power output end SC1 is used for controlling the speed of the clock signal output unit 103 to output the clock signal, wherein the magnitude of the current output by the first power output end SC1 is in positive correlation with the speed of the clock signal output unit 103, that is, the greater the current output by the first power output end SC1, the faster the speed of the clock signal output unit 103 to output the clock signal. In this embodiment, the current signal output by the first power output end SC1 is used as the speed regulation control signal CH.

In this embodiment, the first switch 1021 includes a first switch control terminal K10, a first switch conductive terminal K11, and a second switch conductive terminal K12. The first switch control terminal K10 receives the initial clock signal CK0, the first switch conductive terminal K11 is connected to the first power output terminal SC1, and the second switch conductive terminal K12 is connected to the clock signal output unit 103. The first switch 1021 may be a switching element such as a transistor, or the like, and the first switch 1021 is an N-type switch, that is, the first switch 1021 is turned on or in an on state when receiving a high potential (high level), and is turned off or in an off state when receiving a low potential (low level).

The first switch 1023 is connected to the second switch 1022 and the power terminal VDD, and is configured to selectively electrically connect the power terminal VDD to the second switch 1022 under the control of the initial clock signal CK0, so that the power signal provided by the power terminal VDD is transmitted to the second switch 1022.

In this embodiment, the first switching tube 1023 includes a first conductive control terminal M10, a first conductive terminal M11 and a second conductive terminal M12. The first conductive control terminal M10 receives the initial clock signal CK0, and the first switching tube 1023 is in an on state or an off state under the control of the initial clock signal CK 0. The first conductive terminal M11 is connected to the power supply terminal VDD, and the second conductive terminal M12 is connected to the second switch 1022.

When the first switch tube 1023 is turned on or is in a conductive state, the first conductive terminal M11 and the second conductive terminal M12 are electrically conductive, and the power signal provided by the power terminal VDD is transmitted to the second conductive terminal M12 through the first conductive terminal M11 of the first switch tube 1023. Conversely, when the first switch tube 1023 is turned off or is in the off state, the first conductive terminal M11 is electrically disconnected from the second conductive terminal M12, and the power signal provided by the power terminal VDD stops being transmitted to the second conductive terminal M12 through the first conductive terminal M11 of the first switch tube 1023.

In this embodiment, the first switching transistor 1023 is a P-type transistor, that is, the first switching transistor 1023 is turned on or turned on when receiving a low potential, and turned off or turned off when receiving a high potential. Of course, in other embodiments of the present application, the first switch 1023 is an N-type transistor, and the control manner is opposite to that of a P-type transistor.

In the present embodiment, the first conductive terminal M11 is connected to the power supply terminal VDD, and is configured corresponding to the characteristics of the second switch 1022 and the second switch 1024, that is, the power supply voltage provided by the power supply terminal VDD is used as the on voltage or the start voltage for controlling the first switch 1023 to be turned on, and the power supply terminal VDD is used as the start voltage terminal. When the second switch 1022 and the second switch tube 1024 are of different types, the first conductive terminal M11 may also be connected to the ground terminal GND.

The second switch 1022 is connected to the second power output SC2 of the current source 1020, the first switching tube 1023, and the clock signal output unit 103. The second switch 1022 is configured to be in an on state or an off state under the control of the power signal provided by the first switching transistor 1023, so as to selectively transmit the second power output terminal SC2 to the clock signal output unit 103, thereby controlling the speed at which the clock signal output unit 103 outputs the clock signal.

In this embodiment, the second switch 1022 includes a second switch control terminal K20, a third switch conductive terminal K23, and a fourth switch Guan Daodian terminal K24. The second switch control terminal K20 is connected to the second conductive terminal M12 of the first switch tube 1023, receives the power signal from the first switch tube 1023 as the start voltage of the second switch 1022, the third switch conductive terminal K23 is connected to the second power output terminal SC2 of the current source 1020, and the fourth switch Guan Daodian terminal K24 is connected to the clock signal output unit 103. In this embodiment, the second switch 1022 may be a switching element such as a transistor or a transistor, and the first switch 1021 is an N-type switch, that is, the first switch 1021 is turned on or in an on state when receiving a high potential as a start voltage, and is turned off or in an off state when receiving a low potential (an off voltage).

When the second switch 1022 is in the on state, the third switch conductive terminal K23 and the fourth switch Guan Daodian terminal K24 are electrically conductive, the second power output terminal SC2 of the current source 1020 is electrically conductive to the clock signal output unit 103, and the current output by the second power output terminal SC2 of the current source 1020 is transmitted to the clock signal output unit 103. Conversely, when the second switch 1022 is turned off or is in the off state, the third switch conductive terminal K23 is electrically disconnected from the fourth switch Guan Daodian terminal K24, the second power output terminal SC2 of the current source 1020 is electrically disconnected from the clock signal output unit 103, and the current output from the second power output terminal SC2 of the current source 1020 stops being transmitted to the clock signal output unit 103.

In this embodiment, the magnitude of the current output by the second power output terminal SC2 is used to control the speed of the clock signal output unit 103 outputting the clock signal, where the magnitude of the current output by the second power output terminal SC2 is positively correlated with the speed of the clock signal output unit 103 outputting the clock signal, that is, the greater the current output by the second power output terminal SC2, the faster the speed of the clock signal output unit 103 outputting the clock signal. In this embodiment, the current signal output by the second power output end SC2 is used as the speed regulation control signal CH. It will be appreciated that the first power output SC1 and the second power output SC2 output currents of the same magnitude.

The clock signal output unit 103 includes a first voltage output subunit 1031 and a second voltage output subunit 1032. The first voltage output subunit 1031 is connected to the first switch 1021 and the first voltage terminal VGH of the adjusting unit 102, and is configured to receive the speed regulation control signal CH from the first switch 1021, and transmit the first voltage provided by the first voltage terminal VGH to the clock signal output terminal CKout according to the speed regulation control signal CH at a corresponding speed. Similarly, the second voltage output subunit 1032 is connected to the second switch 1022 and the second voltage terminal VGL of the adjusting unit 102, and is configured to receive the speed regulation control signal CH from the second switch 1022, and transmit the second voltage provided by the second voltage terminal VGL to the clock signal output terminal CKout according to the speed regulation control signal CH at a corresponding speed.

It can be understood that the first voltage provided by the first voltage terminal VGH and the second voltage provided by the second voltage terminal VGL form the clock signal CLK output from the clock signal output terminal CKout. In this embodiment, the first voltage is high, and the second voltage is low.

Specifically, the first voltage output subunit 1031 includes a first output switching tube S1, where the first output switching tube S1 includes a first output control terminal S10, a first output conductive terminal S11, and a second output conductive terminal S12. In this embodiment, the first output control terminal S10 is electrically connected to the second switch conductive terminal K12 of the first switch 1021, and is configured to receive the speed regulation control signal CH from the first switch 1021. The first output conductive terminal S11 is connected to the first conductive terminal VGH, and the second output conductive terminal S12 is connected to the clock signal output terminal CKout.

The first output switch tube S1 is in an on state or an off state under the control of the speed regulation control signal CH received by the first output control end S10, and when the first output switch tube S1 is on or in an on state, the first output conductive end S11 and the second output conductive end S12 are electrically conductive, and the first voltage output by the first conductive end VGH is transmitted to the clock signal output end CKout through the first output conductive end S11 and the second output conductive end S12.

It can be understood that the speed adjusting control signal CH may control the conducting speed of the first output switching tube S1, that is, the magnitude of the current serving as the speed adjusting control signal CH may control the conducting speed of the first output switching tube S1, for example, the larger the current serving as the speed adjusting control signal CH, the faster the conducting speed of the first output switching tube S1, and the faster the corresponding speed of outputting the first voltage; conversely, the smaller the current of the speed regulation control signal CH, the slower the speed at which the first output switching tube S1 is turned on, and the slower the corresponding speed at which the first voltage is output.

In this embodiment, the first output switch S1 is a P-type transistor, that is, the first output switch S1 is turned on or turned on when receiving a low potential, and turned off or turned off when receiving a high potential. Of course, in other embodiments of the present application, the first output switch S1 is an N-type transistor, and the control manner is opposite to that of the P-type transistor.

The second voltage output sub-unit 1032 includes a second output switching transistor S2 and a third output switching transistor S3.

The second output switching tube S2 includes a second output control terminal S20, a third output conductive terminal S23, and a fourth output conductive terminal S24. In this embodiment, the second output control terminal S20 is electrically connected to the fourth switch Guan Daodian terminal K24 of the second switch 1022, and is configured to receive the speed regulation control signal CH from the second switch 1022. The third output conductive terminal S23 is connected to the first voltage terminal VGH, and the fourth output conductive terminal S24 is connected to the third output switching tube S3.

The second output switching tube S2 is turned on under the control of the speed regulation control signal CH according to a corresponding speed, that is, the speed regulation control signal CH can control the speed at which the second output switching tube S2 is turned on, in other words, the magnitude of the current serving as the speed regulation control signal CH can control the speed at which the second output switching tube S2 is turned on. For example, the larger the current as the speed regulation control signal CH, the faster the second output switching tube S2 is turned on, and the faster the corresponding first voltage is output; conversely, the smaller the current of the speed regulation control signal CH, the slower the speed at which the second output switching tube S2 is turned on, and the slower the corresponding speed at which the first voltage is output.

The third output switching tube S3 includes a third output control terminal S30, a fifth output conductive terminal S35, and a sixth output conductive terminal S36. In this embodiment, the third output control terminal S30 is electrically connected to the fourth output conductive terminal S24 of the second output switching tube S2, and is configured to receive the speed regulation control signal CH from the second output switching tube S2. The fifth output conductive terminal S35 is connected to the second conductive terminal VGL, and the sixth output conductive terminal S36 is connected to the clock signal output terminal CKout.

The third output switch tube S3 is in a conducting state under the control of the second voltage received by the third output control end S30, when the third output switch tube S3 is conducting or in a conducting state, the fifth output conductive end S35 and the sixth output conductive end S36 are electrically conducting, and the second voltage provided by the second conductive end VGL is transmitted to the clock signal output end CKout through the fifth output conductive end S35 and the sixth output conductive end S36, so as to be used for forming or generating a clock signal.

In this embodiment, the second output switch S2 is a P-type transistor, that is, the second output switch S2 is turned on or turned on when receiving a low potential, and turned off or turned off when receiving a high potential. Of course, in other embodiments of the present application, the second output switch S2 is an N-type transistor, and the control manner is opposite to that of the P-type transistor.

In this embodiment, the third output switch S3 is an N-type transistor, that is, the third output switch S3 is turned on or turned on when receiving a high potential, and turned off or turned off when receiving a low potential. Of course, in other embodiments of the present application, the third output switch S3 may be a P-type transistor, and the control manner is opposite to that of the N-type transistor.

Referring to fig. 7 and 10 together, fig. 10 is a schematic diagram illustrating the adjustment of the clock signal CK by the adjustment unit 102 shown in fig. 7, wherein the operation of the level shifter circuit 100 for adjusting the clock signal is specifically described with reference to fig. 7 and 10.

After the display device 1 and the display panel 10 are powered on, the level shifter circuit 100 receives the trigger enable signal STV and the initial clock signal CK0 from the timing control circuit 11, and also receives the first initial high potential VGH0 and the first initial low potential VGL0 from the power management circuit 300.

The control unit 101 starts operating under the trigger of the trigger enable signal STV, and outputs the clock adjustment signal CKc according to the initial clock signal CK 0.

The clock adjustment signal CKc controls the current source 1020 in the adjustment unit 102 to start working, and correspondingly outputs the speed adjusting control signal CH to the clock signal output unit 103 according to the clock adjustment signal CKc. Specifically, when the power control terminal SC0 receives the clock adjustment signal CKc, the current source 1020 outputs the timing control signals CH with different current levels according to the clock adjustment signal CKc.

Meanwhile, the first switch 1021 is turned on under the high-potential control of the initial clock signal CK0, so that the speed regulating control signal CH is transmitted to the first output switch tube S1 in the first voltage output subunit 1031 through the first power output end SC1, the speed regulating control signal CH is transmitted to the first output control end S10 of the first output switch tube S1, and the magnitude of the speed regulating control signal CH can influence the on speed of the first output switch tube S1. That is, the larger the speed control signal CH is, the faster the first output switching tube S1 is turned on, and the smaller the speed control signal CH is, the slower the first output switching tube S1 is turned on. The first output switch S1 is turned on under the low-potential control of the speed regulation control signal CH, so that the first conductive terminal VGH outputs the first voltage to the clock signal output terminal CKout as the first voltage of the clock signal CK.

Similarly, the initial clock signal CK0 outputs a low potential after the high potential reaches a preset time, the first switch tube 1023 is turned on under the control of the low potential in the initial clock signal CK0 to control the second switch 1022 to be turned on, and the speed regulating control signal CH is transmitted to the second output switch tube S2 in the second voltage output subunit 1032 through the second power output end SC2, the speed regulating control signal CH is transmitted to the second output control end S20 of the second output switch tube S2, and the magnitude of the speed regulating control signal CH can influence the on speed of the second output switch tube S2. That is, the larger the speed regulating control signal CH, the faster the second output switching tube S2 is turned on, and the smaller the speed regulating control signal CH, the slower the second output switching tube S2 is turned on.

The second output switch tube S2 is turned on under the low potential control of the speed regulation control signal CH, so that the first conductive end VGH outputs a first voltage to the third output control end S30 of the third output switch tube S3, the third output switch tube S3 is turned on under the control of the first voltage, and the second conductive end VGL is transmitted to the clock signal output end CKout through the third output switch tube S3 and is used as a second voltage of the clock signal CK, so that the clock signal K completes one clock cycle output corresponding to one pulse cycle of the initial clock signal CK 0.

It will be appreciated that the pulse width signals of the other periods of the clock signal K also correspond to complete outputs.

In the output process of the clock signal K, the comparing unit 104 obtains the detection signal TH from the clock signal output terminal CKout, compares the detection signal TH with the reference clock signal RF to obtain the first comparison result TC, and transmits the first comparison result TC to the control unit 101, where the control unit 101 outputs different clock adjustment signals CKc to the current source 1020 corresponding to the first comparison result TC according to the adjustment manner shown in fig. 10 and table 1, and the current source 1020 correspondingly outputs the speed regulation control signals CH with different current values to the first output switching tube S1, so as to control the first voltage terminal VGH to output the first voltage according to the corresponding speed, that is, to adjust the time for the clock signal CK to rise from the low potential to the high potential.

TABLE 1

For example, the detection signal TH is compared with the reference clock signal RF to obtain a first comparison result TC of 0.1 volt (V), and the timing control signal CH with a current value of 1mn (milliamp) is correspondingly output to the first output switch tube S1, so that the time required for the clock signal CK01 to rise from the low potential to the high potential is 0.05 microseconds (μs).

The detection signal TH is compared with the reference clock signal RF to obtain a first comparison result TC of 0.2 volt (V), and the timing control signal CH with a current value of 2mn (milliamp) is correspondingly output to the first output switch tube S1, so that the time required for the clock signal CK02 to rise from the low potential to the high potential is 0.045 microseconds (μs).

The detection signal TH is compared with the reference clock signal RF to obtain a first comparison result TC of 0.4 volt (V), and the timing control signal CH with a current value of 4mn (milliamp) is correspondingly output to the first output switch tube S1, so that the time required for the clock signal CK03 to rise from the low potential to the high potential is 0.035 microseconds (μs).

In this embodiment, when the clock signal CK actually output by the clock signal output terminal CKout is affected due to the load variation, and the corresponding detection signal TH and the reference clock signal RF have a difference, that is, what kind of scanning signal is output by the scanning driving circuit 13 as a load connected to the scanning signal in the display panel 10, or what kind of scanning signal as a load is light and heavy, the level conversion circuit 100 can timely adjust the clock signal CK, the control unit 101 can adjust and change the waveform of the adjusting clock signal CK by adjusting the current output by the current source 1020, and adjust the difference between the adjusting clock signal CK and the reference clock signal RF as much as possible, so that the difference between the adjusting clock signal and the reference clock signal RF is within the preset range, thereby ensuring that the clock signal CK is accurately output, and simultaneously enabling the scanning signal to meet the image display requirement of the sub-pixel P, so that the image display effect is better.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims

1. The level conversion circuit is used for receiving an initial clock signal and correspondingly outputting an adjusted clock signal, and is characterized by comprising a control unit, an adjusting unit and a clock signal output unit, wherein the control unit is used for receiving the initial clock signal and correspondingly outputting the clock adjusting signal, the adjusting unit is connected with the control unit and outputs a speed regulation control signal to the clock signal output unit according to the clock adjusting signal, the clock signal output unit is connected with the adjusting unit, a first conducting end and a second conducting end, the first conducting end is used for providing a first voltage, the second conducting end is used for providing a second voltage, the first conducting end and the second conducting end are alternately selected according to the speed regulation control signal received from the adjusting unit and are connected with the clock signal output end, the first voltage and the second voltage form a clock signal, and the speed regulation control signal is used for adjusting the speed of the clock signal output unit to output the clock signal.

2. The level shift circuit of claim 1, wherein the adjustment unit comprises a power unit, a first switch output unit, and a second switch output unit;

The power unit is connected with the control unit and outputs the speed regulation control signals with different powers according to the clock regulation signals; the first switch output unit is connected with the power unit and the clock signal output unit, and transmits the speed regulation control signal to the clock signal output unit under the control of a first potential of the initial clock signal; the second switch output unit is connected with the power unit and the clock signal output unit, receives the initial clock signal and transmits the speed regulation control signal to the clock signal output unit under the control of a second potential of the initial clock signal;

the initial clock signal is a plurality of periodic pulse width signals, and the pulse width signal in each period comprises the first potential and the second potential.

3. The level shifter circuit of claim 2, wherein the power unit includes a power control terminal, a first power output terminal, and a second power output terminal, the power control terminal being coupled to the control unit and receiving the clock adjustment signal, the power unit outputting the clock adjustment signal from the first power output terminal and the second power output terminal under control of the clock adjustment signal.

4. The level shifter circuit of claim 3, wherein,

The power unit comprises a current source, wherein the current source is used for outputting different currents from the first power output end and the second power output end as the clock adjustment signal according to the clock adjustment signal;

the first switch output unit comprises a first switch which is conducted under the control of a first potential of the initial clock signal, and the clock adjustment signal is transmitted from the first switch to the clock signal output unit;

The second switch output unit comprises a second switch and a first switch tube, the first switch tube is conducted under the control of a second potential of the initial clock signal, the starting voltage output by the starting voltage end is transmitted to the second switch and is controlled to be conducted, and the clock adjustment signal is transmitted to the clock signal output unit through the second switch.

5. The level shifter circuit according to any one of claims 3 to 4, wherein the clock signal output unit includes a first voltage output subunit and a second voltage output subunit,

The first voltage output subunit is connected with the adjusting unit and the first voltage end, and is used for receiving the speed regulation control signal from the adjusting unit and transmitting the first voltage provided by the first voltage end to the clock signal output end according to the speed regulation control signal at a corresponding speed;

The second voltage output subunit is connected with the adjusting unit and the second voltage end and is used for receiving the speed regulation control signal from the speed searching adjusting unit, transmitting the second voltage provided by the second voltage end to the clock signal output end according to the speed regulation control signal and the corresponding speed, and the first voltage and the second voltage form a pulse width signal of the clock signal in one period.

6. The level shifter circuit of claim 5, wherein the logic circuit,

The first voltage output subunit comprises a first output switch tube, wherein the first output switch tube comprises a first output control end, a first output conductive end and a second output conductive end, the first output control end is electrically connected with the adjusting unit and receives a speed regulation control signal, the first output conductive end is connected with the first conductive end, the second output conductive end is connected with the clock signal output end, the first output switch is in a conducting state according to the corresponding speed under the control of the speed regulation control signal, and the first voltage output by the first conductive end is transmitted to the clock signal output end through the first output conductive end and the second output conductive end.

7. The level shifter circuit of claim 5, wherein the second voltage output subunit comprises a second output switch tube and a third output switch tube,

The second output switch tube comprises a second output control end, a third output conductive end and a fourth output conductive end, the second output control end is electrically connected with the adjusting unit and receives the speed regulation control signal, the third output conductive end is connected with the first voltage end, and the fourth output conductive end is connected with the third output switch tube;

the third output switch tube comprises a third output control end, a fifth output conductive end and a sixth output conductive end, wherein the third output control end is electrically connected with the fourth output conductive end and is used for receiving the speed regulation control signal from the second output switch tube, the fifth output conductive end is connected with the second conductive end, and the sixth output conductive end is connected with the clock signal output end;

the second output switch is in a conducting state according to the corresponding speed under the control of the speed regulation control signal, the first voltage output by the first conducting end is transmitted to the third output switch tube through the third output conducting end and the fourth output conducting end, the first voltage correspondingly controls the third output switch tube to be conducted, and the second voltage output by the second conducting end is transmitted to the clock signal output end through the second output switch tube.

8. The level shift circuit according to any one of claims 1 to 7, further comprising a comparing unit connected to the control unit and the clock signal output unit, for detecting the clock signal output by the clock signal output unit and obtaining a detection signal, and comparing the detection signal with a reference clock signal to obtain a first comparison result, and transmitting the first comparison result to the control unit, wherein the control unit outputs different clock adjustment signals according to the first comparison result to adjust a speed at which the clock signal output unit outputs the clock signal.

9. The level shift circuit according to any one of claims 1 to 7, further comprising a temperature detection unit connected to the control unit, the temperature detection unit being configured to detect a temperature of the level shift circuit and output a temperature adjustment signal to the control unit according to the detected temperature, the control unit outputting different clock adjustment signals according to the temperature adjustment signal to adjust a speed at which the clock signal is output as the clock signal output unit.

10. A display device, comprising a display panel and the level conversion circuit according to any one of claims 1 to 9, wherein the display area of the display panel comprises a plurality of sub-pixels arranged in a matrix, and further comprises a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction, the first direction is perpendicular to the second direction, the sub-pixels are located at the crossing positions of the scan lines and the data lines, the display panel comprises a data driving circuit, a scan driving circuit, and a timing control circuit, the timing control circuit is configured to output an initial clock signal to the level conversion circuit, the level conversion circuit outputs a scan signal to the scan driving circuit according to the initial clock signal, the timing control circuit further outputs the data signal to the data driving circuit, and the scan signal is configured to control the sub-pixels to receive the data signal from the data driving circuit to perform image display.