CN118116429A - Word line control circuit and magnetic random access memory - Google Patents

Abstract

A word line control circuit and a magnetic random access memory are provided. The word line control circuit includes: the control circuit is suitable for receiving the read-write enabling signal and the row decoding signal and generating a first boost control signal and a second boost control signal with opposite logic; and the boosting circuit is suitable for adjusting the voltages of the first output end and the second output end based on the first boosting control signal and the second boosting control signal when different operations are performed. And a voltage selection circuit adapted to apply a write voltage to a corresponding word line when performing a write operation, and to disconnect a path connected to the second output terminal under control of the second output terminal voltage; when a read operation is performed, a read voltage is applied to the corresponding word line, and a path connected to the first output terminal is disconnected under the control of the first output terminal voltage. By adopting the scheme, the influence on normal data writing can be avoided, and the power consumption of reading operation can be reduced.

Description

Word line control circuit and magnetic random access memory

Technical Field

The invention relates to the technical field of memories, in particular to a word line control circuit and a magnetic random access memory.

Background

The nonvolatile magnetic random access memory (MAGNETIC RAM, MRAM) is regarded as one of the most promising next-generation memories as a novel nonvolatile memory, which has the advantages of low power consumption, high reliability, sustainable miniaturization, compatibility with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) processes, and the like, and combines the high-speed read-write capability of the static random access memory (Static Random Access Memory, SRAM) with the high integration of the dynamic random access memory (Dynamic Random Access Memory, DRAM).

In practical applications, the write current of MRAM is large and the read current is small, so the word line control circuit of MRAM needs to be able to output a dual-voltage waveform, providing different operating voltages during read/write operations.

However, in the word line control circuit of the conventional MRAM, the word line voltage cannot reach the required high voltage during the writing operation, so that the normal writing of data is affected, and the waste of power consumption is caused during the reading operation.

Disclosure of Invention

The invention aims to solve the problems that: how to avoid influencing the normal writing of data and reduce the power consumption of reading operation.

To solve the above problems, an embodiment of the present invention provides a word line control circuit including:

The control circuit is suitable for receiving the read-write enabling signal and the row decoding signal and generating a first boost control signal and a second boost control signal with opposite logic;

The boost circuit is connected with the control circuit and provided with a first output end and a second output end; the boost circuit is suitable for adjusting the voltages of the first output end and the second output end based on the first boost control signal and the second boost control signal when different operations are performed;

and a voltage selection circuit connected to the control circuit and the boost circuit, adapted to apply a write voltage to a corresponding word line when performing a write operation, and to disconnect a path connected to the second output terminal under control of the second output terminal voltage; when a read operation is performed, a read voltage is applied to the corresponding word line, and a path connected to the first output terminal is disconnected under the control of the first output terminal voltage.

Optionally, the voltage boosting circuit is adapted to set the voltage of the first output terminal to a low level under the control of the first voltage boosting control signal and the second voltage boosting control signal when performing a write operation, and raise the voltage of the first output terminal to a write voltage and set the voltage of the second output terminal to a low level when performing a read operation or not performing a read operation.

Optionally, the boost circuit includes:

The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube and the second NMOS tube;

The first PMOS tube, the third PMOS tube and the first NMOS tube are connected in series, and the second PMOS tube, the fourth PMOS tube and the second NMOS tube are connected in series; the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the writing voltage output end; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the second boost control signal; the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube are connected with the first boost control signal; the grid electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube and is used as the first output end; and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube and is used as the second output end.

Optionally, the voltage selection circuit includes:

A first voltage selection sub-circuit, one end of which is connected with the second output end, and the other end of which is connected with the word line, and is suitable for applying the read voltage to the corresponding word line when the read operation is performed, and disconnecting a passage connected to the first output end under the control of the voltage of the first output end;

A second voltage selection sub-circuit, one end of which is connected with the first output end and the other end of which is connected with the word line, and which is suitable for applying the writing voltage to the corresponding word line when writing operation is performed, and disconnecting the passage connected to the second output end under the control of the voltage of the second output end;

And the word line closing sub-circuit is connected with the first voltage selecting sub-circuit and the second voltage selecting sub-circuit and is suitable for closing the word line.

Optionally, the first voltage selection sub-circuit includes: a fifth PMOS tube and a sixth PMOS tube connected in series; the source electrode of the fifth PMOS tube and the read voltage output end; the grid electrode of the fifth PMOS tube is connected with the inverted signal of the row decoding signal; and the grid electrode of the sixth PMOS tube is connected with the second output end.

Optionally, the second voltage selection sub-circuit includes: and the grid electrode of the seventh PMOS tube is connected with the first output end, the source electrode of the seventh PMOS tube is connected with the writing voltage output end, and the drain electrode of the seventh PMOS tube is connected with the word line.

Optionally, the word line closing circuit includes: the third NMOS tube and the fourth NMOS tube are connected in series; the grid electrode of the third NMOS tube is connected with a second boost control signal, and the grid electrode of the fourth NMOS tube is connected with an inverted signal of the row decoding signal; and the source electrode of the fourth NMOS tube is grounded.

Optionally, the control circuit includes: the first AND gate circuit, the first inverter and the second inverter;

The input end of the first AND gate circuit is connected with the read-write enabling signal and the row decoding signal; the output end of the first AND gate circuit generates the first boost control signal; the output end of the first AND gate circuit is connected with the input end of the first inverter, and the output end of the first inverter generates the second boost control signal; the input end of the second inverter is connected with the row decoding signal, and the output end of the second inverter is connected with the voltage selection circuit.

Optionally, the control circuit is further adapted to receive a read drive control signal, and generate the voltage selection circuit control signal based on the read drive control signal, a read/write enable signal, and a row decode signal, so as to close the word line after reading out the data.

Optionally, the control circuit includes: the first and circuit, the second and circuit, the first inverter, the second inverter and the third inverter;

The input end of the third inverter is connected with the read drive control signal; the input end of the second AND gate circuit is connected with the row decoding signal and the output signal of the third inverter; the input end of the first AND gate circuit is connected with the read-write enabling signal and the output signal of the second AND gate circuit; the output end of the first AND gate circuit generates the first boost control signal; the output end of the first AND gate circuit is connected with the input end of the first inverter, and the output end of the first inverter generates the second boost control signal; the input end of the second inverter is connected with the output signal of the second AND gate circuit, and the output end of the second inverter is connected with the voltage selection circuit.

The embodiment of the invention also provides a magnetic random access memory, which comprises any one of the word line control circuits.

Optionally, the magnetic random access memory further includes:

The clock control circuit is suitable for being connected with a clock signal and the read-write enabling signal and generating a read drive pre-charge signal and a read drive control signal;

the read driving circuit is connected with the clock control circuit and is suitable for executing read operation under the control of the read driving pre-charge signal and the read driving control signal;

the precharge circuit is connected with the read driving circuit and is suitable for precharging the bit line and the source line;

A write driving circuit connected to the precharge circuit and adapted to control voltages of the bit line and the source line to perform a write operation;

A row decoder connected to the word line control circuit and adapted to generate a row decoding signal;

the storage array is connected with the word line control circuit;

the word line control circuit is connected with the row decoder and the clock control circuit and is suitable for controlling the word line voltage based on the read-write enabling signal, the row decoding signal and the read driving control signal so as to meet the operation requirement.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

By applying the scheme of the invention, the voltage of the first output end and the second output end of the voltage boosting circuit can be regulated when different operations are carried out, the voltage selection circuit can apply the writing voltage to the corresponding word line when writing operations are carried out, and under the control of the voltage of the second output end, the passage connected to the second output end is disconnected, so that the numerical value of the writing voltage on the word line can be prevented from being influenced because the passage connected with the second output end of the voltage boosting circuit is not completely disconnected, and the normal writing of data is further prevented from being influenced. The voltage selection circuit can also apply the read voltage to the corresponding word line when performing the read operation, and under the control of the voltage of the first output end, the channel connected to the first output end is disconnected, so that the waste of power consumption caused by incomplete disconnection of the channel connected between the voltage selection circuit and the first output end of the booster circuit can be avoided.

Drawings

FIG. 1 is a schematic diagram of a prior art row decoder driver;

FIG. 2 is a schematic diagram of a word line control circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a word line control circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another word line control circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a MRAM in accordance with an embodiment of the present invention;

fig. 6 is a schematic diagram of a sense amplifier.

Detailed Description

Spin-Transfer Torque magnetic memory (Spin-Transfer Torque MAGNETIC RAM, STT-MRAM) is a new type of MRAM that enables information writing by Spin current. Taking STT-MRAM as an example, the memory cell of STT-MRAM is typically composed of one access transistor (1T) and 1 magnetic tunnel junction (1 MTJ). In STT-MRAM writing operation, current in different directions is applied to a Magnetic Tunnel Junction (MTJ) according to different requirements of writing data, in particular, when writing a high resistance state, current from a source line to a bit line is required to be applied to a 1T-1 MTJ; when writing a low resistance state, a current from the bit line to the source line needs to be applied to the 1T-1 MTJ.

The write current needs to reach a critical switching current that is either write high or write low, which is typically large. Under advanced processes, in order to achieve a corresponding critical switching current, an increase in the size of the access transistor or word line over-voltage is typically employed.

The two modes have the following defects: increasing the size of the access transistor results in an increase in the area of the memory array, thereby increasing the area of the entire MRAM circuit; the over-voltage operation of the word line affects the reliability of the circuit, and the STT-MRAM read current is small and the over-voltage of the word line is not needed to avoid the erroneous writing during the read operation.

For this reason, the word line control circuit of the MRAM needs to be capable of outputting waveforms of dual voltages, providing different operating voltages at the time of read/write operations.

In order to enable the word line control circuit of MRAM to output dual voltages, one method is to switch between a read voltage and a write voltage by the charge sharing principle. Specifically, a capacitor may be provided in the word line control circuit. In a write operation, the word line voltage is raised to a write voltage. In a read operation, the word line voltage is pulled down to the read voltage by charging the capacitor.

By adopting the scheme, on one hand, when in read operation, delay is increased when the capacitor is charged, so that the power supply voltage of the word line control circuit needs to be switched for a long time, and the switching transistor in the MRAM is in an over-voltage state for a quite long time when in read operation, so that the reliability of the transistor is affected. On the other hand, the capacitor occupies a larger circuit area.

To reduce the delay and circuit area, the word line voltage scheme shown in fig. 1 has been proposed. Specifically, referring to fig. 1, the row decoding driver 10 may include: the power supply selection circuit 110 and the plurality of decoding driving circuits 120. Wherein:

One input end of the power supply selection circuit 110 is connected to the read-write selection signal VPPSW, and the other input end is connected to the address selection signal AIN. The read/write select signal VPPSW and the address select signal AIN are inverted to generate the read enable signal REN. The read enable signal REN controls the on-off of the read voltage control tube M2. After the reading enable signal REN is inverted, a writing enable signal WEN is obtained, and the writing enable signal WEN controls the on-off of the writing voltage control tube M1.

An output terminal of the power supply selection circuit 110 is connected to the common node VPP. The power supply selection circuit 110 makes the voltage of the common node VPP be a read voltage when the read/write selection signal VPPSW is in a read state and the address selection signal AIN is active, and vice versa.

One input terminal of the decode driving circuit 120 is connected to the driving selection signal BIN, and the other input terminal is connected to the address selection signal AIN, so that the voltage of the common node VPP can be applied to the corresponding word line.

By adopting the scheme, the word line voltage is selected through simple read-write enabling logic control, but when the difference between the first voltage VDD1 and the second voltage VDD2 is larger, the write enabling signal WEN is effective, the write voltage control tube M1 is turned on, the read voltage control tube M2 cannot be completely turned off, voltage drop is generated, the voltage of the common node VPP cannot be pulled up to the first voltage VDD1, and normal writing of data is possibly affected; when the reading enable is effective, the reading voltage control tube M2 is turned on, the writing voltage control tube M1 cannot be completely turned off, the common node VPP is charged, the voltage of the common node VPP is higher than the second voltage VDD2, and power consumption is wasted.

In view of this problem, the present invention provides a word line control circuit, in which a voltage boosting circuit and a voltage selecting circuit are provided, the voltage boosting circuit can adjust voltages of a first output terminal and a second output terminal thereof when different operations are performed, the voltage selecting circuit can apply the write voltage to a corresponding word line when performing a write operation, and under the control of the voltage of the second output terminal, a channel connected to the second output terminal is disconnected, so that it is possible to avoid influencing normal writing of data due to incomplete disconnection of a channel connected to the second output terminal of the voltage selecting circuit and the voltage boosting circuit, and on the other hand, it is also possible to apply a read voltage to a corresponding word line when performing a read operation, and under the control of the voltage of the first output terminal, disconnect a channel connected to the first output terminal, so that it is possible to avoid wasting power consumption due to incomplete disconnection of a channel connected to the voltage selecting circuit and the first output terminal of the voltage boosting circuit.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 2, an embodiment of the present invention provides a word line control circuit 20, the word line control circuit 20 may include: a control circuit 21, a booster circuit 22, and a voltage selection circuit 23. Wherein:

The control circuit 21 is configured to receive the read/write enable signal and the row decode signal, and generate a first boost control signal and a second boost control signal with opposite logic;

The booster circuit 22 is connected to the control circuit 21 and has a first output terminal and a second output terminal; the voltage boosting circuit 22 is adapted to adjust the voltages of the first and second output terminals based on the first and second voltage boosting control signals when different operations are performed

The voltage selection circuit 23 is connected to the control circuit 21 and the boost circuit 22, and is adapted to apply the write voltage to the corresponding word line when performing a write operation, and to disconnect a path connected to the second output terminal under the control of the second output terminal voltage; when a read operation is performed, a read voltage is applied to the corresponding word line, and a path connected to the first output terminal is disconnected under the control of the first output terminal voltage.

Since the path of the voltage selection circuit 23 connected to the second output terminal is open at the time of performing the write operation, it is possible to avoid the voltage of the word line from being lowered by discharging the word line through the path by the second output terminal of the booster circuit, thereby affecting the normal writing of data. In addition, when the read operation is performed, the path of the voltage selection circuit 23 connected to the first output terminal is disconnected, so that it is possible to avoid wasting power consumption.

In a specific implementation, the voltage boosting circuit 22 may set the voltage of the first output terminal to a low level under the control of the first boost control signal and the second boost control signal when performing the write operation, and raise the voltage of the first output terminal to a write voltage and set the voltage of the second output terminal to a low level when performing the read operation or not performing the read operation.

In a specific implementation, the booster circuit 22 may have various circuit structures, which are not limited herein, so long as the word line voltage can be raised to the write voltage.

In an embodiment of the present invention, referring to fig. 2, the boost circuit 22 includes:

The first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the first NMOS tube MN1 and the second NMOS tube MN2.

The first PMOS transistor MP1, the third PMOS transistor MP3 and the first NMOS transistor MN1 are connected in series, and the second PMOS transistor MP2, the fourth PMOS transistor MP4 and the second NMOS transistor MN2 are connected in series; the sources of the first PMOS tube MP1 and the second PMOS tube MP2 are connected with the writing voltage output end; the gate of the first PMOS MP1 and the gate of the first NMOS MN1 are connected to the second boost control signal xan; the grid electrode of the second PMOS tube MP2 and the grid electrode of the second NMOS tube MN2 are connected with the first boost control signal xa; the grid electrode of the third PMOS tube MP3 is connected with the drain electrode of the fourth PMOS tube MP4 and is used as the first output end Z; the grid electrode of the fourth PMOS tube MP4 is connected with the drain electrode of the third PMOS tube MP3 and is used as the second output end ZN.

In a specific implementation, the first boost control signal xa is logically opposite to the second boost control signal xan, i.e., when the first boost control signal xa is high, the second boost control signal xan is low, and when the first boost control signal xa is low, the second boost control signal xan is high.

In a specific implementation, the write voltage output terminal outputs a write voltage V _WL. When the write operation is performed, the first boost control signal xa is set to a high level, the second boost control signal xan is set to a low level, at this time, the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, the first output terminal Z is set to a low level, the third PMOS transistor MP3 is turned on, and the voltage of the second output terminal ZN rises to the write voltage V _WL. When the read operation is performed or the read/write operation is not performed, the first boost control signal xa is set to a low level, the second boost control signal xan is set to a high level, at this time, the second PMOS transistor MP2 and the first NMOS transistor MN1 are turned on, the second output terminal ZN is set to a low level, the fourth PMOS transistor MP4 is turned on, and finally, the voltage of the first output terminal Z rises to the write voltage V _WL.

In a specific implementation, the voltage selection circuit 23 may have various circuit structures, which are not limited herein.

In an embodiment of the present invention, referring to fig. 2, the voltage selection circuit 23 may include: a first voltage selection sub-circuit 231, a second voltage selection sub-circuit 232, and a first voltage selection sub-circuit 233.

Wherein:

The first voltage selecting sub-circuit 231 has one end connected to the second output terminal and the other end connected to the word line, and is adapted to apply the read voltage to the corresponding word line when performing a read operation, and to disconnect a path connected to the first output terminal under the control of the voltage of the first output terminal;

The second voltage selecting sub-circuit 232 has one end connected to the first output terminal and the other end connected to the word line, and is adapted to apply a write voltage to the corresponding word line when performing a write operation, and disconnect a path connected to the second output terminal under the control of the voltage of the second output terminal;

The word line closing sub-circuit 233 is connected to the first voltage selecting sub-circuit and the second voltage selecting sub-circuit, and is adapted to close the word line.

In a specific implementation, the write voltage is higher than the read voltage.

In an embodiment of the present invention, referring to fig. 3, the first voltage selection sub-circuit 231 may include: a fifth PMOS tube MP5 and a sixth PMOS tube MP6 connected in series; the source electrode of the fifth PMOS tube MP5 and the read voltage output end; the grid electrode of the fifth PMOS tube MP5 is connected with the inverted signal EN of the row decoding signal A; and the grid electrode of the sixth PMOS tube MP6 is connected with the second output end ZN.

In an embodiment of the present invention, referring to fig. 3, the second voltage selection sub-circuit 232 may include: seventh PMOS tube MP7. And the grid electrode of the seventh PMOS tube MP7 is connected with the first output end Z, the source electrode is connected with the writing voltage output end, and the drain electrode is connected with the word line WL.

When the write operation is performed, the row decoding signal a is valid, and the inverted signal EN of the row decoding signal a turns on the fifth PMOS MP 5. Meanwhile, the first output terminal Z of the boost circuit 23 is at a low level, the voltage of the second output terminal ZN is the write voltage V _WL, and at this time, the sixth PMOS transistor MP6 is turned off, i.e. the path connected to the second output terminal ZN is turned off. The seventh PMOS transistor MP7 is turned on, so that the write voltage V _WL is applied to the corresponding word line WL.

When the read operation is performed, the row decoding signal a is valid, and the inverted signal EN of the row decoding signal a turns on the fifth PMOS MP 5. Meanwhile, the voltage at the first output terminal Z of the boost circuit 23 is a write voltage, the voltage ZN at the second output terminal is a low level, and at this time, the sixth PMOS transistor MP6 is turned on, and the read voltage Vcore is applied to the word line WL. Meanwhile, the seventh PMOS MP7 is turned off, so that the path connected to the first output terminal is turned off.

The voltage fed back by the output end of the booster circuit 23 can clamp the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 in different states, so that the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 can be prevented from entering the triode region, and the voltage of the word line WL can be kept at the required potential under the condition of reading and writing.

In a specific implementation, the first PMOS transistor MP1 to the seventh PMOS transistor MP7, and the first NMOS transistor to the fourth NMOS transistor may be high-voltage MOS transistors, so that an overpressure problem may be avoided.

In an embodiment of the present invention, referring to fig. 3, the word line closing circuit 233 may include: the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected in series; the gate of the third NMOS transistor MN3 is connected to the second boost control signal xan, and the gate of the fourth NMOS transistor MN4 is connected to the inverted signal EN of the row decoding signal a; the source of the fourth NMOS transistor MN4 is grounded.

Specifically, when the second boost control signal xan is at a high level, the third NMOS transistor MN3 is turned on, and vice versa. When the row decoding signal a is active, the fourth NMOS transistor MN4 is turned on, and vice versa. The word line closing circuit 23 can thereby ground the word line WL when the read/write operation is not performed, and form a ground path, thereby closing the word line.

In a specific implementation, the control circuit 21 may have various circuit structures, which are not limited herein.

In an embodiment of the present invention, referring to fig. 3, the control circuit includes: the first AND gate circuit Y1, the first inverter f1 and the second inverter f2. The input end of the first AND gate circuit Y1 is connected with the read-write enabling signal WREN and the row decoding signal A; the output end of the first AND gate circuit Y1 generates the first boost control signal xa; the output end of the first and gate circuit Y1 is connected to the input end of the first inverter f1, and the output end of the first inverter f1 generates the second boost control signal xan; the input end of the second inverter f2 is connected to the row decoding signal a, and the output end of the second inverter f2 is connected to the voltage selection circuit.

Specifically, the row decode signal a is set to a low level when no read-write operation is performed. At this time, the inversion signal EN of the row decoding signal a is set to a high level, the first boost control signal xa is set to a low level, the second boost control signal xan is set to a high level, so that the fourth NMOS transistor MN4, the second PMOS transistor MP2, and the first NMOS transistor MN1 are turned on, the second output terminal ZN is set to a low level, the fourth PMOS transistor MP4 is turned on, the voltage at the first output terminal Z finally rises to the write voltage V _WL, the seventh PMOS transistor MP7 is turned off, the second boost control signal xan is at a high level at this time, the third NMOS transistor MN3 is turned on, and the voltage of the word line WL is set to a low level.

When a read operation is performed, the row decode signal a is valid, the read/write enable signal WREN is set to a low level, the first boost control signal xa is set to a low level, the second boost control signal xan is set to a high level, the fifth PMOS transistor MP5 is turned on, the voltage at the first output terminal Z is increased to the write voltage V _WL, the seventh PMOS transistor MP7 is turned off, the second output terminal ZN is set to a low level, the sixth PMOS transistor MP6 is turned on, and the voltage at the word line WL is set to the read voltage V _CORE.

When a write operation is performed, the row decode signal a is valid, the read/write enable signal WREN is set to a high level, the first boost control signal xa is set to a high level, the second boost control signal xan is set to a low level, at this time, the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, the voltage of the first output terminal Z is a low level, the third PMOS transistor MP3 is turned on, the voltage of the second output terminal ZN rises to the write voltage V _WL, the seventh PMOS transistor MP7 is turned on, the voltage of the word line WL is set to the write voltage V _WL, and the high potential of the second output terminal ZN further turns off the sixth PMOS transistor MP6.

In practical applications, the read-out time of the mram is usually much faster than the write-in time, the same external clock control circuit is used in the synchronous circuit for reading and writing, the same period is maintained for reading and writing, and for the mram, the word line is still kept open for a longer time after reading out the data, which results in waste of power consumption, and meanwhile, the probability of erroneous writing is also easily improved.

In an embodiment of the present invention, in order to reduce the power consumption waste and reduce the probability of erroneous writing, the control circuit is further adapted to receive the read driving control signal SE, and generate the control signal of the voltage selection circuit based on the read driving control signal SE, the read/write enable signal WREN and the row decoding signal a together, so as to turn off the word line WL after completing the data reading, thereby effectively shortening the word line turn-on time during the read operation.

Specifically, referring to fig. 4, the control circuit may include: the first and circuit Y1, the second and circuit Y2, the first inverter f1, the second inverter f2, and the third inverter f3. Wherein,

The input end of the third inverter f3 is connected with the read drive control signal SE; the input end of the second AND gate circuit Y2 is connected with the row decoding signal A and the output signal of the third inverter f 3; the input end of the first AND gate circuit Y1 is connected with the read-write enabling signal WREN and the output signal of the second AND gate circuit Y2; the output end of the first AND gate circuit Y1 generates the first boost control signal xa; the output end of the first and gate circuit Y1 is connected to the input end of the first inverter f1, and the output end of the first inverter f1 generates the second boost control signal xan; the input end of the second inverter f2 is connected to the output end a_wr of the second and gate circuit Y2, and the output end of the second inverter f2 is connected to the voltage selection circuit.

The second and circuit Y2 and the third inverter f3 are added with respect to the control circuit shown in fig. 2, and the read drive control signal SE is introduced. The read drive control signal SE is used for controlling the read drive circuit to complete the read operation. When the read drive control signal SE is at a high level, data readout is completed rapidly, and at this time, the voltage selection circuit may turn off the word line, thereby reducing power consumption.

By adopting the word line control circuit in the embodiment of the invention, the quick switching of the word line voltage and the time sequence control of the read operation can be realized through simple logic control without charging and discharging of a capacitor, the word line control circuit is simple in design and easy to realize, and the stability of the word line voltage is ensured. And by adding a read drive control signal in the word line control circuit, the word line is closed after the data is read, so that the word line opening time during the read operation is effectively shortened.

The embodiment of the invention also provides a magnetic random access memory, which can comprise the word line control circuit in the embodiment.

In one embodiment of the present invention, referring to fig. 5, the magnetic random access memory further includes: clock control circuit 51, read drive circuit 52, precharge circuit 53, write drive circuit 54, row decoder 55, and memory array 56. Wherein:

The clock control circuit 51 is adapted to access the clock signal CLK and the read/write enable signal WREN, and generate a read drive precharge signal SAE and a read drive control signal SE;

The read driving circuit 52 is connected to the clock control circuit 51 and is adapted to perform a read operation under the control of the read driving precharge signal SAE and the read driving control signal SE;

The precharge circuit 53, connected to the read drive circuit 52, adapted to precharge the bit line BL and the source line SL;

the write driving circuit 54, connected to the precharge circuit 53, is adapted to control voltages of the bit line BL and the source line SL to perform a write operation;

The row decoder 55 is connected to the word line control circuit 20 and adapted to generate a row decoding signal a;

the memory array is connected with the word line control circuit 20;

the word line control circuit 20 is connected to the row decoder 55 and the clock control circuit 51, and is adapted to control the voltage of the word line WL based on the read/write enable signal WREN, the row decoding signal a, and the read drive control signal SE, so as to satisfy the operation requirement.

Assuming that the storage units in the storage array are m rows and n columns and the reference units are s, then: the row decode signal A output by the row decoder is m bits, which can be expressed as A < m-1:0>; the number of memory cell bit lines is n, which can be expressed as BL < n-1:0>; the number of memory cell source lines is also n, which can be expressed as SL < n-1:0>; the number of memory cell word lines is m, which can be expressed as WL < m-1:0>, the number of reference cell bit lines is s, which can be expressed as ref-BL < s-1:0>; the number of reference cell source lines is s, which can be expressed as ref-SL < s-1:0>.

In an implementation, the clock signal CLK and the read/write enable signal WREN generate the read drive precharge signal SAE and the read drive control signal SE through the clock control circuit 51. The read drive precharge signal SAE and the read drive control signal SE are used as inputs to the sense amplifier of the read drive circuit 52. The read-drive precharge signal SAE is set to a high level during a read operation, and the read-drive control signal SE is then set to a high level, and is set to a low level after the read operation is completed and at other stages such as a write operation.

The read drive control signal SE and the row decoder output signal A < m-1:0>, the read-write enable signal WREN generates word line potentials required for different operations through the word line control circuit 20. Specifically, when performing a write operation, the corresponding word line is set to a high voltage V _WL, the memory cell is turned on, the precharge circuit 54 releases the bit line BL and the source line SL, and the write data controls the voltages of the bit line BL and the source line SL through the write driving circuit 53, thereby achieving the write of the corresponding memory cell. When a read operation is performed, the corresponding word line is set to a high voltage V _CORE, the memory cell is turned on, the precharge circuit releases the bit line BL, the source line SL, the reference cell bit line ref-BL, and the reference cell source line ref-SL, and data of the corresponding memory cell is read out through the read driving circuit 52. When the read drive control signal SE is set high, the data is read out quickly, and the word line control circuit 20 turns off the corresponding word line, thereby reducing power consumption.

In a specific implementation, the read driving circuit may be provided with a plurality of sense amplifiers, and each sense amplifier is connected to a plurality of memory cells and a reference cell, and is used for reading data of the connected memory cells.

Fig. 6 is a schematic circuit configuration of a conventional sense amplifier. Referring to fig. 6, the sense amplifier may include: the first to eleventh switching transistors Q1 to Q11. The gates of the first switching tube Q1 and the second switching tube Q2 are connected to a CLAMP signal CLAMP, and form a CLAMP circuit. The gates of the third switching tube Q3 and the fourth switching tube Q4 are connected with a read drive control signal SE to form a switch control circuit of the sensitive amplifier, and the fifth switching tube Q5 to the eighth switching tube Q8 form a cross inverter. The gates of the ninth to eleventh switching transistors Q9 to Q11 are connected to the read drive precharge signal SAE and constitute a precharge circuit.

The memory unit 61 is connected to one end of the first switching tube Q1 through a pair of column selection tubes, and the reference unit 62 is connected to one end of the second switching tube Q2 through a pair of column selection tubes. The gate of one column selection tube of the pair of column selection tubes is connected with the column selection signal cs, and the gate of the other column selection tube is connected with the inverted signal csn of the column selection signal. Memory cell 61 includes one MTJ and one access transistor, and reference cell 62 includes one or more MTJs and one access transistor. The memory cell 61 is connected to the word line WL and the bit line BL, and the reference cell 62 is connected to the reference word line ref-WL and the reference bit line ref-BL.

When the read operation is started, the read drive precharge signal SAE signal is set to a high level prior to the read drive control signal SE, and the sense amplifier generates different currents according to the difference in resistance between the memory cell 61 and the reference cell 62, thereby generating a potential difference at the drains of the third switching transistor Q3 and the fourth switching transistor Q4. Then, the read drive control signal SE is set to be high level, and the output ends OUT and OUT_b are rapidly pulled to corresponding high and low potentials under the feedback effect, so that quick reading of data is realized.

By adopting the magnetic random access memory architecture and the word line control circuit thereof, the whole architecture has simple design and easy realization, can realize the rapid switching of word line voltage in different operations, and reduces the read power consumption.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (12)

1. A word line control circuit, comprising:

The control circuit is suitable for receiving the read-write enabling signal and the row decoding signal and generating a first boost control signal and a second boost control signal with opposite logic;

The boost circuit is connected with the control circuit and provided with a first output end and a second output end; the boost circuit is suitable for adjusting the voltages of the first output end and the second output end based on the first boost control signal and the second boost control signal when different operations are performed;

and a voltage selection circuit connected to the control circuit and the boost circuit, adapted to apply a write voltage to a corresponding word line when performing a write operation, and to disconnect a path connected to the second output terminal under control of the second output terminal voltage; when a read operation is performed, a read voltage is applied to the corresponding word line, and a path connected to the first output terminal is disconnected under the control of the first output terminal voltage.

2. The word line control circuit of claim 1, wherein the boost circuit is adapted to set the voltage at the first output terminal to a low level under control of the first boost control signal and the second boost control signal when performing a write operation, to boost the voltage at the second output terminal to a write voltage when performing a read operation or not, and to boost the voltage at the first output terminal to a write voltage when performing a read operation or not.

3. The word line control circuit of claim 2, wherein the boost circuit comprises:

The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube and the second NMOS tube;

The first PMOS tube, the third PMOS tube and the first NMOS tube are connected in series, and the second PMOS tube, the fourth PMOS tube and the second NMOS tube are connected in series; the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the writing voltage output end; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the second boost control signal; the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube are connected with the first boost control signal; the grid electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube and is used as the first output end; and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube and is used as the second output end.

4. A word line control circuit as claimed in any one of claims 1 to 3, wherein the voltage selection circuit comprises:

A first voltage selection sub-circuit, one end of which is connected with the second output end, and the other end of which is connected with the word line, and is suitable for applying the read voltage to the corresponding word line when the read operation is performed, and disconnecting a passage connected to the first output end under the control of the voltage of the first output end;

A second voltage selection sub-circuit, one end of which is connected with the first output end and the other end of which is connected with the word line, and which is suitable for applying the writing voltage to the corresponding word line when writing operation is performed, and disconnecting the passage connected to the second output end under the control of the voltage of the second output end;

And the word line closing sub-circuit is connected with the first voltage selecting sub-circuit and the second voltage selecting sub-circuit and is suitable for closing the word line.

5. The word line control circuit of claim 4, wherein the first voltage selection sub-circuit comprises: a fifth PMOS tube and a sixth PMOS tube connected in series; the source electrode of the fifth PMOS tube and the read voltage output end; the grid electrode of the fifth PMOS tube is connected with the inverted signal of the row decoding signal; and the grid electrode of the sixth PMOS tube is connected with the second output end, and the drain electrode of the sixth PMOS tube is connected with the word line.

6. The word line control circuit of claim 4, wherein the second voltage selection sub-circuit comprises: and the grid electrode of the seventh PMOS tube is connected with the first output end, the source electrode of the seventh PMOS tube is connected with the writing voltage output end, and the drain electrode of the seventh PMOS tube is connected with the word line.

7. The word line control circuit of claim 4, wherein the word line shutdown circuit comprises: the third NMOS tube and the fourth NMOS tube are connected in series; the grid electrode of the third NMOS tube is connected with a second boost control signal, and the grid electrode of the fourth NMOS tube is connected with an inverted signal of the row decoding signal; and the source electrode of the fourth NMOS tube is grounded.

8. The word line control circuit of claim 1, wherein the control circuit comprises: the first AND gate circuit, the first inverter and the second inverter;

The input end of the first AND gate circuit is connected with the read-write enabling signal and the row decoding signal; the output end of the first AND gate circuit generates the first boost control signal; the output end of the first AND gate circuit is connected with the input end of the first inverter, and the output end of the first inverter generates the second boost control signal; the input end of the second inverter is connected with the row decoding signal, and the output end of the second inverter is connected with the voltage selection circuit.

9. The word line control circuit of claim 1, wherein the control circuit is further adapted to receive a read drive control signal and to collectively generate the control signal for the voltage selection circuit based on the read drive control signal, a read write enable signal, and a row decode signal to turn off the word line after the data is read.

10. The word line control circuit of claim 9, wherein the control circuit comprises: the first and circuit, the second and circuit, the first inverter, the second inverter and the third inverter;

The input end of the third inverter is connected with the read drive control signal; the input end of the second AND gate circuit is connected with the row decoding signal and the output signal of the third inverter; the input end of the first AND gate circuit is connected with the read-write enabling signal and the output signal of the second AND gate circuit; the output end of the first AND gate circuit generates the first boost control signal; the output end of the first AND gate circuit is connected with the input end of the first inverter, and the output end of the first inverter generates the second boost control signal; the input end of the second inverter is connected with the output signal of the second AND gate circuit, and the output end of the second inverter is connected with the voltage selection circuit.

11. A magnetic random access memory comprising the word line control circuit of any one of claims 1 to 10.

12. The magnetic random access memory of claim 11 further comprising:

The clock control circuit is suitable for being connected with a clock signal and the read-write enabling signal and generating a read drive pre-charge signal and a read drive control signal;

the read driving circuit is connected with the clock control circuit and is suitable for executing read operation under the control of the read driving pre-charge signal and the read driving control signal;

The precharge circuit is connected with the read driving circuit and is suitable for precharging the bit line and the source line; a write driving circuit connected to the precharge circuit and adapted to control voltages of the bit line and the source line to perform a write operation;

A row decoder connected to the word line control circuit and adapted to generate a row decoding signal;

the storage array is connected with the word line control circuit;

the word line control circuit is connected with the row decoder and the clock control circuit and is suitable for controlling the word line voltage based on the read-write enabling signal, the row decoding signal and the read driving control signal so as to meet the operation requirement.