CN118093321A - PCIe system temperature control method and device - Google Patents

Abstract

The invention provides a PCIe system temperature control method and device, which are used for monitoring the current temperature of a PCIe system in real time, when the current temperature exceeds a preset early warning temperature threshold value, if a target link is not in a first low power consumption state, modifying a timer value corresponding to the first low power consumption state of an ASPM module so as to shorten the time of the target link entering the first low power consumption state; if the current temperature exceeds a preset maximum temperature threshold, setting the target link to a second low power consumption state when the target link is set to a first low power consumption state, and reducing the port link rate when the target link is not in the first low power consumption state; and when the current temperature is lower than a preset minimum temperature threshold value, restoring the links in the first and second low power consumption states to a normal state, and carrying out rate restoration on the ports with the reduced link rates. The invention dynamically and adaptively adjusts the temperature of the PCIe system on the premise of ensuring the integrity of the data service.

Description

PCIe system temperature control method and device

Technical Field

The present invention belongs to the field of temperature control, and in particular relates to a PCIe system temperature control method and device.

Background technique

As chip complexity increases, chip temperature control is becoming an increasingly important factor affecting the reliability of the entire system. When the chip's normal operating temperature is exceeded, the reliability of the device will decrease exponentially, affecting the chip's service life. For PCIe high-speed I/O chips, since they are responsible for the entire high-speed data I/O interaction, the PCIe protocol requires real-time transmission of a large amount of data, and the surface temperature will be higher. Therefore, a temperature management control system is required to monitor, respond to, and manage the chip temperature in real time. Otherwise, the chip's static power consumption will increase, and the chip's reliability will be significantly reduced, increasing the risk of device failure.

In order to support higher transmission efficiency, the PCIe standard protocol supports multi-port transmission. One port supports one or more physical layers to form a port. Each port is independent of each other and has higher transmission efficiency. A typical multi-port array is shown in Figure 1.

The traditional PCIe system temperature control method adds a temperature control module Tsensor at the chip level. When the chip operating temperature is too high and exceeds the warning value, the Tsensor module reports the temperature abnormality interrupt to the chip, and the CPU forces the entire system to shut down to prevent the chip from being damaged due to overheating. It can be seen that the traditional solution directly shuts down the entire system when the temperature exceeds the threshold, lacks current transmission status detection, and will directly affect the normal business transmission of the current PCIe system. It is impossible to distinguish the current transmission status of each port, and it is impossible to accurately perform independent temperature control on each port without affecting business transmission.

In addition, the PCIe system can effectively reduce the system's operating power consumption by automatically managing the power consumption state through its own active power management module (ASPM), including the link entering the L0s, L1, L1.1, L1.2 and other states. However, the traditional solution lacks the interaction between the power consumption state and the system temperature. The timer for entering the low power mode is a fixed value after the initial configuration, and the time to enter the low power mode cannot be dynamically adjusted according to the temperature, so the temperature of the PCIe controller cannot be adaptively adjusted.

Summary of the invention

The object of the present invention is to provide a PCIe system temperature control method and device, which dynamically and adaptively adjust the temperature of the PCIe system under the premise of ensuring data service integrity.

According to a first aspect of the present invention, there is provided a PCIe system temperature control method, comprising:

Monitor the current temperature of the PCIe system in real time, and when the current temperature exceeds a preset warning temperature threshold, if the target link is not in the first low power consumption state, modify the timer value of the first low power consumption state of the corresponding ASPM module to shorten the time for the target link to enter the first low power consumption state;

If the current temperature exceeds a preset maximum temperature threshold, when the target link has been set to a first low power consumption state, the target link is set to a second low power consumption state, and when the target link is not in the first low power consumption state, the link rate of the target link is reduced, wherein the maximum temperature threshold is higher than the warning temperature threshold, and the power consumption of the second low power consumption state is lower than that of the first low power consumption state;

When the current temperature is lower than a preset minimum temperature threshold, the port states in the first low power consumption state and the second low power consumption state are restored to a normal power consumption state, and the rate of the port whose link rate is reduced is restored.

Preferably, after setting the target link to the first low power consumption state, the method further comprises:

If the current temperature is lower than the warning temperature threshold, the timer value of the first low power consumption state of the ASPM module is changed back to a default value.

The reducing the link rate of the target link further comprises:

A speed reduction or lane reduction operation is started on the target link. If the current temperature still exceeds the maximum temperature threshold, speed reduction or lane reduction operations are performed on other ports in turn until the current temperature does not exceed the maximum temperature threshold.

The first low power consumption state is an ASPM L1 low power consumption state, and the second low power consumption state is an ASPM L1.1 or L1.2 low power consumption sub-state.

The step of setting the target link to a second low power consumption state further comprises:

The target link is set to the ASPM L1.1 or L1.2 low power consumption sub-state. If the current temperature still exceeds the maximum temperature threshold, other ports are set to the ASPM L1.1 or L1.2 low power consumption sub-state in sequence until the current temperature does not exceed the maximum temperature threshold.

According to a second aspect of the present invention, there is provided a PCIe system temperature control device, comprising:

Temperature monitoring unit, used to monitor the current temperature of the PCIe system in real time;

A first control unit, configured to modify a timer value of the first low power consumption state of the corresponding ASPM module when the current temperature exceeds a preset warning temperature threshold, if the target link is not in the first low power consumption state, so as to shorten the time for the target link to enter the first low power consumption state;

a second control unit, configured to, when the current temperature exceeds a preset maximum temperature threshold, set the target link to a second low power consumption state when the target link has been set to a first low power consumption state, and to reduce a link rate of the target link when the target link is not in the first low power consumption state, wherein the maximum temperature threshold is higher than the warning temperature threshold, and the power consumption of the second low power consumption state is lower than that of the first low power consumption state;

The third control unit is used to restore the port states in the first low power consumption state and the second low power consumption state to the normal power consumption state when the current temperature is lower than the preset minimum temperature threshold, and restore the rate of the port whose link rate is reduced.

Compared with the related art, the technical solution of the present invention has the following advantages:

By setting three levels of minimum temperature threshold, warning temperature threshold and maximum temperature threshold, the temperature of the PCIe system transmission process is monitored by utilizing the interaction between the Tsensor module and the PCIe system. Combined with the transmission state of the current link, when the system temperature exceeds the threshold temperature, the target link is respectively selected to lower the ASPM timer configuration to enter L1, start the target link to enter the L1.1/L1.2 sub-state, start the target link speed reduction and Lane reduction operations to achieve temperature reduction, more directly and accurately control the temperature, and enter the low power consumption mode faster. The PCIe system temperature control method proposed in the present invention is simple, clear, and easy to implement. No host intervention is required throughout the process. The ASPM mechanism in PCIe is combined with temperature control to ensure the integrity of business transmission and not affect the normal transmission of business.

Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by implementing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the structures and processes indicated in the description and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG. 1 is a schematic diagram of a multi-port array of a PCIe system according to the prior art.

FIG. 2 is a schematic diagram of a multi-port array of a PCIe system according to the present invention.

FIG. 3 is a flow chart of a PCIe system temperature control method according to the present invention.

FIG. 4 is a schematic diagram of the temperature control principle according to the present invention.

FIG. 5 is a diagram of a PCIe system temperature control process according to a specific embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In view of the shortcomings of PCIe system temperature control, the present invention proposes a PCIe system temperature control method and device. Based on the Tsensor module inside the chip shown in Figure 2, the temperature of the chip during the current transmission process is monitored. Combined with the transmission status of the current link, when the chip temperature exceeds the warning temperature threshold, the timer for the link to enter L1 is dynamically modified and started to enter a low power consumption mode (L1.1, L1.2). Under the premise of ensuring the integrity of data services, the temperature of the PCIe system is dynamically and adaptively adjusted to improve the reliability of the chip and extend the service life of the chip.

The Tsensor module of the present invention pre-sets the minimum temperature threshold, the warning temperature threshold and the maximum temperature threshold respectively. When the chip temperature is between the minimum temperature threshold and the warning temperature threshold, the chip works normally. When the temperature exceeds the warning temperature threshold, the Tsensor reports the abnormal temperature interrupt to the PCIe system. After receiving the interrupt, the PCIe system adjusts the timer of each port entering ASPM L1 so that it can enter the low power consumption state faster. If the temperature returns to normal, the timer value of ASPM L1 is changed back to the default value.

When the temperature rises further and reaches the maximum temperature threshold, it is first determined whether the target link is in the L1 low power state. If it is in the L1 low power state, the L1.1 or L1.2 state request will be initiated port by port, which can further reduce power consumption and thus reduce temperature. If the temperature exceeds the maximum temperature threshold and is not currently in the L1 low power state, it means that the link is sending data, but the chip temperature seriously exceeds the normal range. The controller initiates a speed reduction and Lane (data path) reduction request for each port, and reduces power consumption by reducing the link rate, thereby reducing temperature. For example, the speed reduction operation can be reduced from 16G/s to 8G/s. The Lane reduction operation can close some of the multiple Lanes and keep only some Lanes working. As the chip temperature decreases, when the temperature is less than the minimum temperature threshold, the PCIe system sends a recovery rate and Lane recovery instruction to each port, so that each port can return to normal working state and be in the normal working temperature range. The entire solution fully adaptively adjusts the working state and temperature control of the PCIe system according to the current temperature of the chip without affecting the current data transmission.

Referring to the flowchart of FIG. 3 , the PCIe system temperature control method provided by the present invention includes:

Step S1: monitor the current temperature of the PCIe system in real time. When the current temperature exceeds the preset warning temperature threshold, if the target link is not in the first low power state, modify the timer value of the first low power state of the corresponding ASPM module to shorten the time for the target link to enter the first low power state.

The principle diagram of the specific scheme of PCIe system temperature control proposed by the present invention is shown in FIG4. When the system temperature exceeds the warning temperature threshold, the Tsensor module reports the temperature abnormality interrupt to the PCIe system. After receiving the interrupt, the PCIe system adjusts the timer value of each port entering ASPM L1 so that the corresponding port enters the L1 low power state faster, that is, process ① in FIG4. The ASPM L1 timer is used to characterize how long the link idle state lasts before automatically entering the low power state. The default value is generally 64us. For example, when the temperature exceeds the warning threshold, it can be set to 2us to accelerate the entry into the L1 state.

Step S2: If the current temperature exceeds a preset maximum temperature threshold, when the target link has been set to a first low power consumption state, the target link is set to a second low power consumption state, and when the target link is not in the first low power consumption state, the link rate of the target link is reduced, wherein the maximum temperature threshold is higher than the warning temperature threshold, and the power consumption of the second low power consumption state is lower than that of the first low power consumption state.

After the temperature in step S1 returns to normal, the ASPM L1 timer value is changed back to the default value. If the temperature rises further and exceeds the set maximum temperature threshold, it is first determined whether the target link is in the L1 low power state. For example, after the temperature returns to normal, the previously modified timer value of 2us is changed back to 64us, indicating that the link will automatically enter the low power state after being idle for 64us.

When the current link is in the L1 low power state, the link is initiated port by port to enter the L1.1/L1.2 low power state, further reducing power consumption and thus reducing temperature, as shown in process ② in Figure 4. In a further embodiment, when the temperature is still the highest temperature threshold after the link is initiated port by port to enter the L1.1 low power state, the link is initiated port by port to enter the L1.2 low power state.

When the temperature exceeds the maximum temperature threshold and the current link is not in the L1 low power state, it means that the link is transmitting data, but the system temperature seriously exceeds the normal operating range of the chip. Therefore, the controller initiates a speed reduction and Lane reduction request for each port, reducing power consumption by reducing the link rate, thereby reducing the temperature.

Step S3: when the current temperature is lower than a preset minimum temperature threshold, the port states in the first low power consumption state and the second low power consumption state are restored to a normal power consumption state, and the rate of the port whose link rate is reduced is restored.

After the above cooling operation, as the system temperature continues to drop, when the temperature is lower than the minimum temperature threshold, the PCIe system sends a command to restore the L0 working state to each port, so that each port can resume normal working state and ensure that it is in the normal working temperature range, which is process ③ in Figure 4. The whole scheme adaptively adjusts the transmission state of the PCIe system according to the current temperature of the PCIe system.

According to a specific embodiment of the present invention, a complete flow chart of the temperature control scheme is shown in FIG5 .

In process 101, the Tsensor temperature monitoring module is started, the minimum temperature threshold, the warning temperature threshold and the maximum temperature threshold are set, and the temperature change of the PCIe system in the current operating state is monitored in real time.

In process 102, it is determined whether the current temperature exceeds the maximum temperature threshold. If it exceeds the maximum temperature threshold, the process proceeds to process 103, otherwise, the process proceeds to process 107.

In process 103, it is determined whether the current link is in the L1 low power consumption state. If it is in the L1 low power consumption state, the process proceeds to process 104, otherwise, the process proceeds to process 105.

In process 104, the chip temperature exceeds the maximum temperature threshold and the current link is not in the L1 low power state, indicating that the current port can transmit data normally, and the speed reduction or lane reduction operation is started for the current port. If the temperature still exceeds the maximum temperature threshold, the speed reduction or lane reduction operation is performed on the second port in turn until all ports have completed the speed reduction or lane reduction or the temperature no longer exceeds the maximum temperature threshold.

In process 105, if the chip temperature exceeds the maximum temperature threshold and the current link is in the L1 low power state, the current port is further made to enter the L1.1 or L1.2 sub-state. If the temperature still exceeds the maximum temperature threshold, the second port is made to enter the L1.1 or L1.2 sub-state in turn until all ports complete the operation.

In process 106, after the current ports have completed the startup and entered L1.1/L1.2 or the speed reduction or Lane reduction operation, if the temperature still exceeds the maximum temperature threshold, the second port is designated to repeat the above operation until the temperature is lower than the maximum temperature threshold.

In process 107, it is determined whether the current temperature exceeds the warning temperature threshold. If it exceeds the warning temperature threshold, the process proceeds to process 108, otherwise, the process proceeds to process 109.

In process 108, the current temperature exceeds the warning temperature threshold but is lower than the maximum temperature threshold, indicating that the current temperature of the system exceeds the normal value but does not exceed the maximum warning value. It is necessary to adaptively reduce the waiting time for entering the low power state. By configuring the current port to enter the ASPM L1 timer, the target link can quickly enter the L1 low power state, thereby reducing the system temperature.

In process 109 , it is determined whether the current temperature is lower than the minimum temperature threshold. If it is lower than the minimum temperature threshold, the process proceeds to process 110 , otherwise, the process proceeds to process 106 .

In process 110, the system temperature is continuously monitored, and when the temperature is less than the minimum temperature threshold, it is checked whether the current port has started to reduce lane or frequency (ie, reduce speed). If it has been started, process 111 is entered, otherwise process 106 is entered.

In process 111, when all ports exit low power mode and the current chip temperature is less than the minimum temperature threshold, the rate of the current slowed-down port is specified to increase, and the temperature continues to be monitored. If the chip temperature is still less than the minimum temperature threshold, the rate of the second slowed-down port is specified to increase until all slowed-down ports increase their transmission rates or until the temperature exceeds the minimum temperature threshold.

In process 106, the remaining ports continue to transmit the PCIe link services, thereby automatically and dynamically adjusting the current PCIe system according to the temperature of the chip without affecting the normal data services, thereby achieving adaptive control of the PCIe system.

It can be seen that the PCIe system temperature control method proposed in the present invention has the following advantages compared with the related art:

By setting three levels of minimum temperature threshold, warning temperature threshold and maximum temperature threshold, the temperature of the PCIe system transmission process is monitored by utilizing the interaction between the Tsensor module and the PCIe system. Combined with the transmission state of the current link, when the system temperature exceeds different threshold temperatures, the target link is respectively selected to lower the ASPM timer configuration to enter L1, start the target link to enter the L1.1/L1.2 sub-state, start the target link speed reduction and Lane reduction operations to achieve temperature reduction, more directly and accurately control the temperature, and enter the low power consumption mode faster. The PCIe system temperature control method proposed in the present invention is simple, clear and easy to implement, and does not require host intervention throughout the process. The ASPM mechanism in PCIe is combined with temperature control to ensure the integrity of business transmission and not affect the normal transmission of business.

According to simulation verification, the operating frequency of a single-Lane PCIe system is reduced from 32G to 2.5G, and its system power consumption can be reduced by 30%; the system power consumption of a single-Lane PCIe system can be reduced by 80% when it enters the L1.2 sub-state from the L0s state. This solution can significantly reduce power consumption, thereby achieving the purpose of controlling system temperature.

Accordingly, the present invention provides a PCIe system temperature control device in a second aspect, comprising:

Temperature monitoring unit, used to monitor the current temperature of the PCIe system in real time;

A first control unit, configured to modify a timer value of the first low power consumption state of the corresponding ASPM module when the current temperature exceeds a preset warning temperature threshold, if the target link is not in the first low power consumption state, so as to shorten the time for the target link to enter the first low power consumption state;

a second control unit, configured to, when the current temperature exceeds a preset maximum temperature threshold, set the target link to a second low power consumption state when the target link has been set to a first low power consumption state, and to reduce a link rate of the target link when the target link is not in the first low power consumption state, wherein the maximum temperature threshold is higher than the warning temperature threshold, and the power consumption of the second low power consumption state is lower than that of the first low power consumption state;

The third control unit is used to restore the port states in the first low power consumption state and the second low power consumption state to the normal power consumption state when the current temperature is lower than the preset minimum temperature threshold, and restore the rate of the port whose link rate is reduced.

The above-mentioned device can be implemented by the PCIe system temperature control method provided by the embodiment of the first aspect above. The specific implementation method can be found in the description of the embodiment of the first aspect, which will not be repeated here.

It is understood that the system structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily think of combinations and adjustments to the structural features of the above embodiments according to the use requirements, and the concept of the present invention should not be limited to the specific details of the above examples.

Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A PCIe system temperature control method, comprising: Monitor the current temperature of the PCIe system in real time, and when the current temperature exceeds a preset warning temperature threshold, if the target link is not in the first low power consumption state, modify the timer value of the first low power consumption state of the corresponding ASPM module to shorten the time for the target link to enter the first low power consumption state; If the current temperature exceeds a preset maximum temperature threshold, when the target link has been set to a first low power consumption state, the target link is set to a second low power consumption state, and when the target link is not in the first low power consumption state, the link rate of the target link is reduced, wherein the maximum temperature threshold is higher than the warning temperature threshold, and the power consumption of the second low power consumption state is lower than that of the first low power consumption state; When the current temperature is lower than a preset minimum temperature threshold, the port states in the first low power consumption state and the second low power consumption state are restored to a normal power consumption state, and the rate of the port whose link rate is reduced is restored. 2. The PCIe system temperature control method according to claim 1, characterized in that after setting the target link to the first low power consumption state, further comprising: If the current temperature is lower than the warning temperature threshold, the timer value of the first low power consumption state of the ASPM module is changed back to a default value. 3. The PCIe system temperature control method according to claim 1, wherein reducing the link rate of the target link further comprises: A speed reduction or lane reduction operation is started on the target link. If the current temperature still exceeds the maximum temperature threshold, speed reduction or lane reduction operations are performed on other ports in turn until the current temperature does not exceed the maximum temperature threshold. 4. The PCIe system temperature control method according to claim 1, characterized in that the first low power consumption state is an ASPM L1 low power consumption state, and the second low power consumption state is an ASPM L1.1 or L1.2 low power consumption sub-state. 5. The PCIe system temperature control method according to claim 4, wherein the step of setting the target link to the second low power consumption state further comprises: The target link is set to the ASPM L1.1 or L1.2 low power consumption sub-state. If the current temperature still exceeds the maximum temperature threshold, other ports are set to the ASPM L1.1 or L1.2 low power consumption sub-state in sequence until the current temperature does not exceed the maximum temperature threshold. 6. A PCIe system temperature control device, comprising: Temperature monitoring unit, used to monitor the current temperature of the PCIe system in real time; A first control unit, configured to modify a timer value of the first low power consumption state of the corresponding ASPM module when the current temperature exceeds a preset warning temperature threshold, if the target link is not in the first low power consumption state, so as to shorten the time for the target link to enter the first low power consumption state; a second control unit, configured to, when the current temperature exceeds a preset maximum temperature threshold, set the target link to a second low power consumption state when the target link has been set to a first low power consumption state, and to reduce a link rate of the target link when the target link is not in the first low power consumption state, wherein the maximum temperature threshold is higher than the warning temperature threshold, and the power consumption of the second low power consumption state is lower than that of the first low power consumption state; The third control unit is used to restore the port states in the first low power consumption state and the second low power consumption state to the normal power consumption state when the current temperature is lower than the preset minimum temperature threshold, and restore the rate of the port whose link rate is reduced. 7. The PCIe system temperature control device according to claim 6, wherein the first control unit is further configured to: After the target link is set to the first low power consumption state, if the current temperature is lower than the warning temperature threshold, the timer value of the first low power consumption state of the ASPM module is changed back to a default value. 8. The PCIe system temperature control device according to claim 6, wherein the second control unit is further configured to: A speed reduction or lane reduction operation is started on the target link. If the current temperature still exceeds the maximum temperature threshold, speed reduction or lane reduction operations are performed on other ports in turn until the current temperature does not exceed the maximum temperature threshold. 9. The PCIe system temperature control device according to claim 6, wherein the first low power consumption state is an ASPM L1 low power consumption state, and the second low power consumption state is an ASPM L1.1 or L1.2 low power consumption sub-state. 10. The PCIe system temperature control device according to claim 9, wherein the second control unit is further configured to: The target link is set to the ASPM L1.1 or L1.2 low power consumption sub-state. If the current temperature still exceeds the maximum temperature threshold, other ports are set to the ASPM L1.1 or L1.2 low power consumption sub-state in sequence until the current temperature does not exceed the maximum temperature threshold.