CN118039464A - Ion implantation method for reducing silicon carbide surface damage and silicon carbide device - Google Patents

Abstract

An ion implantation method and silicon carbide device for reducing damage to the silicon carbide surface include: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer; performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern; performing annealing on the first mask dielectric layer to form a dense and uniform first mask dielectric layer; performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer; wherein the second mask dielectric layer and the first mask dielectric layer have different thicknesses and materials. In the present invention, two layers of dielectric films are used for ion implantation. Due to the presence of the first mask dielectric layer, when etching the second mask dielectric layer, the etching can be stopped at the place where the etching of the second mask dielectric layer is completed. The remaining first mask dielectric layer can prevent the etching ions and the implanted ions from bombarding the surface of the silicon carbide wafer and causing damage.

Description

An ion implantation method for reducing silicon carbide surface damage and silicon carbide device

Technical Field

The present invention belongs to the technical field of SiC semiconductor power device process preparation, and in particular relates to an ion implantation method for reducing silicon carbide surface damage and a silicon carbide device.

Background technique

In the past two decades, due to the excellent material properties of silicon carbide (SiC), power devices based on SiC have developed rapidly in many aspects such as academic research and technical manufacturing. SiC semiconductor materials are the third generation of wide bandgap semiconductor materials developed after the first generation of elemental semiconductor materials (Si) and the second generation of compound semiconductor materials (GaAs, GaP, InP). 4H-SiC has a large bandgap width, high critical breakdown field strength, large saturation drift velocity and good thermal conductivity. The commonality of the third generation wide bandgap semiconductors is that they have a large bandgap width. The bandgap width of 4H-SiC is 3.26eV, which is basically three times the bandgap width of Si. At 300K, the intrinsic carrier concentration of Si is 1.4x1010cm-3, while the intrinsic carrier concentration of 4H-SiC under the same conditions is only 6.7x10-11cm-3. The critical breakdown field strength of 4H-SiC is 10 times that of traditional semiconductor Si. For the same breakdown voltage, the drift region of 4H-SiC devices can use a higher doping concentration and a smaller thickness. Compared with Si, 4H-SiC devices have a smaller specific on-state resistance in the drift region when turned on. In addition, when applying power electronic devices, reducing the number of devices in series can also achieve the required blocking voltage. 4H-SiC has a large electron saturation velocity and a large switching speed, which has obvious advantages over Si in high-frequency applications. Higher thermal conductivity has a greater effect on the application of 4H-SiC in high-density power devices, effectively simplifying the cooling system and reducing costs.

In traditional device processes, common doping methods include diffusion and ion implantation. In SiC, due to its strong chemical bonds, the diffusion constant of doped impurities is very small even above 1600°C. Due to the strong molecular bond energy of SiC and the extremely low diffusion constant of impurities in SiC, it is unrealistic to achieve regional selective doping using a diffusion process. Therefore, ion implantation is a key process for preparing SiC devices, and ion implantation is a very important step in the selective regional doping technology in the manufacturing process of silicon carbide devices. The principle is to inject an ion beam accelerated to a certain high energy into the surface layer of a solid material through a high electric field, and stop the ions at a specific position. For each ion injected into a solid material, it must collide with the nuclei and electrons of the original material. The ions will lose energy while colliding. After several collisions, the ions will stay in the substrate for a section of the path they have traveled.

However, when the doped ions in the ion implantation process bombard silicon carbide, the crystal structure of the wafer is damaged due to the collision of the incident ions. A common defect caused by ion implantation is vacancy-interstitial. When the implanted ions collide with the atoms of the original material, energy is lost and eventually stops at a certain depth. At the same time, the atoms of the original material that are hit are also knocked out of their original positions and stay in non-lattice positions, and vacancy-interstitial defects are generated. When the implantation dose is high, as the ion implantation bombardment continues, the implanted ions collide more and more with the target atoms, and the proportion of target atoms lost in the lattice of the implanted area continues to increase. When the impurity atoms and target atoms in the lattice interstitial occupy the main body, the dislocation-intensive area may become amorphous. In order to restore the lattice to the crystal form and repair point defects such as vacancies, a high-temperature annealing process needs to be introduced. The higher the implantation dose, the easier it is for the target material closer to the surface to be bombarded into an amorphous state, and it may even be impossible to repair it by high-temperature annealing.

After silicon carbide is implanted, the surface is prone to form an amorphous state and is difficult to repair, resulting in damage, which leads to abnormal interfaces in the subsequent device preparation process and incomplete process presentation. For example, problems such as low gate oxide mobility due to excessive interface state density or metal shedding due to rough surface may occur. Therefore, how to solve the implantation surface damage and reduce the problems caused by the interface has become an urgent problem to be solved.

Summary of the invention

In order to overcome the above-mentioned deficiencies of the prior art, the present invention proposes an ion implantation method for reducing surface damage of silicon carbide, comprising:

sequentially growing a first mask dielectric layer and a second mask dielectric layer on the silicon carbide wafer;

Performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer having a preset pattern;

Performing annealing treatment on the first mask dielectric layer to form a dense and uniform first mask dielectric layer;

Performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer;

The second mask dielectric layer and the first mask dielectric layer have different thickness and material.

Preferably, the thickness of the second mask dielectric layer is 1.0 um to 3.5 um.

Preferably, the material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG and PSG.

Preferably, the gas used for dry etching the second mask dielectric layer is a fluorine-based gas.

Preferably, the gas flow rate range for dry etching the second mask dielectric layer is 10 sccm to 80 sccm.

Preferably, the power range of dry etching the second mask dielectric layer is 40W-100W.

Preferably, the thickness of the first mask dielectric layer is 30 nm to 60 nm.

Preferably, the material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG and PSG.

Preferably, the step of dry etching the second mask dielectric layer to obtain the second mask dielectric layer having a preset pattern comprises:

Spin-coating a photoresist film on the second mask dielectric layer, exposing, developing and hardening the photoresist film through a photomask with a preset pattern, and forming a photoresist film with a preset pattern on the second mask dielectric layer;

The second mask dielectric layer is dry-etched through the photoresist film to obtain a second mask dielectric layer with a preset pattern.

Preferably, the temperature range of the annealing treatment on the first mask dielectric layer is 900° C. to 1100° C.

Preferably, the annealing treatment time ranges from 10 min to 1 h.

Based on the same inventive concept, the present invention also provides a silicon carbide device for reducing surface damage of silicon carbide, the silicon carbide device comprising: a silicon carbide wafer, a first mask dielectric layer on the silicon carbide wafer, a second mask dielectric layer located on the first mask dielectric layer, and an ion implantation region located on the silicon carbide wafer;

Wherein, the ion implantation area is obtained according to the ion implantation method for reducing surface damage of silicon carbide.

Preferably, the thickness of the first mask dielectric layer is 30 nm to 60 nm.

Preferably, the material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG and PSG.

Preferably, the thickness of the second mask dielectric layer is 1.0 um to 3.5 um.

Preferably, the material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG and PSG.

Preferably, the ion implantation region is a silicon carbide wafer region corresponding only to the first mask dielectric layer.

Compared with the closest prior art, the present invention has the following beneficial effects:

1. An ion implantation method and a silicon carbide device for reducing surface damage of silicon carbide, comprising: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer; performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern; performing annealing on the first mask dielectric layer to form a dense and uniform first mask dielectric layer; performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer; wherein the second mask dielectric layer and the first mask dielectric layer have different thicknesses and materials. In the present invention, two layers of dielectric films are used for ion implantation. Due to the presence of the first mask dielectric layer, when etching the second mask dielectric layer, the etching can be stopped at the place where the etching of the second mask dielectric layer is completed, so that the remaining first mask dielectric layer can prevent the etching ions and the implanted ions from bombarding the surface of the silicon carbide wafer and causing damage, thereby reducing the surface roughness of the silicon carbide wafer and preventing the subsequent processes such as the growth quality of the passivation layer film and the metal film from being affected.

2. The present invention adopts two layers of dielectric films for ion implantation, which can make the ion implantation depth and longitudinal ion concentration controllable. The presence of two layers of dielectrics prevents over-etching of silicon carbide and surface damage of silicon carbide caused by ion implantation. On this basis, the implantation process is controllable and the stability of the process is enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of an ion implantation method for reducing surface damage of silicon carbide provided by the present invention;

FIG2 is a schematic diagram of the structure of a pre-cleaned silicon carbide wafer according to the present invention;

FIG3 is a schematic diagram of the structure of a silicon carbide wafer on which a first mask dielectric layer is grown in the present invention;

FIG4 is a schematic diagram of the structure of a silicon carbide wafer on which a second mask dielectric layer is grown in the present invention;

FIG5 is a schematic diagram of the structure of a silicon carbide wafer with spin-coated photoresist in the present invention;

FIG6 is a schematic diagram of the structure of a silicon carbide wafer after etching to form a second mask dielectric layer with a preset pattern in the present invention;

FIG7 is a silicon carbide device structure capable of reducing silicon carbide surface damage formed by debonding-annealing-ion implantation according to the present invention;

FIG8 is a schematic diagram of the surface structure of a silicon carbide wafer after only a single-layer mask is implanted;

FIG9 is a surface structure of a silicon carbide wafer implanted through a double mask layer and retaining the first mask layer;

Description of the drawings:

1-silicon carbide wafer; 2-first mask dielectric layer; 3-second mask dielectric layer; 4-photoresist.

Detailed ways

The specific implementation modes of the present invention are further described in detail below with reference to the accompanying drawings.

Embodiment 1:

An ion implantation method for reducing surface damage of silicon carbide provided by the present invention is shown in FIG1 , comprising:

Step 1: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer;

Step 2: performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer having a preset pattern;

Step 3: performing annealing treatment on the first mask dielectric layer to form a dense and uniform first mask dielectric layer;

Step 4: performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer;

The second mask dielectric layer and the first mask dielectric layer have different thickness and material.

Specifically, before step 1, the surface of the silicon carbide wafer is pretreated to remove organic contamination and particles on the surface of the silicon carbide wafer. The cleaned silicon carbide wafer 1 is shown in FIG2 ;

The cleaning solutions and corresponding cleaning times required for pre-cleaning the silicon carbide wafer are: 3#-10 to 30 min, 1#-10 to 30 min, and hydrofluoric acid (DHF)-10 to 30 min.

Specifically, the step 2 includes: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer;

sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer by LPCVD or PECVD;

The thickness of the first mask dielectric layer 2 is 30 nm to 60 nm, and the silicon carbide wafer structure for growing the first mask dielectric layer is shown in FIG3 ;

The material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG and PSG;

The thickness of the second mask dielectric layer 3 is 1.0 um to 3.5 um, and the silicon carbide wafer structure for growing the first mask dielectric layer is shown in FIG4 ;

The material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG and PSG;

The first mask dielectric layer is relatively thin, and the second mask dielectric layer mainly acts as an injection mask, and its thickness is related to the injection conditions;

The first mask dielectric layer serves as a stopper during dry etching of the second mask dielectric layer and as a buffer during high-temperature ion implantation.

Specifically, the steps include: spin coating a photoresist film 4 on the second mask dielectric layer, exposing, developing and hardening the photoresist film through a photomask having a preset pattern, and forming a photoresist film having a preset pattern on the second mask dielectric layer, as shown in FIG. 5 ;

The second mask dielectric layer is dry-etched through the photoresist film to obtain a second mask dielectric layer having a preset pattern, as shown in FIG6 ;

The gas used for dry etching the second mask dielectric layer is a fluorine-based gas;

The gas flow rate range for dry etching the second mask dielectric layer is: 10 sccm to 80 sccm;

The power range of dry etching the second mask dielectric layer is: 40W to 100W;

Among them, the thickness range of the photoresist film is 1.5um~2.8um; the exposure time range is 280~320mes, and the exposure distance range is 0.2~0.2um; the development adopts dynamic development method, and the development time range is 60~120s; the hardening time range is 60~240s, and the hardening temperature range is 90~120℃.

Due to the existence of the first mask dielectric layer, when etching the second mask dielectric layer, the etching can be stopped at the place where the second mask dielectric layer is etched. In this way, the remaining first mask dielectric layer can prevent the etching ions and the implanted ions from bombarding the surface of the silicon carbide wafer and causing damage, thereby reducing the surface roughness of the silicon carbide wafer and preventing subsequent processes such as the growth quality of the passivation layer film and the metal film from being affected.

Specifically, the step 3 includes: performing annealing treatment on the first mask dielectric layer to form a dense and uniform first mask dielectric layer;

The temperature range of the annealing treatment on the first mask dielectric layer is: 900° C. to 1100° C.;

The time range of the annealing treatment is: 10min～1h;

Specifically, the step 4 includes: performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer;

Since the single-step implantation ion concentration and depth present a Gaussian distribution, multi-step implantation is generally used to form a box-type structure. Generally, Al ions are used for P-type implantation and N ions are used for N-type implantation. Different energies can be selected to determine the implantation depth;

The structure of a silicon carbide device capable of reducing surface damage of silicon carbide after cleaning to remove the photoresist and then annealing and ion implantation is shown in FIG. 7 .

Among them, the above method mainly uses the following consumables and equipment:

Consumables:

a. Photoresist is a light-sensitive liquid organic compound composed of photosensitive resin, tackifier and solvent. After it is exposed to ultraviolet light, its solubility in the developing solution will change.

b. The main component of the developer is the developer, which has different solubility in exposed and unexposed photoresists.

c. Polycrystalline silicon is a form of elemental silicon. When molten elemental silicon solidifies under supercooling conditions, silicon atoms are arranged in the form of diamond lattices to form many crystal nuclei. If these crystal nuclei grow into grains with different crystal plane orientations, these grains will combine and crystallize into polycrystalline silicon. Polycrystalline silicon generally uses F-containing etchants, but its etching is generally isotropic. In order to obtain good anisotropy, _O2 , _H2 , chloride or bromide are added. However, H2 etching will cause etching of silicon oxide. Therefore, in order to obtain good anisotropy of polycrystalline silicon etching and a high etching selectivity with silicon oxide, chloride or bromide gas is generally used.

d. Silicon oxide has the characteristics of high hardness, good wear resistance, good thermal insulation and strong corrosion resistance. Generally, silicon dioxide is etched using fluorine-based or chlorine-based gases, which produce fluorine ions or chloride ions in the glow discharge and react with the surface silicon dioxide.

equipment:

a.LPCVD: Low pressure chemical vapor deposition is widely used for silicon oxide, nitride, and polysilicon deposition. The process is performed in a tube furnace and requires a fairly high temperature.

b.PECVD: It uses microwaves or radio frequencies to ionize the gas containing the atoms of the film components, forming plasma locally. The plasma has strong chemical activity and is easy to react, depositing the desired film on the substrate. In order to make the chemical reaction proceed at a lower temperature, the activity of the plasma is used to promote the reaction, so this type of CVD is called plasma enhanced chemical vapor deposition. It has good film quality, fast deposition rate, small pinholes, and is not easy to crack.

c. Stepper lithography machine: The exposure system irradiates the mask through a slit exposure belt (slit), and the workpiece stage carrying the mask moves in one direction under the slit, which is equivalent to the exposure system scanning the mask.

d.ICP etcher: The full name is inductively coupled plasma etcher, which is an indispensable equipment in the micro-nano processing of semiconductor chips. It can process micro-patterns at the micron and nano levels. There are two types of etching in the process of etching semiconductor materials with etching gases: physical etching and chemical etching. Physical etching uses ions to bombard the surface of the wafer for etching. It has directionality. If the etching effect is too strong, it will form an inverted frustum-shaped etching result; chemical etching uses ions and the surface of the wafer to react chemically. It has no directionality. If the etching effect is too strong, it will etch under the mask. When physical etching and chemical etching are balanced, the ideal and required vertical etching effect can be obtained.

e. Cleaning and drying machine: used to remove the photoresist mask after etching. Since dry etching will burn the photoresist, acidic solution is generally used for removal.

f. High-temperature ion implantation: In view of the ion doping characteristics of silicon carbide, high-temperature ion implantation is generally used. Therefore, photoresist cannot be used as an implantation mask, and a hard mask is required as a mask layer. The high-temperature ion implanter heats the wafer during implantation to achieve P-type and N-type SiC doping processes with good surface characteristics and electrical properties.

In a specific embodiment, according to the above-mentioned ion implantation method steps for reducing surface damage of silicon carbide, a first mask dielectric layer made of polycrystalline silicon and having a thickness ranging from 30 to 60 nm is first grown on the pretreated silicon carbide wafer by LPCVD;

And growing a second mask dielectric layer made of silicon oxide and having a thickness ranging from 1 to 3.5 um on the first mask dielectric layer by PECVD;

Spin-coating a photoresist with a thickness ranging from 1.5 to 2.8 um on the second mask dielectric layer, and exposing, developing and hardening the photoresist through a photomask with a preset pattern;

The exposure time ranges from 280 to 320 mes, and the exposure distance ranges from 0.2 to 0.2 um; the development adopts a dynamic development method, and the development time ranges from 60 to 120 s; the film hardening time ranges from 60 to 240 s, and the film hardening temperature ranges from 90 to 120°C;

Etching the second mask dielectric layer based on the photoresist after the photolithography process, and cleaning and removing the photoresist;

Among them, the solution for removing the photoresist and the corresponding processing time are: 3#-10～30min, 1#-10～30min;

Finally, the first mask dielectric layer is subjected to high temperature annealing in the annealing range of 900° C. to 1100° C. and the corresponding annealing time is 10 min to 1 h;

After annealing, Al ion implantation is performed based on the first mask dielectric layer and the second mask dielectric layer. The Al ion implantation energy and dose are shown in Table 1 below:

Table 1

energy 500kev 400kev 300kev 200kev 100kev dose 8e13 6e13 6e13 4e13 2e13

In a specific embodiment, according to the above-mentioned ion implantation method steps for reducing surface damage of silicon carbide, a first mask dielectric layer made of polycrystalline silicon and having a thickness ranging from 30 to 60 nm is first grown on the pretreated silicon carbide wafer by LPCVD;

And growing a second mask dielectric layer made of silicon oxide and having a thickness ranging from 1 to 3.5 um on the first mask dielectric layer by PECVD;

Spin-coating a photoresist with a thickness ranging from 1.5 to 2.8 um on the second mask dielectric layer, and exposing, developing and hardening the photoresist through a photomask with a preset pattern;

The exposure time ranges from 280 to 320 mes, and the exposure distance ranges from 0.2 to 0.2 um; the development adopts a dynamic development method, and the development time ranges from 60 to 120 s; the film hardening time ranges from 60 to 240 s, and the film hardening temperature ranges from 90 to 120°C;

Etching the second mask dielectric layer based on the photoresist after the photolithography process, and cleaning and removing the photoresist;

Among them, the solution for removing the photoresist and the corresponding processing time are: 3#-10～30min, 1#-10～30min;

Finally, the first mask dielectric layer is subjected to high temperature annealing in the annealing range of 900° C. to 1100° C. and the corresponding annealing time is 10 min to 1 h;

After the annealing is completed, N ion implantation is performed based on the first mask dielectric layer and the second mask dielectric layer. The N ion implantation energy and dose are shown in Table 2 below:

Table 2

energy 250kev 160kev 80kev dose 1e14 8e13 6e13

In a specific embodiment, due to the presence of the first mask dielectric layer, when etching the second mask dielectric layer, the etching can be stopped at the place where the second mask dielectric layer is etched, so that the remaining first mask dielectric layer can prevent the etching ions and the implanted ions from bombarding the surface of the silicon carbide wafer and causing damage, thereby reducing the surface roughness of the silicon carbide wafer and preventing the subsequent processes such as the growth quality of the passivation layer film and the metal film from being affected;

Among them, under different implantation conditions, the surface roughness measurement results of silicon carbide wafers after implantation with single/double-layer implantation masks are shown in Table 3:

table 3

In summary, the surface of the silicon carbide wafer is rougher after only the single-layer mask injection, and the surface of the device silicon carbide wafer retains the smooth etched surface of the first mask layer after the double-layer mask injection. The surface structure of the silicon carbide wafer after only the single-layer mask injection is shown in Figure 8;

The surface structure of a silicon carbide wafer implanted through a double-layer mask and retaining the first mask layer is shown in FIG9 .

Embodiment 2:

The structure diagram of a silicon carbide device for reducing silicon carbide surface damage provided by the present invention is shown in FIG4 , and includes:

A silicon carbide wafer, a first mask dielectric layer on the silicon carbide wafer, a second mask dielectric layer located on the first mask dielectric layer, and an ion implantation region located on the silicon carbide wafer;

Wherein, the ion implantation area is obtained according to the ion implantation method for reducing surface damage of silicon carbide;

The thickness of the first mask dielectric layer is: 30nm-60nm;

The material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG and PSG;

The thickness of the second mask dielectric layer is: 1.0um to 3.5um;

The material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG and PSG;

The ion implantation region is a silicon carbide wafer region corresponding only to the first mask dielectric layer.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that after reading the present invention, those skilled in the art can still make various changes, modifications or equivalent substitutions to the specific implementation methods of the application, but these changes, modifications or equivalent substitutions are all within the protection scope of the claims to be approved.

Claims (17)

1. An ion implantation method for reducing surface damage of silicon carbide, characterized by comprising: sequentially growing a first mask dielectric layer and a second mask dielectric layer on the silicon carbide wafer; Performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer having a preset pattern; Performing annealing treatment on the first mask dielectric layer to form a dense and uniform first mask dielectric layer; Performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer; The second mask dielectric layer and the first mask dielectric layer have different thickness and material. 2 . The method according to claim 1 , wherein the thickness of the second mask dielectric layer is 1.0 um to 3.5 um. 3 . The method according to claim 2 , wherein a material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG and PSG. 4 . The method according to claim 3 , wherein the gas used for dry etching the second mask dielectric layer is a fluorine-based gas. 5 . The method according to claim 4 , wherein the gas flow rate for dry etching the second mask dielectric layer is in the range of 10 sccm to 80 sccm. 6 . The method according to claim 5 , wherein the power range of dry etching the second mask dielectric layer is 40 W to 100 W. 7 . The method according to claim 1 , wherein the thickness of the first mask dielectric layer is 30 nm to 60 nm. 8 . The method according to claim 7 , wherein a material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG, and PSG. 9. The method according to claim 1, wherein the step of dry etching the second mask dielectric layer to obtain the second mask dielectric layer having a preset pattern comprises: Spin-coating a photoresist film on the second mask dielectric layer, exposing, developing and hardening the photoresist film through a photomask with a preset pattern, and forming a photoresist film with a preset pattern on the second mask dielectric layer; The second mask dielectric layer is dry-etched through the photoresist film to obtain a second mask dielectric layer with a preset pattern. 10. The method according to claim 1, wherein the temperature range of annealing the first mask dielectric layer is 900°C to 1100°C. 11. The method according to claim 10, characterized in that the time range of the annealing treatment is: 10 minutes to 1 hour. 12. A silicon carbide device for reducing silicon carbide surface damage, characterized in that the silicon carbide device comprises: a silicon carbide wafer, a first mask dielectric layer on the silicon carbide wafer, a second mask dielectric layer located on the first mask dielectric layer, and an ion implantation region located on the silicon carbide wafer; Wherein, the ion implantation area is obtained according to an ion implantation method for reducing surface damage of silicon carbide as described in claims 1-14. 13 . The silicon carbide device according to claim 12 , wherein the thickness of the first mask dielectric layer is 30 nm to 60 nm. 14 . The silicon carbide device according to claim 13 , wherein a material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG and PSG. 15 . The silicon carbide device according to claim 12 , wherein the thickness of the second mask dielectric layer is 1.0 um to 3.5 um. 16 . The silicon carbide device according to claim 15 , wherein a material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG and PSG. 17 . The silicon carbide device according to claim 12 , wherein the ion implantation region is a silicon carbide wafer region corresponding only to the first mask dielectric layer.