CN118039464A - Ion implantation method for reducing silicon carbide surface damage and silicon carbide device - Google Patents
Ion implantation method for reducing silicon carbide surface damage and silicon carbide device Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 114
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 105
- 238000005468 ion implantation Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 44
- 150000002500 ions Chemical class 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 23
- 238000001312 dry etching Methods 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 230000000873 masking effect Effects 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 7
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 125000001153 fluoro group Chemical group F* 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 28
- 239000010410 layer Substances 0.000 description 134
- 238000002513 implantation Methods 0.000 description 15
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- 238000004140 cleaning Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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Abstract
An ion implantation method for reducing silicon carbide surface damage and a silicon carbide device, comprising: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer; performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern; annealing the first mask dielectric layer to form a compact and uniform first mask dielectric layer; performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer; the second mask medium layer is different from the first mask medium layer in thickness and material. In the invention, two layers of dielectric films are adopted for ion implantation, and due to the existence of the first mask dielectric layer, the second mask dielectric layer can be automatically cut off at the position where the etching of the second mask dielectric layer is finished when the second mask dielectric layer is etched, and the residual first mask dielectric layer can prevent etching ions and implanted ions from damaging the surface bombardment of the silicon carbide wafer.
Description
Technical Field
The invention belongs to the technical field of SiC semiconductor power device process preparation, and particularly relates to an ion implantation method for reducing silicon carbide surface damage and a silicon carbide device.
Background
For the last two decades, due to the excellent material properties of silicon carbide (SiC), siC-based power devices have been rapidly developed in many fields such as academic research and technical manufacturing. The SiC semiconductor material is a third generation wide band gap semiconductor material developed from the first generation elemental semiconductor material (Si) and the second generation compound semiconductor material (GaAs, gaP, inP). The 4H-SiC has large forbidden bandwidth, high critical breakdown field strength, large saturation drift speed and good thermal conductivity. The third generation wide bandgap semiconductor has the common characteristic of having a larger bandgap, the bandgap of 4H-SiC is 3.26eV which is basically 3 times of the bandgap of Si, the intrinsic carrier concentration of Si at 300K is 1.4x1010cm < -3 >, and the intrinsic carrier concentration of 4H-SiC under the same conditions is only 6.7x10 < -11 > cm < -3 >. The critical breakdown field strength of 4H-SiC is 10 times that of the traditional semiconductor Si, and for the same breakdown voltage, the drift region of the 4H-SiC device can use higher doping concentration and smaller thickness, and compared with Si, the drift region of the 4H-SiC device has smaller specific on-state resistance when being conducted. In addition, when power electronics are used, the required blocking voltage can be achieved by reducing the number of components connected in series. The electron saturation velocity of 4H-SiC is larger, the switching speed is larger, and the 4H-SiC has obvious advantages in high-frequency application compared with Si. The higher heat conductivity has great effect on the application of 4H-SiC to high-density power devices, effectively simplifies a cooling system and reduces the cost.
In conventional device processing, common doping approaches include diffusion and ion implantation. In SiC, the diffusion constant of doped impurities is very small, even above 1600 c, due to its strong chemical bonds. Because of the strong molecular bond energy of SiC and the extremely low diffusion constant of impurities within SiC, it is impractical to achieve region-selective doping with diffusion processes. Ion implantation is therefore a critical process for the fabrication of SiC devices, which is a very important step in the selective area doping technique in the silicon carbide device fabrication process. The principle is that an ion beam accelerated to a certain high energy is injected into the surface layer of a solid material by a high electric field, and the ions are stopped at a specific position. For each ion injected into the solid material, the ion collides with atomic nucleus and electrons of the original material, energy is lost when the ion collides, and after a plurality of collisions, the ion stays in the substrate along a path.
However, the wafer crystal structure is damaged by the impact of the incident ions when the doped ions in the ion implantation process bombard the silicon carbide. A common defect created by ion implantation is vacancy-interstitial. When the implanted ions collide with the original material atoms, energy is lost, and finally the ion implantation is stopped at a certain depth. At the same time, the impacted original material atoms are impacted out of position and stay at non-lattice positions, so that vacancy-interstitial defects are generated. When the implantation dose is higher, as the ion implantation bombardment continues, the collisions of the implanted ions with the target atoms are more and more, and the target atom fraction of lattice loss in the implanted region continues to increase. When impurity atoms and target atoms of the lattice gap occupy the host, the dislocation-concentrated region may become amorphous. In order to restore the crystal lattice to the crystal morphology and repair point defects such as vacancies, a high temperature annealing process is required. The higher the implantation dose, the more likely the target material near the surface is bombarded into an amorphous state, and is not even repairable by high temperature annealing.
Because amorphous state is easy to form on the surface after silicon carbide implantation, and is not easy to repair, damage is caused, interface between the silicon carbide and the silicon carbide is abnormal in the subsequent device preparation process, the process cannot be completely presented, and the problems of excessively low gate oxide mobility or metal falling off due to rough surface and the like can occur, for example. Therefore, how to solve the damage of the implantation surface and reduce the problems caused by the interface is a urgent problem to be solved.
Disclosure of Invention
In order to overcome the above-mentioned shortcomings in the prior art, the present invention provides an ion implantation method for reducing silicon carbide surface damage, comprising:
Sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer;
performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern;
annealing the first mask dielectric layer to form a compact and uniform first mask dielectric layer;
Performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer;
the second mask medium layer is different from the first mask medium layer in thickness and material.
Preferably, the thickness of the second mask dielectric layer is as follows: 1.0um to 3.5um.
Preferably, the material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG, and PSG.
Preferably, the gas used for dry etching the second mask dielectric layer is fluorine-containing gas.
Preferably, the gas flow range of dry etching the second mask dielectric layer is as follows: 10sccm to 80sccm.
Preferably, the power range of dry etching the second mask dielectric layer is as follows: 40W-100W.
Preferably, the thickness of the first mask dielectric layer is as follows: 30 nm-60 nm.
Preferably, the material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG, and PSG.
Preferably, the dry etching the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern includes:
Spin-coating a photoresist film on the second mask medium layer, exposing, developing and hardening the photoresist film through a photoetching plate with a preset pattern, and forming the photoresist film with the preset pattern on the second mask medium layer;
and carrying out dry etching on the second mask dielectric layer through the photoresist film to obtain the second mask dielectric layer with the preset pattern.
Preferably, the temperature range of the annealing treatment of the first mask dielectric layer is as follows: 900-1100 ℃.
Preferably, the annealing treatment time range is as follows: and the time is 10 min-1 h.
Based on the same inventive concept, the present invention also provides a silicon carbide device for reducing damage to a silicon carbide surface, the silicon carbide device comprising: the silicon carbide wafer, a first mask dielectric layer on the silicon carbide wafer, a second mask dielectric layer on the first mask dielectric layer and an ion implantation region on the silicon carbide wafer;
the ion implantation area is obtained according to the ion implantation method for reducing the damage of the silicon carbide surface.
Preferably, the thickness of the first mask dielectric layer is as follows: 30 nm-60 nm.
Preferably, the material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG, and PSG.
Preferably, the thickness of the second mask dielectric layer is as follows: 1.0um to 3.5um.
Preferably, the material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG, and PSG.
Preferably, the ion implantation region is a silicon carbide wafer region corresponding to only the first mask dielectric layer.
Compared with the closest prior art, the invention has the following beneficial effects:
1. An ion implantation method for reducing silicon carbide surface damage and a silicon carbide device, comprising: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer; performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern; annealing the first mask dielectric layer to form a compact and uniform first mask dielectric layer; performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer; the second mask medium layer is different from the first mask medium layer in thickness and material. In the invention, two layers of dielectric films are adopted for ion implantation, and due to the existence of the first mask dielectric layer, the second mask dielectric layer can be automatically cut off at the position where the etching of the second mask dielectric layer is completed when the second mask dielectric layer is etched, so that the residual first mask dielectric layer can prevent etching ions and implanted ions from damaging the surface bombardment of the silicon carbide wafer, thereby reducing the surface roughness of the silicon carbide wafer and preventing the growth quality of subsequent processes such as passivation layer films and metal films from being influenced.
2. According to the invention, the ion implantation is carried out by adopting the two layers of dielectric films, so that the ion implantation depth and the longitudinal ion concentration can be controlled, the existence of the two layers of dielectric films prevents the overetching of silicon carbide and the surface damage of the silicon carbide caused by the ion implantation, the implantation process is controllable on the basis, and the process stability is enhanced.
Drawings
FIG. 1 is a flow chart of an ion implantation method for reducing silicon carbide surface damage provided by the invention;
FIG. 2 is a schematic diagram of a pre-cleaned silicon carbide wafer according to the present invention;
FIG. 3 is a schematic view of a silicon carbide wafer grown with a first masking dielectric layer according to the present invention;
FIG. 4 is a schematic view of a silicon carbide wafer grown with a second masking dielectric layer according to the present invention;
FIG. 5 is a schematic view of a silicon carbide wafer spin-coated with photoresist according to the present invention;
FIG. 6 is a schematic view of a silicon carbide wafer etched to form a second mask dielectric layer with a predetermined pattern according to the present invention;
FIG. 7 illustrates the formation of a silicon carbide device structure capable of reducing silicon carbide surface damage via photoresist stripping-annealing-ion implantation in accordance with the present invention;
FIG. 8 is a schematic view of the surface structure of a silicon carbide wafer after single layer mask implantation;
FIG. 9 is a silicon carbide wafer surface structure implanted through a bilayer mask and retaining a first mask layer;
Description of the drawings:
1-silicon carbide wafer; 2-a first mask medium layer; 3-a second mask medium layer; 4-photoresist.
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to the drawings.
Example 1:
The invention provides an ion implantation method for reducing silicon carbide surface damage, which is shown in figure 1, and comprises the following steps:
step 1: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer;
Step 2: performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern;
step 3: annealing the first mask dielectric layer to form a compact and uniform first mask dielectric layer;
Step 4: performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer;
the second mask medium layer is different from the first mask medium layer in thickness and material.
Specifically, the method further comprises the steps of preprocessing the surface of the silicon carbide wafer to remove organic contamination and particles on the surface of the silicon carbide wafer, wherein the cleaned silicon carbide wafer 1 is shown in fig. 2;
The cleaning solution and the corresponding cleaning time required for pre-cleaning the silicon carbide wafer are respectively as follows: 3-30 min, 1-10-30 min and hydrofluoric acid (DHF) -10-30 min.
Specifically, the step 2 includes: sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer;
sequentially growing a first mask dielectric layer and a second mask dielectric layer on the silicon carbide wafer by LPCVD or PECVD;
The thickness of the first mask medium layer 2 is as follows: the silicon carbide wafer structure for growing the first mask dielectric layer is shown in figure 3, and the silicon carbide wafer structure is 30-60 nm;
the material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG, and PSG;
the thickness of the second mask medium layer 3 is as follows: 1.0um to 3.5um, and the silicon carbide wafer structure for growing the first mask dielectric layer is shown in figure 4;
the material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG, and PSG;
the first mask medium layer is thinner, the second mask medium layer mainly plays a role of injecting a mask, and the thickness is related to injection conditions;
The first mask medium layer has the function of stopping in dry etching of the second mask medium layer and has the function of buffering in high-temperature ion implantation.
Specifically, the steps include: spin-coating a photoresist film 4 on the second mask medium layer, exposing, developing and hardening the photoresist film through a photoetching plate with a preset pattern, and forming the photoresist film with the preset pattern on the second mask medium layer, as shown in fig. 5;
Carrying out dry etching on the second mask dielectric layer through the photoresist film to obtain a second mask dielectric layer with a preset pattern, as shown in fig. 6;
the gas adopted by the dry etching of the second mask dielectric layer is fluorine-containing gas;
The gas flow range of the dry etching of the second mask dielectric layer is as follows: 10sccm to 80sccm;
the power range of the dry etching of the second mask dielectric layer is as follows: 40W-100W;
Wherein, the thickness range of the photoresist film is 1.5 um-2.8 um; the exposure time ranges from 280 to 320mes, and the distance between the exposure time and the focal length (Focus) ranges from 0.2 to 0.2um; the development adopts a dynamic development mode, and the development time range is 60-120 s; the hardening time ranges from 60 to 240s, and the hardening temperature ranges from 90 to 120 ℃.
Due to the existence of the first mask dielectric layer, the second mask dielectric layer can be automatically cut off at the position where the etching of the second mask dielectric layer is completed when the second mask dielectric layer is etched, so that the residual first mask dielectric layer can prevent etching ions and implanted ions from damaging the surface bombardment of the silicon carbide wafer, thereby reducing the surface roughness of the silicon carbide wafer and preventing the growth quality of subsequent processes such as passivation layer films and metal films from being influenced.
Specifically, the step 3 includes: annealing the first mask dielectric layer to form a compact and uniform first mask dielectric layer;
The temperature range for annealing the first mask medium layer is as follows: 900-1100 ℃;
The time range of the annealing treatment is as follows: 10 min-1 h;
Specifically, the step 4 includes: performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer;
because the concentration and depth of the single-step implanted ions show gaussian distribution, multi-step implantation is generally adopted to form a box-type structure. Al ions are adopted in general P-type injection, N ions are adopted in N-type injection, and different energies can be selected to determine injection depth;
the silicon carbide device structure capable of reducing the damage to the silicon carbide surface after removal of the photoresist by cleaning and then annealing and ion implantation is shown in fig. 7.
The method mainly uses the following consumables and equipment:
Consumable:
a. Photoresists are light-sensitive liquid organic compounds composed of a photosensitive resin, an adhesion promoter, and a solvent that undergo a change in solubility in a developing solution upon exposure to ultraviolet light.
B. the main component of the developer is a developer, and the solubility of the developer is different between the exposed photoresist and the unexposed photoresist.
C. polysilicon is a form of elemental silicon. When the melted elemental silicon solidifies under supercooling conditions, the silicon atoms are arranged in the form of diamond lattices into a plurality of crystal nuclei, and if the crystal nuclei grow into crystal grains with different crystal face orientations, the crystal grains combine to crystallize into polycrystalline silicon. The polysilicon is usually made of F-containing etchant, but the etching is isotropic, O 2、H2, chloride or bromide is selected to obtain good anisotropy, but H2 etching can cause silicon oxide etching, so that chloride or bromide gas is generally used to obtain good anisotropy of polysilicon etching and high etching selectivity to silicon oxide.
D. The silicon oxide has the characteristics of high hardness, good wear resistance, good heat insulation performance and strong erosion resistance. In general, the etching of silicon dioxide uses a gas containing fluorine or chlorine radicals, and generates fluorine ions or chlorine ions in glow discharge to react with the surface silicon dioxide.
The device comprises:
LPCVD: low pressure chemical vapor deposition is widely used for silicon oxide, nitride, polysilicon deposition, the process being performed in a tube furnace, which requires relatively high temperatures.
PECVD: the gas containing film component atoms is ionized by microwave or radio frequency, etc., plasma is formed locally, and the chemical activity of the plasma is strong, so that the reaction can easily occur, and the desired film can be deposited on the substrate. In order to enable chemical reactions to proceed at lower temperatures, the activity of the plasma is utilized to promote the reaction, and thus such CVD is called plasma-enhanced chemical vapor deposition. The film has good film forming quality, high deposition rate, small pinholes and difficult cracking.
C. Step-by-step lithography machine: the exposure system irradiates the mask with a slit type exposure belt (slit), and the workpiece table carrying the mask moves under the slit in one direction, which is equivalent to the exposure system scanning the mask.
Icp etcher: the inductively coupled plasma etching machine is an indispensable device in the micro-nano processing process of semiconductor chips, and can process micro-patterns with micron-scale and nano-scale. In the process of etching a semiconductor material by etching gas, there are two types of etching: physical etching and chemical etching. The physical etching is to bombard the surface of the wafer by utilizing ions to etch, and has directivity, and an inverted frustum-shaped etching result can be formed when the etching effect is too strong; the chemical etching is performed by utilizing chemical reaction between ions and the surface of the wafer, and has no directivity, and the etching effect is too strong and can be performed under the mask. When the physical etching and the chemical etching are balanced, ideal and required vertical etching effects can be obtained.
E. Cleaning and spin-drying machine: for removing the resist mask after etching, an acidic solution is generally used for removal because dry etching can burn the resist.
F. High temperature ion implantation: for the ion doping characteristic of silicon carbide, high-temperature ion implantation is generally adopted, so that photoresist cannot be used as an implantation mask, a hard mask is required to be used as a mask layer, and a high-temperature ion implanter can realize a P-type and N-type SiC doping process with good surface characteristics and electrical characteristics by heating a wafer during implantation.
In a specific embodiment, according to the above-mentioned ion implantation method for reducing the damage to the surface of silicon carbide, a first mask dielectric layer made of polysilicon and having a thickness ranging from 30 nm to 60nm is grown on the pretreated silicon carbide wafer by LPCVD;
growing a second mask medium layer which is made of silicon oxide and has the thickness ranging from 1 um to 3.5um on the first mask medium layer by PECVD;
spin-coating photoresist with the thickness range of 1.5-2.8 um on the second mask medium layer, and exposing, developing and hardening the photoresist through a photoetching plate with a preset pattern;
Wherein, the time range of the exposure time is 280-320 mes, and the distance range between the exposure time and the focal length (Focus) is 0.2-0.2 um; the development adopts a dynamic development mode, and the development time range is 60-120 s; the hardening time ranges from 60 to 240s, and the hardening temperature ranges from 90 to 120 ℃;
Etching the second mask dielectric layer based on the photoresist after the photoetching treatment, and cleaning to remove the photoresist;
Wherein, the solution for removing the photoresist and the corresponding treatment time are as follows: 3-30 min, 1-10-30 min;
Finally, the annealing range of the first mask dielectric layer is as follows: high-temperature annealing is carried out at 900-1100 ℃ for 10 min-1 h corresponding to the annealing time;
and carrying out Al ion implantation based on the first mask dielectric layer and the second mask dielectric layer after annealing is completed, wherein the energy and the dosage of the Al ion implantation are shown in the following table 1:
TABLE 1
| Energy (energy) | 500kev | 400kev | 300kev | 200kev | 100kev |
| Dosage of | 8e13 | 6e13 | 6e13 | 4e13 | 2e13 |
In a specific embodiment, according to the above-mentioned ion implantation method for reducing the damage to the surface of silicon carbide, a first mask dielectric layer made of polysilicon and having a thickness ranging from 30 nm to 60nm is grown on the pretreated silicon carbide wafer by LPCVD;
growing a second mask medium layer which is made of silicon oxide and has the thickness ranging from 1 um to 3.5um on the first mask medium layer by PECVD;
spin-coating photoresist with the thickness range of 1.5-2.8 um on the second mask medium layer, and exposing, developing and hardening the photoresist through a photoetching plate with a preset pattern;
Wherein, the time range of the exposure time is 280-320 mes, and the distance range between the exposure time and the focal length (Focus) is 0.2-0.2 um; the development adopts a dynamic development mode, and the development time range is 60-120 s; the hardening time ranges from 60 to 240s, and the hardening temperature ranges from 90 to 120 ℃;
Etching the second mask dielectric layer based on the photoresist after the photoetching treatment, and cleaning to remove the photoresist;
Wherein, the solution for removing the photoresist and the corresponding treatment time are as follows: 3-30 min, 1-10-30 min;
Finally, the annealing range of the first mask dielectric layer is as follows: high-temperature annealing is carried out at 900-1100 ℃ for 10 min-1 h corresponding to the annealing time;
And after annealing is completed, carrying out N ion implantation based on the first mask dielectric layer and the second mask dielectric layer, wherein the N ion implantation energy and the dosage are shown in the following table 2:
TABLE 2
| Energy (energy) | 250kev | 160kev | 80kev |
| Dosage of | 1e14 | 8e13 | 6e13 |
In a specific embodiment, due to the existence of the first mask dielectric layer, the second mask dielectric layer can be automatically cut off at the position where the etching of the second mask dielectric layer is completed when the second mask dielectric layer is etched, so that the residual first mask dielectric layer can prevent etching ions and implanted ions from damaging the surface bombardment of the silicon carbide wafer, thereby reducing the surface roughness of the silicon carbide wafer and preventing the growth quality of subsequent processes such as passivation layer films and metal films from being influenced;
Wherein, for the silicon carbide wafer surface roughness measurement results after single/double layer implantation mask implantation under different implantation conditions are shown in table 3:
TABLE 3 Table 3
In summary, only the surface of the silicon carbide wafer after single-layer mask implantation is rougher, the etched surface of the first mask layer is smooth on the surface of the device silicon carbide wafer after double-layer mask implantation, and only the surface structure of the silicon carbide wafer after single-layer mask implantation is shown in fig. 8;
The silicon carbide wafer surface structure implanted through the bilayer mask and leaving the first mask layer is shown in fig. 9.
Example 2:
The structure diagram of the silicon carbide device for reducing the surface damage of the silicon carbide provided by the invention is shown in fig. 4, and comprises the following steps:
The silicon carbide wafer, a first mask dielectric layer on the silicon carbide wafer, a second mask dielectric layer on the first mask dielectric layer and an ion implantation region on the silicon carbide wafer;
wherein the ion implantation region is obtained according to the ion implantation method for reducing the damage of the silicon carbide surface;
the thickness of the first mask medium layer is as follows: 30 nm-60 nm;
the material of the first mask dielectric layer is at least one or more of the following: polysilicon, BPSG, and PSG;
The thickness of the second mask medium layer is as follows: 1.0um to 3.5um;
the material of the second mask dielectric layer is at least one or more of the following: silicon oxide, BPSG, and PSG;
the ion implantation area is a silicon carbide wafer area corresponding to the first mask medium layer only.
It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the scope of protection thereof, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that various changes, modifications or equivalents may be made to the specific embodiments of the application after reading the present invention, and these changes, modifications or equivalents are within the scope of protection of the claims appended hereto.
Claims (17)
1. An ion implantation method for reducing damage to a silicon carbide surface, comprising:
Sequentially growing a first mask dielectric layer and a second mask dielectric layer on a silicon carbide wafer;
performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern;
annealing the first mask dielectric layer to form a compact and uniform first mask dielectric layer;
Performing ion implantation on the silicon carbide wafer based on the first mask dielectric layer and the second mask dielectric layer;
the second mask medium layer is different from the first mask medium layer in thickness and material.
2. The method of claim 1, wherein the second masking dielectric layer has a thickness of: 1.0um to 3.5um.
3. The method of claim 2, wherein the material of the second masking dielectric layer is at least one or more of: silicon oxide, BPSG, and PSG.
4. The method of claim 3, wherein the gas used for dry etching the second masking dielectric layer is a fluorine-containing gas.
5. The method of claim 4, wherein the dry etching of the second masking dielectric layer is performed at a gas flow rate in the range of: 10sccm to 80sccm.
6. The method of claim 5, wherein the dry etching of the second masking dielectric layer has a power range of: 40W-100W.
7. The method of claim 1, wherein the first masking dielectric layer has a thickness of: 30 nm-60 nm.
8. The method of claim 7, wherein the material of the first masking dielectric layer is at least one or more of: polysilicon, BPSG, and PSG.
9. The method of claim 1, wherein performing dry etching on the second mask dielectric layer to obtain a second mask dielectric layer with a preset pattern, comprises:
Spin-coating a photoresist film on the second mask medium layer, exposing, developing and hardening the photoresist film through a photoetching plate with a preset pattern, and forming the photoresist film with the preset pattern on the second mask medium layer;
and carrying out dry etching on the second mask dielectric layer through the photoresist film to obtain the second mask dielectric layer with the preset pattern.
10. The method of claim 1, wherein the annealing the first masked dielectric layer is performed at a temperature in a range of: 900-1100 ℃.
11. The method of claim 10, wherein the annealing process is performed for a time period ranging from: and the time is 10 min-1 h.
12. A silicon carbide device for reducing surface damage to silicon carbide, the silicon carbide device comprising: the silicon carbide wafer, a first mask dielectric layer on the silicon carbide wafer, a second mask dielectric layer on the first mask dielectric layer and an ion implantation region on the silicon carbide wafer;
wherein the ion implantation zone is obtained according to an ion implantation method for reducing surface damage of silicon carbide according to claims 1-14.
13. The silicon carbide device of claim 12, wherein the first masking dielectric layer has a thickness of: 30 nm-60 nm.
14. The silicon carbide device of claim 13, wherein the material of the first masking dielectric layer is at least one or more of: polysilicon, BPSG, and PSG.
15. The silicon carbide device of claim 12, wherein the second masking dielectric layer has a thickness of: 1.0um to 3.5um.
16. The silicon carbide device of claim 15, wherein the material of the second masking dielectric layer is at least one or more of: silicon oxide, BPSG, and PSG.
17. The silicon carbide device of claim 12, wherein the ion implanted region is a silicon carbide wafer region corresponding to only the first masking dielectric layer.
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