CN118038948A

CN118038948A - Memory device

Info

Publication number: CN118038948A
Application number: CN202211361069.8A
Authority: CN
Inventors: 鲁耀华
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-11-02
Filing date: 2022-11-02
Publication date: 2024-05-14
Also published as: WO2024093045A1

Abstract

The present application provides a memory comprising: the storage device comprises N storage arrays which are sequentially arranged, wherein at least one storage array is a redundant array, at least one storage array is a main storage array, and the redundant array is used for replacing a fault storage unit in the main storage array; n selection circuits for receiving N-1 groups of data; the 1 st selection circuit receives 1 st data and is used for outputting or not outputting the 1 st data to the 1 st storage array according to the 1 st selection signal; the N-1 data is received by the N-th selection circuit and is used for outputting or not outputting the N-1 data to the N-th storage array according to the N-th selection signal; the ith selection circuit receives the ith-1 data and the ith data, and the ith selection circuit is used for outputting the ith-1 data or the ith data to the ith memory array according to the ith selection signal. The scheme can realize data processing under fault replacement.

Description

Memory device

Technical Field

The present disclosure relates to memory technologies, and in particular, to a memory.

Background

With the development of memory technology, memories are widely used in various fields, such as dynamic random access memories (Dynamic Random Access Memory, abbreviated as DRAMs).

In practical application, during the production and use of the memory, the memory unit may fail, and the failed memory unit cannot work normally and needs to be replaced and repaired. Therefore, how to ensure accurate data processing of the memory is achieved in combination with consideration of the case where replacement repair is possible becomes a problem to be considered.

Disclosure of Invention

Embodiments of the present application provide a memory.

According to some embodiments, a first aspect of the application provides a memory comprising: the N storage arrays are respectively marked as a 1 st storage array, a 2 nd storage array, … th storage array, an i th storage array, … th storage array and an N th storage array, wherein at least one storage array is a redundant array and at least one storage array is a main storage array, the redundant array is used for replacing a fault storage unit in the main storage array, i is more than 1 and less than N,2 is less than or equal to N, and i and N are positive integers; n selection circuits respectively marked as a 1 st selection circuit, a 2 nd selection circuit, … th selection circuit, an i th selection circuit, … th selection circuit and an N-1 st selection circuit, wherein the N selection circuits receive N-1 sets of data respectively marked as 1 st data, 2 nd data, … th data, … th data and N-1 st data; the 1 st selection circuit receives the 1 st data and is used for outputting or not outputting the 1 st data to the 1 st storage array according to a 1 st selection signal; the N-1-th data is received by the N-th selection circuit and is used for outputting or not outputting the N-1-th data to the N-th storage array according to an N-th selection signal; the ith selection circuit receives the ith-1 data and the ith data, and the ith selection circuit is used for outputting the ith-1 data or the ith data to the ith storage array according to an ith selection signal.

In some embodiments, the storage array and the redundant array each include M columns, respectively denoted as 1 st column, 2 nd column, … th column, … th column, and M th column, where the j th column of the redundant array is used to replace the j th column of any one of the main storage arrays, 1.ltoreq.j.ltoreq.m, and j and M are positive integers.

In some embodiments, the selection circuit comprises: each sub-selection circuit of the 1 st selection circuit receives 1bit data in the 1 st data, each sub-selection circuit of the i th selection circuit receives the i-1 st data and 1bit data in the i th data respectively, and each sub-selection circuit of the N th selection circuit receives 1bit data in the N-1 st data.

In some embodiments, the sub-selection circuit includes a data selector, a first data input of the data selector of the 1 st selection circuit receives 1bit data of the 1 st data, a selection end of the data selector of the 1 st selection circuit receives the 1 st selection signal, a first data input of the data selector of the i st selection circuit receives 1bit data of the i-1 st data, a second data input of the data selector of the i st selection circuit receives 1bit data of the i st data, a selection end of the data selector of the i st selection circuit receives the i st selection signal, a first data input of the data selector of the N st selection circuit receives 1bit data of the N-1 st data, and a selection end of the data selector of the N selection circuit receives the N selection signal.

In some embodiments, the number of redundant arrays is one.

In some embodiments, the 1 st storage array is the redundant array.

In some embodiments, when there is no defective memory cell, the 1 st selection circuit outputs no data, the nth selection circuit outputs the N-1 st data, and the ith selection circuit outputs the i-1 st data; when the fault memory unit in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the ith selection circuit outputs the ith data in the range of 1 < i < N, the ith selection circuit outputs the ith-1 st data in the range of N < i < N, and N is a positive integer; when a defective memory cell in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the i-th selection circuit outputs the i-th data, and the nth selection circuit does not output data.

In some embodiments, the nth storage array is the redundant array.

In some embodiments, when there is no defective memory cell, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs no data, and the ith selection circuit outputs the ith data; when the fault memory unit in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the ith selection circuit outputs the ith data in the range of 1 < i < N, and the ith selection circuit outputs the ith-1 st data in the range of N < i < N, wherein N is a positive integer; when a defective memory cell in the 1 st memory array is replaced by the redundant array, the 1 st selection circuit outputs no data, the i-th selection circuit outputs the i-1 st data, and the N-th selection circuit outputs the N-1 st data.

In some embodiments, the mth storage array is the redundant array, 1 < m < N and m is a positive integer.

In some embodiments, when there is no defective memory cell, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the mth selection circuit outputs no data, and in a range of 1 < i < m, the ith selection circuit outputs the ith data, in a range of m < i < N, the ith selection circuit outputs the i-1 st data; when a faulty memory cell in an nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the nth selection circuit does not output data, the ith selection circuit outputs the ith data in a range of 1 < i < N, the ith selection circuit outputs the ith-1 st data in a range of N < i < N, N < m, and N is a positive integer; when a faulty memory cell in a kth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the kth selection circuit does not output data, the ith selection circuit outputs the ith data in a range of 1 < i < k, the ith selection circuit outputs the ith-1 st data in a range of k < i < N, m < k < N, and k is a positive integer; when a faulty memory cell in a1 st memory array is replaced by the redundant array, the 1 st selection circuit does not output data, the nth selection circuit outputs the N-1 st data, and the ith selection circuit outputs the i-1 st data; when a defective memory cell in an nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit does not output data, and the ith selection circuit outputs the ith data.

In some embodiments, the number of redundant arrays is a plurality and the redundant arrays are not adjacent.

In some embodiments, at least one of the primary storage arrays is a check code storage array for storing check code data.

In some embodiments, the memory further comprises: a verification module; the verification module is connected with the N selection circuits, the data received by the N selection circuits comprise data to be written and verification code data, and the verification module is used for generating the verification code data according to the data to be written.

The memory provided by the embodiment of the application comprises N storage arrays which are sequentially arranged, wherein the N storage arrays comprise at least one main storage array and at least one redundant array, the redundant array is used for providing fault unit replacement of the main storage array, and N selection circuits, each selection circuit receives data corresponding to a bit sequence and the last adjacent data, and each selection circuit responds to own selection signals and realizes data processing under a fault replacement scene by selecting and outputting corresponding signals. According to the memory, the plurality of selection circuits are arranged, and the selection circuits are controlled to output corresponding data according to the replacement condition of the fault units of the memory, so that data processing under fault replacement is realized, and the accuracy and reliability of the data processing are ensured.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the embodiments of the application.

FIG. 1 is a diagram showing an example architecture of a memory according to an embodiment;

FIG. 2 is a diagram showing an example of the structure of a memory cell according to an embodiment;

FIGS. 3 and 4 are, respectively, an exemplary alternative architecture diagram;

FIG. 5 is a diagram showing an example of a memory structure according to an embodiment;

Fig. 6 and 7 are diagrams showing examples of states in different cases, respectively;

FIG. 8 is an exemplary diagram of a memory array architecture;

FIG. 9 is a diagram showing an example of the structure of a memory;

fig. 10 to 12 are diagrams showing examples of states in different cases;

FIG. 13 is a diagram showing an example of the structure of a memory;

Fig. 14 to 16 are diagrams showing examples of states in different cases;

FIG. 17 is a diagram showing an example of the structure of a memory;

Fig. 18 to 21 are diagrams showing examples of states in different cases.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The terms "comprising" and "having" in the present application are used to mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second," etc. are used merely as labels or distinction and do not limit the order or quantity of their objects. Furthermore, the various elements and regions in the figures are only schematically illustrated and are therefore not limited to the dimensions or distances illustrated in the figures.

The technical scheme is described in detail below with specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing an example of a memory architecture according to an embodiment, and as shown in FIG. 1, a DRAM is taken as an example, and includes a data input/output buffer, a row decoder, a column decoder, a sense amplifier, and a memory array. Wherein the data input/output buffers belong to a peripheral area circuit, and the sense amplifier, the row decoder, the column decoder, and the memory array belong to an array area circuit. The memory array is mainly composed of word lines, bit lines and memory cells. Word lines in the memory array extend in a row direction, bit lines in the memory array extend in a column direction, and intersections of the word lines and the bit lines are memory cells of the memory array.

Wherein each memory cell is for storing one bit (bit) of data. As shown in fig. 2, fig. 2 is a schematic diagram showing a structure example of a memory cell according to an embodiment, and the memory cell mainly includes a transistor switch M and a capacitor C. The capacitor is used for storing data, and the transistor switch is used for being turned off or turned on according to the selected state.

A certain memory cell may be activated by controlling the word line and the bit line to enable access to the memory cell. As an example in connection with a read scenario: when the data in the memory cell needs to be read, the word line of the row where the memory cell is located can be selected through the row decoder, correspondingly, the transistor M in the illustration is turned on, and the state on the capacitor C at the moment can be perceived through the sense amplification of the bit line signal. For example, if the bit data stored in the memory cell is 1, then transistor M will read 1 from the bit line of the memory cell after being turned on, and vice versa. In addition, the write scenario is taken as an example: when bit data needs to be written into a certain memory cell, for example, 1 is written. The word line of the row in which the memory cell is located can be selected by a row decoder, and the transistor M in the corresponding figure is turned on, and the capacitor C is charged, i.e. a1 is written to the memory cell, by setting the logic level of the bit line to 1. Conversely, if a 0 is to be written, then the logic level of the bit line is set to 0, causing the capacitor C to discharge, i.e., write a 0 to the memory cell.

In practical applications, DRAM has a certain probability of producing faulty memory cells during production, or with the aging damage of devices, especially the operating environment has challenges (high temperature environment), and requires frequently operated memories, and faulty memory cells may be produced in the memory array. In order to avoid that the fault storage units affect the normal operation of the memory, a redundant array is planned in addition to a main storage array containing conventional storage units, and the storage units in the redundant array are used as redundant parts for realizing the replacement of the fault storage units in the main storage array.

The term "replacement" as used herein refers to replacement in terms of storage function, that is, the number of storage units that can be normally used for storing data after replacement is guaranteed, and specific replacement methods include, but are not limited to, storing bit data that a faulty storage unit originally needs to store by using a redundant storage unit, or only guaranteeing that after adding a redundant storage unit, the number of storage units that can normally work can guarantee storage of complete data, and no limitation is made as to which storage unit stores which bit data.

In some alternatives, such as LCR (Local Column Repair), a memory column containing conventional memory cells and a redundant column containing redundant memory cells are designed in the memory array, the redundant column and the memory column sharing the data lines of the memory array, the data lines being used to transfer read or write data. To further facilitate design, in some alternatives, such as CCR (Central Column Repair), all redundant memory cells are disposed in separate redundant arrays, the redundant arrays and the conventional memory arrays are each disposed independently, each having independent data lines, so it is desirable to provide an efficient solution to support data processing, such as normal writing of data, in the event of a failure replacement under the architecture.

For ease of understanding, fig. 3 and 4 illustrate alternative architecture diagrams of an example, respectively, taking a memory comprising N memory arrays as an example, a1 st memory array, a2 nd memory array, and a … nd memory array, respectively. The fault replacement scheme adopted in fig. 3 is an LCR scheme, where columns filled with hatching are redundant columns, and portions not filled with hatching are conventional storage columns, and it is known that in the LCR scheme, each redundant column is integrated in each storage array, and a storage column and a redundant column under each storage array share a data line. The failure alternative scheme adopted in fig. 4 is a CCR scheme, where the array filled with the shadow is a redundant array, and the portion not filled with the shadow is a conventional main storage array, where the redundant array is independently provided, and the storage units in the redundant array are used to replace the failed storage units in the main storage array, and each array is configured with an independent data line. It should be noted that the illustration is only an example, and the specific array architecture may be adjusted according to actual needs, and is not limited to the illustration.

Aspects of embodiments of the present application relate to the above considerations. The following description is presented by way of example in connection with some embodiments of the application. FIG. 5 is a diagram showing an example of the structure of a memory according to an embodiment, as shown in FIG. 5, the memory includes:

The N storage arrays 11 are sequentially arranged and are respectively marked as a1 st storage array, a2 nd storage array, … th storage array, an i-th storage array, … th storage array and an N-th storage array, wherein at least one storage array is a redundant array and at least one storage array is a main storage array, the redundant array is used for replacing a fault storage unit in the main storage array, i is more than 1 and less than N,2 is less than or equal to N, and i and N are positive integers;

n selection circuits 12, respectively marked as1 st selection circuit, 2 nd selection circuit, … th selection circuit, i selection circuit, … th selection circuit, N selection circuits, which receive N-1 sets of data, respectively marked as1 st data, 2 nd data, …, i data, … th data, N-1 st data;

The 1 st selection circuit receives 1 st data and is used for outputting or not outputting the 1 st data to the 1 st storage array according to the 1 st selection signal; the N-1 data is received by the N-th selection circuit and is used for outputting or not outputting the N-1 data to the N-th storage array according to the N-th selection signal; the ith selection circuit receives the ith-1 data and the ith data, and is used for outputting the ith-1 data or the ith data to the ith storage array according to the ith selection signal, so that the selection circuit outputs complete data, and the storage array can accurately store the data output by the selection circuit, and accurate writing of the data is realized.

The number of the data groups received by the selection circuit can be determined according to the data amount which is actually required to be written into the memory. In practical applications, the type of the memory provided in the present embodiment is not limited, and may be applied to, for example, a double rate synchronous dynamic random access memory (DDR) or the like.

Wherein a primary storage array of the storage arrays is used to store written data without a failed storage unit. In practical application, in order to verify the accuracy of data reading when the data reading is performed later, data verification can be performed on the read data. Thus, in one example, at least one of the primary storage arrays is a check code storage array for storing check code data. The Data eventually written to the N storage arrays will include the Data to be written data_cp, as well as the check code Data data_ecc. The check code storage array is used for storing check code data, which can be interpreted as that the check code storage array normally stores the check code data when no fault storage unit exists in the check code storage array, and it can be understood that if the fault storage unit exists in the check code storage array, the redundant array can also be used for replacing the fault storage unit in the check code storage array, and correspondingly, the check code data corresponding to the fault storage unit is written into a certain storage unit after the replacement.

In practical applications, errors may occur during the writing, reading and transmitting of data, so in order to avoid and timely find such errors, a data verification method may be used to verify the read data. As an example, the data verification method may include, but is not limited to, parity check, cyclic redundancy check, etc., and in the verification scheme, verification is required based on the verification code data, so that when writing data into the storage array, the verification code data is generated and written together, so that when reading data, data verification is performed on the read storage data according to the read verification code data. Accordingly, in one example, the memory further comprises: a verification module 13; the verification module 13 is connected with the N selection circuits 12, and the data received by the N selection circuits 12 includes data to be written and verification code data, and the verification module 13 is configured to generate the verification code data according to the data to be written. By setting the check code module, the corresponding check code data can be generated and stored in the storage array when the data is written, so that the read data can be subjected to data check when the data is read, and the accuracy and the reliability of data processing are further improved.

The circuit operation principle of the present embodiment is exemplified below with reference to the accompanying drawings: taking the write-once complete Data as 34 groups of Data for example, the Data are recorded as 1 st Data data_1 to 34 th Data data_34, and the 18 th storage array is a redundant array. In practical applications, the length and content of the write-once data may be determined according to the type of memory and the operating parameters. Wherein, the 1 st Data data_1 represents the Data which should be written into the 1 st main storage array under normal conditions in the complete 34 sets of Data; data 2 data_2 represents the Data in the 2 nd main storage array that should be written in the normal case, out of the complete 34 sets of Data; and so on. It will be appreciated that when there is no failure in the primary storage array, no data may be stored in the redundant array, i.e., null data; or when the column of the main storage array where the faulty storage unit is located is replaced by the redundant array, the data in the redundant array is specifically the data stored after the faulty storage unit is replaced, where the data may be one of 34 sets of data, specifically, which set of data may be determined according to the actual situation, which will be described later will be illustrated.

First, FIG. 6 is a state example diagram for a case where there are no failed memory cells in the primary storage array. When there are no failed memory cells in the primary storage array, the written 34 sets of data should be stored in the corresponding primary storage array. In connection with the example in the figure, it is assumed that the memory includes 35 memory arrays, i.e., n=35, where the redundant array is the 18 th memory array, and the remaining 1 st to 17 th memory arrays and 19 th to 35 th memory arrays are all main memory arrays. Specifically, the 1 st Data data_1 in the written Data needs to be stored in the 1 st storage array (1 st main storage array), the 2 nd Data data_2 needs to be stored in the 2 nd storage array (2 nd main storage array), and so on until the 17 th Data data_17 needs to be stored in the 17 th storage array (17 th main storage array), then the 18 th storage array is a redundant array, so that no Data is stored, then the 18 th Data data_18 needs to be stored in the 19 th storage array (18 th main storage array), the 19 th Data data_19 needs to be stored in the 20 th storage array (19 th main storage array), and so on until the 34 th Data data_34 needs to be stored in the 35 th storage array (34 th main storage array).

Correspondingly, the 1 st selection circuit receives the 1 st data, the N selection circuit receives the N-1 st data, and the i selection circuit receives the i-1 st data and the i data. Referring to fig. 6, the 1 st selection circuit receives the 1 st Data data_1, the 2 nd selection circuit receives the 1 st Data data_1 and the 2 nd Data data_2, the … th selection circuit receives the 16 th Data data_16 and the 17 th Data data_17, the 18 th selection circuit receives the 17 th Data data_17 and the 18 th Data data_18, the 19 th selection circuit receives the 18 th Data data_18 and the 19 th Data data_19, the … th selection circuit receives the 33 th Data data_33 and the 35 th Data data_34, and the 35 th selection circuit receives the 34 th Data data_34. Based on the above situation, when there is no defective memory cell, the 1 st selection circuit outputs the 1 st Data to write the 1 st Data data_1 to the 1 st memory array, among the N selection circuits, the i selection circuit selects and outputs the i-th Data to write the i-th Data to the i-th memory array in a range of 1 < i < 18, and the i selection circuit selects and outputs the i-1 st Data data_i-1 to write the i-1 st Data data_i-1 to the i-th memory array in a range of 18 < i < 35, and the 35 th selection circuit outputs the 34 th Data data_34 to write the 34 th Data data_34 to the 35 th memory array, thereby enabling the selection circuit to output complete Data, and thus the memory array to accurately store the Data output by the selection circuit, enabling accurate writing of Data.

The above is the case where there is no failed storage unit. By way of example, FIG. 7 is a state example diagram for another scenario in which a failed storage unit is present in the primary storage array. Still in connection with the architecture shown in FIG. 6, taking the example of a failed storage unit in the 1 st storage array, in FIG. 7, a redundant array (18 th storage array) is used to replace the failed storage unit in the 1 st storage array. In one example, the 1 st Data data_1 that is originally required to be written to the 1 st storage array is required to be written to the 2 nd storage array, the 2 nd Data data_2 that is originally required to be written to the 2 nd storage array is required to be written to the 3 rd storage array, and the replacement of the failed storage unit in the 1 st storage array is realized until the 17 th Data data_17 that is originally required to be written to the 17 th storage array is required to be written to the redundant array (in the 18 th storage array). At this time, the column in which the defective memory cell in the 1 st memory array is located may not store Data, so the 1 st selection circuit does not output the 1 st Data data_18, the 19 st to 35 th selection circuits output the 18 th Data data_18 to 34 th Data data_34, and further write the 18 th Data data_18 to 34 th Data data_34 to the 19 st to 35 th memory arrays, so that the selection circuit outputs complete Data, and further the memory array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of Data.

In this embodiment, N selection circuits are provided for N storage arrays, so that accurate writing of complete data can be realized by controlling the selection circuits to select and output corresponding data no matter whether a faulty storage unit is replaced or not, and accuracy and reliability of data processing are ensured. The scheme of the embodiment is convenient for circuit design and preparation, and can be suitable for scenes with high integration level such as memories.

The specific implementation circuit of the selection circuit 12 may be designed according to practical situations. As an example, fig. 8 is a schematic diagram of a memory array, where, as shown in fig. 8, the main memory array and the redundancy array each include a plurality of columns, for example, M columns, respectively denoted as 1 st column, 2 nd column, … th column, j-th column, … th column, and M-th column.

Specifically, the jth column of the redundant array is used for replacing the jth column of the main storage array, wherein j is more than or equal to 1 and less than or equal to M, and j and M are positive integers. Here, a single "column" refers to a control object of a single column selection signal. For example, a memory array includes a plurality of physical rows (e.g., understood to be word lines) and a plurality of physical columns (e.g., understood to be bit lines) in a physical structure. In some memory designs, multiple physical columns in a memory array are divided into multiple groups of columns, with all physical columns in each group of columns being controlled by the same column select signal, with different groups of column-controlled column select signals being different. For example, assuming that a memory array includes 16 physical columns, dividing the memory array by every 4 physical columns will result in 4 columns (column_1 to column_4), the column_1 to column_4 respectively correspond to the column selection signals 1 to 4, the 4 physical columns in each column correspond to the same column selection signal, and each column can be regarded as a "column" in this example. It should be noted that, in the case of multiple memory arrays, the same column selection signal is used to select the same column in different memory arrays, where the same column refers to the column that is located identically in different memory arrays, such as column selection signal 1 is used to select column_1 in all memory arrays. In other memory designs, a single "rank" in this example is a single physical rank, e.g., a memory array contains 8 physical ranks, each of which may be considered a "rank" in this example, each of which is controlled by 8 rank select signals. The present embodiment is not limited thereto.

Taking as an example a matching of the former design, in one example the selection circuit 12 comprises: a plurality of sub-selection circuits 121, each sub-selection circuit of the 1 st selection circuit receives 1bit data of the 1 st data, each sub-selection circuit of the i-th selection circuit receives i-1 st data and 1bit data of the i-th data, respectively, and each sub-selection circuit of the N-th selection circuit receives 1bit data of the N-1 st data.

In connection with the first design, as shown in fig. 8, the data writing process of the memory is exemplified as follows: as shown in fig. 8, a plurality of memory arrays 11 are shown, each memory array 11 comprising a plurality of columns 21, each column 21 further comprising a plurality of physical columns (e.g., 4 bits), with an enlarged view of one of the memory arrays being taken as an example. When writing data, the column decoder parses a column select signal from the write command, e.g., the column select signal characterizes the address of column 1. In response to the column selection signal, column 1 of the plurality of memory arrays 11 is selected. Thus, in connection with the example of fig. 6, the i-th data includes 4-bit data to be written to column 1 of a certain memory array, i.e., the 1-th data includes 4-bit data to be written to column 1 of a certain memory array, the 2-th data includes 4-bit data to be written to column 1 of another memory array, and so on. Therefore, each selection circuit correspondingly comprises 4 sub-selection circuits, the sub-selection circuits respectively correspond to 1bit data in 4bit data, the output end of each selection circuit is connected with the data line of the corresponding storage array, and the data output by the selection circuits are written into the corresponding storage array through the data line.

Specifically, each sub-selection circuit in the ith selection circuit receives 1bit data in the ith-1 data (including 4bit data) and 1bit data in the ith data (including 4bit data), and each sub-selection circuit in the nth selection circuit receives 1bit data in the nth-1 data. The column selection signals are identical in the positions of columns selected by different storage arrays, wherein physical columns to which the two bit data received by the sub selection circuits are written are distributed in the columns with identical positions of the different two storage arrays, and the positions of the physical columns in the respective columns are identical. For example, assuming that the column selection signal is the address of the 1 st column, the 1 st sub-selection circuit of the 2 nd selection circuit receives two bits of data from the 1 st bit of 4 bits of the 1 st data and the 1 st bit of 4 bits of the 2 nd data, respectively.

It will be appreciated that in practice, the selection circuit may comprise one or more sub-selection circuits, the selection signals of the sub-selection circuits being identical in the same selection circuit. So in one example, sub-selection circuits in the same selection circuit may share one selection signal, with different selection circuits receiving respective independent selection signals.

In combination with the foregoing, the sub-selection circuit is operable to select one of the data outputs from the received data in response to a selection signal. In practical applications, the implementation of the sub selection circuit is not limited, in one example, the sub selection circuit includes a data selector MUX, the first data input terminal of the data selector of the 1 st selection circuit receives 1bit data of the 1 st data, the selection terminal of the data selector of the 1 st selection circuit receives the 1 st selection signal, the first data input terminal of the data selector of the i st selection circuit receives 1bit data of the i-1 st data, the second data input terminal of the data selector of the i st selection circuit receives 1bit data of the i st data, the selection terminal of the data selector of the i st selection circuit receives the i st selection signal, the first data input terminal of the data selector of the N st selection circuit receives 1bit data of the N-1 st data, and the selection terminal of the data selector of the N selection circuit receives the N selection signal, wherein the second data input terminal of the data selector of the 1 st selection circuit and the first data input terminal of the data selector of the N selection circuit may not receive any data, such as a floating terminal, or a fixed level, for example, VDD or ground voltage.

In this example, how the data selector outputs data according to the level of the selection signal may be set according to actual requirements, for example, when the 1 st selection signal is at a high level, the output end of the data selector of the 1 st selection circuit outputs 1bit data in the 1 st data, when the 1 st selection signal is at a low level, the output end of the data selector of the 1 st selection circuit does not output data, when the i st selection signal is at a high level, the output end of the data selector of the i st selection circuit outputs 1bit data in the i st data, when the i st selection signal is at a low level, the output end of the data selector of the i st selection circuit outputs 1bit data in the i-1 st data, when the N st selection signal is at a high level, the output end of the data selector of the N st selection circuit does not output 1 st data, wherein when the selection end of the data selector does not receive the signal, i.e. the output end of the data selector is at a low level, the data selector is not output, thereby simplifying the data selector structure according to the conventional implementation.

In one example, the sub-selection circuit in the 1 st selection circuit includes a first switch tube, a first end of the first switch tube receives 1bit in the 1 st data, a second end of the first switch tube is an output end of the sub-selection circuit, the first switch tube is closed or opened according to the 1 st selection signal, the sub-selection circuit in the i st selection circuit includes a second switch tube and a third switch tube, a first end of the second switch tube receives 1bit in the i-1 st data, a first end of the third switch tube receives 1bit in the i st data, a second end of the second switch tube and a second end of the third switch tube serve as output ends of the sub-selection circuit, wherein the second switch tube or the third switch tube is closed according to the i st selection signal, or the second switch tube and the third switch tube are both opened according to the i st selection signal, the sub-selection circuit in the N selection circuit includes a fourth switch tube, a first end of the fourth switch tube receives 1bit in the N-1 st data, and a second end of the fourth switch tube is the fourth switch tube or the fourth switch tube is opened according to the i th selection signal.

In practical application, the arrangement of each storage array can be designed according to the needs. As an example, the number of redundant arrays may be one or more. Taking the number of redundant arrays as one example, there are also various arrangements of redundant arrays. For example, the redundant array may be located at an edge of the entire memory array, e.g., the 1 st memory array or the N-th memory array is the redundant array. For another example, the redundant array may be located between memory arrays, e.g., the mth memory array is a redundant array, 1< m < N and m is a positive integer.

In one example, the number of redundant arrays is one. Specifically, each column in the redundant array may be used to replace a column in any primary storage array that is located in the same position, e.g., column 1 in the redundant array may be used to replace column 1 in any primary storage array, and column 2 in the redundant array may be used to replace column 2 in any primary storage array. Or when there are faulty memory cells in both columns of a certain main memory array, the two columns with the same position in the redundant array can be replaced. Replacement of defective memory cells can be achieved by providing a redundant array.

In connection with different locations of a redundancy array, as a possible manner of the above example, fig. 9 is a diagram illustrating a structure of a memory of an example, where, as shown in fig. 9, the 1 st storage array is a redundancy array, the storage array filled with shadows is a redundancy array, and the storage array not filled with shadows is a main storage array.

The circuit operation principle when the redundant array is the 1 st memory array is exemplified by the following with reference to the accompanying drawings: the example is again given with 34 sets of data as the complete data for one write. FIG. 10 is a state example diagram for a case where there are no failed memory cells in the primary storage array. Specifically, when there is no defective memory cell, the 1 st selection circuit does not output the 1 st Data data_1, the 35 th selection circuit outputs the 34 th Data data_34, and the i-th selection circuit outputs the i-1 st Data.

In connection with the example of fig. 10, the 1 st storage array is a redundant array, and the 2 nd to 35 th storage arrays are all main storage arrays. Since the 1 st memory array is a redundant array, when the main memory array fails, the column in which the failed memory cell in the 1 st memory array is located does not store Data, and at this time, the 1 st selection circuit does not output the 1 st Data data_1, and the 2 nd to 35 nd selection circuits output the 1 st Data data_1 to 34 th Data data_34, respectively, so that the 1 st to 34 th Data data_1 to 34 th data_34 are written into the 2 nd to 35 th memory arrays (34 main memory arrays), respectively. Based on the above situation, among the N selection circuits, the 1 st selection circuit does not output the 1 st Data data_1, the i selection circuit outputs the i-1 st Data, and the 35 th selection circuit outputs the 34 th Data data_34, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of the Data.

FIG. 11 is a state example diagram for another scenario in which a failed storage unit is present in the primary storage array. Specifically, when the column in which the faulty memory cell in the nth memory array is located is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data when writing data into the memory array according to the column address of the column in which the faulty memory cell is located, the nth selection circuit outputs the N-1 st data, the ith selection circuit outputs the ith data in the range of 1 < i < N, the ith selection circuit outputs the ith-1 st data in the range of N < i < N, N is a positive integer, the nth selection circuit may not output data, power consumption can be saved, either the nth-1 st data or the nth data may be output, because whether the column in which the faulty memory cell is located stores data does not affect the storage of the whole data or not, and only the data need not be read out from the column in which the faulty memory cell is located when the data is read out.

For example, referring to fig. 11, a main storage array has a faulty storage unit, and the main storage array is not the last storage array, for example, assume that in fig. 11, the 17 th storage array has a faulty storage unit, that is, n=17 is taken as an example, in conjunction with the example in the drawing, data is not written into a column where the faulty storage unit of the 17 th storage array is located, 16 th Data data_16 originally required to be written into the 17 th storage array needs to be written into the 16 th storage array, 15 th Data data_15 originally required to be written into the 16 th storage array needs to be written into the 15 th storage array, and so on, until 1 st Data data_1 originally required to be written into the 2 nd storage array needs to be written into the 1 st storage array (redundant array), thereby realizing faulty unit replacement. Accordingly, in order to accurately write Data according to the above-described fail-over scheme, the 1 st selection circuit outputs the 1 st Data data_1 to write the 1 st Data data_1 to the 1 st storage array; in the range of 1 < i < 17, the ith selection circuit outputs the ith Data, namely the 2 nd to 16 th selection circuits respectively output the 2 nd Data data_2 to 16 th Data data_16, and further respectively write the 2 nd Data data_2 to 16 th Data data_16 into the 2 nd to 16 th storage arrays; the 17 th selection circuit does not output data so as to avoid writing data into the column where the fault storage unit is located; within the range of 17 < i < 35, the i-th selection circuit outputs the i-1-th Data, i.e., the 18-34-th selection circuit outputs the 17-th Data data_17-33-th Data data_33 to write the 17-33-th Data data_33 into the 18-34-th storage arrays, respectively; at this time, the 35 th selection circuit outputs the 34 th Data data_34 to write the 34 th Data data_34 into the 35 th storage array, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of the Data.

More specifically, when a defective memory cell in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the i-th selection circuit outputs the i-th data, and the nth selection circuit does not output the data. That is, when the redundant array is the first memory array and the memory array with the fault replaced is the last memory array, all the selection circuits select to output the ith data to the ith memory array.

For example, referring to fig. 12, a main storage array has a failed storage unit, and the main storage array is the last storage array, for example, the 35 th storage array in fig. 12 has a failed storage unit, and in order to perform the replacement of the failed storage unit, in the 35 th storage array, the column where the failed storage unit is located does not store Data, 34 data_34 that is originally required to be written into the 35 th storage array needs to be written into the 34 th storage array, 33 data_33 that is originally required to be written into the 34 th storage array needs to be written into the 33 st storage array, and so on until 1 Data data_1 that is originally required to be written into the 2 nd storage array needs to be written into the 1 st storage array (redundant array), thereby implementing the replacement of the failed storage unit. Accordingly, in order to implement the above replacement policy to accurately write Data, the 1 st selection circuit outputs the 1 st Data data_1 to write the 1 st Data data_1 to the 1 st storage array; the i-th selection circuit outputs the 2 nd Data data_2 to 34 th Data data_34 from the i-th Data, i.e., the 2 nd to 34 th selection circuits respectively, to write the 2 nd Data data_2 to 34 th Data data_34 to the 2 nd to 34 th memory arrays respectively; at this time, the 35 th selection circuit does not output the 34 th Data data_34 so as to avoid writing Data into the column where the faulty storage unit is located, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of the Data.

Still in connection with the different locations of a redundant array, as one possible way of the above example, fig. 13 is a diagram illustrating an example of the structure of a memory of an example, and as shown in fig. 13, the nth memory array is a redundant array. That is, the redundant array is disposed at the last memory array. In the figure, the storage array filled with shadow is a redundant array, and the storage array not filled with shadow is a main storage array.

The working principle of the circuit when the redundant array is the nth memory array is exemplified by the following with reference to the accompanying drawings: the complete data read at one time is exemplified as 34 sets of data. FIG. 14 is a state example diagram for a case where there are no failed memory cells in the primary storage array. Specifically, when there is no defective memory cell, the 1 st selection circuit outputs the 1 st Data data_1, the 35 th selection circuit does not output the 34 th Data data_34, and the i-th selection circuit outputs the i-th Data.

In connection with the example of fig. 14, the 35 th storage array is a redundant array, and the 1 st to 34 th storage arrays are all main storage arrays. Since the 35 th storage array is a redundant array, the 35 th storage array does not write Data when the main storage array has no failure, and the 1 st Data data_1 to 34 th Data data_34 are respectively written into the 1 st to 34 th storage arrays (34 main storage arrays). Correspondingly, as shown in the figure, the 1 st selection circuit outputs the 1 st Data data_1 to write the 1 st Data data_1 into the 1 st storage array, and the 2 nd to 34 nd selection circuits respectively output the 2 nd Data data_2 to 34 th Data data_34 to write the 2 nd Data data_2 to 34 th Data data_34 into the 2 nd to 34 th storage arrays; at this time, the 35 th selection circuit does not output the 34 th Data data_34. Based on the above situation, the 1 st selection circuit outputs the 1 st Data data_1, the i st selection circuit outputs the i th Data data_i, and the 35 th selection circuit does not output the 34 th Data, so that the selection circuit outputs complete Data, and the memory array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of the Data.

FIG. 15 is a state example diagram for another scenario in which a failed storage unit is present in the primary storage array. Specifically, when the column of the faulty memory cell in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the ith selection circuit outputs the ith data in the range of 1 < i < N, the ith selection circuit outputs the ith-1 st data in the range of N < i < N, and N is a positive integer.

For example, in connection with fig. 15, it is assumed that a main storage array has a faulty storage unit, and the main storage array is not the first storage array, for example, it is assumed that in fig. 15, a faulty storage unit exists in the 17 th storage array, that is, n=17 is taken as an example, and in connection with the example of fig. 14, a faulty storage unit replacement needs to be performed, so that Data is not written to a column where the faulty storage unit of the 17 th storage array is located, 17 th Data data_17 that needs to be written to the 17 th storage array needs to be written to the 18 th storage array, 18 th Data data_18 that needs to be written to the 18 th storage array needs to be written to the 19 th storage array, and so on, until 34 th Data data_34 that needs to be written to the 34 th storage array needs to be written to the 35 th storage array (redundant array), thereby achieving the faulty unit replacement. Accordingly, in order to accurately write Data, the 1 st selection circuit outputs the 1 st Data data_1 to write the 1 st Data data_1 into the 1 st storage array; within the range of 1 < i < 17, the i-th selection circuit outputs the i-th Data, that is, the 2-th to 16-th selection circuits output the 2-th to 16-th Data data_2 to 16-th Data data_16, respectively, to write the 2-th to 16-th Data data_2 to 16-th Data data_16 to the 2-th to 16-th memory arrays, respectively; the 17 th selection circuit does not output data so as to avoid writing data into the column where the fault storage unit is located; within the range of 17 < i < 35, the i-th selection circuit outputs the i-1-th Data, i.e., the 18-34-th selection circuits output the 17-th Data data_17-33-th Data data_33, respectively, to write the 17-33-th Data data_33 to the 18-34-th storage arrays, respectively; at this time, the 35 th selection circuit outputs the 34 th Data data_34 to write the 34 th Data data_34 into the 35 th storage array, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of the Data.

More specifically, when the column in which the defective memory cell in the 1 st memory array is located is replaced by the redundant array, the 1 st selection circuit does not output the 1 st data, the i selection circuit outputs the i-1 st data, and the N selection circuit outputs the N-1 st data. That is, when the redundant array is the last memory array and the memory array with the fault replaced is the first memory array, all the selection circuits select and output the i-1 data. For example, referring to fig. 16, a first storage array has a failed storage unit, for example, the 1 st storage array in fig. 16 has a failed storage unit, and in the example of fig. 16, a failed storage unit replacement needs to be performed, because the 1 st storage array fails, data is not written to the column where the failed storage unit is located in the 1 st storage array, the 1 st selection circuit does not output the 1 st Data data_1, the 1 st Data data_1 originally required to be written to the 1 st storage array needs to be written to the 2 nd storage array, the 2 nd Data data_2 originally required to be written to the 2 nd storage array needs to be written to the 3 rd storage array, and so forth until the 34 th Data data_34 originally required to be written to the 34 th storage array needs to be written to the 35 th storage array (redundant array), thereby achieving a failed storage unit replacement. Correspondingly, in order to accurately write Data, the 1 st selection circuit does not output the 1 st Data data_1 so as to avoid writing Data into the column where the faulty memory cell is located; the i-th selection circuit outputs the i-1-th Data, that is, the 2-34-th selection circuits output the 1 st Data data_1-33-th Data data_33, respectively, so as to write the 1 st Data data_1-33-th Data data_33 into the 2-34-th storage arrays, respectively; the 35 th selection circuit outputs 34 th Data data_34 to write the 34 th Data data_34 into the 35 th storage array, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, and accurate writing of the Data is realized.

Continuing with the different locations of a redundant array, as one possible way of the above example, fig. 17 is a diagram illustrating an example of the structure of a memory of an example, where the mth memory array is a redundant array, 1< m < n, and m is a positive integer, as shown in fig. 17. That is, the redundant array is disposed at a location other than the first or last memory array.

The circuit operation principle when the redundancy array is the mth memory array is exemplified by the following with reference to the accompanying drawings: still taking the complete data read once as 34 sets of data for example, one can make an example with reference to fig. 6 described above. The redundant array illustrated in fig. 6 is the 18 th memory array, i.e., m=18. The state when the main storage array has no failed storage cells is as shown in fig. 6. When no fault storage unit exists, the 1 st selection circuit outputs the 1 st data, the N selection circuit outputs the N-1 st data, the m selection circuit does not output data, the i selection circuit outputs the i data in the range of 1 < i < m, and the i selection circuit outputs the i-1 st data in the range of m < i < N. Referring to fig. 6, when there is no defective memory cell, the 1 st selection circuit outputs the 1 st Data data_1 to write the 1 st Data data_1 to the 1 st memory array, and within a range of 1 < i < 18, the i-th selection circuit selects to output the i-th Data, i.e., the 2-17 th selection circuit outputs the 2 nd Data data_2-17 th Data data_17 to write the 2 nd Data data_2-17 th Data data_17 to the 2-17 th memory array, respectively; since the redundant array (18 th memory array) does not need to store data when the main memory array is normal, the 18 th selection circuit does not output data; in the range of 18 < i < 35, the ith selection circuit selects and outputs the ith-1 Data, namely the 19 th to 34 th selection circuits respectively output 18 th Data data_18 to 33 th Data data_33 so as to write the 18 th Data data_18 to 33 th Data data_33 into 19 th to 34 th storage arrays respectively; at this time, the 35 th selection circuit outputs the 34 th Data data_34 to write the 34 th Data data_34 into the 35 th storage array, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of the Data.

Fig. 18 to 21 are diagrams showing examples of states in different cases when a defective memory cell exists in the main memory array. In one example, when a defective memory cell in an nth memory array is replaced by a redundant array, a1 st selection circuit outputs 1 st data, an nth selection circuit outputs N-1 st data, the nth selection circuit does not output data, the ith selection circuit outputs the ith data in a range of 1 < i < N, the ith selection circuit outputs the ith-1 st data in a range of N < i < N, N < m, and N is a positive integer.

As shown in fig. 18, it is assumed that the failed storage array is one of the 1 st to 17 th storage arrays, for example, the 15 th storage array, that is, n=15. In one example, the column where the failed memory cell of the 15 th memory array is located does not store Data any more, the 15 th Data data_15 that is originally written to the 15 th memory array is required to be written to the 16 th memory array, the 16 th Data data_16 that is originally written to the 16 th memory array is required to be written to the 17 th memory array, and the 17 th Data data_17 that is originally written to the 17 th memory array is required to be written to the 18 th memory array (redundant array), so that the failed replacement is completed. Correspondingly, the 1 st selection circuit outputs the 1 st Data data_1, and writes the 1 st Data data_1 into the 1 st storage array; within the range of 1 < i < 15, the i-th selection circuit outputs the i-th Data, that is, the 2-14-th selection circuits respectively output the 2-th Data data_2-14-th Data data_14 to write the 2-th Data data_2-14-th Data data_14 into the 2-14-th storage arrays respectively; the 15 th selection circuit does not output data so as to avoid writing data into the column where the fault storage unit is located; within the range of 15 < i < 35, the i-th selection circuit outputs the i-1-th Data, that is, the 16-34-th selection circuits output the 15 th Data data_15-33 th Data data_33, respectively, to write the 15 th Data data_15-33 th Data data_33 to the 16-34 th storage arrays, respectively; at this time, the 35 th selection circuit outputs the 34 th Data data_34 to write the 34 th Data data_34 into the 35 th storage array, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, thereby realizing accurate writing of the Data.

In one example, when a defective memory cell in a kth memory array is replaced by a redundant array, a1 st selection circuit outputs 1 st data, an N selection circuit outputs N-1 st data, a kth selection circuit does not output data, an i selection circuit outputs i-th data in a range of 1 < i < k, an i selection circuit outputs i-1 st data in a range of k < i < N, m < k < N, and k is a positive integer.

As shown in fig. 19, it is assumed that the failed storage array is one of the 19 th to 35 th storage arrays, for example, the 21 st storage array, that is, k=21. In one example, the 21 st storage array no longer stores Data, the 20 th Data data_20 that was originally written to the 21 st storage array is to be written to the 20 th storage array, the 19 th Data data_19 that was originally written to the 20 th storage array is to be written to the 19 th storage array, and the 18 th Data data_18 that was originally written to the 19 th storage array is to be written to the 18 th storage array (redundant array), completing the failover. Accordingly, the 1 st selection circuit outputs the 1 st Data data_1 to write the 1 st Data data_1 into the 1 st memory array; in the range of 1 < i < 21, the i-th selection circuit outputs the i-th Data, that is, the 2-th to 20-th selection circuits respectively output the 2-th to 20-th Data data_20 to write the 2-th to 20-th Data data_2 to 20-th Data data_20 into the 2-th to 20-th memory arrays respectively; the 21 st selection circuit does not output data so as to avoid writing data into the column where the fault storage array is located; within the range of 21 < i < 35, the i-th selection circuit outputs the i-1-th Data, that is, the 22-34-th selection circuits output the 21-th Data data_21-33-th Data data_33, respectively, to write the 21-th Data data_21-33-th Data data_33 to the 22-34-th storage arrays, respectively; the 35 th selection circuit outputs 34 th Data data_34 to write the 34 th Data data_34 into the 35 th storage array, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, and accurate writing of the Data is realized.

In one example, when a defective memory cell in the 1 st memory array is replaced by a redundant array, the 1 st selection circuit does not output the 1 st data, the N selection circuit outputs the N-1 st data, and the i selection circuit outputs the i-1 st data.

As shown in connection with fig. 20, it is assumed that the failed storage array is the 1 st storage array. In one example, the column in which the failed memory cell in the 1 st memory array is located does not store Data, the 1 st Data data_1 that is originally written to the 1 st memory array is written to the 2 nd memory array, the 2 nd Data data_2 that is originally written to the 2 nd memory array is written to the 3 rd memory array, and so on, until the 17 th Data data_17 that is originally written to the 17 th memory array is written to the 18 th memory array (redundant array), the failed replacement is completed. Correspondingly, the 1 st selection circuit does not output the 1 st Data data_1 so as to avoid writing Data into the column where the fault storage unit is located; the i-th selection circuit outputs the i-1-th Data, that is, the 2-34-th selection circuits output the 1 st Data data_1-33-th Data data_33, respectively, so as to write the 1 st Data data_1-33-th Data data_33 into the 2-34-th storage arrays, respectively; the 35 th selection circuit outputs 34 th Data data_34 to write the 34 th Data data_34 into the 35 th storage array, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, and accurate writing of the Data is realized.

In one example, when a defective memory cell in an nth memory array is replaced by a redundant array, a1 st selection circuit outputs 1 st data, an nth selection circuit does not output data, and an ith selection circuit outputs i-th data.

As shown in connection with fig. 21, assume that the failed storage array is the 35 th storage array. In one example, the column in which the 35 th storage array failed storage unit is located does not store Data any more, 34 th Data data_34 originally required to be written to the 35 th storage array is required to be written to the 34 th storage array, 33 th Data data_33 originally required to be written to the 34 th storage array is required to be written to the 33 th storage array, and so on until 18 th Data data_18 originally required to be written to the 19 th storage array is required to be written to the 18 th storage array (redundant array), and the failed replacement is completed. Accordingly, the 1 st selection circuit outputs the 1 st Data data_1 to write the 1 st Data data_1 into the 1 st memory array; the ith selection circuit outputs the ith Data, that is, the 2 nd to 34 th selection circuits output the 2 nd Data data_2 to 34 th Data data_34, respectively, to write the 2 nd to 34 th Data data_2 to 34 th Data data_34 into the 2 nd to 34 th memory arrays; the 35 th selection circuit does not output the 34 th Data data_34 so as to avoid writing Data into the column where the fault storage unit is located, so that the selection circuit outputs complete Data, and the storage array can accurately store the Data output by the selection circuit, and accurate writing of the Data is realized.

The above examples are described by way of example with respect to the case where the number of redundant arrays is one, and the cases where there are no and no faulty memory cells are provided in different positions of the redundant arrays, it will be understood that accurate writing of data can be achieved in the case of different examples by controlling the selection circuit to select to output corresponding data.

Further, in another example, the number of redundant arrays is a plurality and the redundant arrays are not adjacent. In particular, when a plurality of redundant arrays are provided, replacement when simultaneously failed for the same-positioned columns in a plurality of main storage arrays can be supported. For example, assuming that the 7 th storage array and the 15 th storage array are redundant arrays, the redundant columns in the 7 th storage array may be used to replace the columns in which the failed storage cells in the 1 st storage array to the 6 th storage array are located, and the redundant columns in the 15 th storage array may be used to replace the columns in which the failed storage cells in the 16 th storage array to the 35 th storage array are located. For the main storage arrays between two adjacent redundant arrays, such as the 8 th storage array to the 14 th storage array, the division can be performed at design time, for example, the 8 th storage array to the 9 th storage array are divided into the 7 th storage array to be responsible for fault replacement, and the 10 th storage array to the 14 th storage array are divided into the 15 th storage array to be responsible for fault replacement. The control mechanism for performing the fault replacement and selection circuit is similar to the previous solution. By arranging a plurality of redundant arrays, the simultaneous fault scene of columns with the same positions in a plurality of main storage arrays can be supported, and the reliability of fault repair is improved.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A memory, comprising:

the N storage arrays are respectively marked as a1 st storage array, a 2 nd storage array, … th storage array, an i th storage array, … th storage array and an N th storage array, wherein at least one storage array is a redundant array and at least one storage array is a main storage array, the redundant array is used for replacing a fault storage unit in the main storage array, i is more than 1 and less than N,2 is less than or equal to N, and i and N are positive integers;

N selection circuits respectively marked as a 1 st selection circuit, a2 nd selection circuit, … th selection circuit, an i th selection circuit, … th selection circuit and an N-1 st selection circuit, wherein the N selection circuits receive N-1 sets of data respectively marked as 1 st data, 2 nd data, … th data, … th data and N-1 st data;

The 1 st selection circuit receives the 1 st data and is used for outputting or not outputting the 1 st data to the 1 st storage array according to a1 st selection signal; the N-1-th data is received by the N-th selection circuit and is used for outputting or not outputting the N-1-th data to the N-th storage array according to an N-th selection signal; the ith selection circuit receives the ith-1 data and the ith data, and the ith selection circuit is used for outputting the ith-1 data or the ith data to the ith storage array according to an ith selection signal.

2. The memory of claim 1 wherein said memory array and said redundant array each comprise M columns, labeled column 1, column 2, …, column j, …, and column M, respectively, and wherein column j of said redundant array is used to replace column j of any one of said primary memory arrays, 1.ltoreq.j.ltoreq.m, and j and M are positive integers.

3. The memory of claim 2, wherein the selection circuit comprises:

Each sub-selection circuit of the 1 st selection circuit receives 1bit data in the 1 st data, each sub-selection circuit of the i th selection circuit receives the i-1 st data and 1bit data in the i th data respectively, and each sub-selection circuit of the N th selection circuit receives 1bit data in the N-1 st data.

4. A memory according to claim 3, wherein the sub-selection circuit comprises a data selector, a first data input of the data selector of the 1 st selection circuit receives 1bit data of the 1 st data, a selection end of the data selector of the 1 st selection circuit receives the 1 st selection signal, a first data input of the data selector of the i-1 st selection circuit receives 1bit data of the i-1 st data, a second data input of the data selector of the i-th selection circuit receives 1bit data of the i-th data, a selection end of the data selector of the i-th selection circuit receives the i-th selection signal, a first data input of the data selector of the N-th selection circuit receives 1bit data of the N-1 st data, and a selection end of the data selector of the N-th selection circuit receives the N-th selection signal.

5. The memory of claim 1, wherein the number of redundant arrays is one.

6. The memory of claim 5, wherein the 1 st memory array is the redundant array.

7. The memory according to claim 6, wherein when there is no defective memory cell, the 1 st selection circuit does not output 1 st data, the nth selection circuit outputs the N-1 st data, and the i-1 st selection circuit outputs the i-1 st data;

when the fault memory unit in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the ith selection circuit outputs the ith data in the range of 1< i < N, the ith selection circuit outputs the ith-1 st data in the range of N < i < N, and N is a positive integer;

when a defective memory cell in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the i st selection circuit outputs the i st data, and the nth selection circuit does not output the N-1 st data.

8. The memory of claim 5, wherein the nth memory array is the redundant array.

9. The memory according to claim 8, wherein when there is no defective memory cell, the 1 st selection circuit outputs the 1 st data, the N-th selection circuit does not output the N-1 st data, and the i-th selection circuit outputs the i-th data;

When the fault memory unit in the nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the ith selection circuit outputs the ith data in the range of 1 < i < N, and the ith selection circuit outputs the ith-1 st data in the range of N < i < N, wherein N is a positive integer;

When a defective memory cell in the 1 st memory array is replaced by the redundant array, the 1 st selection circuit does not output the 1 st data, the i-th selection circuit outputs the i-1 st data, and the N-th selection circuit outputs the N-1 st data.

10. The memory of claim 5, wherein an mth memory array is the redundant array, 1 < m < N and m is a positive integer.

11. The memory according to claim 10, wherein when there is no defective memory cell, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, and in a range of 1 < i < m, the ith selection circuit outputs the ith data, and in a range of m < i < N, the ith selection circuit outputs the i-1 st data;

when a faulty memory cell in an nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the N-1 st data, the ith selection circuit outputs the ith data in a range of 1 < i < N, the ith selection circuit outputs the ith-1 st data in a range of N < i < N, N < m and N is a positive integer;

When a faulty memory cell in a kth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit outputs the nth data, the ith selection circuit outputs the ith data in a range of 1 < i < k, the ith selection circuit outputs the ith data in a range of k < i < N, m < k < N and k is a positive integer;

When a faulty memory cell in a1 st memory array is replaced by the redundant array, the 1 st selection circuit does not output the 1 st data, the nth selection circuit outputs the N-1 st data, and the ith selection circuit outputs the i-1 st data;

When a defective memory cell in an nth memory array is replaced by the redundant array, the 1 st selection circuit outputs the 1 st data, the nth selection circuit does not output the N-1 st data, and the ith selection circuit outputs the i-th data.

12. The memory of claim 1, wherein the number of redundant arrays is a plurality and the redundant arrays are not adjacent.

13. The memory of any of claims 1-12, wherein at least one of the primary storage arrays is a check code storage array for storing check code data.

14. The memory of claim 13, wherein the memory further comprises: a verification module;

The verification module is connected with the N selection circuits, the data received by the N selection circuits comprise data to be written and verification code data, and the verification module is used for generating the verification code data according to the data to be written.