CN117938140A - Power tube overshoot-preventing driving circuit and driving method - Google Patents
Power tube overshoot-preventing driving circuit and driving method Download PDFInfo
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- CN117938140A CN117938140A CN202410310243.9A CN202410310243A CN117938140A CN 117938140 A CN117938140 A CN 117938140A CN 202410310243 A CN202410310243 A CN 202410310243A CN 117938140 A CN117938140 A CN 117938140A
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- 239000003990 capacitor Substances 0.000 claims description 15
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- 230000001934 delay Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000007493 shaping process Methods 0.000 description 2
- UYVFCOCPXKPSEW-UHFFFAOYSA-N 3-(1,2-benzothiazol-3-yl)-n,n-dimethyl-3-phenylpropan-1-amine Chemical compound N=1SC2=CC=CC=C2C=1C(CCN(C)C)C1=CC=CC=C1 UYVFCOCPXKPSEW-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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Abstract
The invention discloses a power tube overshoot-preventing driving circuit and a driving method. The circuit comprises a direct drive circuit, a pre-drive circuit and a strong drive circuit which are sequentially connected in series; the direct drive circuit is used for driving the power tube according to the input signal; the pre-driving circuit is used for acquiring and driving the power tube in an auxiliary manner according to the first output voltage of the power tube after the first delay; and the strong driving circuit is used for acquiring and finishing driving of the power tube according to the second output voltage of the power tube after the second delay. The overshoot-preventing driving circuit or method for the power tube disclosed by the invention has a simple structure, is easy to realize, can effectively prevent the power tube from overshooting during driving, and can obviously improve the reliability of the power tube.
Description
Technical Field
The invention relates to the technical field of driving circuit design, in particular to a power tube overshoot-preventing driving circuit and a driving method.
Background
At present, the low-voltage differential signal driving circuit is widely used in various systems, such as image data transmission, because of the advantages of low power consumption, low error rate, low crosstalk, low radiation, low noise, easy integration and the like.
But the general driving circuit drives an external load through a power tube; when the power tube is opened or closed too fast, an instant large current is generated, so that voltage overshoot occurs at the output end, and the reliability of the power tube is affected, wherein the overshoot voltage waveform is shown in figure 1;
Therefore, how to make the low-voltage differential signal driving circuit realize the overshoot prevention is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of this, the present invention provides a driving circuit and a driving method for preventing overshoot of a power tube, which aims to avoid overshoot when driving the power tube, so as to ensure the working reliability of the power tube.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
on one hand, the invention discloses an overshoot-preventing driving circuit of a power tube, which comprises a direct-drive circuit, a pre-drive circuit and a strong-drive circuit which are sequentially connected in series; wherein,
The direct drive circuit is used for driving the power tube according to the input signal;
The pre-driving circuit is used for acquiring and driving the power tube in an auxiliary manner according to the first output voltage of the power tube after the first delay;
and the strong driving circuit is used for acquiring and finishing driving of the power tube according to the second output voltage of the power tube after the second delay.
Further, the source electrode of the first PMOS tube is connected with a power supply voltage, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded; and meanwhile, the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the input signal output end together, and a common node between the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is connected with the grid electrode of the power tube together.
Further, the pre-driving circuit comprises a second PMOS tube, a third PMOS tube, a second NMOS tube and a third NMOS tube;
The source electrode of the second PMOS tube is connected with a power supply voltage, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded;
The grid electrode of the second PMOS tube and the grid electrode of the third NMOS tube are jointly connected with an input signal output end, the grid electrode of the third PMOS tube and the grid electrode of the second NMOS tube are jointly connected with an output signal output end of the power tube after first delay, and a common node between the drain electrode of the third PMOS tube and the drain electrode of the second NMOS tube is jointly connected with the grid electrode of the power tube.
Further, the strong driving circuit comprises a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube;
The source electrode of the fourth PMOS tube is connected with a power supply voltage, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the source electrode of the fifth NMOS tube is grounded;
The grid electrode of the fourth PMOS tube and the grid electrode of the fifth NMOS tube are jointly connected with an input signal output end, the grid electrode of the fifth PMOS tube and the grid electrode of the fourth NMOS tube are jointly connected with an output signal output end of the power tube after second delay, and a common node between the drain electrode of the fifth PMOS tube and the drain electrode of the fourth NMOS tube is jointly connected with the grid electrode of the power tube.
Further, the input signal is acquired and then inverted.
Further, the power tube further comprises an output voltage delay module, wherein the output voltage delay module is used for setting the time for collecting the output voltage of the power tube, and the output voltage delay module comprises a first delay and a second delay, and the duration of the first delay is smaller than that of the second delay.
Further, the output voltage delay module comprises a first inverter and a second inverter, and the output end of the power tube is sequentially connected with the first inverter and the second inverter in series and is used for realizing first delay through the first inverter and the second inverter.
Further, the second inverter is sequentially connected with the third inverter, the fourth inverter, the fifth inverter and the capacitor in series, the other end of the capacitor is connected with a power supply voltage, and a common node between the fifth inverter and the capacitor is used as an output voltage acquisition point to realize second delay.
In this embodiment, the capacitor C is controllable by adding Trim.
Further, the output voltage delay module delays through RC.
On the other hand, the invention also discloses an overshoot-preventing driving method for the power tube, which comprises the following steps:
s1, driving a power tube according to an input signal;
S2, after a first time delay, acquiring and driving the power tube in an auxiliary manner according to a first output voltage of the power tube;
and S3, after a second time delay, acquiring and finishing driving of the power tube according to the second output voltage of the power tube.
Compared with the prior art, the invention discloses the overshoot-preventing driving circuit and the driving method for the power tube, which can be used for driving the power tube in advance through the direct driving circuit according to an input signal so as to enable the power tube to generate initial output voltage; after a first time delay, collecting output voltage of the power tube, and accelerating driving speed of the power tube through a pre-driving circuit; and finally, after the second time delay, collecting the output voltage of the power tube again for directly and quickly completing the driving of the power tube by using the strong driving circuit.
The power tube passing-through driving circuit provided by the application has a simple structure, is easy to realize, can effectively prevent the overshoot phenomenon during driving of the power tube, further reduces the damage risk of the power tube, and improves the reliability of the power tube.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a voltage waveform diagram showing an overshoot in the prior art provided by the present invention;
FIG. 2 is a circuit diagram of an overshoot prevention driving circuit of a power tube according to the present invention;
FIG. 3 is a schematic diagram of an overshoot prevention driving module of a power tube according to the present invention;
FIG. 4 is a schematic diagram of the internal circuit of the output voltage delay module according to the present invention;
FIG. 5 is a diagram showing another example of the internal circuit structure of the output voltage delay module according to the present invention;
Fig. 6 is a graph showing correspondence between signal waveforms in the overshoot-preventing driving process of the power tube according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Specifically, the power tube overshoot-preventing driving circuit disclosed by the embodiment of the invention sequentially comprises a direct-drive circuit, a pre-drive circuit and a strong-drive circuit;
When the power tube driving circuit works, an input signal sequentially passes through the direct-drive circuit, the pre-drive circuit and the strong-drive circuit to drive the power tube; in the implementation, the power tube to be driven is an NMOS tube or a PMOS tube or other power tubes needing to be driven, and the invention does not limit the type and the type of the power tube;
The direct-drive circuit is used for driving the power tube according to the input signal;
The pre-driving circuit is used for acquiring and driving the power tube in an auxiliary manner according to the first output voltage of the power tube after the first delay;
and the strong driving circuit is used for acquiring and finishing driving of the power tube according to the second output voltage of the power tube after the second delay.
In the present invention, as shown in fig. 2,
The direct drive circuit comprises a first PMOS tube PM1 and a first NMOS tube NM1,
And the source electrode of the first PMOS tube PM1 is connected with the power supply voltage, the drain electrode is connected with the drain electrode of the first NMOS tube NM1, the source electrode of the first NMOS tube NM1 is grounded, meanwhile, the grid electrode of the first PMOS tube PM1 and the grid electrode of the first NMOS tube NM1 are jointly connected with the output end of the input signal INN, and the common node between the drain electrode of the first PMOS tube PM1 and the drain electrode of the first NMOS tube NM1 is jointly connected with the grid electrode of the power tube NM 0.
The pre-driving circuit comprises a second PMOS tube PM2a, a third PMOS tube PM 2b, a second NMOS tube NM2b and a third NMOS tube PM2a;
the connection relation is as follows: the source electrode of the second PMOS tube PM2a is connected to the supply voltage, the drain electrode is connected to the source electrode of the third PMOS tube PM2b, the drain electrode of the third PMOS tube PM2b is connected to the drain electrode of the second NMOS tube NM2b, the source electrode of the second NMOS tube NM2b is connected to the drain electrode of the third NMOS tube NM2a, and the source electrode of the third NMOS tube NM2a is grounded;
The gate of the second PMOS tube PM2a and the gate of the third NMOS tube NM2a are connected together to the input signal INN output end, the gate of the third PMOS tube PM2b and the gate of the second NMOS tube NM2b are connected together to the output signal output end of the power tube NM0 after the first delay t1, and the common node between the drain of the third PMOS tube PM2b and the drain of the second NMOS tube NM2b is connected together to the gate of the power tube NM 0.
The strong driving circuit comprises a fourth PMOS tube PM3a, a fifth PMOS tube PM3b, a fourth NMOS tube NM3b and a fifth NMOS tube NM3a;
The connection relation is as follows: the source electrode of the fourth PMOS tube PM3a is connected to the supply voltage, the drain electrode is connected to the source electrode of the fifth PMOS tube PM3b, the drain electrode of the fifth PMOS tube PM3b is connected to the drain electrode of the fourth NMOS tube NM3b, the source electrode of the fourth NMOS tube NM3b is connected to the drain electrode of the fifth NMOS tube NM3a, and the source electrode of the fifth NMOS tube NM3a is grounded;
The gate of the fourth PMOS tube PM3a and the gate of the fifth NMOS tube NM3a are connected together to the output end of the input signal INN, the gate of the fifth PMOS tube PM3b and the gate of the fourth NMOS tube NM3b are connected together to the output end of the output signal INN of the power tube NM0 after the second delay t2, and a common node between the drain of the fifth PMOS tube PM3b and the drain of the fourth NMOS tube NM3b is connected together to the gate of the power tube NM 0.
In this embodiment, as shown in fig. 3, the control module controls the opening of the pre-driving circuit and the strong driving circuit; preferably, the control module is set as an output voltage delay module in a matching manner, and the control module is used for setting the time for collecting the output voltage of the power tube, including a first delay and a second delay, wherein the duration of the first delay is smaller than that of the second delay, so as to reduce the direct driving time and further accelerate the overall driving speed of the power tube.
In an exemplary embodiment, as shown in fig. 4, the output voltage delay module includes a first inverter INV1a and a second inverter INV1b, and the output end of the power tube is sequentially connected in series with the first inverter INV1a and the second inverter INV1b, so that the output voltage delay module is used for shaping signals, that is, converting the output signals into normal logic levels, on the one hand, and is also used for realizing the first delay t1 through the first inverter INV1a and the second inverter INV1b, on the other hand, because the first delay time is shorter.
Further, the second inverter INV1b is sequentially connected in series with the third inverter INV2a, the fourth inverter INV2b, the fifth inverter INV2C and the capacitor C1, the other end of the capacitor C is connected to the supply voltage, and meanwhile, a common node between the fifth inverter INV2C and the capacitor C1 is used as an output voltage acquisition point, and similarly, the plurality of inverters are used for signal shaping and delay, and the capacitor C1 is designed because the second delay t2 has relatively long time, and the second delay t2 is realized through the charge-discharge assistance of the capacitor C1.
It should be noted that the number of inverters is only one of the preferred embodiments, and the specific number should not be taken as a specific limitation.
In this embodiment, the capacitor C1 is controlled by adding Trim.
Alternatively, the output voltage delay module may also delay through RC.
In another embodiment, the voltage delay circuit is copied as another branch and is commonly connected with the output end of the power tube so as to activate the pre-driving circuit and the strong driving circuit to complete the driving of the power tube.
As shown in fig. 5, the other branch includes inverters INV3a, INV3a and INV4a, INV4b, INV4C, and a capacitor C2; the common node between the inverters INV3a and INV4a is used as the acquisition end of the signal C, and the common node between the inverter INV4C and the capacitor C2 is used as the acquisition end of the signal D.
IN the invention, IN order to further optimize the technical scheme, the phase inversion is performed after the input signal is acquired, so as to ensure that the phases of the input signal IN and the output signal OUT are consistent.
At this time, the working principle of the overshoot-preventing driving circuit of the invention is as follows:
The obtained output signal is IN, and as shown IN fig. 6, the signal INN is obtained after passing through the inverter INV 0;
When the IN signal is at a high level, INN is at a low level, and at this time, the first NMOS transistor NM1, the second PMOS transistor PM2a and the fifth NMOS transistor NM3a are all IN a closed state,
Meanwhile, in the first stage, the first PMOS tube PM1 is turned on under the action of INN, that is, the on current I1 is transmitted to the gate of the power tube NM0 through the common node between the drain of the first PMOS tube PM1 and the drain of the first NMOS tube NM1, so that the power tube NMO is turned on to generate an initial output voltage OUT;
In the second stage, after a first time delay t1, the output voltage of the power tube NM0 is collected to obtain signals A and C, and the signals A and C are respectively input to the gates of the third PMOS tube PM2b and the second NMOS tube NM2 b; because the second PMOS tube PM2a is turned off, the loop where the second NMOS tube NM2b is located cannot be turned on, at this time, the closed second PMOS tube PM2a and the third PMOS tube PM2b form a current I2, which is superimposed to the gate of the power tube NM0, so that the control signal of the gate of the power tube NM0 is increased to increase the driving speed of the power tube NM 0;
In the third stage, after the second delay t2, output signals of the power tube NM0 turned over by three inverters are collected, referring to signals B and D in FIG. 6, and the signals B and D at low level are transmitted to the fifth PMOS tube PM3B and the fourth NMOS tube NM3B; similarly, since the fifth NMOS transistor NM3a is in the off state, the fourth NMOS transistor NM3b cannot form a loop; at this time, the fourth PMOS tube PM3a and the fourth NMOS tube NM3b are closed to generate the current I3, which is further superimposed on the gate of the power tube NM0, thereby directly completing the driving of the power tube NM 0.
When the INN signal is at a low level, the INN signal is at a high level, and at this time, the closed channels of the first PMOS tube PM1, the second PMOS tube PM2a and the fourth PMOS tube PM3a are narrowed, so that the on-current of each loop becomes smaller, and at the same time, the first NMOS tube NM1, the second PMOS tube PM2a and the fifth NMOS tube NM3a are all turned on, and the driving current to the power tube NM0 starts to be gradually reduced.
Namely, the first NMOS tube NM1 is firstly started, and the current I1 is conducted to be grounded, so that the output voltage is primarily reduced; then, as the output voltage is reduced, the output current I2 is further reduced, and meanwhile, under the action of the second NMOS tube NM2b and the second PMOS tube PM2a, the second NMOS tube NM2b and the second PMOS tube PM2a are gradually conducted to be grounded; the principle of stopping driving in the third stage is the same as that described above, and the description thereof will not be repeated here. The waveform of the output voltage of the power tube before and after driving is shown as OUT in FIG. 6, so that the impact generated during driving of the power tube can be effectively reduced.
In another embodiment, the invention also discloses an overshoot-preventing driving method for the power tube, which comprises the following steps:
s1, driving a power tube according to an input signal;
S2, after a first time delay, acquiring and driving the power tube in an auxiliary manner according to a first output voltage of the power tube;
and S3, after a second time delay, acquiring and finishing driving of the power tube according to the second output voltage of the power tube.
The circuit used for direct driving, auxiliary driving and final finishing driving is consistent with the method disclosed by the power tube over-drive circuit, so that repeated description is omitted here.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The overshoot-preventing driving circuit for the power tube is characterized by comprising a direct-drive circuit, a pre-drive circuit and a strong-drive circuit which are sequentially connected in series; wherein,
The direct drive circuit is used for driving the power tube according to the input signal;
The pre-driving circuit is used for acquiring and driving the power tube in an auxiliary manner according to the first output voltage of the power tube after the first delay;
and the strong driving circuit is used for acquiring and finishing driving of the power tube according to the second output voltage of the power tube after the second delay.
2. The power tube overshoot prevention driving circuit according to claim 1, wherein the direct drive circuit comprises a first PMOS tube and a first NMOS tube,
The source electrode of the first PMOS tube is connected with a power supply voltage, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded; and meanwhile, the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the input signal output end together, and a common node between the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube is connected with the grid electrode of the power tube together.
3. The overshoot-preventing driving circuit of the power tube according to claim 1, wherein the pre-driving circuit comprises a second PMOS tube, a third PMOS tube, a second NMOS tube and a third NMOS tube;
The source electrode of the second PMOS tube is connected with a power supply voltage, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the third NMOS tube is grounded;
The grid electrode of the second PMOS tube and the grid electrode of the third NMOS tube are jointly connected with an input signal output end, the grid electrode of the third PMOS tube and the grid electrode of the second NMOS tube are jointly connected with an output signal output end of the power tube after first delay, and a common node between the drain electrode of the third PMOS tube and the drain electrode of the second NMOS tube is jointly connected with the grid electrode of the power tube.
4. The power tube overshoot prevention driving circuit according to claim 1, wherein the strong driving circuit comprises a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube;
The source electrode of the fourth PMOS tube is connected with a power supply voltage, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the source electrode of the fifth NMOS tube is grounded;
The grid electrode of the fourth PMOS tube and the grid electrode of the fifth NMOS tube are jointly connected with an input signal output end, the grid electrode of the fifth PMOS tube and the grid electrode of the fourth NMOS tube are jointly connected with an output signal output end of the power tube after second delay, and a common node between the drain electrode of the fifth PMOS tube and the drain electrode of the fourth NMOS tube is jointly connected with the grid electrode of the power tube.
5. The overshoot prevention driving circuit of claim 1, wherein the input signal is first inverted after being obtained.
6. The power tube overshoot prevention driving circuit according to claim 1, further comprising an output voltage delay module, wherein the output voltage delay module is configured to set a time for collecting the output voltage of the power tube, and the output voltage delay module comprises a first delay and a second delay, and wherein a duration of the first delay is less than a duration of the second delay.
7. The overshoot-preventing driving circuit of claim 6, wherein the output voltage delay module comprises a first inverter and a second inverter, and the output terminal of the power tube is connected in series with the first inverter and the second inverter in sequence, so as to realize the first delay through the first inverter and the second inverter.
8. The overshoot-preventing driving circuit of claim 7, wherein the second inverter is sequentially connected in series with a third inverter, a fourth inverter, a fifth inverter and a capacitor, the other end of the capacitor is connected to a supply voltage, and a common node between the fifth inverter and the capacitor is used as an output voltage acquisition point to realize the second delay.
9. The power tube overshoot prevention driving circuit of claim 6, wherein said output voltage delay module delays through RC.
10. The overshoot-preventing driving method for the power tube is characterized by comprising the following steps of:
s1, driving a power tube according to an input signal;
S2, after a first time delay, acquiring and driving the power tube in an auxiliary manner according to a first output voltage of the power tube;
and S3, after a second time delay, acquiring and finishing driving of the power tube according to the second output voltage of the power tube.
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| CN202410310243.9A CN117938140B (en) | 2024-03-19 | 2024-03-19 | Power tube overshoot-preventing driving circuit and driving method |
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| CN202410310243.9A CN117938140B (en) | 2024-03-19 | 2024-03-19 | Power tube overshoot-preventing driving circuit and driving method |
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| US20020140452A1 (en) * | 1998-07-01 | 2002-10-03 | Jed Griffin | Constatnt CMOS driver |
| US20030164723A1 (en) * | 2002-03-04 | 2003-09-04 | Fujitsu Limited | Output buffer circuit |
| CN1518224A (en) * | 2002-11-20 | 2004-08-04 | 威盛电子股份有限公司 | Output driver with low ground jump noise |
| CN105576946A (en) * | 2015-12-28 | 2016-05-11 | 上海数明半导体有限公司 | Power tube driving circuit and method |
| CN108462488A (en) * | 2017-02-20 | 2018-08-28 | 意法半导体国际有限公司 | Tolerate the I/O drivers of aging |
| CN111224647A (en) * | 2020-03-13 | 2020-06-02 | 无锡硅动力微电子股份有限公司 | High-reliability GaN power tube rapid gate drive circuit |
-
2024
- 2024-03-19 CN CN202410310243.9A patent/CN117938140B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020140452A1 (en) * | 1998-07-01 | 2002-10-03 | Jed Griffin | Constatnt CMOS driver |
| US20030164723A1 (en) * | 2002-03-04 | 2003-09-04 | Fujitsu Limited | Output buffer circuit |
| CN1518224A (en) * | 2002-11-20 | 2004-08-04 | 威盛电子股份有限公司 | Output driver with low ground jump noise |
| CN105576946A (en) * | 2015-12-28 | 2016-05-11 | 上海数明半导体有限公司 | Power tube driving circuit and method |
| CN108462488A (en) * | 2017-02-20 | 2018-08-28 | 意法半导体国际有限公司 | Tolerate the I/O drivers of aging |
| CN111224647A (en) * | 2020-03-13 | 2020-06-02 | 无锡硅动力微电子股份有限公司 | High-reliability GaN power tube rapid gate drive circuit |
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