CN117891510B - Instruction acquisition method, apparatus, computer device and storage medium - Google Patents
Instruction acquisition method, apparatus, computer device and storage medium Download PDFInfo
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- 238000004590 computer program Methods 0.000 claims description 21
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the application provides an instruction acquisition method, an instruction acquisition device, computer equipment and a storage medium, wherein the instruction acquisition method comprises the following steps: the method comprises the steps that under the condition that the number of preset instruction storage modules does not exceed the preset number, an instruction acquisition module sends an instruction address to the instruction storage modules, wherein the instruction storage modules are connected with the instruction acquisition module; the instruction storage module receives the instruction address and checks the instruction address; the instruction storage module determines whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address, so that the work task of the instruction acquisition module can be simplified, and the clock frequency of the assembly line during work can be improved.
Description
Technical Field
The present application relates to the field of instruction processing technologies of central processing units, and in particular, to an instruction acquisition method, an instruction acquisition device, a computer device, and a storage medium.
Background
As shown in FIG. 1, an instruction may be executed in a CPU in a number of stages, such as a 4-stage pipeline, and may be divided into five operations, namely, instruction fetch, decode, execute, and write back.
The instruction fetch module accesses the storage space storing the instruction and acquires the corresponding instruction, so that for the instruction fetch module which expects to return, the first step requires checking (the checking process is combinational logic) the address, and depending on the checking result, distributing access (such as which module is accessed to which module) to fetch the instruction to return, or checking not to pass the non-issuing access (such as that the address authority is checked in the current mode, or the hole address is accessed), that is, not sending the instruction fetch request to the storage space, and returning the reason why the checking is not passed according to the order of the instructions in the pipeline.
Disclosure of Invention
The embodiment of the application provides an instruction acquisition method, an instruction acquisition device, computer equipment and a storage medium.
In a first aspect of an embodiment of the present application, there is provided an instruction acquisition method, including:
The method comprises the steps that under the condition that the number of preset instruction storage modules does not exceed the preset number, an instruction acquisition module sends an instruction address to the instruction storage modules, wherein the instruction storage modules are connected with the instruction acquisition module;
the instruction storage module receives the instruction address and checks the instruction address; and determining whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address.
In an alternative embodiment of the present application, the checking of instruction addresses is performed; and determining whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address through multiplexing the logic circuit and the beating mode of the instruction storage module.
In an alternative embodiment of the present application, the check types for the instruction address include a first check type and a second check type, the method further comprising:
under the condition that the number of the preset instruction storage modules exceeds the preset number, the instruction acquisition module acquires the inspection type of the instruction address;
in the case that the checking type of the instruction address is the first checking type, the instruction acquisition module locally checks the instruction address and
The method comprises the steps that an inspection result is sent to an instruction storage module, the instruction storage module receives the inspection result, and whether the instruction acquisition module sends an instruction to the instruction storage module is determined according to the inspection result of an instruction address;
Under the condition that the checking type of the instruction address is a second checking type, the instruction acquisition module sends the instruction address to the instruction storage module, the instruction storage module receives the instruction address, checks the instruction address, and determines whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address, wherein the first checking type combination logic circuit is the universality checking of the instruction storage module connected with the instruction acquisition module, and the second checking type combination logic circuit is the individuation checking of the instruction storage module.
In an alternative embodiment of the present application, the checking of the attribute of the instruction address includes validity checking, attribute checking, and authority checking of the instruction address.
In an optional embodiment of the present application, the determining, according to the result of the checking the instruction address, whether the instruction obtaining module sends the instruction to the instruction storing module includes:
When the checking of the instruction address is the validity checking of the instruction address, responding to the instruction address as the hole address, and returning information without sending the instruction to the instruction acquisition module; in response to the instruction address being an accessible address, returning information to the instruction fetch module to send instructions to the instruction store module,
When the inspection of the instruction address is attribute inspection, responding to the attribute of the instruction address as the device attribute, and returning information without sending the instruction to the instruction acquisition module; and returning information of no instruction to be sent to the instruction acquisition module in response to the attribute of the instruction address being not the device attribute.
In an optional embodiment of the present application, in a case that the checking of the instruction address is a permission check, the checking of the instruction address includes:
Acquiring a working mode of an instruction acquisition module, and determining a mode access authority of an instruction address in the working mode according to the instruction address;
extracting the regional access rights of the instruction address from the instruction address;
And determining whether the instruction acquisition module has the authority to acquire the instruction corresponding to the instruction address according to the mode access authority and the area access authority of the instruction address, and taking the instruction as an authority checking result of the instruction address.
In an optional embodiment of the present application, the determining, according to the result of the checking the instruction address, whether the instruction obtaining module sends the instruction to the instruction storing module includes:
Under the condition that the instruction acquisition module has permission to acquire an instruction corresponding to the instruction address, returning information for transmitting the instruction to the instruction storage module to the instruction acquisition module;
and returning information of the invalid instruction to the instruction acquisition module under the condition that the instruction acquisition module does not have permission to acquire the instruction corresponding to the instruction address.
In a second aspect of the embodiment of the present application, there is provided an instruction fetch apparatus, including:
the instruction acquisition module is used for sending instruction addresses to the instruction storage module under the condition that the number of the preset instruction storage modules does not exceed the preset number, wherein the instruction storage module is connected with the instruction acquisition module;
the instruction storage module is used for receiving the instruction address and checking the instruction address; and determining whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address.
In a third aspect of the embodiment of the present application, there is provided a computer apparatus including: comprising a memory storing a computer program and a processor implementing the steps of any of the methods described above when the processor executes the computer program.
In a fourth aspect of embodiments of the present application, there is provided a computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any of the above.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of a prior art execution process of an instruction in a CPU;
FIG. 2 is a schematic diagram of a prior art execution process for acquiring instructions in a CPU;
FIG. 3 is a flow chart of a method for instruction fetching according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating an execution process of acquiring an instruction in a CPU according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating an execution process of acquiring an instruction in a CPU according to another embodiment of the present application;
FIG. 6 is a schematic diagram of another prior art execution process for fetching instructions in a CPU;
FIG. 7 is a schematic diagram illustrating an execution process of acquiring an instruction in a CPU according to another embodiment of the present application;
FIG. 8 is a schematic diagram of an instruction fetch device according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a computer device according to an embodiment of the present application.
Detailed Description
In the process of implementing the present application, the inventor finds that, at present, after the instruction address is inspected, the instruction address is judged to send or not send a request for fetching to each storage space, in this process, as shown in fig. 2, the address inspection is complicated, if the inspection (combinational logic) is not finished, and if the inspection (combinational logic) is finished, the instruction address is not sent, and the clock frequency is often reduced when the central processor core works due to the inspection and the post-inspection processing.
In view of the above problems, in the instruction acquisition method, the instruction acquisition device, the computer device and the storage medium are provided, where in the instruction acquisition method, when the number of preset instruction storage modules does not exceed the preset number, the instruction acquisition module sends an instruction address to the instruction storage module, where the instruction storage module is connected with the instruction acquisition module; the instruction storage module receives the instruction address and checks the instruction address; the instruction storage module determines whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address, so that the work task of the instruction acquisition module can be simplified, and the clock frequency of the assembly line during work can be improved.
The scheme in the embodiment of the application can be realized by adopting various computer languages, such as object-oriented programming language Java, an transliteration script language JavaScript and the like.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application and not exhaustive of all embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
Referring to fig. 3, the method for acquiring an instruction provided in the embodiment of the present application includes the following steps:
S1, under the condition that the number of the preset instruction storage modules does not exceed the preset number, the instruction acquisition module sends instruction addresses to the instruction storage modules, wherein the instruction storage modules are connected with the instruction acquisition module.
In this embodiment, the preset number may be any one integer.
In this embodiment, the instruction obtaining module may be a fetching module in the central processing unit, but is not limited thereto, as long as the fetching request to be sent out has a corresponding return.
In this embodiment, the instruction storage module includes, but is not limited to, an instruction local memory or an instruction cache.
S2, the instruction storage module receives the instruction address and checks the instruction address.
In this embodiment, the checking of the instruction address includes a validity check, an attribute check, and a permission check of the instruction address, where the validity check of the instruction address is used to check whether the instruction address is a hole address (an address where a memory space is not allocated).
In this embodiment, the attributes of the instruction address include, but are not limited to, a device attribute, a non-cacheable attribute, and a cacheable attribute, where the device attribute is used for memory mapped peripherals and similar locations, the non-cacheable attribute indicates that a memory region is not cached, and does not have out-of-order execution and early write policies, the cacheable attribute is used to indicate whether a block of memory region can be cached, and when a memory region is marked cacheable, the system will attempt to store the data of that region in cache so that it can be retrieved more quickly when needed, and the cacheable attribute can be applied to instruction and data storage.
In this embodiment, the checking of the instruction address determines the checking type of the instruction address according to the type of the instruction storage module accessed by the instruction fetching module, and in the actual application scenario, the instruction fetching module accesses the instruction local memory and the instruction cache, and the accessed instruction address needs to check the access rights under different modes.
In this embodiment, the checking of instruction addresses is performed; and determining whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address through multiplexing the logic circuit and the beating mode of the instruction storage module.
In this embodiment, part of the inspection logic of the instruction fetching module on the main pipeline is moved to the downstream instruction storage module, the instruction storage module executes the instruction and performs parallel inspection, the logic of the instruction storage module is multiplexed, the inspection result is shot along with the return of the inspection result by the instruction storage module, a clean signal is obtained, and the clean signal is used for processing, so that the working frequency of the main pipeline can be increased.
S3, the instruction storage module determines whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address. Referring to fig. 4, in the application scenario of the cpu pipeline, the method of the present application embeds the address check into the existing pipeline stage, and returns a check result without affecting the original logic, so that the instruction fetch module obtains a clean check result, and then processes the result, although the instruction memory module adds some repeated combinational logic checks, the number of the downstream instruction memory modules is not particularly large, so that the increase area is small, and therefore, the processing of the value fetch module can be simplified, the main frequency of the cpu is improved, and the number of beats is not increased. Therefore, the complex part of the attribute inspection is put downstream to be done, the frequency is ensured to be improved, and the beating number of each stage of pipeline is not increased.
In this embodiment, the check types for the instruction address include a first check type and a second check type, and the method further includes:
under the condition that the number of the preset instruction storage modules exceeds the preset number, the instruction acquisition module acquires the inspection type of the instruction address;
in the case that the checking type of the instruction address is the first checking type, the instruction acquisition module locally checks the instruction address and
The method comprises the steps that an inspection result is sent to an instruction storage module, the instruction storage module receives the inspection result, and whether the instruction acquisition module sends an instruction to the instruction storage module is determined according to the inspection result of an instruction address;
Under the condition that the checking type of the instruction address is a second checking type, the instruction acquisition module sends the instruction address to the instruction storage module, the instruction storage module receives the instruction address, checks the instruction address, and determines whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address, wherein the first checking type combination logic circuit is the universality checking of the instruction storage module connected with the instruction acquisition module, and the second checking type combination logic circuit is the individuation checking of the instruction storage module.
Referring to fig. 5, if the timing paths of the combinational logic circuit of the inspection of the access region in different modes are relatively small, and the timing paths of the combinational logic circuit of the pmp inspection are relatively large, the inspection of the access region may be inspected in the instruction fetch module as a first inspection type, and the pmp inspection may be inspected in the corresponding instruction storage module as a second inspection type. If the timing paths of the combinational logic circuits of the access area inspection under different modes are smaller but exceed the preset timing path threshold, the partial combinational logic circuits of the access area inspection are inspected in the instruction fetch module as a first inspection type, the rest of the combinational logic circuits of the access area inspection and pmp inspection are inspected in the corresponding instruction storage module as a second inspection type, wherein the second inspection types in the instruction storage module A and the instruction storage module B can be the same or different, or no inspection and processing are performed in the instruction storage module A or the instruction storage module B, wherein pmp inspection is a physical memory protection inspection, and the physical memory protection inspection records the memory area which can be accessed by a processor through a group of registers, and each register comprises a physical address range and corresponding access authority.
The instruction acquisition method of the application distributes the inspection and processing logic of the instruction fetch module to each stage of running water evenly, so that the time sequence of the main running water is better.
Aiming at the module to be checked, namely the instruction fetching module, if the checking and the processing are concentrated on the main flow, the timing sequence or the frequency of the main flow are inevitably influenced, the instruction fetching module is complex to realize, part of the checking with complex logic is adopted and is put down to the downstream to be checked and processed, and a clean checking result is returned to the instruction fetching module, and the instruction fetching module only needs to transmit the checking and processing result downwards.
In this embodiment, the determining, according to the result of checking the instruction address, whether the instruction acquisition module sends the instruction to the instruction storage module includes:
When the checking of the instruction address is the validity checking of the instruction address, responding to the instruction address as the hole address, and returning information without sending the instruction to the instruction acquisition module; in response to the instruction address being an accessible address, returning information to the instruction fetch module to send instructions to the instruction store module,
When the inspection of the instruction address is attribute inspection, responding to the fact that the attribute of the instruction address is not the device attribute, returning information for sending the instruction to the instruction storage module to the instruction acquisition module; and returning information without sending the instruction to the instruction acquisition module in response to the attribute of the instruction address being the device attribute.
In this embodiment, in a case where the checking of the instruction address is a permission check, the checking of the instruction address includes:
Acquiring a working mode of an instruction acquisition module, and determining a mode access authority of an instruction address in the working mode according to the instruction address;
extracting the regional access rights of the instruction address from the instruction address;
And determining whether the instruction acquisition module has the authority to acquire the instruction corresponding to the instruction address according to the mode access authority and the area access authority of the instruction address, and taking the instruction as an authority checking result of the instruction address.
In this embodiment, the determining, according to the result of checking the instruction address, whether the instruction acquisition module sends the instruction to the instruction storage module includes:
Under the condition that the instruction acquisition module has permission to acquire an instruction corresponding to the instruction address, returning information for transmitting the instruction to the instruction storage module to the instruction acquisition module;
and returning information of the invalid instruction to the instruction acquisition module under the condition that the instruction acquisition module does not have permission to acquire the instruction corresponding to the instruction address.
The address judgment of the instruction fetching module of the instruction obtaining method does not carry out inspection and processing on the main running water, but is put down into the storage space to carry out inspection processing and beating, so that the frequency on the main running water can be ensured, the instruction fetching module is easy to realize, and the instruction does not need to be additionally processed when the inspection is over.
In this embodiment, the method further includes:
under the condition that the number of the inspection types of the preset instruction storage module is one and the time sequence path of the combinational logic circuit of the inspection type is larger than the preset time sequence path, the instruction acquisition module locally inspects the instruction address and sends the inspection result of the instruction address to the instruction storage module, wherein the instruction storage module is connected with the instruction acquisition module;
the instruction storage module determines whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address.
Referring to fig. 6 and 7, the upstream instruction fetching module is simple in inspection processing, and the previous processing is to process whether to issue access according to the inspection result, but all the inspection is finished, the access is issued to the instruction storage module, the processing mode is the same, and the processing is only performed by the downstream instruction storage module, and the processing mode is as follows: in the current mode, if the corresponding address has no access right, an error signal and an error type are returned, wherein the access right comprises reading, writing and executing; accessing to a hole address, etc., returning a bus error. In fig. 6 and 7, the storage space is provided in the data storage module, and in practical applications, the storage space may also be provided outside the data storage module.
It should be understood that, although the steps in the flowchart are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or other steps.
Referring to fig. 8, an embodiment of the present application provides an instruction fetch apparatus, including:
The instruction acquisition module 11 is configured to send an instruction address to the instruction storage module when the number of preset instruction storage modules does not exceed the preset number, where the instruction storage module is connected with the instruction acquisition module;
An instruction storage module 12 for receiving an instruction address and checking the instruction address; and determining whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address.
The specific limitation of the instruction acquiring device may be referred to the limitation of the instruction acquiring method hereinabove, and will not be described herein. The various modules in the instruction fetch apparatus described above may be implemented in whole or in part in software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 9. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is for storing data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement an instruction fetching method as described above. Comprising the following steps: the system comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes any step of the instruction acquisition method when executing the computer program.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, can implement any of the steps of the instruction acquisition method as above.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. A method of instruction fetching, the method comprising:
The method comprises the steps that under the condition that the number of preset instruction storage modules does not exceed the preset number, an instruction acquisition module sends an instruction address to the instruction storage modules, wherein the instruction storage modules are connected with the instruction acquisition module;
The instruction storage module receives the instruction address and checks the instruction address; and determining whether the instruction acquisition module transmits an instruction to the instruction storage module according to the checking result of the instruction address,
Wherein the check type for the instruction address includes a first check type and a second check type, the method further comprising:
under the condition that the number of the preset instruction storage modules exceeds the preset number, the instruction acquisition module acquires the inspection type of the instruction address;
Under the condition that the checking type of the instruction address is the first checking type, the instruction acquisition module locally checks the instruction address and sends a checking result to the instruction storage module, the instruction storage module receives the checking result and determines whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address;
Under the condition that the checking type of the instruction address is a second checking type, the instruction acquisition module sends the instruction address to the instruction storage module, the instruction storage module receives the instruction address, checks the instruction address, and determines whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address, wherein the first checking type combination logic circuit is the universality checking of the instruction storage module connected with the instruction acquisition module, and the second checking type combination logic circuit is the individuation checking of the instruction storage module.
2. The method of claim 1, wherein the checking for instruction addresses is performed; and determining whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address through multiplexing the logic circuit and the beating mode of the instruction storage module.
3. A method according to any one of claims 1 to 2, wherein the checking of instruction addresses comprises validity checking, attribute checking and authority checking of instruction addresses.
4. A method according to claim 3, wherein determining whether the instruction fetch module sends an instruction to the instruction store module based on the result of the checking of the instruction address comprises:
When the checking of the instruction address is the validity checking of the instruction address, responding to the instruction address as the hole address, and returning information without sending the instruction to the instruction acquisition module; in response to the instruction address being an accessible address, returning information to the instruction fetch module to send instructions to the instruction store module,
When the inspection of the instruction address is attribute inspection, responding to the attribute of the instruction address as the device attribute, and returning information without sending the instruction to the instruction acquisition module; and returning information of no instruction to be sent to the instruction acquisition module in response to the attribute of the instruction address being not the device attribute.
5. A method according to claim 3, wherein, in the case where the checking of the instruction address is a permission check, the checking of the instruction address comprises:
Acquiring a working mode of an instruction acquisition module, and determining a mode access authority of an instruction address in the working mode according to the instruction address;
extracting the regional access rights of the instruction address from the instruction address;
And determining whether the instruction acquisition module has the authority to acquire the instruction corresponding to the instruction address according to the mode access authority and the area access authority of the instruction address, and taking the instruction as an authority checking result of the instruction address.
6. The method of claim 5, wherein determining whether the instruction fetch module sends the instruction to the instruction store module based on the result of the checking the instruction address comprises:
Under the condition that the instruction acquisition module has permission to acquire an instruction corresponding to the instruction address, returning information for transmitting the instruction to the instruction storage module to the instruction acquisition module;
and returning information of the invalid instruction to the instruction acquisition module under the condition that the instruction acquisition module does not have permission to acquire the instruction corresponding to the instruction address.
7. An instruction fetch apparatus comprising:
the instruction acquisition module is used for sending instruction addresses to the instruction storage module under the condition that the number of the preset instruction storage modules does not exceed the preset number, wherein the instruction storage module is connected with the instruction acquisition module;
The instruction storage module is used for receiving the instruction address and checking the instruction address; determining whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address,
Wherein the check types for the instruction address include a first check type and a second check type,
Under the condition that the number of the preset instruction storage modules exceeds the preset number, the instruction acquisition module acquires the inspection type of the instruction address;
Under the condition that the checking type of the instruction address is the first checking type, the instruction acquisition module locally checks the instruction address and sends a checking result to the instruction storage module, the instruction storage module receives the checking result and determines whether the instruction acquisition module sends an instruction to the instruction storage module according to the checking result of the instruction address;
Under the condition that the checking type of the instruction address is a second checking type, the instruction acquisition module sends the instruction address to the instruction storage module, the instruction storage module receives the instruction address, checks the instruction address, and determines whether the instruction acquisition module sends the instruction to the instruction storage module according to the checking result of the instruction address, wherein the first checking type combination logic circuit is the universality checking of the instruction storage module connected with the instruction acquisition module, and the second checking type combination logic circuit is the individuation checking of the instruction storage module.
8. A computer device, comprising: comprising a memory and a processor, said memory storing a computer program, characterized in that the processor implements the steps of the instruction fetch method of any of claims 1 to 6 when said computer program is executed.
9. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the instruction fetch method of any of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410302692.9A CN117891510B (en) | 2024-03-18 | 2024-03-18 | Instruction acquisition method, apparatus, computer device and storage medium |
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