CN117765995A - Memory bit and MRAM - Google Patents

Abstract

The application provides a memory bit and MRAM, this memory bit includes the MOS device, first bottom metal wire, first top metal wire, MTJ cell and second bottom metal wire, wherein, first bottom metal wire is located one side of MOS device, the one end of first bottom metal wire is connected with the drain terminal electricity of MOS device, first top metal wire is in one side of keeping away from the MOS device of first bottom metal wire, first top metal wire is connected with the other end electricity of first bottom metal wire, the MTJ cell is located between first top metal wire and the MOS device, the first end and the first top metal wire electricity of MTJ cell are connected, the second bottom metal wire is located between MTJ cell and the MOS device, the second bottom metal wire is connected with the second end electricity of MTJ cell, second bottom metal wire is not connected with first bottom metal wire. The method and the device avoid plasma damage to the MOS device caused by PID effect caused by MTJ etching.

Description

Memory bit and MRAM

Technical Field

The present application relates to the field of information storage, and in particular, to a memory bit and MRAM.

Background

The magnetic random access memory (Spin Transfer Torque-Based Magnetoresistive RAM, STT-MRAM) based on spin transfer torque has the advantages of non-volatility, unlimited erasable and fast writing, and the like, and is expected to become a next-generation low-power consumption general memory. The STT-MRAM basic memory cell includes a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, metal Oxide semiconductor field effect transistor) device and a magnetic tunnel junction (Magnetic Tunnel Junctions, abbreviated as MTJ).

The MTJ is prepared by inevitably introducing plasma charges related to etching and the like between the back-end Cu and Al processes of the MOS device, especially the MTJ etching is generally IBE (Ion beam etching), and the principle is that bombardment is performed by using bombarding particles, which introduces plasma charges, i.e., PID (plasma induced damage, potential induced decay) effect, to damage the MOS device, thereby affecting the electrical parameters of the MTJ and MOS devices in MRAM bits.

The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.

Disclosure of Invention

The main objective of the present application is to provide a memory bit and MRAM, so as to solve the problem in the prior art that the PID effect caused by MTJ etching damages the MOS device.

In order to achieve the above object, according to one aspect of the present application, there is provided a memory bit including a MOS device, a first bottom metal line, a first top metal line, an MTJ cell, and a second bottom metal line, wherein the first bottom metal line is located at one side of the MOS device, and one end of the first bottom metal line is electrically connected to a drain terminal of the MOS device; the first top metal wire is positioned on one side of the first bottom metal wire, which is far away from the MOS device, and the first top metal wire is electrically connected with the other end of the first bottom metal wire; the MTJ unit is positioned between the first top-layer metal wire and the MOS device, and the first end of the MTJ unit is electrically connected with the first top-layer metal wire; the second bottom metal line is located between the MTJ unit and the MOS device, the second bottom metal line is electrically connected with the second end of the MTJ unit, and the second bottom metal line is not connected with the first bottom metal line.

Optionally, the first top metal line is used for electrically connecting to a bit line, the source end of the MOS device is used for electrically connecting to a source line, and the gate of the MOS device is used for electrically connecting to a word line.

Optionally, the memory bit further includes a first via, a second via, a third via, and a fourth via, where one end of the first bottom metal line is electrically connected to the drain of the MOS device through the first via; the first top metal wire is electrically connected with the other end of the first bottom metal wire through the second through hole; the first end of the MTJ cell is electrically connected with the first top-layer metal line through the third through hole; the second bottom metal line is electrically connected to the second end of the MTJ cell through the fourth via.

Optionally, the memory bit further includes a second top metal line, where the second top metal line is located on a side of the second bottom metal line away from the MOS device and is electrically connected to the second bottom metal line, and the second top metal line is not connected to the first top metal line.

Optionally, the second top metal line is used for electrically connecting to a bit line, the source end of the MOS device is used for electrically connecting to a source line, and the gate of the MOS device is used for electrically connecting to a word line.

Optionally, the memory bit further includes a fifth via, wherein the second top metal line is electrically connected to the second bottom metal line through the fifth via, and/or the first bottom metal line and the second bottom metal line are located on the same structural layer; the first top metal line and the second top metal line are located on the same structural layer.

Optionally, the MOS device is an SOI (Silicon on buried oxide, silicon-on-insulator) -MOS device.

Optionally, the MTJ cell includes a reference layer, a tunneling layer, and a free layer that are stacked in sequence, where a surface of the free layer away from the tunneling layer is a first end of the MTJ cell, and a surface of the reference layer away from the tunneling layer is a second end of the MTJ cell.

Optionally, the MTJ cell is an in-plane magnetic anisotropic MTJ or a perpendicular magnetic anisotropic MTJ.

According to another aspect of the present application, there is also provided an MRAM including any one of the memory bits.

By adopting the technical scheme, the first section of the MTJ unit is connected with the first bottom metal wire through the first bottom metal wire, the drain end of the MOS device is electrically connected with the second section of the MTJ unit, and the second bottom metal wire is not connected with the first bottom metal wire, so that the second bottom metal wire connected with the MTJ is separated from the first bottom metal wire connected with the MOS device, the bottom metal wire of the MOS device is not directly connected with the MTJ, plasma damage to the MOS device due to MTJ etching is avoided, and the process quality and yield of products are improved. And further, the problem that the MOS device is damaged due to PID effect caused by MTJ etching in the prior art is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram of a memory bit structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memory bit structure according to another embodiment of the present application;

FIG. 3 illustrates a basic structural schematic of an MTJ according to an embodiment of the disclosure;

fig. 4 shows a basic structure diagram of a memory bit according to an embodiment of the present application.

Wherein the above figures include the following reference numerals:

10. a MOS device; 11. a source end; 12. a gate; 13. a drain end; 14. a top layer of silicon; 15. an oxygen burying layer; 20. an MTJ cell; 21. a first underlying metal line; 22. a second underlying metal line; 23. a first top metal line; 24. a second top metal line; 30. a first through hole; 31. a second through hole; 32. a third through hole; 33. a fourth through hole; 34. and a fifth through hole.

Detailed Description

It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background, the MTJ etching in the prior art causes PID effect, thereby damaging the MOS device, and in order to solve the above problem, the present application provides a memory bit and MRAM.

According to an exemplary embodiment of the present application, there is provided a memory bit, as shown in fig. 1, where the memory bit includes a MOS device 10, a first bottom metal line 21, a first top metal line 23, an MTJ cell 20, and a second bottom metal line 22, where the first bottom metal line 21 is located on one side of the MOS device 10, and one end of the first bottom metal line 21 is electrically connected to a drain terminal 13 of the MOS device 10; the first top metal line 23 is located on a side of the first bottom metal line 21 away from the MOS device 10, and the first top metal line 23 is electrically connected to the other end of the first bottom metal line 21; the MTJ cell 20 is located between the first top metal line 23 and the MOS device 10, and a first end of the MTJ cell 20 is electrically connected to the first top metal line 23; the second bottom metal line 22 is located between the MTJ cell 20 and the MOS device 10, the second bottom metal line 22 is electrically connected to the second terminal of the MTJ cell 20, and the second bottom metal line 22 is not connected to the first bottom metal line 21.

The storage bit adopts the first top metal wire to connect the first end of the MTJ unit and the first bottom metal wire, the first bottom metal wire is electrically connected with the drain end of the MOS device, the second end of the MTJ unit is electrically connected with the second bottom metal wire, and the second bottom metal wire is not connected with the first bottom metal wire, so that the second bottom metal wire connected with the MTJ is separated from the first bottom metal wire connected with the MOS device, thereby ensuring that the bottom metal wire of the MOS device is not directly connected with the MTJ, avoiding plasma damage to the MOS device due to the etching of the MTJ, eliminating the influence of PID effect on the electrical parameters of the MTJ and the MOS device in the storage bit, improving the process quality and yield of products, and effectively solving the problem that the MOS device is damaged due to the PID effect caused by the etching in the prior art.

In addition, as shown in fig. 4, the conventional memory bit in the prior art directly connects the MOS device with the MTJ unit, where the gate of the MOS is electrically connected to the word line and the source is electrically connected to the bit line, and the conventional memory bit structure causes potential induced attenuation caused by etching the MTJ, ion migration, and component performance attenuation causes great damage to the MOS device.

In the prior art, in order to solve the problem that plasma damage is caused to an MOS device by MTJ etching, a channel for discharging charges such as a protection diode is added in a bit, so that the volume of the bit is relatively increased, the bit area is relatively reduced by adopting the storage bit structure, and the miniaturization of the bit is realized.

According to one embodiment of the present application, as shown in fig. 1, the first top metal line 23 is used for electrically connecting to a bit line, the source terminal 11 of the MOS device 10 is used for electrically connecting to a source line, and the gate 12 of the MOS device 10 is used for electrically connecting to a word line. In the application, the bottom metal wire (namely the first bottom metal wire) of the MOS device is not directly connected with the MTJ unit, but is firstly jumped to the first top metal wire, and then is connected to the second bottom metal wire from the first top metal wire, so that plasma damage to the MOS device caused by MTJ etching is further avoided, and the process quality and yield of the product are improved.

In another embodiment, as shown in fig. 1, the memory bit further includes a first via 30, a second via 31, a third via 32, and a fourth via 33, wherein one end of the first bottom metal line 21 is electrically connected to the drain terminal 13 of the MOS device 10 through the first via 30; the first top metal line 23 is electrically connected to the other end of the first bottom metal line 21 through the second via hole 31; a first end of the MTJ cell 20 is electrically connected to the first top metal line 23 through the third via 32; the second underlying metal line 22 is electrically connected to the second terminal of the MTJ cell 20 through the fourth via 33. Thus, the electric connection of each component can be well realized, and the fact that the bottom metal wire of the MOS device is not directly connected with the MTJ unit is further ensured.

In actual production, the bottom structural layer is firstly manufactured, and then the upper structural layer is manufactured, so that the structural layer where the MOS device is arranged is firstly manufactured, then the structural layer where the first through hole is arranged is manufactured, then the structural layer where the first bottom metal wire and the second bottom metal wire are arranged is manufactured, then the structural layers where the second through hole, the third through hole, the fourth through hole and the MTJ unit are arranged are manufactured, and finally the structural layer where the first top metal wire is arranged is manufactured. Therefore, even if the structure of the whole memory bit is that the first end of the MTJ cell is electrically connected to the first top metal line through the third via, the first top metal line is electrically connected to the first bottom metal line through the second via, and the first bottom metal line is electrically connected to the MOS device through the first via, in the actual production process, the MTJ cell is fabricated without being electrically connected to the MOS device through the first top metal line and the first bottom metal line, so that the PID effect generated when the MTJ cell is fabricated will not affect the MOS device through the first top metal line and the first bottom metal line.

In order to further eliminate the effect of plasma on the whole device, in one embodiment, as shown in fig. 2, the memory bit further includes a second top metal line 24, where the second top metal line 24 is located on a side of the second bottom metal line 22 away from the MOS device 10 and is electrically connected to the second bottom metal line 22, and the second top metal line 24 is not connected to the first top metal line 23. In this embodiment, the MTJ is also connected from the second bottom metal line to the second top metal line by an upward jumper method, so as to further avoid the damage of the device caused by the plasma generated in the MTJ manufacturing process.

Specifically, as shown in fig. 2, the second top metal line 24 is used for electrically connecting to a bit line, the source terminal 11 of the MOS device 10 is used for electrically connecting to a source line, and the gate 12 of the MOS device 10 is used for electrically connecting to a word line.

According to yet another embodiment of the present application, the memory bit further includes a fifth via 34 as shown in fig. 2, wherein the second top metal line 24 is electrically connected to the second bottom metal line 22 through the fifth via 34.

In addition, in the actual process of manufacturing the memory bit, in order to ensure that the manufacturing process is simpler, the memory bit structure is more easily obtained, and the first bottom metal line 21 and the second bottom metal line 22 are illustratively located on the same structural layer; the first top metal line 23 and the second top metal line 24 are located on the same structural layer.

In actual production, the bottom structural layer is firstly manufactured, and then the upper structural layer is manufactured, so that the structural layer where the MOS device is arranged is firstly manufactured, then the structural layer where the first through hole is arranged is manufactured, then the structural layer where the first bottom metal wire and the second bottom metal wire are arranged is manufactured, then the structural layers where the second through hole, the third through hole, the fourth through hole, the fifth through hole and the MTJ unit are manufactured, and finally the structural layers where the first top metal wire and the second top metal wire are arranged are manufactured. Therefore, the second top metal line can well avoid the influence of PID effect generated during etching the MTJ unit on the bit line, and further avoid the influence on the subsequent process.

The MOS device can be Bulk CMOS, for Bulk MOS device, the influence on Bulk CMOS in the process of MTJ manufacturing process is mainly concentrated on the damage to gate oxide, and the source and drain ends can be used as charge release paths. Through the memory bit structure, the damage of the PID effect in the MTJ manufacturing process to the gate oxide of Bulk CMOS is further avoided.

Of course, the MOS device described above in the present application is not limited to the Bulk CMOS device described above, and in another specific embodiment, the MOS device is a Silicon on buried oxide MOS (SOI-MOS) device. Compared with Bulk (nano Bulk silicon) CMOS devices, SOI-MOS devices are applied to radio frequency RF (Radio Frequency), low power chips due to their extremely low static power consumption and small threshold voltage variation. For the SOI-MOS device, charge enrichment introduced by the source and drain ends in the process cannot be discharged to the substrate, so that the threshold voltage, saturation current, leakage current and other parameters of the SOI-MOS device are also affected, and the distribution characteristics (Variation) are deteriorated. For SOI-MOS devices, plasma damage is introduced to the gate, source and drain terminals during the MTJ fabrication process, and the drift of device parameters is caused by fixed or trapped charges at the interface between the insulating layer and the top silicon layer. By using the memory bit structure, the first bottom metal wire of the SOI-MOS device is not directly connected with the MTJ, but is firstly jumped from the first through hole to the first top metal wire, and then is connected to the MTJ and the second bottom metal wire from the first top metal wire through the second through hole Kong Hui.

Specifically, as shown in fig. 1, the SOI-MOS device includes a source terminal 11, a gate electrode 12, a drain terminal 13, a top silicon layer 14, and a buried oxide layer 15, and the specific positional relationship thereof is shown in fig. 1. The buried oxide layer 15 separates the body of the MOS device 10 from the substrate.

In a specific embodiment, as shown in fig. 3, the MTJ cell includes a reference layer, a tunneling layer, and a free layer stacked in sequence, where a surface of the free layer away from the tunneling layer is a first end of the MTJ cell, and a surface of the reference layer away from the tunneling layer is a second end of the MTJ cell.

Illustratively, the MTJ cell described above may be selected as an in-plane magnetically anisotropic MTJ or as a perpendicular magnetically anisotropic MTJ. The in-plane magnetic anisotropy refers to magnetic anisotropy in a certain plane or interface, and refers to a phenomenon in which the magnetic properties of a substance change with direction. The magnetic susceptibility of the soft magnetic body and the magnetization curve of the ferromagnetic body are changed along with the magnetization direction. The in-plane magnetic anisotropy effect has directionality, the magnitude and sign of which are related to distance and direction. The perpendicular magnetic anisotropy is applied to a perpendicular magnetic anisotropy random access memory, and the perpendicular magnetic anisotropy material has lower critical flip current density and higher thermal stability, and can have potential application value in high-density spin torque.

According to another exemplary embodiment of the present application, there is also provided an MRAM including any one of the above memory bits.

According to the MRAM, the first top metal wire is used for connecting the first section of the MTJ unit with the first bottom metal wire, the first bottom metal wire is electrically connected with the drain end of the MOS device, the second section of the MTJ unit is electrically connected with the second bottom metal wire, the second bottom metal wire is not connected with the first bottom metal wire, the second bottom metal wire connected with the MTJ is separated from the first bottom metal wire connected with the MOS device, therefore, the bottom metal wire of the MOS device is not directly connected with the MTJ, the influence of PID effect caused by MTJ etching on parameters of the SOI MOS device in the prior art is avoided, plasma damage to the MOS device due to MTJ etching is avoided, and the process quality and yield of products are improved.

In another embodiment, in the memory bit of the MRAM, the MOS device is an SOI-MOS device, and the MRAM process can be fully compatible with the SOI-CMOS process, so that an additional photomask is not required, thereby reducing the manufacturing cost.

From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

1) According to the storage bit, the first top metal wire is used for connecting the first end of the MTJ unit with the first bottom metal wire, the first bottom metal wire is electrically connected with the drain end of the MOS device, the second end of the MTJ unit is electrically connected with the second bottom metal wire, the second bottom metal wire is not connected with the first bottom metal wire, and the second bottom metal wire connected with the MTJ is separated from the first bottom metal wire connected with the MOS device, so that the bottom metal wire of the MOS device is not directly connected with the MTJ, plasma damage to the MOS device due to MTJ etching is avoided, influence of PID effect on electrical parameters of the MTJ and the MOS device in the storage bit is eliminated, the process quality and yield of products are improved, and the problem that the MOS device is damaged due to the PID effect caused by the MTJ etching in the prior art is effectively solved.

2) According to the MRAM, the first top metal wire is used for connecting the first section of the MTJ unit with the first bottom metal wire, the first bottom metal wire is electrically connected with the drain end of the MOS device, the second section of the MTJ unit is electrically connected with the second bottom metal wire, the second bottom metal wire is not connected with the first bottom metal wire, the second bottom metal wire connected with the MTJ is separated from the first bottom metal wire connected with the MOS device, therefore, the bottom metal wire of the MOS device is not directly connected with the MTJ, the influence of PID effect caused by MTJ etching on parameters of the SOI MOS device in the prior art is avoided, plasma damage to the MOS device due to MTJ etching is avoided, and the process quality and yield of products are improved.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A memory bit, comprising:

a MOS device;

the first bottom metal wire is positioned at one side of the MOS device, and one end of the first bottom metal wire is electrically connected with the drain end of the MOS device;

the first top metal wire is positioned on one side of the first bottom metal wire, which is far away from the MOS device, and is electrically connected with the other end of the first bottom metal wire;

the MTJ unit is positioned between the first top-layer metal wire and the MOS device, and the first end of the MTJ unit is electrically connected with the first top-layer metal wire;

and the second bottom metal wire is positioned between the MTJ unit and the MOS device, is electrically connected with the second end of the MTJ unit, and is not connected with the first bottom metal wire.

2. The memory bit of claim 1, wherein the first top metal line is for electrically connecting a bit line, a source terminal of the MOS device is for electrically connecting a source line, and a gate of the MOS device is for electrically connecting a word line.

3. The memory bit of claim 1, wherein the memory bit further comprises:

one end of the first bottom metal wire is electrically connected with the drain end of the MOS device through the first through hole;

the first top metal wire is electrically connected with the other end of the first bottom metal wire through the second through hole;

a third via through which a first end of the MTJ cell is electrically connected to the first top metal line;

and the second bottom metal wire is electrically connected with the second end of the MTJ unit through the fourth through hole.

4. The memory bit of claim 1, wherein the memory bit further comprises:

and the second top metal wire is positioned on one side of the second bottom metal wire far away from the MOS device and is electrically connected with the second bottom metal wire, and the second top metal wire is not connected with the first top metal wire.

5. The memory bit of claim 4, wherein the second top metal line is for electrically connecting a bit line, a source terminal of the MOS device is for electrically connecting a source line, and a gate of the MOS device is for electrically connecting a word line.

6. The memory bit of claim 4, wherein,

the memory bit further includes: a fifth via, through which the second top metal line is electrically connected to the second bottom metal line,

and/or the number of the groups of groups,

the first bottom metal line and the second bottom metal line are positioned on the same structural layer;

the first top metal line and the second top metal line are located on the same structural layer.

7. The memory bit according to any one of claims 1 to 6, wherein the MOS device is an SOI-MOS device.

8. The memory bit of any of claims 1-6, wherein the MTJ cell comprises a reference layer, a tunneling layer, and a free layer stacked in sequence, wherein a surface of the free layer away from the tunneling layer is a first end of the MTJ cell, and a surface of the reference layer away from the tunneling layer is a second end of the MTJ cell.

9. The memory bit of any one of claims 1 to 6, wherein the MTJ cell is an in-plane magnetically anisotropic MTJ or a perpendicular magnetically anisotropic MTJ.

10. An MRAM, comprising: the memory bit of any one of claims 1 to 9.