CN117728778A - Low-voltage robustness enhanced capacitor bias floating inverting amplifier - Google Patents

Abstract

The invention discloses a low-voltage robustness enhanced capacitor bias floating inverting amplifier, which comprises a capacitor bias circuit, a capacitor coupling inverting amplifying circuit and a storage capacitor circuit, wherein the capacitor bias circuit is used for providing bias voltage for the capacitor coupling inverting amplifying circuit; the energy storage capacitor circuit is used for supplying power to the capacitive coupling inverting amplification circuit; the capacitive coupling inverting amplifying circuit is used for amplifying the differential input signal to obtain a differential output signal. The floating inverting amplifier has simple control logic, adopts a capacitance bias and auto-zero mode to determine the bias of the transistor, improves the robustness of the bias current of the amplifying tube, and can lead the circuit to work under lower power supply voltage.

Description

Low-voltage robustness enhanced capacitor bias floating inverting amplifier

Technical Field

The invention belongs to the technical field of analog circuits, and particularly relates to a low-voltage robustness-enhanced capacitor bias floating inverting amplifier.

Background

In internet of things applications, many sensors and biomedical devices are powered by an energy harvester, and the output voltage of the energy harvester is typically within a few hundred mV, so it is highly desirable that the amplifier can operate at low voltages.

However, under sub-1V (less than 1V) power supply, the design difficulty of the analog circuit is also greatly increased. Amplifiers are the most basic analog circuit blocks, which are very widely used. However, under the condition of sub-1V power supply, a complex amplifier design cannot be realized, and a simple structure is required to realize the amplifier function.

The floating inverting amplifier (Floating Inverter Amplifier, FIA) as a dynamic amplifier of simple construction has numerous advantages: static power consumption is not required, so that the energy efficiency is high; the bandwidth and the power consumption are adjustable along with the working frequency; the output common mode is stable, and an additional common mode feedback circuit and the like are not needed. However, the FIA cannot operate under the sub-1V power supply, and in patent zl202310955562. X, the applicant proposes a compact Low Voltage Floating Inverter Amplifier (LVFIA), as shown in fig. 1. LVFIA can realize sub-1V power supply, but at phase phi ₁ When the NMOS and PMOS currents are defined independently, the problem of current adaptation is unavoidable, and therefore the robustness is still insufficient. And this scheme requires a plurality of control timing clocks, and is complex.

Disclosure of Invention

The invention aims to: the invention aims to solve the technical problem of providing a low-voltage robustness enhanced capacitor bias floating inverting amplifier aiming at the defects of the prior art.

In order to solve the technical problems, the invention discloses a low-voltage robustness-enhanced capacitor bias floating inverting amplifier (Capacitively Bias FIA, CBFIA), which comprises a capacitor bias circuit, a capacitor coupling inverting amplifying circuit and a storage capacitor circuit, wherein the capacitor bias circuit is used for providing bias voltage for the capacitor coupling inverting amplifying circuit; the energy storage capacitor circuit is used for supplying power to the capacitive coupling inverting amplification circuit; the capacitive coupling inverting amplifying circuit is used for amplifying the differential input signal to obtain a differential output signal.

Further, the capacitive coupling inverting amplifier circuit comprises a first input transistor circuit and a second input transistor circuit, wherein one input end of the first input transistor circuit is connected with one input end of the second input transistor circuit, and the connection part receives the differential input signal Vx and passes through a first switch S ₁ Grounding; the other input end of the first input transistor circuit is connected with the other input end of the second input transistor circuit, and the connection part receives the differential input signal Vy and passes through the fourth switch S ₄ Grounding; the two output ends of the first input transistor circuit are respectively connected with the two output ends of the second input transistor circuit, and the connection part forms a differential output node V _ON And V _OP 。

Further, the first input transistor circuit comprises a first pair of input transistors and an auto-zero capacitor respectively connected with the gates of the first pair of input transistors, the source stages of the first pair of input transistors are connected, and the connection part is connected with one end of the energy storage capacitor circuit; one end of the energy storage capacitor circuit is also connected with a tenth switch S ₁₀ Grounding; the gates of the first pair of input transistors are respectively connected with a fifth switch S ₅ And a sixth switch S ₆ And the connecting part is connected with the capacitor bias circuit.

Further, the capacitance bias circuit includes a first capacitance bias circuit for providing a bias voltage for the first pair of input transistors, including a first capacitance C ₁ Transistor M ₅ Seventh switch S ₇ And an eighth switch S ₈ The transistor M ₅ The source electrode of (2) is grounded, the grid electrode is connected with the drain electrode, and the connection part is connected with a seventh switch S ₇ Is connected with one end of the connecting rod; first capacitor C ₁ One end of which is grounded and the other end of which is connected with a seventh switch S ₇ Is connected with the other end of the fifth switch S ₅ And a sixth switch S ₆ Is connected with the connecting part of the two parts; first capacitor C ₁ The other end of (2) also passes through an eighth switch S ₈ And connecting a power supply voltage. Due to the introduction of additional transistors M ₅ Diode connections are made so that the CBFIA circuit can be operated at lower supply voltages.

Further, the second input transistor circuit comprises a second pair of input transistors and an auto-zero capacitor respectively connected with the gates of the second pair of input transistors, the source stages of the second pair of input transistors are connected, and the connection part is connected with the other end of the energy storage capacitor circuit; the other end of the energy storage capacitor circuit is also provided with a ninth switch S ₉ Connecting a power supply voltage; the gates of the second pair of input transistors are respectively connected with a second switch S ₂ And differential output node V _ON Connected to and through a third switch S ₃ And differential output node V _OP And (5) connection.

And the bias of the first pair of input transistors and the bias of the second pair of input transistors are determined by adopting a capacitance bias and auto-zero mode, so that the same current flowing through the second pair of input transistors and the first pair of input transistors is ensured, and the robustness of the bias current of the input transistors is improved.

Further, the drains of the first pair of input transistors are respectively connected with the drains of the second pair of input transistors, and a differential output node V is formed at the connection position _ON And V _OP 。

Further, the first input transistor circuit further comprises a third pair of input transistors, the second input transistor circuit further comprises a fourth pair of input transistors, the drains of the first pair of input transistors are respectively connected with the source stages of the third pair of input transistors, the drains of the third pair of input transistors are respectively connected with the drains of the fourth pair of input transistors, and the junction forms a differential output node V _ON And V _OP The method comprises the steps of carrying out a first treatment on the surface of the The source of the fourth pair of input transistors is connected with the drain of the second pair of input transistors respectively; the gates of the third pair of input transistors are connected with the bias voltage V ₄ The grid electrodes of the fourth pair of input transistors are connected with the bias voltage V ₃ . The direct current gain can be improved by expanding the structure into a cascode structure.

Further, the first switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth switch S ₉ And a tenth switch S ₁₀ From auto-zero phase phi ₁ Control, eighth switch S ₈ From the amplified phase phi ₂ Control of the auto-zero phase phi ₁ And amplifying the phase phi ₂ Are mutually in opposite phase;

in the auto-zero phase phi ₁ First switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth switch S ₉ And a tenth switch S ₁₀ Closing, eighth switch S ₈ Disconnecting the energy storage capacitor circuit and charging; first capacitor C precharged in the previous phase ₁ And an auto-zero capacitor connected to the gates of the first pair of input transistors respectively for charge sharing and passing through transistor M ₅ Discharging;

the bias voltage of the gate of the first pair of input transistors is recorded as V ₂ The bias voltage of the grid electrode of the second pair of input transistors is V ₁ By controlling the auto-zero phase phi ₁ Can change the bias voltage V ₂ To determine the bias current of the first pair of input transistors while the second pair of input transistors is auto-zeroed to bias voltage V ₁ And storing the offset voltage and the flicker noise together on an auto-zero capacitor respectively connected with the gates of the second pair of input transistors. Since the bias of both the first and second pairs of input transistors is controlled by the auto-zero phase Φ ₁ The duty cycle of (2) is freely determined, so that the output swing of the CBFIA is not limited by the threshold voltage Vth of the MOS transistor.

Further, at the amplifying phase Φ ₂ First switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ First, theNine switches S ₉ And a tenth switch S ₁₀ Open, eighth switch S ₈ Closing, first capacitance C ₁ Charging; the energy storage capacitor circuit supplies power to the capacitive coupling inverting amplifying circuit, V ₁ And V ₂ For auto-zeroing phase phi ₁ The differential input signal is coupled to the first and second pairs of input transistors through an auto-zero capacitance, and the first and second pairs of input transistors amplify the signals to obtain a differential output signal.

Further, the capacitance bias circuit further comprises a second capacitance bias circuit and a third capacitance bias circuit, wherein the second capacitance bias circuit is used for providing bias voltage V ₃ A third capacitor bias circuit for providing bias voltage V ₄ ；

The second capacitance bias circuit comprises a second capacitance C ₂ Transistor M ₁₀ Eleventh switch S ₁₁ And a twelfth switch S ₁₂ The transistor M ₁₀ The source electrode of (1) is grounded, the grid electrode is connected with the drain electrode, and a bias voltage V is formed at the connection part ₃ And is connected with an eleventh switch S ₁₁ Is connected with one end of the connecting rod; second capacitor C ₂ One end of which is grounded and the other end of which is connected with an eleventh switch S ₁₁ Is connected with the other end of the connecting rod; second capacitor C ₂ The other end of (2) also passes through a twelfth switch S ₁₂ Connecting a grounding voltage;

the third capacitor bias circuit comprises a third capacitor C ₃ Transistor M ₁₁ Thirteenth switch S ₁₃ And a fourteenth switch S ₁₄ The transistor M ₁₁ The source electrode of (1) is grounded, the grid electrode is connected with the drain electrode, and a bias voltage V is formed at the connection part ₄ And is connected with thirteenth switch S ₁₃ Is connected with one end of the connecting rod; third capacitor C ₃ One end of which is grounded and the other end of which is connected with a thirteenth switch S ₁₃ Is connected with the other end of the connecting rod; third capacitor C ₃ The other end of (2) also passes through a fourteenth switch S ₁₄ Connecting a power supply voltage;

eleventh switch S ₁₁ And a thirteenth switch S ₁₃ From auto-zero phase phi ₁ Control, twelfth switch S ₁₂ And a fourteenth switch S ₁₄ From the amplified phase phi ₂ And (5) controlling.

The bias of the cascode structure is also generated by a capacitive bias mode, so that the robustness of CBFIA along with the change of the supply voltage is maintained while the gain is improved.

The beneficial effects are that:

1) The low-voltage robust enhanced capacitor bias floating inverting amplifier provided by the application introduces an additional transistor M ₅ The diode connection is carried out, so that the circuit can work at a lower power supply voltage, and sub-1V power supply can be easily realized.

2) And the bias of the first pair of input transistors and the bias of the second pair of input transistors are determined by adopting a capacitance bias and auto-zero mode, so that the same current flowing through the second pair of input transistors and the first pair of input transistors is ensured, and the robustness of the bias current of the input transistors is improved.

3) And due to skillfully combining an automatic zeroing technology, offset voltage and flicker noise are reduced, so that the noise performance of the floating inverting amplifier is improved.

4) Since the bias of both the first and second pairs of input transistors is controlled by the auto-zero phase Φ ₁ The duty cycle of (2) is freely determined, so that the output swing of the floating inverting amplifier is not limited by the threshold voltage Vth of the MOS transistor.

5) The control logic is simple, and only one group of reverse clocks is needed.

Drawings

The foregoing and/or other advantages of the invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings and detailed description.

Fig. 1 is a circuit schematic of a low voltage floating inverter amplifier.

Fig. 2 is a schematic circuit diagram of a low-voltage robust enhanced capacitor bias floating inverting amplifier according to an embodiment of the present application.

Fig. 3 is a schematic diagram of another circuit of a low-voltage robust enhanced capacitor bias floating inverting amplifier according to an embodiment of the present application.

Fig. 4 is a schematic circuit diagram of a low-voltage robust enhanced capacitor bias floating inverting amplifier in an auto-zero phase according to an embodiment of the present application.

Fig. 5 is a schematic circuit diagram of a low-voltage robust enhanced capacitor bias floating inverting amplifier in an amplifying phase according to an embodiment of the present application.

Fig. 6 is a schematic circuit diagram of a cascode structure of a low-voltage robust enhanced capacitor bias floating inverting amplifier according to an embodiment of the present application.

Fig. 7 is a schematic circuit diagram of a cascode structure of a low-voltage robust enhanced capacitor-biased floating-inverting amplifier according to an embodiment of the present application.

Fig. 8 is a graph showing a gain versus output swing of a further circuit of a low voltage robust enhancement mode capacitor bias floating inverting amplifier according to an embodiment of the present application.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings.

The inventor of the invention discovers that the traditional FIA can not work normally because the grid source voltage Vgs of the amplifying tube is smaller than the threshold voltage Vth under the power supply of sub-1V under the condition that the PMOS bias and the NMOS bias are under the same bias voltage, and the amplifying tube is cut off. LVFIA has multiple complex control clocks and the system cost is high. And NMOS and PMOS currents are defined independently, there is a reliability problem. Based on the above, the invention aims to realize the FIA compatible with sub-1V power supply and strong in robustness under the condition of low cost, and can be applied to low-power consumption application scenes such as energy collection, battery power supply and the like.

The embodiment of the invention discloses a low-voltage robustness enhanced Capacitor Bias Floating Inverting Amplifier (CBFIA), which comprises a capacitor bias circuit, a capacitor coupling inverting amplifying circuit and a storage capacitor circuit, wherein the capacitor bias circuit is used for providing bias voltage for the capacitor coupling inverting amplifying circuit; the energy storage capacitor circuit is used for supplying power to the capacitive coupling inverting amplification circuit; the capacitive coupling inverting amplifying circuit is used for amplifying the differential input signal to obtain a differential output signal.

The capacitive coupling inverting amplifier circuit comprises a first input transistor circuit and a second input transistor circuit, wherein one input end of the first input transistor circuit is connected with one input end of the second input transistor circuit, and the connection part receives a differential input signal Vx and passes through a first switch S ₁ Grounding; the other input end of the first input transistor circuit is connected with the other input end of the second input transistor circuit, and the connection part receives the differential input signal Vy and passes through the fourth switch S ₄ Grounding; the two output ends of the first input transistor circuit are respectively connected with the two output ends of the second input transistor circuit, and the connection part forms a differential output node V _ON And V _OP 。

The first input transistor circuit comprises a first pair of input transistors M ₃ 、M ₄ And with the first pair of input transistors M ₃ 、M ₄ Self-zeroing capacitor C connected with grid electrodes of the capacitor C _c3 、C _c4 The first pair of input transistors M ₃ Source and M of (2) ₄ The source stage of the energy storage capacitor circuit is connected with one end of the energy storage capacitor circuit; one end of the energy storage capacitor circuit is also connected with a tenth switch S ₁₀ Grounding; the first pair of input transistors M ₃ Gate and M of (2) ₄ The gates of (2) are respectively connected with a fifth switch S ₅ And a sixth switch S ₆ And the connecting part is connected with the capacitor bias circuit. First pair of input transistors M ₃ 、M ₄ Either NMOS or PMOS transistors.

The capacitance bias circuit includes a first capacitance bias circuit for a first pair of input transistors M ₃ And M ₄ Providing a bias voltage comprising a first capacitor C ₁ Transistor M ₅ Seventh switch S ₇ And an eighth switch S ₈ The transistor M ₅ The source electrode of (2) is grounded, the grid electrode is connected with the drain electrode, and the connection part is connected with a seventh switch S ₇ Is connected with one end of the connecting rod; first capacitor C ₁ One end of which is grounded and the other end of which is connected with a seventh switch S ₇ Is connected with the other end of the fifth switch S ₅ And a sixth switch S ₆ Is connected with the connecting part of the two parts; first capacitor C ₁ The other end of (2) also passes through an eighth switch S ₈ And connecting a power supply voltage. Transistor M ₅ Either NMOS or PMOS transistors, needed and first pair of input transistors M ₃ 、M ₄ The type of (c) remains consistent.

The second input transistor circuit comprises a second pair of input transistors M ₁ 、M ₂ And with the second pair of input transistors M ₁ 、M ₂ Self-zeroing capacitor C connected with grid electrodes of the capacitor C _c1 、C _c2 The second pair of input transistors M ₁ Source and M of (2) ₂ The connection part is connected with the other end of the energy storage capacitor circuit; the other end of the energy storage capacitor circuit is also provided with a ninth switch S ₉ Connecting a power supply voltage; the second pair of input transistors M ₁ Through a second switch S ₂ And differential output node V _ON Connection and M ₂ Through a third switch S ₃ And differential output node V _OP And (5) connection. A second pair of input transistors M ₁ 、M ₂ The transistor can be a PMOS transistor or an NMOS transistor; when the first pair of input transistors M ₃ 、M ₄ In the case of NMOS transistors, the second pair of input transistors M ₁ 、M ₂ Is a PMOS transistor; when the first pair of input transistors M ₃ 、M ₄ In the case of a PMOS transistor, the second pair of input transistors M ₁ 、M ₂ Is an NMOS transistor.

FIG. 2 is a circuit topology of CBFIA, in which the first pair of input transistors M ₃ 、M ₄ Is an NMOS transistor, a second pair of input transistors M ₁ 、M ₂ Is a PMOS transistor, transistor M ₅ Is an NMOS transistor.

FIG. 3 is a further circuit topology of CBFIA, in which the first pair of input transistors M ₃ 、M ₄ Is a PMOS transistor, a second pair of input transistors M ₁ 、M ₂ Is an NMOS transistor, transistor M ₅ Is a PMOS transistor.

In a specific implementation process, the energy storage capacitor circuit comprises an energy storage capacitor C _res 。

As shown in fig. 2, in some embodiments, a first pair of input transistors M ₃ Drain electrode of M ₄ The drains of the second pair of input transistors M ₁ Drain electrode of M ₂ Drain electrode connection of (a), the connection part forms a differential output node V _ON And V _OP 。

The operation of CBFIA is divided into two phases: auto-zero phase phi ₁ And an amplifying phase Φ. The first switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth switch S ₉ Tenth switch S ₁₀ Eleventh switch S ₁₁ And a thirteenth switch S ₁₃ From auto-zero phase phi ₁ Control, eighth switch S ₈ Twelfth switch S ₁₂ And a fourteenth switch S ₁₄ From the amplified phase phi ₂ Control of the auto-zero phase phi ₁ And amplifying the phase phi ₂ Are mutually in opposite phase; the CBFIA works in each phase as follows:

1) Auto-zero phase, as shown in FIG. 4, a first switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth switch S ₉ And a tenth switch S ₁₀ Closing, eighth switch S ₈ Disconnecting; energy storage capacitor C _res Charging; first capacitor C precharged in the previous phase ₁ And auto-zero capacitor C _c3 、C _c4 A transistor M5 for charge sharing and discharging through diode connection (capacitance bias mode);

the bias voltage of the gate of the first pair of input transistors is recorded as V ₂ The bias voltage of the grid electrode of the second pair of input transistors is V ₁ By controlling the auto-zero phase phi ₁ Can change the bias voltage V ₂ To thereby determine the first pair of input transistors M ₃ And M ₄ At the same time as the second pair of input crystalsTube M ₁ And M ₂ Automatically zeroing the bias voltage V ₁ The offset voltage and the flicker noise are stored in the auto-zero capacitor C _c1 And C _c2 And (3) upper part.

2) Amplifying phase, as shown in FIG. 5, a first switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth switch S ₉ And a tenth switch S ₁₀ Open, eighth switch S ₈ Closing, first capacitance C ₁ Charging; from an energy-storage capacitor C _res Power supply for capacitive coupling inverting amplifying circuit, V ₁ And V ₂ For auto-zeroing phase phi ₁ The differential input signal passes through the auto-zero capacitor C at the determined bias voltage value _c3 、C _c4 、C _c1 And C _c2 Coupled to a first pair of input transistors M ₃ 、M ₄ And a second pair of input transistors M ₁ 、M ₂ A first pair of input transistors M ₃ 、M ₄ And a second pair of input transistors M ₁ 、M ₂ And amplifying the differential input signal to obtain a differential output signal.

The above is the workflow of CBFIA in one complete cycle. In the working process, the lowest power supply of the amplifier is more than Vgs+vdsat, and the sub-1V power supply can be easily realized. Wherein Vgs represents the gate-source voltage difference of the MOS tube, and vdsat represents the saturation voltage of the MOS tube.

The scheme only needs two opposite-phase control clocks, so that the control logic is simple and the cost is low. And M in the first pair of input transistors ₃ And M in the second pair of input transistors ₁ The current is always the same, M ₄ And M ₂ The current is always the same, and there is no mismatch problem, so the robustness is high.

In other embodiments, the CBFIA may be extended to a cascode configuration to increase dc gain, with a circuit topology as shown in fig. 6. The bias of the cascode transistors is also generated by a capacitive bias mode, so that the robustness of CBFIA along with the change of the supply voltage is maintained while the gain is improved.Specifically, the first input transistor circuit further includes a third pair of input transistors M ₈ 、M ₉ The second input transistor circuit further comprises a fourth pair of input transistors M ₆ 、M ₇ The first pair of input transistors M ₃ Drain electrode of M ₄ The drains of the (a) and (b) are respectively connected with the third pair of input transistors M ₈ Source level, M of (2) ₉ Source-side connection of the third pair of input transistors M ₈ Drain electrode of M ₉ The drains of the (a) and the fourth pair of input transistors M ₆ Drain electrode of M ₇ Drain electrode connection of (a), the connection part forms a differential output node V _ON And V _OP The method comprises the steps of carrying out a first treatment on the surface of the Fourth pair of input transistors M ₆ Source level, M of (2) ₇ Respectively with the second pair of input transistors M ₁ Drain electrode of M ₂ Is connected with the drain electrode of the transistor; third pair of input transistors M ₈ Gate, M of (2) ₉ The grid electrodes of (a) are connected with the bias voltage V ₄ Fourth pair of input transistors M ₆ Gate, M of (2) ₇ The grid electrodes of (a) are connected with the bias voltage V ₃ . Third pair of input transistors M ₈ 、M ₉ Type of (c) and first pair of input transistors M ₃ 、M ₄ Concordance, fourth pair of input transistors M ₆ 、M ₇ Type of (v) and second pair of input transistors M ₁ 、M ₂ And consistent.

The capacitance bias circuit also comprises a second capacitance bias circuit and a third capacitance bias circuit, wherein the second capacitance bias circuit is used for providing bias voltage V ₃ A third capacitor bias circuit for providing bias voltage V ₄ ；

The second capacitance bias circuit comprises a second capacitance C ₂ Transistor M ₁₀ Eleventh switch S ₁₁ And a twelfth switch S ₁₂ The transistor M ₁₀ The source electrode of (1) is grounded, the grid electrode is connected with the drain electrode, and a bias voltage V is formed at the connection part ₃ And is connected with an eleventh switch S ₁₁ Is connected with one end of the connecting rod; second capacitor C ₂ One end of which is grounded and the other end of which is connected with an eleventh switch S ₁₁ Is connected with the other end of the connecting rod; second capacitor C ₂ The other end of (2) also passes through a twelfth switch S ₁₂ Connecting a grounding voltage; transistor M ₁₀ Either NMOS or PMOS transistors, requiring and fourth pair of input transistors M ₆ 、M ₇ The type of (c) remains consistent.

The third capacitor bias circuit comprises a third capacitor C ₃ Transistor M ₁₁ Thirteenth switch S ₁₃ And a fourteenth switch S ₁₄ The transistor M ₁₁ The source electrode of (1) is grounded, the grid electrode is connected with the drain electrode, and a bias voltage V is formed at the connection part ₄ And is connected with thirteenth switch S ₁₃ Is connected with one end of the connecting rod; third capacitor C ₃ One end of which is grounded and the other end of which is connected with a thirteenth switch S ₁₃ Is connected with the other end of the connecting rod; third capacitor C ₃ The other end of (2) also passes through a fourteenth switch S ₁₄ Connecting a power supply voltage; transistor M ₁₁ Either NMOS or PMOS transistors, requiring and third pair of input transistors M ₈ 、M ₉ The type of (c) remains consistent.

FIG. 6 is a circuit topology of a cascode CBFIA in which a first pair of input transistors M ₃ 、M ₄ And a third pair of input transistors M ₈ 、M ₉ Is an NMOS transistor, a second pair of input transistors M ₁ 、M ₂ And a fourth pair of input transistors M ₆ 、M ₇ Is a PMOS transistor, transistor M ₅ Is an NMOS transistor, transistor M ₁₀ Is a PMOS transistor, transistor M ₁₁ Is an NMOS transistor.

FIG. 7 is a further circuit topology of a cascode CBFIA in which a first pair of input transistors M ₃ 、M ₄ And a third pair of input transistors M ₈ 、M ₉ Is a PMOS transistor, a second pair of input transistors M ₁ 、M ₂ And a fourth pair of input transistors M ₆ 、M ₇ Is an NMOS transistor, transistor M ₅ Is a PMOS transistor, transistor M ₁₀ Is an NMOS transistor, transistor M ₁₁ Is a PMOS transistor.

When it is required to provide bias voltage V ₃ And V ₄ At the time of auto-zero phase phi ₁ Eleventh switch S ₁₁ And a thirteenth switch S ₁₃ Closing the twelfth switch S ₁₂ And a fourteenth switch S ₁₄ And (5) disconnecting. Second capacitor C pre-charged by the previous phase ₂ And a third capacitor C ₃ M10 and M11, which are connected by diodes, respectively, are discharged, and reasonable V3 and V4 are established by controlling the discharge time period (Φ1 high-level time period). In the amplifying phase phi ₂ Eleventh switch S ₁₁ And a thirteenth switch S ₁₃ Opening the twelfth switch S ₁₂ And a fourteenth switch S ₁₄ Closing a second capacitor C ₂ And a third capacitor C ₃ And (5) charging.

By means of the characteristic of CBFIA, the cascode CBFIA realizes direct current gain of >60dB under 0.8V power supply, and the output swing is >200mV, and the simulation result is shown in FIG. 8.

The invention provides a low-voltage robust enhanced capacitor bias floating inverting amplifier, and the method and the way for realizing the technical scheme are numerous, the above description is only a preferred embodiment of the invention, and it should be noted that, for a person skilled in the art, several improvements and modifications can be made, and the improvements and modifications should be regarded as the protection scope of the invention. The components not explicitly described in this embodiment can be implemented by using the prior art.

Claims (10)

1. The low-voltage robustness-enhanced capacitor bias floating inverting amplifier is characterized by comprising a capacitor bias circuit, a capacitor coupling inverting amplifying circuit and a storage capacitor circuit, wherein the capacitor bias circuit is used for providing bias voltage for the capacitor coupling inverting amplifying circuit; the energy storage capacitor circuit is used for supplying power to the capacitive coupling inverting amplification circuit; the capacitive coupling inverting amplifying circuit is used for amplifying the differential input signal to obtain a differential output signal.

2. The low voltage robust enhancement mode capacitor biased floating inverter amplifier of claim 1, wherein said capacitively coupled inverting amplifier circuit comprises a first input transistor circuit and a second input transistor circuit, one of said first input transistor circuitAn input terminal connected to an input terminal of the second input transistor circuit for receiving the differential input signal Vx and passing through the first switch S ₁ Grounding; the other input end of the first input transistor circuit is connected with the other input end of the second input transistor circuit, and the connection part receives the differential input signal Vy and passes through the fourth switch S ₄ Grounding; the two output ends of the first input transistor circuit are respectively connected with the two output ends of the second input transistor circuit, and the connection part forms a differential output node V _ON And V _OP 。

3. The low voltage robust enhancement mode capacitor bias floating inverter amplifier of claim 2, wherein said first input transistor circuit comprises a first pair of input transistors and auto-zero capacitors respectively connected to gates of said first pair of input transistors, source stages of said first pair of input transistors being connected to one end of a tank capacitor circuit; one end of the energy storage capacitor circuit is also connected with a tenth switch S ₁₀ Grounding; the gates of the first pair of input transistors are respectively connected with a fifth switch S ₅ And a sixth switch S ₆ And the connecting part is connected with the capacitor bias circuit.

4. A low voltage robust enhancement mode capacitor biased floating inverter amplifier according to claim 3, wherein said capacitor bias circuit comprises a first capacitor bias circuit for providing a bias voltage to a first pair of input transistors, comprising a first capacitor C ₁ Transistor M ₅ Seventh switch S ₇ And an eighth switch S ₈ The transistor M ₅ The source electrode of (2) is grounded, the grid electrode is connected with the drain electrode, and the connection part is connected with a seventh switch S ₇ Is connected with one end of the connecting rod; first capacitor C ₁ One end of which is grounded and the other end of which is connected with a seventh switch S ₇ Is connected with the other end of the fifth switch S ₅ And a sixth switch S ₆ Is connected with the connecting part of the two parts; first capacitor C ₁ The other end of (2) also passes through an eighth switch S ₈ And connecting a power supply voltage.

5. The low voltage robust enhancement mode capacitor biased floating inverter amplifier of claim 4, wherein said second input transistor circuit comprises a second pair of input transistors and auto-zero capacitors respectively connected to gates of said second pair of input transistors, source stages of said second pair of input transistors being connected to one another and to the other end of said tank capacitor circuit; the other end of the energy storage capacitor circuit is also provided with a ninth switch S ₉ Connecting a power supply voltage; the gates of the second pair of input transistors are respectively connected with a second switch S ₂ And differential output node V _ON Connected to and through a third switch S ₃ And differential output node V _OP And (5) connection.

6. The low voltage robust enhancement mode capacitor biased floating inverter amplifier of claim 5, wherein the drains of the first pair of input transistors are respectively connected to the drains of the second pair of input transistors, the connection forming a differential output node V _ON And V _OP 。

7. The low voltage robust enhancement mode capacitor biased floating inverter amplifier of claim 5, wherein the first input transistor circuit further comprises a third pair of input transistors, the second input transistor circuit further comprises a fourth pair of input transistors, the drains of the first pair of input transistors are respectively connected to the source of the third pair of input transistors, the drains of the third pair of input transistors are respectively connected to the drains of the fourth pair of input transistors, and the junction forms a differential output node V _ON And V _OP The method comprises the steps of carrying out a first treatment on the surface of the The source of the fourth pair of input transistors is connected with the drain of the second pair of input transistors respectively; the gates of the third pair of input transistors are connected with the bias voltage V ₄ The grid electrodes of the fourth pair of input transistors are connected with the bias voltage V ₃ 。

8. A low voltage robust enhanced capacitive biased floating inversion according to any of claims 5-7An amplifier, characterized in that the first switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth switch S ₉ And a tenth switch S ₁₀ From auto-zero phase phi ₁ Control, eighth switch S ₈ From the amplified phase phi ₂ Control of the auto-zero phase phi ₁ And amplifying the phase phi ₂ Are mutually in opposite phase;

in the auto-zero phase phi ₁ First switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth switch S ₉ And a tenth switch S ₁₀ Closing, eighth switch S ₈ Disconnecting the energy storage capacitor circuit and charging; first capacitor C precharged in the previous phase ₁ And an auto-zero capacitor connected to the gates of the first pair of input transistors respectively for charge sharing and passing through transistor M ₅ Discharging;

the bias voltage of the gate of the first pair of input transistors is recorded as V ₂ The bias voltage of the grid electrode of the second pair of input transistors is V ₁ By controlling the auto-zero phase phi ₁ Can change the bias voltage V ₂ To determine the bias current of the first pair of input transistors while the second pair of input transistors is auto-zeroed to bias voltage V ₁ And storing the offset voltage and the flicker noise together on an auto-zero capacitor respectively connected with the gates of the second pair of input transistors.

9. The low voltage robust enhancement mode capacitor biased floating inverter amplifier of claim 8, wherein during the amplifying phase Φ ₂ First switch S ₁ Second switch S ₂ Third switch S ₃ Fourth switch S ₄ Fifth switch S ₅ Sixth switch S ₆ Seventh switch S ₇ Ninth openingSwitch S ₉ And a tenth switch S ₁₀ Open, eighth switch S ₈ Closing, first capacitance C ₁ Charging; the energy storage capacitor circuit supplies power to the capacitive coupling inverting amplifying circuit, V ₁ And V ₂ For auto-zeroing phase phi ₁ The differential input signal is coupled to the first and second pairs of input transistors through an auto-zero capacitance, and the first and second pairs of input transistors amplify the signals to obtain a differential output signal.

10. The low voltage robust enhancement mode capacitor bias floating inverter amplifier of claim 9, wherein said capacitor bias circuit further comprises a second capacitor bias circuit for providing a bias voltage V and a third capacitor bias circuit ₃ A third capacitor bias circuit for providing bias voltage V ₄ ；

The second capacitance bias circuit comprises a second capacitance C ₂ Transistor M ₁₀ Eleventh switch S ₁₁ And a twelfth switch S ₁₂ The transistor M ₁₀ The source electrode of (1) is grounded, the grid electrode is connected with the drain electrode, and a bias voltage V is formed at the connection part ₃ And is connected with an eleventh switch S ₁₁ Is connected with one end of the connecting rod; second capacitor C ₂ One end of which is grounded and the other end of which is connected with an eleventh switch S ₁₁ Is connected with the other end of the connecting rod; second capacitor C ₂ The other end of (2) also passes through a twelfth switch S ₁₂ Connecting a grounding voltage;

the third capacitor bias circuit comprises a third capacitor C ₃ Transistor M ₁₁ Thirteenth switch S ₁₃ And a fourteenth switch S ₁₄ The transistor M ₁₁ The source electrode of (1) is grounded, the grid electrode is connected with the drain electrode, and a bias voltage V is formed at the connection part ₄ And is connected with thirteenth switch S ₁₃ Is connected with one end of the connecting rod; third capacitor C ₃ One end of which is grounded and the other end of which is connected with a thirteenth switch S ₁₃ Is connected with the other end of the connecting rod; third capacitor C ₃ The other end of (2) also passes through a fourteenth switch S ₁₄ Connecting a power supply voltage;

eleventh switch S ₁₁ And a thirteenth switch S ₁₃ From auto-zero phase phi ₁ Control, twelfth switch S ₁₂ And a fourteenth switch S ₁₄ From the amplified phase phi ₂ And (5) controlling.