CN117577617A

CN117577617A - Power module and vehicle

Info

Publication number: CN117577617A
Application number: CN202210929121.9A
Authority: CN
Inventors: 孙鑫宇; 靳满智; 张�林; 袁宝成
Original assignee: Beijing CHJ Automobile Technology Co Ltd
Current assignee: Beijing CHJ Automobile Technology Co Ltd
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2024-02-20

Abstract

The application provides a power module, including base plate and a plurality of chip, wherein: the substrate comprises an even number of areas, the even number of areas are symmetrically arranged along the central axis of the substrate in pairs, at least two chips electrically connected with the areas are arranged in each area, the number of the chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also symmetrically electrically connected in pairs along the central axis of the substrate. According to the power module, the chips are symmetrically arranged on the substrate, so that the current sharing characteristic of the parallel chip group can be improved, and the working efficiency and the reliability of the power module are guaranteed.

Description

Power module and vehicle

Technical Field

The present disclosure relates to the field of electronic circuits, and more particularly to a power module and a vehicle.

Background

The SiC (silicon carbide) material plays an important role in improving the power density and efficiency of semiconductor devices and power electronic systems due to the advantages of high forbidden bandwidth, high critical electric field, high thermal conductivity and the like, the high switching frequency of a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is one of important directions of SiC application, but along with the increase of the switching frequency, the current change rate di/dt is increased, and under the parasitic inductance effect of a power module, great voltage overshoot is generated in the rapid on-off process of the MOSFET, so that the voltage stress of a chip is increased, and the voltage withstand class requirement of the chip is improved; meanwhile, the voltage overshoot can also cause serious oscillation of the switching waveform, and electromagnetic interference is increased. In addition, the active area of the SiC MOSFET chip is limited, and a single chip is difficult to bear large current, so that the application of the SiC MOSFET in high-power electronic equipment is severely limited. In order to improve the working current level of SiC MOSFETs, chips are usually connected in parallel to form groups, but the problem of unbalanced current of each branch inevitably occurs in an asymmetric parallel circuit, and the current imbalance brings about differences in losses, current and voltage stresses and switching speeds of the parallel MOSFETs, and the differences cause damage to individual devices due to long-time loss and overstress states, so that other parallel devices and the whole system fail.

Disclosure of Invention

In view of the foregoing, an object of the present application is to provide a power module and a vehicle.

Based on the above object, the present application provides a power module, including a substrate and a plurality of chips, wherein: the substrate comprises an even number of areas, the even number of areas are symmetrically arranged along the central axis of the substrate in pairs, at least two chips electrically connected with the areas are arranged in each area, the number of the chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also symmetrically electrically connected in pairs along the central axis of the substrate.

Alternatively, when the number of chips in the same area is three or more, the pitches of two adjacent chips in the area are the same.

Optionally, the power module further includes a current sharing connector, and the chips in the two symmetrically arranged areas are electrically connected through the current sharing connector.

Optionally, the substrate further includes a middle region, the middle region is located between the two symmetrically arranged regions, and the current sharing connector is further electrically connected with the middle region.

Optionally, the current equalizing connector includes a main body part and a bonding part, the bonding part is located at two ends of the main body part and is fixedly connected with the main body part, and two ends of the main body part respectively point to the two symmetrically arranged areas; the main body part is used for being electrically connected with the middle area, and the bonding part is used for being electrically connected with a chip positioned in the same area.

Optionally, the bonding portion includes two at least connecting portions and many bonding lines, two at least connecting portions with two at least chips are relative to each other to be set up one by one, the one end of connecting portion with the chip electricity that sets up relatively is connected, the other end with main part fixed connection, two adjacent connecting portions by many parallel settings the bonding line is connected.

Optionally, the main body portion and the connecting portion are both sheet structures that can be attached to the intermediate region or the chip.

Optionally, the current sharing connecting piece is a copper piece.

Optionally, the power module further includes a plastic package housing disposed outside the power module, where the plastic package housing includes at least one hole, and the hole is configured to expose a part of the even number of areas and/or a part of the middle area, so that the part of the even number of areas and/or the part of the middle area is electrically connected with an external device.

Based on the same inventive concept, the application also provides a vehicle comprising any one of the power modules.

As can be seen from the above, the power module provided in the present application includes a substrate and a plurality of chips, wherein: the substrate comprises an even number of areas, the even number of areas are symmetrically arranged along the central axis of the substrate in pairs, at least two chips electrically connected with the areas are arranged in each area, the number of the chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also symmetrically electrically connected in pairs along the central axis of the substrate. According to the power module, the chips are symmetrically arranged on the substrate, so that the current sharing characteristic of the parallel chip group can be improved, and the working efficiency and the reliability of the power module are guaranteed.

Drawings

In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic diagram a of a power module according to an embodiment of the present application;

fig. 2 is a schematic diagram B of a power module according to an embodiment of the present application;

fig. 3 is a schematic diagram of a flow equalization connector according to an embodiment of the present application;

fig. 4 is a schematic diagram of a power module package according to an embodiment of the present application.

The list of components represented by the reference numerals in the drawings is as follows:

1. a substrate; 2. a plastic package shell; 10. a first region; 20. a second region; 30. a third region; 40. a fourth region; 50. a fifth region; 60. a sixth region; 70. a seventh region; 80. a main body portion; 90. a bonding portion; 100. a first hole; 110. a second hole; 120. a third hole; 130. a resistive region; 140. a connection part; C1-C8, chip; P1-P8, pins; w 1-w 4, bonding wire; clip1, first flow equalization connector; clip2, second flow equalizing connector.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.

Fig. 1 to 4 are schematic views of power modules in the same embodiment, and reference is made to other drawings for non-labeled portions in one drawing.

In view of this, an embodiment of the present application provides a power module, including a substrate and a plurality of chips, wherein the substrate includes an even number of regions, and this even number of regions is all along the two-by-two symmetry settings of axis of substrate, is equipped with in every region with this region two at least chips of electrical connection, and the chip quantity is the same in two regions of symmetry setting, and the chip in two regions of symmetry setting is also all along the two-by-two symmetry electrical connection setting of axis of substrate.

In a specific embodiment, taking the power module shown in fig. 1 as an example, the substrate 1 includes a first area 10, a second area 20, a third area 30, and a fourth area 40, that is, the even number of areas, the first area 10 is provided with chips C1 and C2, the second area 20 is provided with chips C3 and C4, the third area 30 is provided with chips C5 and C6, and the fourth area 40 is provided with chips C7 and C8.

At least two chips electrically connected to the first region 10, the second region 20, the third region 30 and the fourth region 40 are respectively provided on the first region 10, the second region 20 and the third region 30, the number of chips in the first region 10 and the second region 20 is the same, the number of chips in the third region 30 and the fourth region 40 is the same, and the pitches of the chips in the same region are the same.

The chips C1, C2 in the first area 10 are symmetrically arranged with the chips C3, C4 in the second area 20, and the chips C5, C6 in the third area 30 are symmetrically arranged with the chips C7, C8 in the fourth area 40.

According to the power module, the chips are symmetrically arranged on the substrate, so that the current loops of the parallel chips are identical as much as possible, the current sharing characteristic of the parallel chip group is improved, and the working efficiency and the reliability of the power module are guaranteed. The same number of chips in the mutually symmetrical areas can further ensure that the power module has better current sharing characteristic.

In the implementation, if more chips need to be carried, the power module may further include more areas with the same functions and connection manners as the first area to the fourth area, and are all within the protection scope of the application.

In a specific embodiment, in order to solve the problem set forth in the background technology more specifically, the chip is a SiC MOSFET, but in specific implementation, other chips with the problem set forth in the background technology may also be adopted to solve the corresponding problem by using the power module provided in the embodiment, and all the chips are within the protection scope of the present application.

In a specific embodiment, the chip is electrically connected to the substrate by means of silver sintering. The silver sintering technology is also called a low-temperature connection technology, and compared with the traditional connection mode, the silver sintering connection layer has the advantages that the silver is used as a component, and the silver sintering connection layer has excellent electric conductivity and heat conductivity; since the melting point of silver is as high as 961 ℃, typical fatigue effects occurring in solder connection layers with melting points less than 300 ℃ will not occur, with extremely high reliability; the sintered material does not contain lead, and belongs to an environment-friendly material.

In some embodiments, when the number of chips in the same area is three or more, the distances between two adjacent chips in the area are the same, so that the power module can be further ensured to have better current sharing characteristic.

In some embodiments, the power module further includes a current sharing connector through which the chips in the two symmetrically disposed regions are electrically connected. The current sharing connecting piece is made of conductive materials, and when the chips in the two areas are electrically connected with the outside through the current sharing connecting piece, the current sharing connecting piece can share the current passing through the chips in the two areas, so that the currents passing through the chips in the different areas are the same.

Taking the power module shown in fig. 1 and fig. 2 as an example, the power module includes a first current equalizing connector clip1 and a second current equalizing connector clip2, the chips C1, C2, C3 and C4 in the first area 10 and the second area 20 are electrically connected through the first current equalizing connector clip1, and the chips C5, C6, C7 and C8 in the third area 30 and the fourth area 40 are electrically connected through the second current equalizing connector clip 2.

At present, the parallel connection of chips adopts an aluminum wire bonding or copper wire bonding as an interconnection mode, but because the sectional area of bonding wires is smaller, a plurality of bonding wires are needed when large current passes through, the complexity of the process is improved, and more space is occupied. Meanwhile, the bonding wire is easy to age and even fall off at the bonding point under high-temperature application, so that the power module is invalid, and the reliability of the power module is reduced. Finally, in the application of parallel connection of a plurality of identical chips, the current sharing and the temperature sharing of each chip are difficult to realize by the related bonding wire interconnection mode, and the chip is not current-sharing, so that a single chip is damaged due to excessive stress and loss for a long time, and further, other parallel devices and the whole system are damaged. The parallel connection among a plurality of chips is realized through the current sharing connecting piece, so that the power module can be further ensured to have better current sharing characteristic and higher reliability; in addition, parasitic inductance in the power loop can be reduced by reducing the use of bonding wires, and the power module can work at a higher voltage level and a higher frequency; meanwhile, compared with a bonding wire, the current sharing connecting piece has a larger heat dissipation area and can achieve a better heat dissipation effect. The arrangement that the number of the chips in the mutually symmetrical areas is the same and the intervals of the chips in the same area are the same can be matched with the current sharing connecting piece, so that the power module is further guaranteed to have good current sharing characteristics and high reliability.

In specific implementation, the size of the current equalizing connector may be designed according to the actual required size of the chip and the power module, and the width of the current equalizing connector is preferably the same as the total width of the chip in the same area to be connected, so as to achieve the maximum heat dissipation area, and taking fig. 2 as an example, the width of the first current equalizing connector clip1 is preferably the distance from the leftmost end of C1 to the rightmost end of C2. In specific implementation, the number of chips in the same area connected by one current sharing connecting piece can be two or more, the connection mode is similar to that given by the attached drawing of the embodiment, the person skilled in the art can implement without labor on the basis of the disclosure of the application, and the number of chips in the same area connected by one current sharing connecting piece can be two or more, which are all within the protection scope of the application.

In some embodiments, the substrate further comprises a middle region, the middle region is located between the two symmetrically arranged regions, and the current sharing connector is further electrically connected with the middle region. Taking the power module shown in fig. 1 and 2 as an example, a fifth region 50 and a sixth region 60 are the middle region, the fifth region 50 is located between the first region 10 and the second region 20, and the sixth region 60 is located between the third region 30 and the fourth region 40. The first current equalizing connector clip1 is further electrically connected to the fifth region 50, and the second connector clip2 is further electrically connected to the sixth region 60. In a specific embodiment, the first region 10, the second region 20 and the sixth region 60 are electrically connected, and the first region 10, the second region 20 and the sixth region 60 are integrally interconnected copper-clad regions. Compared with the traditional technology adopting aluminum wire bonding or copper wire bonding as an interconnection mode, the current sharing connecting piece can realize the electric connection with the middle area while interconnecting the chips by a simpler process.

In some embodiments, the substrate is a copper-clad ceramic substrate, and the first region to the sixth region are copper-clad regions. The copper-clad ceramic substrate has the characteristics of excellent thermal cycling performance, stable shape, good rigidity, high heat conductivity, high reliability, no pollution and no public nuisance, and the use temperature can be from-55 ℃ to 850 ℃, so that the stability of the work of the power module can be further ensured by using the copper-clad ceramic substrate. The first region to the sixth region are copper-clad regions on the substrate.

In a specific embodiment, the current sharing connectors are electrically connected with the chip and the substrate through silver sintering.

In some embodiments, as shown in fig. 2 and fig. 3, the flow equalization connector includes a main body portion 80 and a bonding portion 90, where the bonding portion 90 is located at two ends of the main body portion 80 and is fixedly connected to the main body portion 80, and the two ends of the main body portion 80 are respectively directed to the two symmetrically arranged areas; the main body 80 is used for electrically connecting with the middle region, and the bonding portion 90 is used for electrically connecting with chips located in the same region. The main body part is used for improving the current sharing characteristic among chips in different areas, the bonding part is used for improving the current sharing characteristic among chips in the same area, and the current sharing connecting piece is utilized to further ensure the current sharing characteristic among chips connected in parallel, so that the reliability of the power module is further improved.

In some embodiments, as shown in fig. 2 and 3, the bonding portion 90 includes at least two connection portions 140 and a plurality of bonding wires w1 to w4, the at least two connection portions 140 are disposed opposite to the at least two chips one by one, one end of each connection portion 140 is electrically connected to the opposite chip, the other end is fixedly connected to the main body portion 80, and two adjacent connection portions 140 are connected by the plurality of bonding wires w1 to w4 disposed in parallel. The bonding portion 90 includes a plurality of bonding wires w1 to w4, which can improve the overall current-carrying capacity of the current-sharing connector, and further improve the current-sharing characteristics between the chips.

In some embodiments, the main body 80 and the connecting portion 140 are each sheet-like structures that can be attached to the intermediate region or the chip. The main body part and the connecting part are of sheet-shaped structures, so that on one hand, the chip loop has larger current-carrying sectional area so as to improve the current-carrying capacity of the chip loop; on the other hand, the flow equalization connecting piece has larger heat dissipation area, and the flow equalization connecting piece and the substrate have larger contact area, so that reliable electrical connection is convenient to realize.

In some embodiments, the flow equalization connection is a copper piece. Copper has good physical and chemical characteristics such as electric conductivity, thermal conductivity, corrosion resistance, ductility and the like, and the adoption of the copper current sharing connecting piece can further ensure that the power module has good current sharing characteristics.

In some embodiments, the power module further includes a plastic package housing disposed outside the power module, where the plastic package housing includes at least one hole, and the hole is configured to expose a partial area of the even number of areas and/or a partial area of the middle area, so that the partial area of the even number of areas and/or the partial area of the middle area is electrically connected with an external device.

In a specific embodiment, taking the power module shown in fig. 1, fig. 2 and fig. 4 as an example, the plastic package 2 includes a first hole 100, the substrate 1 further includes a seventh area 70 electrically connected to the sixth area 60, and the seventh area 70 may be regarded as an extension of the sixth area 60 from the aspect of function and connection, and is regarded as the middle area together with the sixth area 60; the first hole 100 is used for exposing a part of the seventh area 70, so that the seventh area 70 is electrically connected to an external device, and the sixth area 60 is electrically connected to the external device through the seventh area 70. Although the embodiment of fig. 4 shows two first holes 100, as seen in fig. 1 and 2, the two first holes 100 in fig. 4 can be simplified into one first hole 100 at the same position without affecting the technical effect.

The plastic package 2 further includes a second hole 110, where the second hole 110 is used to expose a part of the fifth area 50, so that the fifth area 50 is electrically connected to an external device. Although the embodiment of fig. 4 shows two second holes 110, as seen in fig. 1 and 2, the two second holes 110 in fig. 4 can be simplified into one second hole 110 at the same position without affecting the technical effect.

The plastic package 2 further includes a third hole 120, where the third hole 120 is configured to expose a part of the third area 30 and a part of the fourth area 40, so that the part of the third area 30 and the part of the fourth area 40 are electrically connected to an external device.

The plastic package shell can enable the copper-clad area to be directly interconnected with the outside, signal wiring on a substrate is reduced, the size of the power module can be reduced, parasitic inductance of the power module can be reduced, and the power module can work at higher voltage level and higher frequency to realize high power density; meanwhile, the design that part of the copper-clad ceramic substrate is exposed can enable the power module to have better heat dissipation performance, and enable the power module to work at a higher temperature.

Although a plurality of holes are shown in the embodiment of fig. 4, the plurality of holes are a preferred arrangement in implementation, and the effect achieved by a single hole is the same as the above effect, so that the arrangement that the plastic package housing includes a hole is also within the scope of protection of the present application. In a specific embodiment, when the plastic package casing includes a plurality of holes, the plurality of holes are symmetrically arranged according to positions of the chip and the copper-clad area on the substrate.

In a specific embodiment, as shown in fig. 1 and 2, the sixth area 60 is configured to be electrically connected to an AC (Alternating Current) terminal, the fifth area 50 is configured to be electrically connected to a DC (Direct current) negative electrode, and the third area 30 and the fourth area 40 are configured to be electrically connected to a DC positive electrode, so as to form a complete half-bridge power module circuit.

In the embodiment, as shown in fig. 1 and 2, taking a chip as a MOSFET, the drains of the chips C1 to C8 are located on the back of the chip and directly soldered to the copper-clad area of the substrate. The drains of the chips C1-C4 are electrically connected with the AC end, the sources of the chips C1-C4 and the DC negative electrode are interconnected through a first connecting piece clip1, and the chips C1-C4 form a lower bridge arm of the half-bridge power module loop; the drains of the chips C5-C8 are electrically connected with the DC positive electrode, the sources of the chips C5-C8 and the AC end are interconnected through a second connecting piece clip2, and the chips C5-C8 form an upper bridge arm of the half-bridge power module loop.

In a specific embodiment, as shown in fig. 2, the power module further includes a plurality of pins P1 to P8, where the pins P1 to P8 are all used for electrically connecting with a peripheral driving control board. The grid electrodes of the chips C1 and C2 are electrically connected with the pin P2 through bonding wires, and the source electrode of the chip C1 is electrically connected with the pin P1 through bonding wires; the grid electrodes of the chips C3 and C4 are electrically connected with the pin P6 through bonding wires, and the source electrode of the chip C3 is electrically connected with the pin P5 through bonding wires; the grid electrodes of the chips C5 and C6 are electrically connected with the pin P4 through bonding wires, and the source electrode of the chip C5 is electrically connected with the pin P3 through bonding wires; the grid electrodes of the chips C7 and C8 are electrically connected with the pin P8 through bonding wires, and the source electrode of the chip C7 is electrically connected with the pin P7 through bonding wires.

In a specific embodiment, the substrate further includes a resistor area 130, taking the power module shown in fig. 1 and fig. 2 as an example, the resistor area 130 is disposed between the sixth area 60 and the seventh area 70, and the width of the resistor area 130 is smaller than the copper-clad width of the copper-clad areas on both sides, so that the resistance of the resistor area 130 is greater than the resistance of the copper-clad areas on both sides, and the resistor area is used for connecting with an external current sensor through a pin to collect current data of the power module.

Based on the same inventive concept, corresponding to the method of any embodiment, the application further provides a vehicle, where the vehicle includes the corresponding power module in any embodiment, and has the beneficial effects of the corresponding method embodiment, which are not described herein.

It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform on which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements and/or the like which are within the spirit and principles of the embodiments are intended to be included within the scope of the present application.

Claims

1. A power module comprising a substrate and a plurality of chips, wherein:

the substrate comprises an even number of areas, the even number of areas are symmetrically arranged along the central axis of the substrate in pairs, at least two chips electrically connected with the areas are arranged in each area, the number of the chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also symmetrically electrically connected in pairs along the central axis of the substrate.

2. The power module of claim 1, wherein when the number of chips in the same region is three or more, the pitch of two adjacent chips in the region is the same.

3. The power module of claim 1 further comprising current sharing connectors through which chips in the two symmetrically disposed regions are electrically connected.

4. The power module of claim 3 wherein the substrate further comprises a middle region, the middle region being located between the symmetrically disposed two regions, the current sharing connection further being electrically connected to the middle region.

5. The power module according to claim 4, wherein the current equalizing connection member comprises a main body portion and a bonding portion, the bonding portion is located at two ends of the main body portion and is fixedly connected with the main body portion, and the two ends of the main body portion are respectively directed to the two symmetrically arranged areas;

the main body part is used for being electrically connected with the middle area, and the bonding part is used for being electrically connected with a chip positioned in the same area.

6. The power module of claim 5, wherein the bonding portion includes at least two connection portions and a plurality of bonding wires, the at least two connection portions are disposed opposite to the at least two chips one by one, one end of each connection portion is electrically connected to the opposite chip, the other end is fixedly connected to the main body portion, and two adjacent connection portions are connected by the plurality of bonding wires disposed in parallel.

7. The power module of claim 6, wherein the main body portion and the connecting portion are each of a sheet-like structure that can be bonded to the intermediate region or the chip.

8. The power module of claim 3 wherein the current sharing connection is a copper piece.

9. The power module of claim 4, further comprising a plastic package housing disposed outside the power module, the plastic package housing including at least one hole for exposing a partial region of the even number of regions and/or a partial region of the intermediate region to electrically connect the partial region of the even number of regions and/or the partial region of the intermediate region with an external device.

10. A vehicle, characterized in that it comprises a power module according to any one of claims 1-9.