CN117577617A - Power module and vehicle - Google Patents

Abstract

The present application provides a power module, including a substrate and a plurality of chips, wherein: the substrate includes an even number of regions, the even number of regions are arranged symmetrically in pairs along the central axis of the substrate, and each region is provided with the At least two of the chips are electrically connected in one area, and the number of chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also electrically connected symmetrically in pairs along the central axis of the substrate. The power module provided by this application can improve the current sharing characteristics of the parallel chipset and ensure the working efficiency and reliability of the power module by symmetrically disposing the chip on the substrate.

Description

A power module and vehicle

Technical field

The present application relates to the field of electronic circuit technology, and in particular, to a power module and a vehicle.

Background technique

SiC (silicon carbide) material plays an important role in improving the power density and efficiency of semiconductor devices and power electronic systems due to its advantages such as high band gap, high critical electric field and high thermal conductivity. SiC MOSFET (Metal-Oxide-Semiconductor) The high switching frequency of Field-Effect Transistor (Metal Oxide Semiconductor Field Effect Transistor) is one of the important directions for SiC applications. However, as the switching frequency increases, the current change rate di/dt increases, which affects the parasitic power of the power module. Under the action of the inductor, a large voltage overshoot will be generated during the rapid switching process of the MOSFET, which increases the voltage stress of the chip and improves the voltage resistance level requirements of the chip. At the same time, the voltage overshoot will also cause serious oscillation in the switching waveform. , increasing electromagnetic interference. In addition, the active area of SiC MOSFET chips is limited, and it is difficult for a single chip to carry large currents, which severely limits the application of SiC MOSFETs in high-power power electronic equipment. In order to increase the operating current level of SiC MOSFETs, chips are usually connected in parallel to form groups. However, in an asymmetric parallel circuit, the problem of current imbalance in each branch will inevitably occur. This current imbalance will bring about differences in the loss of parallel MOSFETs. Differences in current and voltage stress and switching speeds can cause a single device to be damaged due to long-term loss and excessive stress, which can lead to failure of other parallel devices and the entire system.

Contents of the invention

In view of this, the purpose of this application is to propose a power module and a vehicle.

Based on the above purpose, this application provides a power module, including a substrate and a plurality of chips, wherein: the substrate includes an even number of regions, and the even number of regions are all symmetrically arranged in pairs along the central axis of the substrate, and each region There are at least two chips electrically connected to this area. The number of chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also arranged in pairs along the central axis of the substrate. Symmetrical electrical connection setup.

Optionally, when the number of chips in the same area is three or more, the spacing between two adjacent chips in the area is the same.

Optionally, the power module further includes a current sharing connector, and the chips in the two symmetrically arranged areas are electrically connected through the current sharing connector.

Optionally, the substrate further includes a middle region, the middle region is located between the two symmetrically arranged regions, and the current sharing connector is also electrically connected to the middle region.

Optionally, the current equalizing connector includes a main body part and a bonding part, the bonding parts are located at both ends of the main body part and are fixedly connected to the main body part, and the two ends of the main body part point to the There are two areas arranged symmetrically; the main body part is used to electrically connect with the middle area, and the bonding part is used to electrically connect chips located in the same area.

Optionally, the bonding portion includes at least two connecting portions and a plurality of bonding wires, the at least two connecting portions are arranged opposite to the at least two chips, and one end of the connecting portion is arranged opposite to The chip is electrically connected, and the other end is fixedly connected to the main body part. Two adjacent connection parts are connected by a plurality of bonding wires arranged in parallel.

Optionally, both the main body portion and the connecting portion are sheet-like structures that can be bonded to the middle region or the chip.

Optionally, the current-sharing connecting piece is a copper piece.

Optionally, the power module further includes a plastic shell disposed outside the power module. The plastic shell includes at least one hole, and the hole is used to make part of the even-numbered areas and/or the middle area Parts of the regions are exposed, so that parts of the even-numbered regions and/or part of the middle region are electrically connected to external devices.

Based on the same inventive concept, this application also provides a vehicle, which includes any one of the power modules described above.

As can be seen from the above, the power module provided by the present application includes a substrate and a plurality of chips, wherein: the substrate includes an even number of regions, and the even number of regions are all symmetrically arranged in pairs along the central axis of the substrate. Each area is provided with at least two chips electrically connected to the area. The number of chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also along the central axis of the substrate. Pairs of symmetrical electrical connection settings. The power module provided by this application can improve the current sharing characteristics of the parallel chipset and ensure the working efficiency and reliability of the power module by symmetrically disposing the chip on the substrate.

Description of the drawings

In order to more clearly illustrate the technical solutions in this application or related technologies, the drawings needed to be used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings in the following description are only for the purposes of this application. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram A of a power module according to an embodiment of the present application;

Figure 2 is a schematic diagram B of the power module according to the embodiment of the present application;

Figure 3 is a schematic diagram of the current sharing connector according to the embodiment of the present application;

Figure 4 is a schematic diagram of a power module package according to an embodiment of the present application.

The parts represented by the numbers in the drawings are listed as follows:

1. Substrate; 2. Plastic shell; 10. First area; 20. Second area; 30. Third area; 40. Fourth area; 50. Fifth area; 60. Sixth area; 70. Seventh area ; 80. Main part; 90. Bonding part; 100. First hole; 110. Second hole; 120. Third hole; 130. Resistance area; 140. Connection part; C1～C8, chip; P1～P8, Pins; w1~w4, bonding wires; clip1, the first current sharing connector; clip2, the second current sharing connector.

Detailed ways

In order to understand the above objects, features and advantages of the present disclosure more clearly, the solutions of the present disclosure will be further described below. It should be noted that, as long as there is no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

Many specific details are set forth in the following description to fully understand the present disclosure, but the present disclosure can also be implemented in other ways different from those described here; obviously, the embodiments in the description are only part of the embodiments of the present disclosure, and Not all examples.

Figures 1 to 4 are all schematic diagrams of power modules in the same embodiment. For unlabeled parts in a certain drawing, please refer to other drawings.

In view of this, one embodiment of the present application provides a power module, including a substrate and a plurality of chips, wherein the substrate includes an even number of regions, and the even number of regions are all symmetrically arranged in pairs along the central axis of the substrate, Each area is provided with at least two chips electrically connected to the area. The number of chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also along the center of the substrate. The axes are electrically connected symmetrically in pairs.

In a specific embodiment, taking the power module shown in Figure 1 as an example, the substrate 1 includes a first region 10, a second region 20, a third region 30 and a fourth region 40, which are the above-mentioned even number of regions. , the first area 10 is provided with chips C1 and C2, the second area 20 is provided with chips C3 and C4, the third area 30 is provided with chips C5 and C6, and the fourth area 40 is provided with chips C7 and C8.

The first area 10 , the second area 20 , the third area 30 and the fourth area 40 are each provided with at least two chips electrically connected thereto. In the first area 10 The number of chips in the second area 20 is the same, the number of chips in the third area 30 and the fourth area 40 is the same, and the spacing between the chips located in the same area is the same.

The chips C1 and C2 in the first region 10 are symmetrically arranged with the chips C3 and C4 in the second region 20 , and the chips C5 and C6 in the third region 30 are symmetrically arranged with the chips C3 and C4 in the fourth region 40 . C7 and C8 are set symmetrically.

The power module provided by this application can make the current loops of parallel chips as identical as possible by arranging the chips symmetrically on the substrate, thereby improving the current sharing characteristics of the parallel chipset and ensuring the working efficiency and reliability of the power module. The same number of chips in mutually symmetrical areas can further ensure that the power module has better current sharing characteristics.

During specific implementation, if it is necessary to carry more chips, the above-mentioned power module can also include more areas with the same functions and connection methods as the above-mentioned first to fourth areas, and they are all within the protection scope of this application.

In a specific embodiment, in order to more specifically solve the problems raised in the background technology, the chip is a SiC MOSFET. However, during specific implementation, other chips that have the problems mentioned in the background technology can also use this embodiment. The power modules provided solve corresponding problems, and are all within the protection scope of this application.

In a specific embodiment, the chip is electrically connected to the substrate through silver sintering. Silver sintering technology is also called low-temperature connection technology. Compared with traditional connection methods, the silver sintering connection layer is composed of silver and has excellent electrical and thermal conductivity properties; because the melting point of silver is as high as 961°C, there will be no melting point less than 300°C. Typical fatigue effects that occur in the soldered connection layer, with extremely high reliability; the sintered material does not contain lead and is an environmentally friendly material.

In some embodiments, when the number of chips in the same area is three or more, the distance between two adjacent chips in the area is the same, which can further ensure that the power module has better current sharing characteristics.

In some embodiments, the power module further includes a current sharing connector, and the chips in the two symmetrically arranged areas are electrically connected through the current sharing connector. The current-sharing connector is made of conductive material. When the chips in the two areas are electrically connected to the outside world through the current-sharing connector, the current-sharing connector can share the current flowing through the chips in the two areas. Make the current flowing through the chips in different areas the same.

Taking the power module shown in Figure 1 and Figure 2 as an example, the power module includes a first current sharing connector clip1 and a second current sharing connector clip2. The first area 10 and the second area 20 are The chips C1, C2, C3, and C4 are electrically connected through the first current-sharing connector clip1, and the chips C5, C6, C7, and C8 in the third region 30 and the fourth region 40 are electrically connected through the first current-sharing connector clip1. The two current-sharing connecting pieces clip2 are electrically connected.

Currently, chips are connected in parallel using aluminum wire bonding or copper wire bonding as the interconnection method. However, due to the small cross-sectional area of the bonding wires, many bonding wires are needed to pass large currents, which increases the complexity of the process and takes up more space. more space. At the same time, bonding wires are prone to aging or even falling off at the bonding points under high-temperature applications, causing power module failure and reducing the reliability of the power module. Finally, in applications where multiple chips of the same type are connected in parallel, the related bonding wire interconnection method is difficult to achieve uniform current and temperature of each chip. Uneven current flow among the chips will cause a single chip to be damaged due to loss and excessive stress for a long time. This will cause harm to other parallel devices and the entire system. The parallel connection between multiple chips through current sharing connectors can further ensure that the power module has better current sharing characteristics and higher reliability; and reducing the use of bonding wires can reduce the parasitic inductance in the power loop. Energy-saving power modules can work at higher voltage levels and higher frequencies; at the same time, compared to bonding wires, current-sharing connectors have a larger heat dissipation area and can achieve better heat dissipation effects. The arrangement of the same number of chips in mutually symmetrical areas and the same spacing between the chips in the same area can cooperate with the current sharing connector to further ensure that the power module has better current sharing characteristics and higher reliability.

During specific implementation, the size of the current sharing connector can be designed according to the actual size requirements of the chip and the power module. The width of the current sharing connector is preferably the same as the total width of the connected chips in the same area, so as to achieve To maximize the heat dissipation area, taking Figure 2 as an example, the width of the first current-sharing connector clip1 is preferably the distance from the leftmost end of C1 to the rightmost end of C2. During specific implementation, the number of chips in the same area connected by a current-sharing connector can be two or more, and the connection method is similar to the connection method shown in the drawings of this embodiment. Those skilled in the art can disclose in this application Basically, the design can be implemented without labor, and the number of chips connected by one current-sharing connector in the same area can be two or more, all of which are within the scope of protection of this application.

In some embodiments, the substrate further includes a middle region, the middle region is located between the two symmetrically arranged regions, and the current sharing connector is also electrically connected to the middle region. Taking the power module shown in FIG. 1 and FIG. 2 as an example, the fifth area 50 and the sixth area 60 are the middle area, and the fifth area 50 is located between the first area 10 and the second area 20 between the third area 30 and the fourth area 40 . The first current-sharing connecting piece clip1 is also electrically connected to the fifth region 50 , and the second connecting piece clip2 is also electrically connected to the sixth region 60 . In a specific embodiment, the first region 10, the second region 20 and the sixth region 60 are electrically connected, and the first region 10, the second region 20 and the sixth region 60 is the integrated interconnection copper area. Compared with the traditional technology that uses aluminum wire bonding or copper wire bonding as the interconnection method, the current sharing connector can achieve electrical connection with the intermediate area while interconnecting the chips with a simpler process.

In some embodiments, the substrate is a copper-clad ceramic substrate, and the first to sixth regions are all copper-clad regions. The copper-clad ceramic substrate has the characteristics of excellent thermal cycle, stable shape, good rigidity, high thermal conductivity, and high reliability. The copper-clad surface can be etched with various patterns, and it is pollution-free and pollution-free. The operating temperature can range from -55℃～850℃, using copper-clad ceramic substrate can further ensure the stability of the power module operation. The first to sixth areas are all copper-clad areas on the substrate.

In a specific embodiment, the current sharing connectors are electrically connected to the chip and the substrate through silver sintering.

In some embodiments, as shown in Figures 2 and 3, the current equalizing connector includes a main body part 80 and a bonding part 90. The bonding part 90 is located at both ends of the main body part 80 and is connected with the The main body part 80 is fixedly connected, and both ends of the main body part 80 point to the two symmetrically arranged areas respectively; the main body part 80 is used to electrically connect with the middle area, and the bonding part 90 is used to electrically connect the chips in the same area. The main body part is used to improve the current sharing characteristics between chips in different areas, and the bonding part is used to improve the current sharing characteristics between chips in the same area. The current sharing connector can further ensure the parallel connection. The current sharing characteristics between chips further improve the reliability of the power module.

In some embodiments, as shown in FIGS. 2 and 3 , the bonding part 90 includes at least two connecting parts 140 and a plurality of bonding wires w1˜w4. The at least two connecting parts 140 and the at least Two chips are arranged opposite each other. One end of the connecting portion 140 is electrically connected to the oppositely arranged chip, and the other end is fixedly connected to the main body portion 80 . Two adjacent connecting portions 140 are composed of a plurality of wires arranged in parallel. The bonding wires w1 to w4 are connected. The bonding portion 90 includes a plurality of bonding wires w1 to w4, which can increase the overall carrying capacity of the current sharing connector and further improve the current sharing characteristics between the chips.

In some embodiments, the main body part 80 and the connecting part 140 are both sheet-like structures that can be attached to the middle area or the chip. The main body part and the connecting part have a sheet-like structure. On the one hand, the chip circuit can have a larger current-carrying cross-sectional area to increase the carrying capacity of the chip circuit; on the other hand, the current-sharing connector can also have a larger current-carrying cross-sectional area. The heat dissipation area also provides a large contact area between the current sharing connector and the substrate, which facilitates reliable electrical connection.

In some embodiments, the current-sharing connecting piece is a copper piece. Copper has good physical and chemical properties such as electrical conductivity, thermal conductivity, corrosion resistance and ductility. Using copper current sharing connectors can further ensure that the power module has better current sharing characteristics.

In some embodiments, the power module further includes a plastic shell disposed outside the power module. The plastic shell includes at least one hole, and the hole is used to make part of the even-numbered areas and/or all Part of the middle region is exposed, so that part of the even number of regions and/or part of the middle region is electrically connected to an external device.

In a specific embodiment, taking the power module shown in Figures 1, 2 and 4 as an example, the plastic housing 2 includes a first hole 100, and the substrate 1 also includes a module electrically connected to the sixth region 60. The seventh region 70 can be regarded as the extension of the sixth region 60 in terms of function and connection relationship, and together with the sixth region 60 can be regarded as the middle region; the first hole 100 is used to expose part of the seventh region 70 so that the seventh region 70 is electrically connected to an external device, and then the sixth region 60 is electrically connected to an external device through the seventh region 70 . Although the embodiment of Figure 4 shows two first holes 100, when viewed in conjunction with Figures 1 and 2, the two corresponding first holes 100 in Figure 4 can be at the same position without affecting the technical effect. Simplified to a first hole 100.

The plastic shell 2 further includes a second hole 110 , which is used to expose part of the fifth region 50 so that the fifth region 50 can be electrically connected to an external device. Although the embodiment of Figure 4 shows two second holes 110, when viewed in conjunction with Figures 1 and 2, the two corresponding second holes 110 in Figure 4 can be at the same position without affecting the technical effect. Simplified to a second hole 110 .

The plastic shell 2 further includes a third hole 120, which is used to expose part of the third region 30 and part of the fourth region 40, so that the third region Partial areas of 30 and part of the fourth area 40 are electrically connected to external devices.

The plastic casing can directly interconnect the copper-clad area with the outside world, reducing signal wiring on the substrate, which can not only reduce the size of the power module, but also reduce the parasitic inductance of the power module, allowing the power module to work at higher temperatures. High power density is achieved at higher voltage levels and higher frequencies; at the same time, the design of exposing part of the copper-clad ceramic substrate enables the power module to have better heat dissipation performance and enable the power module to operate at higher temperatures.

Although multiple holes are shown in the embodiment of Figure 4, multiple holes are a preferred arrangement during specific implementation. A single hole itself can achieve the same effect as the above. Therefore, the setting of the plastic shell including a hole is also within the protection scope of this application. During specific implementation, the number and position of the holes can be adjusted according to actual use. In a specific embodiment, when the plastic housing includes multiple holes, the multiple holes are determined according to the chips and copper cladding on the substrate. The location of the area is set correspondingly symmetrically.

In a specific embodiment, as shown in Figures 1 and 2, the sixth region 60 is used to electrically connect to an AC (Alternating Current, alternating current) terminal, and the fifth region 50 is used to electrically connect to a DC (Alternating Current) terminal. Direct Current (Direct Current) negative electrode is electrically connected, and the third region 30 and the fourth region 40 are used to be electrically connected to the DC positive electrode to form a complete half-bridge power module loop.

In specific implementation, as shown in Figures 1 and 2, taking the chip as a MOSFET as an example, the drains of chips C1 to C8 are located on the back of the chip and are directly welded to the copper-clad area of the substrate. The drains of chips C1 to C4 are electrically connected to the AC terminal, and the sources and DC negative poles of chips C1 to C4 are interconnected through the first connector clip1. Chips C1 to C4 thus form the lower arm of the above-mentioned half-bridge power module circuit. ; The drains of chips C5 to C8 are electrically connected to the DC positive electrode, and the sources and AC terminals of chips C5 to C8 are interconnected through the second connector clip2. Chips C5 to C8 thus form the upper bridge of the above-mentioned half-bridge power module loop. arm.

In a specific embodiment, as shown in FIG. 2 , the power module further includes a plurality of pins P1 to P8, and the pins P1 to P8 are all used for electrical connection with the peripheral drive control board. The gates of chips C1 and C2 are electrically connected to pin P2 via bonding wires, the source of chip C1 is electrically connected to pin P1 via bonding wires, and the gates of chips C3 and C4 are electrically connected to pin P6 via bonding wires. connection, the source of chip C3 is electrically connected to pin P5 via a bonding wire; the gates of chips C5 and C6 are electrically connected to pin P4 via a bonding wire, and the source of chip C5 is electrically connected to pin P3 via a bonding wire. Connection; the gates of chips C7 and C8 are electrically connected to pin P8 via bonding wires, and the source of chip C7 is electrically connected to pin P7 via bonding wires.

In a specific embodiment, the substrate further includes a resistance region 130. Taking the power module shown in FIGS. 1 and 2 as an example, the resistance region 130 is disposed in the sixth region 60 and the seventh region. 70, the width of the resistive area 130 is smaller than the copper-covered width of the copper-covered areas on both sides, so the resistance of the resistor area 130 is greater than the resistance of the copper-covered areas on both sides. This area is used to connect the current sensor of the peripheral device through pins. , to collect the current data of the power module.

Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a vehicle, which includes the corresponding power module in any of the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, I won’t go into details here.

It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the usual meanings understood by those with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Those of ordinary skill in the art should understand that the discussion of any above embodiments is only illustrative, and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; under the spirit of the present application, the above embodiments or Technical features in different embodiments can also be combined, steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

In addition, to simplify illustration and discussion, and so as not to obscure the embodiments of the present application, well-known power supplies/power supplies with integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Ground connection. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and this also takes into account the fact that details regarding the implementation of these block diagram devices are highly dependent on the implementation of the embodiments of the present application. platform (i.e., these details should be well within the understanding of those skilled in the art). Where specific details (eg, circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that construction may be accomplished without these specific details or with changes in these specific details. The embodiments of this application are implemented below. Accordingly, these descriptions should be considered illustrative rather than restrictive.

Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those of ordinary skill in the art from the foregoing description. The present embodiments are intended to embrace all such alternatives, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of this application shall be included in the protection scope of this application.

Claims (10)

1. A power module comprising a substrate and a plurality of chips, wherein:

the substrate comprises an even number of areas, the even number of areas are symmetrically arranged along the central axis of the substrate in pairs, at least two chips electrically connected with the areas are arranged in each area, the number of the chips in the two symmetrically arranged areas is the same, and the chips in the two symmetrically arranged areas are also symmetrically electrically connected in pairs along the central axis of the substrate.

2. The power module of claim 1, wherein when the number of chips in the same region is three or more, the pitch of two adjacent chips in the region is the same.

3. The power module of claim 1 further comprising current sharing connectors through which chips in the two symmetrically disposed regions are electrically connected.

4. The power module of claim 3 wherein the substrate further comprises a middle region, the middle region being located between the symmetrically disposed two regions, the current sharing connection further being electrically connected to the middle region.

5. The power module according to claim 4, wherein the current equalizing connection member comprises a main body portion and a bonding portion, the bonding portion is located at two ends of the main body portion and is fixedly connected with the main body portion, and the two ends of the main body portion are respectively directed to the two symmetrically arranged areas;

the main body part is used for being electrically connected with the middle area, and the bonding part is used for being electrically connected with a chip positioned in the same area.

6. The power module of claim 5, wherein the bonding portion includes at least two connection portions and a plurality of bonding wires, the at least two connection portions are disposed opposite to the at least two chips one by one, one end of each connection portion is electrically connected to the opposite chip, the other end is fixedly connected to the main body portion, and two adjacent connection portions are connected by the plurality of bonding wires disposed in parallel.

7. The power module of claim 6, wherein the main body portion and the connecting portion are each of a sheet-like structure that can be bonded to the intermediate region or the chip.

8. The power module of claim 3 wherein the current sharing connection is a copper piece.

9. The power module of claim 4, further comprising a plastic package housing disposed outside the power module, the plastic package housing including at least one hole for exposing a partial region of the even number of regions and/or a partial region of the intermediate region to electrically connect the partial region of the even number of regions and/or the partial region of the intermediate region with an external device.

10. A vehicle, characterized in that it comprises a power module according to any one of claims 1-9.