CN117544433A - Core particle, low power consumption control method, chip and computer equipment - Google Patents

Abstract

Embodiments of the present application provide a core particle, a low-power control method, a chip, and a computer device. The core particle transmits a data stream with an interconnected counterpart core particle. The core particle includes: a core particle interconnection interface; The core-to-chip interconnection interface includes: a link layer and a physical layer; the link layer is used to close the data transmission path of the link layer during the transmission idle time of the data stream, so that the link layer Enter a low power consumption state; wherein the physical layer maintains its working state unchanged. The embodiments of this application can reduce the power consumption of core-to-die interconnection in the core-to-die interconnection scenario.

Description

Core particle, low power consumption control method, chip and computer equipment

Technical field

The embodiments of the present application relate to the field of chip technology, and specifically relate to a core chip, a low-power control method, a chip, and a computer device.

Background technique

A chip is a unit chip that can achieve certain functions and contains an interconnection interface. Multiple cores are interconnected through the interconnection interface to form a SOC (System On Chip) and other chips. Core-to-core interconnection refers to using an interconnection protocol to coordinate and schedule the communication between two cores on the basis of the physical connection between the interconnection interfaces of two cores, thereby achieving interconnection and interoperability between two cores.

In the scenario of chip interconnection, data transmission and processing between chips consume a lot of power. Therefore, how to provide technical solutions to reduce the power consumption of chip interconnection has become an urgent technical problem that technicians in the field need to solve. .

Contents of the invention

In view of this, embodiments of the present application provide a chip, a low-power control method, a chip, and a computer device to reduce the power consumption of core-to-chip interconnection in a core-to-die interconnection scenario.

In a first aspect, embodiments of the present application provide a core particle that transmits data streams between the core particle and an interconnected counterpart core particle. The core particle includes: a core particle interconnection interface; the core particle interconnection interface includes: Link layer and physical layer;

The link layer is configured to close the data transmission path of the link layer during the idle time of transmission of the data stream, so that the link layer enters a low power consumption state;

Wherein, the physical layer maintains its working state unchanged.

Optionally, transmitting a data stream between the core particle and an interconnected opposite end core particle includes: the core particle sends a data stream to the opposite end core particle; and the link layer is configured to During the transmission idle time, close the data transmission path of the link layer, including:

When the transmission idle time arrives, obtain a low-power entry request;

In response to the low-power entry request, send a low-power entry signal to the opposite end chip, and close the data transmission path of the link layer;

Wherein, the entering low power consumption signal is used to control the link layer of the opposite end core chip to close the data receiving path, so that the link layer of the opposite end core chip enters a low power consumption state.

Optionally, transmitting a data stream between the core particle and an interconnected opposite end core particle includes: the opposite end core particle sends a data stream to the core particle; and the link layer is configured to The transmission idle time, closing the data transmission path of the link layer includes:

When the transmission idle time arrives, obtain the low-power consumption signal sent by the link layer of the opposite end core;

In response to the entering low power consumption signal, the data receiving path of the link layer is closed.

Optionally, the link layer closes the data transmission path of the link layer by turning off the working clock of the data transmission path.

Optionally, the link layer is also configured to open a data transmission path of the link layer during the transmission working time of the data stream, so that the link layer exits the low power consumption state.

Optionally, transmitting a data stream between the core particle and an interconnected opposite end core particle includes: the core particle sends a data stream to the opposite end core particle; and the link layer is configured to The transmission working time is to open the data transmission path of the link layer, including:

When the transmission working time arrives, open the data transmission path of the link layer, and send an exit low-power consumption signal to the opposite end core;

Wherein, the exit low power consumption signal is used to control the link layer of the opposite end core chip to restart the transmission of the data stream.

Optionally, transmitting a data stream between the core particle and an interconnected opposite end core particle includes: the opposite end core particle sends a data stream to the core particle; and the link layer is configured to The transmission working time is to open the data transmission path of the link layer, including:

When the transmission working time arrives, open the data receiving path of the link layer;

Obtain the low-power exit signal sent by the link layer of the opposite end core particle, and restart the transmission of the data stream in response to the low-power exit signal.

Optionally, the link layer starts the data transmission path of the link layer by turning on the working clock of the data transmission path.

Optionally, the link layer uses the working clock of the link layer as a driving clock to close the data transmission path of the link layer, or open the data transmission path of the link layer.

Optionally, the length of the transmission idle time is a preset number of working clock cycles of the link layer.

Optionally, the link layer includes: low power consumption control logic;

The low-power control logic is used to perform the step of closing the data transmission path of the link layer during the transmission idle time of the data stream, so that the link layer enters a low-power state; and Execute the step of opening the data transmission path of the link layer during the transmission working time of the data stream, so that the link layer exits the low power consumption state.

In the second aspect, embodiments of the present application provide a low power consumption control method, which is applied to the core particle as described in the first aspect, and transmits data streams between the core particle and the interconnected counterpart core particle; the method include:

During the idle time of data flow transmission, close the data transmission path of the link layer so that the link layer enters a low power consumption state;

And, maintain the working status of the physical layer unchanged.

Optional, also includes:

During the transmission working time of the data flow, the data transmission path of the link layer is opened so that the link layer exits the low power consumption state.

Optionally, transmitting the data stream between the core particle and the interconnected counterpart core particle includes: the core particle sends the data stream to the counterpart core particle; and during the idle time of the data stream transmission, the link is closed. Layer data transmission path, including:

When the transmission idle time arrives, obtain a low-power entry request;

In response to the low-power entry request, an entry low-power signal is sent to the opposite end core and the data transmission path of the link layer is closed; wherein the entry low-power signal is used to control the opposite end. The link layer of the core particle closes the data receiving path, so that the link layer of the opposite end core particle enters a low power consumption state;

The process of opening the link layer data transmission path during the transmission working time of the data stream includes:

When the transmission working time arrives, the data transmission path of the link layer is opened, and an exit low-power consumption signal is sent to the opposite end core; wherein the exit low-power consumption signal is used to control the opposite end core. The granular link layer restarts the transmission of the data stream.

Optionally, closing the data transmission path of the link layer includes: using the working clock cycle of the link layer as the driving clock, closing the working clock of the data sending path of the link layer;

The step of opening the data transmission path of the link layer includes: using the working clock cycle of the link layer as a driving clock, opening the working clock of the data sending path of the link layer.

Optionally, transmitting the data stream between the core particle and the interconnected opposite end core particle includes: the opposite end core particle sends the data stream to the core particle; and during the idle time of the data stream transmission, the link is closed. Layer data transmission path, including:

When the transmission idle time arrives, obtain the low-power consumption signal sent by the link layer of the opposite end core;

In response to the entering low-power signal, close the data receiving path of the link layer;

The process of opening the link layer data transmission path during the transmission working time of the data stream includes:

When the transmission working time arrives, open the data receiving path of the link layer;

Obtain the low-power exit signal sent by the opposite end core chip, and in response to the low-power exit signal, restart the transmission of the data stream.

Optionally, closing the data receiving path of the link layer includes: using the working clock cycle of the link layer as the driving clock, closing the working clock of the data receiving path of the link layer;

Turning on the data receiving path of the link layer includes: using the working clock cycle of the link layer as the driving clock, turning on the working clock of the data receiving path of the link layer.

In a third aspect, embodiments of the present application provide a chip including a plurality of interconnected core particles, and the core particles are as described in the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer device, including the chip described in the third aspect.

The core particles provided in the embodiments of the present application can be used in core particle interconnection scenarios. In the core particle interconnection scenario, data streams are transmitted between core particles and interconnected peer core particles. Based on this, the core particles provided in the embodiments of the present application may include a core particle interconnection interface, and the core particle interconnection interface may include: a link layer and a physical layer; the link layer is used to transmit the data stream when the data flow is idle. time, the data transmission path of the link layer is closed, so that the link layer enters a low power consumption state; wherein the physical layer maintains the working state unchanged. It can be seen that the core particle provided by the embodiment of the present application can close the data transmission path of the link layer of the core particle when the transmission idle time of the data stream arrives, so that the data transmission path of the link layer of the core particle does not work, and the core particle The link layer enters a low-power state to reduce the power consumption of the core. At the same time, the physical layer of the core particle serves as the next layer of the link layer. Since the data transmission path of the link layer of the core particle does not transmit data, the physical layer of the core particle can enter the low power consumption state when the link layer enters the low power consumption state. Stop the data transmission work, so that the physical layer of the core particle can maintain the working state unchanged, avoiding the physical layer retraining process when the physical layer performs state switching, thereby reducing the power consumption of the physical layer, and increasing the use of data stream transmission time (the added time corresponds to the saved physical layer retraining time) to improve data transmission efficiency.

It can be seen that the embodiment of the present application can control the link layer to enter a low-power state during the idle time of the data stream transmission between the core and the peer core, while the physical layer maintains the working state unchanged, thereby achieving low power consumption of the core. control, reducing the power consumption of the core; and avoiding the retraining process of state switching caused by low-power control at the physical layer, eliminating the power consumption and time occupation caused by retraining of the physical layer, and improving data The time available for streaming. Therefore, the solution provided by the embodiments of this application can reduce the power consumption of core-to-die interconnection in the core-to-die interconnection scenario, and by avoiding retraining of the physical layer, it can increase the time available for data stream transmission and improve data transmission efficiency.

Description of drawings

In order to explain the embodiments of the present application or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only This is an embodiment of the present application. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without exerting creative efforts.

Figure 1 is a schematic diagram of an optional structure of core-to-chip interconnection.

Figure 2 is a schematic diagram of an optional layered structure of the core-to-chip interconnection protocol in the core-to-chip interconnection interface.

Figure 3 is a schematic diagram of another optional structure of core-chip interconnection.

Figure 4 is a schematic flow diagram of an optional low-power control method in a chip-to-chip interconnection scenario.

Figure 5 is a schematic diagram of an optional structure of core-to-chip interconnection provided by an embodiment of the present application.

Figure 6 is an optional flow diagram of the low power consumption control method provided by the embodiment of the present application.

FIG. 7 is a schematic diagram of an optional flow corresponding to entering a low power consumption state in the low power consumption control method provided by the embodiment of the present application.

FIG. 8 is a schematic diagram of an optional flow corresponding to exiting the low power consumption state in the low power consumption control method provided by the embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

In order to facilitate understanding of core-particle interconnection, taking core particle 1 and core particle 2 as an example, Figure 1 exemplarily shows an optional structural schematic diagram of core-particle interconnection. As shown in Figure 1, the core chip may include a core chip interconnection interface and multiple functional modules. The core chip interconnection interface is connected to multiple functional modules through a system bus. Outside the core, core 1 and core 2 can communicate and interconnect through the core interconnect interface to transmit data streams. For any core particle, the opposite core particle of the core particle may be another core particle in communication with the core particle.

It should be noted that the two core particles interconnected through the core particle interconnection interface can be any type of core particles, for example, two functional core particles interconnected through the interconnection interface, a functional core particle and an interface core interconnected through the interconnection interface. Granules etc.

Based on the different types of core particles, the forms of functional modules in the core particles that implement core particle functions may also be different. For example, the functional core may include a processor core (such as a CPU core), and the functional module in the processor core may be a module integrated with a processor core and a cache (Cache), etc. For another example, the interface chip can be the chip where the interface module is located for network communication, USB (Universal Serial Bus, Universal Serial Bus) communication, PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) communication and other communication methods. .

When core particles are interconnected through the core particle interconnection interface, they are based on the core particle interconnection protocol. Among them, the core particle interconnection protocol can define the hierarchical mechanism for data transmission between interconnected core particles. The core layer of the core interconnect protocol can include: application layer, protocol layer, link layer and physical layer from top to bottom. It should be noted that the application layer, protocol layer, link layer and physical layer are circuit modules implemented in the core based on the layering of the core-to-chip interconnection protocol for core-to-chip interconnection; that is to say, the application layer, protocol layer , the link layer and the physical layer can be in the form of circuit modules, for example, application layer circuit module (referred to as application layer), protocol layer circuit module (referred to as protocol layer), link layer circuit module (referred to as link layer), physical layer Circuit module (referred to as physical layer). In a possible implementation, the link layer and physical layer can be deployed on the interconnection interface of the core particle as a circuit module in the interconnection interface; the application layer and protocol layer can be deployed outside the interconnection interface of the core particle and set as the link layer. upper circuit module.

As an optional implementation, the link layer and physical layer can be deployed on the core interconnect interface of the core. In one example, Figure 2 shows an optional structural diagram of the layering of the core interconnection protocol at the core interconnection interface. As shown in Figure 2, the layering of the core interconnection protocol at the core interconnection interface may include links. layer (for example, the link layer 11 of core particle 1 and the link layer 21 of core particle 2 in Figure 2), and the physical layer (for example, the physical layer 12 of core particle 1 and the physical layer 22 of core particle 2 in Figure 2 ).

In core particles, the link layer is used to provide reliability guarantee for communication between core particles, including but not limited to: error correction, verification, retransmission mechanism, etc.

In the core particle, the physical layer is used to provide the physical transmission path (referred to as the path) for the core particle to transmit data.

In the layering of the core-to-chip interconnection protocol, the link layer and the physical layer can be connected through adapted interfaces.

It should be further explained that the layering of the core-to-chip interconnection protocol may also include an application layer and a protocol layer. The application layer is the top layer of the Internet protocol, and software can run on the application layer. For example, the software may be executed by the core's processor hardware, such as the core's processor core, etc., and run at the application layer. The protocol layer is located below the application layer and is used to support the business protocols corresponding to the services carried by the core. It is related to the type of services carried by the core. Moreover, the protocol layer can also support user-defined protocols.

In the direction of the core particle sending data, the core particle's application layer data is received through the protocol layer, and the protocol layer sends the data to the link layer (for example, the protocol layer can divide the data data into sub-data and transmit it to the link layer) , the link layer distributes data to the physical layer for transmission through the corresponding interface.

One of the purposes of core-particle interconnection is to realize communication between cores, that is, to realize data transmission between cores. For example, when the data transmitted between core particles is a data stream, data stream transmission between core particles needs to be implemented. Based on the layering of the core-to-chip interconnection protocol shown in Figure 2, the data sending direction of core 1 is introduced. Inside the core 1, the link layer 11 obtains the data stream sent by the protocol layer. The link layer 11 transmits the data stream to the physical layer 12 through the data transmission path of the link layer. The physical layer 12 of the core 1 transmits the data through the data transmission path. The path transmits the data stream to the physical layer 22 of the peer core 2 . That is to say, in the data sending direction of core 1, the data stream is transmitted layer by layer in the link layer 11 and physical layer 12 of the core, and the data stream is transmitted to the opposite end core 2 through the physical layer 12.

The data receiving direction of core 2 is introduced. The physical layer 22 of the core particle 2 receives the data stream sent by the physical layer 12 of the core particle 1 through the data transmission path; further, inside the core particle 2, the physical layer 22 transmits the data stream to the link through the data transmission path of the physical layer. Layer 21. That is to say, in the data receiving direction of core 2, after the physical layer 22 of core 2 receives the data stream sent by the physical layer 12 of core 1 at the opposite end, the data flow is transmitted between the physical layer 22 of core 2 and the link. Road layer 21 performs layer-by-layer transmission.

It can be seen that the data transmission of the core particle is divided into sending data and receiving data, that is, the core particle can be a sender, sending data information to the opposite end core particle, or it can be a receiver, receiving data information sent by the opposite end core particle. Furthermore, when the data transmission of the core particle is divided into sending data and receiving data, the data transmission path of the core particle can be divided into a data sending path and a data receiving path. Referring to another optional structural diagram of core-chip interconnection shown in Figure 3, the link layer of the core chip may include a data transmission path (Tx Data Signal) and a data reception path (Rx Data Signal); where, the link layer data The transmission path is, for example, the data transmission path 111 of the link layer 11 of the core 1 in the figure, and the data transmission path 212 of the link layer 21 of the core 2; the data reception path of the link layer is, for example, the link layer of the core 1 in the figure. The data receiving path 112 of 11, and the data receiving path 211 of the link layer 21 of core 2. The physical layer of the core particle may include a data transmission path (Tx Data Lane) and a data reception path (Rx Data Lane); the data transmission path of the physical layer is, for example, the data transmission path 121 of the physical layer 12 of the core particle 1 in the figure, and the data transmission path of the core particle 2. The data sending path 222 of the physical layer 22 of the core chip; the data receiving path of the physical layer of the core chip are, for example, the data receiving path 122 of the physical layer 12 of the core chip 1 in the figure, and the data receiving path 221 of the physical layer 22 of the core chip 2.

It should be noted that Tx means sending and Rx means receiving. The core particle as the sender (for example, core particle 1) can transmit data to the data reception path of the core particle as the receiver (for example, core particle 2) through the data sending path, thereby realizing the interconnected communication of the core particles.

It needs to be further explained that due to different transmission paths and differences in physical layer processing, the data in different data transmission paths have different delays in reaching the receiver, so the data in different data transmission paths need to be aligned, for example: in Core 1 The data sending path 111 of the link layer 11 needs to be aligned with the data sending path 121 of the physical layer 12, and the data receiving path 112 of the link layer 11 needs to be aligned with the data receiving path 122 of the physical layer 12; the link layer 21 in the core 2 The data receiving path 211 needs to be aligned with the data receiving path 221 of the physical layer 22, and the data sending path 212 of the link layer 21 needs to be aligned with the data sending path 222 of the physical layer 22. In the core-to-chip interconnection scenario, the link layer of the core-to-grain interconnection interface can control the training of the physical layer to complete the alignment of the data transmission path, so that data can be accurately transmitted and received, and the correct sampling time point can be found.

In the upper-layer business module of the core (such as the protocol layer), there is a business working state and a business idle state. Therefore, the core can be controlled by exiting and entering the low-power state in the business working state and business idle state. Power consumption. For example, when there is no data, the upper-layer business module is in the idle state, and the data in the data stream transmitted by the data transmission channel is empty data. The upper-layer business module can control the chip interconnection interface to enter a low-power state to turn off the data of the physical layer. transmission function to reduce power consumption. When there is data, the upper-layer business module enters the business working state and can control the chip interconnection interface to exit the low-power state and resume normal data transmission.

Taking core 1 as the sender and core 2 as the receiver in the core-to-chip interconnection as an example, core 1 can initiate a low-power entry process to enter the low-power state synchronously with core 2; when it is necessary to exit low-power When, Core 1 can initiate a low-power exit process to exit the low-power state synchronously with Core 2. In an optional implementation, taking the entry and exit of a low-power state by controlling the physical layer as an example, Figure 4 illustrates an optional flow chart of a low-power control method in a core-to-chip interconnection scenario.

As shown in Figure 4, when entering the low power consumption state, the link layer 11 of the core 1 sends an entry low power handshake signal to the link layer 21 of the core 2 to request the core 2 to enter the low power state.

When core 2 receives the low-power handshake signal, if core 2 supports entering the low-power state, it responds to the low-power handshake signal, and the link layer 21 of core 2 establishes a link to core 1. Layer 11 sends the low-power handshake signal, so that the handshake between core 1 and core 2 is successful, completing the interaction to enter the low-power state.

When the interaction to enter the low-power state is completed, the link layer 11 of the core 1 controls the physical layer 12 to enter the low-power state; at the same time, the link layer 21 of the core 2 controls the physical layer 22 to enter the low-power state.

The link layer of the core particle controls the physical layer to enter a low power consumption state and can close the data transmission path of the physical layer. For example, core 1 serves as the sender, and the physical layer 12 of core 1 closes the data transmission path and stops sending new data to the physical layer 21 of core 2; core 2 serves as the receiver, and the physical layer 22 of core 2 closes The data receiving path stops receiving data sent by the physical layer 11 of the core 1.

Since the physical layer closes the data transmission path when entering the low-power state, when exiting the low-power state, the link layer needs to control the physical layer to retrain and adjust the data transmission path to complete the data alignment of the transmission channel. This enables signals transmitted by the link layer to be accurately received and transmitted by the physical layer. Therefore, when exiting the low power consumption state, the link layer 11 of the core 1 controls the physical layer 12 to retrain. At the same time, the link layer 21 of the core 2 controls the physical layer 22 to retrain.

After the physical layer is retrained, the link layer 11 of core 1 sends an exit low-power handshake signal to the link layer 21 of core 2.

When core 2 receives the exit low-power handshake signal sent by core 1, in response to the exit low-power handshake signal, the link layer 21 of core 2 sends an exit low-power handshake signal to the link layer 11 of core 1. The handshake signal completes the interaction with Core 1 to exit the low-power state, and Core 1 and Core 2 resume normal data flow transmission.

It should be noted that the physical layer training process is relatively cumbersome, including data path alignment, clock-to-data alignment, data order preservation, etc., resulting in a longer training time, which generally takes longer microseconds (us). level of time to achieve re-locking of the physical layer. Therefore, through the physical layer entering and exiting the low-power state, the low-power control scheme of the core is implemented. Since the physical layer needs to be retrained when exiting the low-power state, this increases the cost of low-power control of the core. The entry and exit time and operation complexity of power consumption control are not conducive to reducing the power consumption of chip interconnection.

In view of this, embodiments of the present application provide an improved low-power control solution in a core-to-chip interconnection scenario, so that low-power control is implemented based on the link layer without changing the working state of the physical layer.

Based on the above ideas, as an optional implementation, the embodiment of the present application can close the data transmission path of the link layer of the core particle when the transmission idle time of the data stream arrives, so that the data transmission path of the link layer of the core particle does not work. The link layer of the core particle enters a low power consumption state, reducing the power consumption of the core particle. At the same time, the physical layer of the core particle serves as the next layer of the link layer. Since the data transmission path of the link layer of the core particle does not transmit data, the physical layer of the core particle can enter the low power consumption state when the link layer enters the low power consumption state. Stop the data transmission work, so that the physical layer of the core particle can maintain the working state unchanged, avoiding the physical layer retraining process when the physical layer performs state switching, thereby reducing the power consumption of the physical layer, and increasing the use of data stream transmission time (the added time corresponds to the saved physical layer retraining time) to improve data transmission efficiency.

In order to achieve the above purpose, as an optional implementation, embodiments of the present application can improve the link layer, so that when the idle time for the transmission of the data stream arrives, the data transmission path of the link layer is closed, and when the transmission working time of the data stream arrives, When , open the data transmission channel of the link layer. Among them, FIG. 5 exemplarily shows an optional structural schematic diagram of core-chip interconnection according to the embodiment of the present application. As shown in Figure 5, in the core-to-core interconnection scenario, data streams are transmitted between core 1 and interconnected core 2.

Among them, for any core particle (for example, core particle 1 or core particle 2), the core particle may include a core particle interconnection interface, and the core particle interconnection interface may include a link layer and a physical layer. The link layer in the embodiment of the present application may be During the transmission idle time of the data stream, the data transmission path of the link layer is closed, so that the link layer enters a low power consumption state. Among them, the physical layer of the core particle maintains its working state unchanged.

The transmission idle time of the data flow refers to the time during which the upper-layer service module of the link layer transmits empty data in the service idle state.

When the data transmission of the core particle is divided into sending data and receiving data, the data transmission path of the link layer may include a data sending path and a data receiving path.

In some embodiments, corresponding to the closing of the data transmission path of the link layer when entering the low-power control state, the link layer in the embodiment of the present application is also used to open the link during the transmission working time of the data stream. layer data transmission path, so that the link layer exits the low power consumption state.

In order to facilitate understanding of the way in which low power consumption control is performed based on the link layer in this embodiment of the present application, FIG. 6 exemplarily shows an optional flowchart of the low power consumption control method in this embodiment of the present application. Figure 6 shows only one core particle as an example. As shown in Figure 6, low-power control methods applied to core chips can include:

Step S100: The link layer closes the data transmission path of the link layer during the idle time of the data stream transmission.

Step S200: The link layer opens the data transmission path of the link layer during the transmission working time of the data stream.

Correspondingly referring to Figure 5, taking core 1 as the sender and core 2 as the receiver of the core-to-chip interconnection as an example, the low power consumption control process will be described.

During the idle time of data stream transmission, as shown in Figure 5, the link layer 11 of core 1 closes its data sending path 111. As a result, the link layer 11 of core 1 enters a low power consumption state, while the link layer 11 of core 1 The working state of the physical layer 12 remains unchanged. The data transmission path 121 of the physical layer 12 of the core 1 is still in the channel alignment state. Since the data transmission path 111 of the link layer 11 of the core 1 does not transmit data, the core 1 The physical layer 12 can stop the data sending work of the data sending path 121 when the link layer 11 enters the low power consumption state.

Core 2 as the receiver can enter the low power consumption state synchronously with core 1 as the sender. In an optional example, the link layer 11 of core 1 can send a signal corresponding to entering the low power consumption state to the link layer 21 of core 2 during the idle time of data stream transmission, so that the link layer of core 2 The link layer 21 closes its data receiving path 211, thus the link layer 21 of the core 2 enters a low power consumption state, while the working state of the physical layer 22 of the core 2 remains unchanged, and the data of the physical layer 22 of the core 2 remains unchanged. The receiving path 221 is still in the channel aligned state, and since the data receiving path 211 of the link layer 21 of the core 2 does not receive data, the physical layer 22 of the core 2 can stop data when the link layer 21 enters the low power consumption state. The data reception work of the receiving path 221 reduces the power consumption of the chip.

During the transmission working time of the data stream, as shown in Figure 5, the link layer 11 of the core 1 will open its data transmission path 111, so that the link layer 11 of the core 1 exits the low power consumption state. Furthermore, in order to restart the transmission of the data stream, the link layer 11 of the core 1 may send an exit low-power consumption signal to the link layer 21 of the core 2 through the data transmission path 111 .

Core 2 as the receiver and core 1 as the sender exit the low-power state synchronously. The link layer 11 based on core 1 opens its data transmission path 111 during the transmission working time of the data stream. Core 2's The link layer 21 can open its data receiving path 211 during the transmission working time of the data stream, so that the link layer 21 of the core 2 exits the low power consumption state. Furthermore, the data receiving path 211 of the link layer 21 of the core 2 can correspondingly obtain the exit low power consumption signal sent by the link layer 11 of the core 1 to restart the transmission of the data stream.

It should be noted that in Figure 5 , with core 2 as the sender and core 1 as the receiver, the process of implementing low power consumption control can refer to the above content in the same way, and the embodiments of this application will not go into details.

It can be seen that the core particle provided by the embodiment of the present application can close the data transmission path of the link layer of the core particle when the transmission idle time of the data stream arrives, so that the data transmission path of the link layer of the core particle does not work. The link layer of the core particle enters a low power consumption state, reducing the power consumption of the core particle. At the same time, the physical layer of the core particle serves as the next layer of the link layer. Since the data transmission path of the link layer of the core particle does not transmit data, the physical layer of the core particle can enter the low power consumption state when the link layer enters the low power consumption state. Stop the data transmission work, so that the physical layer of the core particle can maintain the working state unchanged, avoiding the physical layer retraining process when the physical layer performs state switching, thereby reducing the power consumption of the physical layer, and increasing the use of data stream transmission time (the added time corresponds to the saved physical layer retraining time) to improve data transmission efficiency.

It can be seen that the embodiment of the present application controls the link layer to enter a low-power state during the idle time of the data stream transmission between the core and the peer core, while the physical layer maintains the working state unchanged, thereby achieving low-power control of the core. , reduce the power consumption of the core; and avoid the retraining process of state switching caused by low-power control at the physical layer, eliminating the power consumption and time occupation caused by retraining of the physical layer, and improving the data flow The time available for transmission. Therefore, the solution provided by the embodiments of this application can reduce the power consumption of core-to-die interconnection in the core-to-die interconnection scenario, and by avoiding the retraining of the physical layer, it can increase the time available for data stream transmission and improve data transmission efficiency.

In an optional implementation, in order to realize that the link layer closes its data transmission path during the idle time of data stream transmission, the link layer in the embodiment of the present application can set low-power control logic (for example, in core 1 in Figure 5 Low power consumption control logic 13, low power consumption control logic 23 in core 2). The function of the link layer of the core particle entering and exiting the low-power state can be implemented by the low-power control logic set by the link layer of the core particle. The low-power control logic is a logic circuit set in the link layer of the core in the embodiment of the present application. The low-power control logic can be used to control the link layer to close the link during the idle time of data stream transmission. The data transmission path of the layer, and during the transmission working time of the data flow, the link layer is controlled to open the data transmission path of the link layer. Therefore, based on the control of low-power control logic, the link layer can realize entry and exit of low-power states.

It can be understood that when the low power consumption control of the link layer is implemented based on the low power consumption control logic of the link layer, when the link layer of the core particle enters the low power consumption state, the physical layer of the core particle The working state remains unchanged, so that after the link layer opens its data transmission path, the link layer can transmit the data stream to the data transmission path of the physical layer through the data transmission path, avoiding the problem when the physical layer of the core chip performs state switching. The physical layer retraining process reduces the power consumption and response time of physical layer retraining.

Based on the above-mentioned core chips, the low power consumption control scheme of the embodiment of the present application is described in detail in the core chip interconnection scenario. FIG. 7 exemplarily shows an optional flow chart corresponding to entering the low power consumption state in the low power consumption control method in the embodiment of the present application.

Based on the characteristics of the data transmission direction in the core-particle interconnection scenario, the core particle can send data streams to the opposite end core particle, and the opposite end core particle can also send data streams to the core particle.

As an optional implementation, starting from the angle of core particle 1 shown in FIG. 7 , core particle 2 serves as the opposite end core particle of core particle 1 . When the data stream transmitted between a core particle and the interconnected peer core particle is that core particle 1 sends a data stream to the peer core particle 2, as shown in Figure 7, the link layer 11 of core particle 1 can perform the following steps .

Step S101: When the transmission idle time arrives, obtain a low power consumption entry request.

The low power consumption entry request may be sent by a protocol layer located above the link layer 11 to the link layer 11 to instruct the link layer 11 to enter a low power consumption state.

Step S102: In response to the low power consumption entry request, send a low power consumption entry signal to the opposite end chip.

Among them, the low-power consumption signal sent by the link layer 11 of the core particle 1 is used to control the link layer 21 of the opposite end core particle 2 to close the data receiving path, so that the link layer 21 of the opposite end core particle 2 enters low power consumption. consumption status. In an optional implementation, the link layer 11 of the core chip 1 sends the low-power consumption signal to the link layer 21 of the opposite core chip 2 through the data transmission path.

In an implementation example, the low-power control logic set in the link layer of the core can send an entry low-power signal to the opposite core after receiving the low-power entry request sent by the protocol layer of the core. For example, the low-power control logic 13 set in the link layer 11 of the core 1 can send an entry low-power signal to the opposite core 2 after receiving the low-power entry request sent by the protocol layer of the core 1. .

While the link layer 11 sends the low-power consumption signal to the opposite end core chip, the link layer 11 may perform step S103 to close the data transmission path.

In some embodiments, closing the data transmission path at the link layer of the core may be implemented based on the working clock of the link layer. In one example, the link layer 11 of the core 1 can close the data transmission path of the link layer 11 by turning off the working clock of the data transmission path. In an optional implementation, the low-power control logic set in the link layer of the core particle can send a working clock shutdown notification to the data transmission path of the link layer of the core particle, so that the link layer of the core particle closes the data transmission path. For example, the low-power control logic 13 provided in the link layer 11 of the core 1 can send a working clock shutdown notification to the data transmission path of the link layer 11 of the core 1, so that the link layer 11 of the core 1 Close the data transmission path.

When the core particle sends a data stream to the opposite end core particle, the low-power control logic set in the link layer of the core particle can send the low-power entry request to the opposite end after obtaining the low-power entry request sent by the protocol layer of the core particle. The core particle sends an entry low-power signal, and sends a working clock shutdown notification to the data transmission path of the link layer of the core particle, so that the link layer of the core particle closes the data transmission path. For example, in FIG. 5 , when the core particle 1 transmits a data stream, the link layer 11 of the core particle 1 closes the data transmission path 111 of the link layer 11 by turning off the working clock of the data transmission path 111 . For example, the low-power control logic 13 set in the link layer 11 of the core 1 can send the low-power entry request to the opposite core 2 after obtaining the low-power entry request sent by the protocol layer of the core 1. signal, and sends a working clock shutdown notification to the transmission path 111 of the link layer 11 of the core particle 1, so that the link layer 11 of the core particle 1 closes the data transmission path 111.

In some embodiments, when the data transmission path is closed by closing the working clock of the data transmission path based on the link layer, the link layer may use the working clock of the link layer as a driver to close the link layer. Data transmission path. For example, the low-power control logic set in the link layer of the core chip can be driven by the working clock of the link layer and send a working clock shutdown notification to the data transmission path of the link layer. For example, the link layer 11 of the core 1 may be a closed data transmission path 111 driven by the working clock of the link layer 11 . For example, the low-power control logic 13 set in the link layer 11 of the core 1 can be driven by the working clock of the link layer 11 after obtaining the low-power entry request sent by the protocol layer of the core 1. The working clock shutdown notification is sent to the transmission path 111 of the link layer 11 of the core particle 1 .

As another optional implementation, starting from the perspective of core particle 2 shown in FIG. 7 , core particle 1 serves as the opposite end core particle of core particle 2 . When the transmission data stream between a core particle and the interconnected peer core particle is that core particle 1 sends a data stream to core particle 2, as shown in Figure 7, when the transmission idle time arrives, core particle 1 based on the peer end sends a data stream to core particle 2. Core 2 sends an incoming low power signal so that the link layer 21 of Core 2 can perform the following steps.

Step S104: When the transmission idle time arrives, obtain the low-power consumption signal sent by the link layer of the opposite end core chip.

Step S105: In response to the low power consumption entry signal, the data receiving path is closed.

It should be noted that, based on the data transmission characteristics of simultaneous flow of data streams between two cores in a core-to-core interconnection scenario, the link layer 21 closing the data receiving path can be executed at the same time as the link layer 11 closing the data sending path. , to realize that the opposite end core particle 2 as the receiver and the core particle 1 as the sender enter the low power consumption state simultaneously.

In an optional implementation, the low-power control logic set in the link layer of the core particle can send a working clock shutdown notification to the data transmission path of the link layer of the core particle, so that the link layer of the core particle closes the data transmission path. For example, the low-power control logic 23 provided in the link layer 21 of the core 2 can send a working clock shutdown notification to the data transmission path of the link layer 21 of the core 2, so that the link layer 21 of the core 2 Close the data transmission path.

In one example, the low-power control logic set in the core can obtain the incoming low-power signal sent by the opposite end core, so that the low-power control logic in the core can send data to the link layer of the core. The transmission path sends a working clock shutdown notification, so that the link layer of the core particle closes the data transmission path. For example, taking core 2 to receive the data stream sent by core 1 as an example, the low-power control logic 23 set up in the link layer 21 of core 2 can receive the low-power signal sent by core 1 at the opposite end, so that The working clock shutdown notification is sent to the data receiving path of the link layer 21 of the core particle 2, so that the link layer 21 of the core particle 2 closes the data receiving path.

In some embodiments, when the data transmission path is closed by closing the working clock of the data transmission path based on the link layer, the link layer may use the working clock of the link layer as a driver to close the link layer. Data transmission path. For example, the low-power control logic set in the link layer of the core chip can be driven by the working clock of the link layer and send a working clock shutdown notification to the data transmission path of the link layer. For example, the link layer 21 of the core 2 may be a closed data receiving path 211 driven by the working clock of the link layer 21 . For example, the low-power control logic 23 set in the link layer 21 of the core particle 2 can, after acquiring the low-power consumption signal sent by the opposite end core particle 1, drive the working clock of the link layer 21 to The data receiving path 211 of the link layer 21 of the core 2 sends a working clock shutdown notification.

In some embodiments, based on the link layer, the working clock of the link layer is used as the driving clock to close the data transmission path of the link layer, so that the speed at which the link layer enters the low power consumption state can be consistent with the working speed of the link layer. Corresponding to the clock cycle, for this reason, the length of the transmission idle time described in the embodiment of the present application can be a preset number of working clock cycles of the link layer, so as to realize that the length of the link layer entering the low power consumption state is consistent with the data flow. The transmission idle time is matched to reduce the power consumption of the chip.

In some embodiments, the corresponding link layer enters the low power consumption state, and when the transmission working time arrives, the link layer needs to exit the low power consumption state. FIG. 8 exemplarily shows an optional flow chart corresponding to exiting the low power consumption state in the low power consumption control method in the embodiment of the present application.

As an optional implementation, starting from the angle of core particle 1 shown in FIG. 8 , core particle 2 serves as the opposite end core particle of core particle 1 . When the data stream transmitted between a core particle and an interconnected peer core particle is: core particle 1 sends a data stream to the peer core particle 2, the link layer 11 of core particle 1 can perform the following steps.

Step S201: When the transmission working time arrives, the data transmission path is opened.

As an optional implementation, the link layer 11 of the core 1 can open the data transmission path based on the low-power exit request of the protocol layer. In a specific example, the protocol layer sends a low-power exit request to the link layer 11 of the core 1 to indicate the arrival of the transmission working time, so that the link layer opens the data transmission path.

As another optional implementation, the length of the transmission idle time can be preset to a preset number of working clock cycles of the link layer, so that after the link layer of the core enters the low power consumption state, after a preset number of The working clock cycle of the link layer can confirm the arrival of the transmission working time of the data stream, and then the link layer of the core can automatically open the data transmission path. In an optional implementation, after the link layer of the core particle enters the low-power state, if the timing reaches a preset number of link layer working clock cycles, the low-power control logic set in the link layer of the core particle , the data transmission path in the link layer of the core particle can be controlled to be opened. For example, the low-power control logic set in the link layer of the core can send a working clock start notification to the data transmission path of the link layer of the core to control the data transmission path in the link layer of the core. Turn on.

For example, the link layer 11 of core 1 can open the data transmission path 111, thereby opening the data transmission path through the link layer 11, and the data flow of the protocol layer in core 1 can be transmitted to the link layer, thereby transmitting to the physical layer 12 .

While the link layer 11 opens the data transmission path, the link layer 11 may perform step S202 and send an exit low-power consumption signal to the opposite end core.

Among them, the exit low-power consumption signal sent by the link layer 11 of the core particle 1 controls the link layer 21 of the opposite end core particle 2 to restart the transmission of the data stream.

In some embodiments, opening the data transmission path at the link layer of the core may be implemented based on the working clock of the link layer. In one example, the link layer 11 of the core 1 can open the data transmission path of the link layer 11 by turning on the working clock of the data transmission path. In an optional implementation, the low-power control logic set in the link layer of the core particle can send a working clock start notification to the data transmission path of the link layer of the core particle, so that the link layer of the core particle starts data transmission path. For example, the low-power control logic 13 provided in the link layer 11 of the core 1 can send a working clock start notification to the data transmission path of the link layer 11 of the core 1, so that the link layer 11 of the core 1 Open the data transmission path.

When the core particle sends a data stream to the peer core particle, the low-power control logic set in the link layer of the core particle can send a low-power exit request to the core particle after obtaining the low-power exit request sent by the protocol layer of the core particle. The data transmission path of the link layer sends a working clock start notification, so that the link layer of the core particle opens the data transmission path. For example, in FIG. 5 , when the core particle 1 sends a data stream, the link layer 11 of the core particle 1 realizes opening the data transmission path 111 of the link layer 11 by turning on the working clock of the data transmission path 111 . For example, the low-power control logic 13 set in the link layer 11 of the core 1 can send a low-power exit request to the link layer 11 of the core 1 after obtaining the low-power exit request sent by the protocol layer of the core 1. The path 111 sends a working clock start notification, so that the link layer 11 of the core 1 opens the data sending path 111 .

In some embodiments, when the data transmission path is opened based on the link layer by turning on the working clock of the data transmission path, the link layer can use the working clock of the link layer as a driver to turn on the link layer. Data transmission path. For example, the low-power control logic set in the link layer of the core chip can be driven by the working clock of the link layer and send a working clock start notification to the data transmission path of the link layer. For example, the link layer 11 of the core 1 may be a data transmission path 111 that is driven by the working clock of the link layer 11 . For example, the low-power control logic 13 set in the link layer 11 of the core 1 can be driven by the working clock of the link layer 11 after obtaining the low-power exit request sent by the protocol layer of the core 1. The working clock start notification is sent to the transmission path 111 of the link layer 11 of the core particle 1 .

As another optional implementation, starting from the angle of core particle 2 shown in FIG. 8 , core particle 1 serves as the opposite core particle of core particle 2 . When the data flow transmitted between the core particle and the interconnected peer core particle is that the peer core particle 1 sends a data stream to core particle 2, when the transmission working time of the peer core particle 1 comes, the link layer starts the data flow. For the transmit path, the link layer 21 of core 2 can perform the following steps.

Step S203: When the transmission working time arrives, the data receiving path is opened.

As an optional implementation, when the length of the transmission idle time is preset to a preset number of working clock cycles of the link layer, when the data stream transmission is idle for a preset number of working clock cycles of the link layer, arrival, indicating that the transmission working time has arrived, the link layer 21 of the core 2 automatically opens the data transmission path, for example, the link layer 21 of the core 2 opens the data receiving path 211. Therefore, the data reception path is opened based on the link layer 21 of the core 2, and the link layer 21 of the core 2 can receive the information transmitted by the link layer 11 of the core 1.

In an optional implementation, the low-power control logic set in the link layer of the core particle can send a working clock start notification to the data transmission path of the link layer of the core particle, so that the link layer of the core particle starts data transmission path. For example, the low-power control logic 23 provided in the link layer 21 of the core 2 can send a working clock start notification to the data transmission path of the link layer 21 of the core 2, so that the link layer 21 of the core 2 Open the data transmission path.

In some embodiments, when the data transmission path is opened based on the link layer by turning on the working clock of the data transmission path, the link layer can use the working clock of the link layer as a driver to turn on the link layer. Data transmission path. For example, the low-power control logic set in the link layer of the core chip can be driven by the working clock of the link layer and send a working clock start notification to the data transmission path of the link layer. For example, the link layer 21 of the core 2 may be a data receiving path 211 that is driven by the working clock of the link layer 21 . For example, the low-power control logic 23 set in the link layer 21 of the core 2 can be driven by the working clock of the link layer 21 to the link of the core 2 after the preset number of working clock cycles arrives. The data receiving path 211 of layer 21 sends the working clock start notification.

Step S204: Obtain the exit low-power consumption signal sent by the link layer of the opposite end core chip, and in response to the exit low-power consumption signal, restart the transmission of the data stream.

Based on the opening of the data sending path of the link layer 11 of the core particle 1 and the opening of the data receiving path of the link layer 21 of the core particle 2, the relationship between the core particle 1 as the sender and the core particle 2 as the receiver can be restored. Normal data streaming.

It can be seen that the core particle in the embodiment of the present application enters a low power consumption state by controlling the link layer during the idle time of the data stream transmission between the core particle and the opposite end core particle, while the physical layer maintains the working state unchanged, realizing that the core particle Low-power control of the chip reduces the power consumption of the chip; and avoids the retraining process of state switching caused by low-power control at the physical layer, saving the power consumption and time caused by retraining of the physical layer. Occupation increases the time available for data stream transmission. Therefore, the solution provided by the embodiments of this application can reduce the power consumption of core-to-die interconnection in the core-to-die interconnection scenario, and by avoiding the retraining of the physical layer, the time available for data stream transmission can be increased, and the data transmission efficiency can be improved.

Embodiments of the present application also provide a chip, including a plurality of interconnected core particles. The core particles may be the core particles provided in the embodiments of the present application.

An embodiment of the present application also provides a computer device, such as a server device or a terminal device. The computer device may include the above-mentioned chip provided in the embodiment of the present application.

The above describes multiple embodiment solutions provided by the embodiments of the present application. The optional methods introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment solutions. These can be considered as embodiments disclosed and disclosed in the embodiments of this application.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims (19)

1. A core particle, characterized in that, a data stream is transmitted between the core particle and an interconnected counterpart core particle, the core particle includes: a core particle interconnection interface; the core particle interconnection interface includes: a link layer and physical layer; The link layer is configured to close the data transmission path of the link layer during the idle time of transmission of the data stream, so that the link layer enters a low power consumption state; Wherein, the physical layer maintains its working state unchanged. 2. The core particle according to claim 1, characterized in that transmitting a data flow between the core particle and an interconnected opposite end core particle includes: the core particle sends a data stream to the opposite end core particle; The link layer is used to close the data transmission path of the link layer during the transmission idle time of the data stream, including: When the transmission idle time arrives, obtain a low-power entry request; In response to the low-power entry request, send a low-power entry signal to the opposite end chip, and close the data transmission path of the link layer; Wherein, the entering low power consumption signal is used to control the link layer of the opposite end core chip to close the data receiving path, so that the link layer of the opposite end core chip enters a low power consumption state. 3. The core particle according to claim 1, characterized in that, transmitting a data stream between the core particle and an interconnected opposite end core particle includes: the opposite end core particle sends a data stream to the core particle; The link layer is used to close the data transmission path of the link layer during the transmission idle time of the data stream, including: When the transmission idle time arrives, obtain the low-power consumption signal sent by the link layer of the opposite end core; In response to the entering low power consumption signal, the data receiving path of the link layer is closed. 4. The core particle according to any one of claims 1 to 3, characterized in that the link layer closes the data transmission path of the link layer by closing the working clock of the data transmission path. 5. The core particle according to claim 1, characterized in that the link layer is also used to open the data transmission path of the link layer during the transmission working time of the data stream, so that the The link layer exits the low power state. 6. The core particle according to claim 5, characterized in that transmitting the data flow between the core particle and the interconnected opposite end core particle includes: the core particle sends a data stream to the opposite end core particle; The link layer is used to open the data transmission path of the link layer during the transmission working time of the data flow, including: When the transmission working time arrives, open the data transmission path of the link layer, and send an exit low-power consumption signal to the opposite end core; Wherein, the exit low power consumption signal is used to control the link layer of the opposite end core chip to restart the transmission of the data stream. 7. The core particle according to claim 5, wherein transmitting a data flow between the core particle and an interconnected opposite end core particle includes: the opposite end core particle sends a data stream to the core particle; The link layer is used to open the data transmission path of the link layer during the transmission working time of the data flow, including: When the transmission working time arrives, open the data receiving path of the link layer; Obtain the low-power exit signal sent by the link layer of the opposite end core particle, and restart the transmission of the data stream in response to the low-power exit signal. 8. The core particle according to any one of claims 5 to 7, characterized in that the link layer opens the data transmission path of the link layer by turning on the working clock of the data transmission path. 9. The core particle according to claim 5, characterized in that the link layer uses the working clock of the link layer as a driving clock to close the data transmission path of the link layer, or to open the link layer. data transmission path. 10. The core particle according to claim 9, wherein the length of the transmission idle time is a preset number of working clock cycles of the link layer. 11. The core particle according to claim 5, characterized in that the link layer includes: low power consumption control logic; The low-power control logic is used to perform the step of closing the data transmission path of the link layer during the transmission idle time of the data stream, so that the link layer enters a low-power state; and Execute the step of opening the data transmission path of the link layer during the transmission working time of the data stream, so that the link layer exits the low power consumption state. 12. A low power consumption control method, characterized in that it is applied to the core particle according to any one of claims 1 to 11, and the data stream is transmitted between the core particle and the interconnected counterpart core particle; Methods include: During the idle time of data flow transmission, close the data transmission path of the link layer so that the link layer enters a low power consumption state; And, maintain the working status of the physical layer unchanged. 13. The low power consumption control method according to claim 12, further comprising: During the transmission working time of the data flow, the data transmission path of the link layer is opened so that the link layer exits the low power consumption state. 14. The low power consumption control method according to claim 13, characterized in that transmitting data flow between the core particle and the interconnected opposite end core particle includes: the core particle sends data to the opposite end core particle. Stream; the method of closing the link layer data transmission path during the idle time of data stream transmission includes: When the transmission idle time arrives, obtain a low-power entry request; In response to the low-power entry request, an entry low-power signal is sent to the opposite end core and the data transmission path of the link layer is closed; wherein the entry low-power signal is used to control the opposite end. The link layer of the core particle closes the data receiving path, so that the link layer of the opposite end core particle enters a low power consumption state; The process of opening the link layer data transmission path during the transmission working time of the data stream includes: When the transmission working time arrives, the data transmission path of the link layer is opened, and an exit low-power consumption signal is sent to the opposite end core; wherein the exit low-power consumption signal is used to control the opposite end core. The granular link layer restarts the transmission of the data stream. 15. The low power consumption control method according to any one of claims 12 to 14, characterized in that said closing the data transmission path of the link layer includes: using the working clock cycle of the link layer as the driving clock, closing the link layer. The working clock of the data transmission path at the path layer; Opening the data transmission path of the link layer includes: using the working clock cycle of the link layer as the driving clock, opening the working clock of the data sending path of the link layer. 16. The low power consumption control method according to claim 13, characterized in that transmitting data flow between the core particle and the interconnected opposite end core particle includes: the opposite end core particle sends data to the core particle. Stream; the method of closing the link layer data transmission path during the idle time of data stream transmission includes: When the transmission idle time arrives, obtain the low-power consumption signal sent by the link layer of the opposite end core; In response to the entering low-power signal, close the data receiving path of the link layer; The process of opening the link layer data transmission path during the transmission working time of the data stream includes: When the transmission working time arrives, open the data receiving path of the link layer; Obtain the low-power exit signal sent by the opposite end core chip, and in response to the low-power exit signal, restart the transmission of the data stream. 17. The low power consumption control method according to claim 16, wherein said closing the data receiving path of the link layer includes: using the working clock cycle of the link layer as the driving clock, closing the data receiving path of the link layer. The working clock of the channel; The step of opening the data receiving path of the link layer includes: using the working clock cycle of the link layer as a driving clock, opening the working clock of the data receiving path of the link layer. 18. A chip, characterized in that it includes a plurality of interconnected core particles, and the core particles are as described in any one of claims 1-11. 19. A computer device, characterized by comprising the chip according to claim 18.