CN117526915B - Circuit and method for turning on/off and resetting medical instrument - Google Patents

Abstract

A switching on/off and resetting circuit of a medical apparatus and a method thereof belong to the field of medical apparatus, in the switching on/off and resetting circuit, a power supply is respectively connected to the input ends of a controllable switching circuit and a key circuit, and the output end of the key circuit is respectively connected to a master control circuit, a first control end of the controllable switching circuit and a delay resetting circuit of a delay and control circuit; the output end of the controllable switch circuit is connected to a voltage-reducing circuit, and the voltage-reducing circuit is respectively connected to a main control chip, a reset circuit and a delay and control circuit of the main control circuit; the delay and control circuit is respectively connected with a main control chip of the main control circuit and a second control end of the controllable switch; the reset circuit is connected with the delay circuit and the control circuit and the main control chip at the same time; the invention can utilize software to set the delay time of delayed shutdown, control the shutdown delay time, and simultaneously, clean and shut down the operation, keep the integrity of the file system and improve the reliability of the reset operation.

Description

Circuit and method for turning on/off and resetting medical instrument

Technical Field

The invention relates to a switching-on/off and resetting circuit and a method thereof, in particular to a switching-on/off and resetting circuit of a medical instrument and a method thereof, belonging to the field of medical instruments.

Background

With the continuous progress of technology, the need for intelligent medical devices in terms of convenience and stability is becoming more important. In the field of medical equipment, the number of buttons of the mechanical equipment is also an integral part for reflecting the convenience and stability of the medical equipment and is also an important integral part for reflecting the intelligent degree of the equipment, in the existing medical equipment, a self-locking switch and a reset key are independently arranged, the reset key can be reset after being pressed, the key has the following defects in multiple aspects,

1. Risk of data loss: in the case of a direct power outage, ongoing tasks and operations may be suddenly interrupted, resulting in the loss of unsaved data. This may have serious consequences for important files, databases, or ongoing computing tasks;

2. Risk of hardware damage: sudden power outages also increase the risk of damage to hardware components. When the power supply has not been completely turned off, the system may be in an unstable state, and abrupt changes in current and voltage may cause stress and overload to the electronic device;

3. Risk of misoperation: since the keys are easily triggered carelessly or touched briefly, the rc reset circuit is susceptible to incorrect operation, possibly resulting in the system being reset in an unnecessary situation. This can interrupt an ongoing task or disrupt data integrity;

4. the anti-jamming capability is weak: the rc reset circuit is sensitive to external noise or interference, such as electromagnetic interference, power supply fluctuations, etc., which can cause the system to reset accidentally, thereby affecting the reliability of the device.

In view of the trend of the current medical devices toward miniaturization and multi-functionalization of keys, how to realize multiple functions by one switch is an important issue of the medical devices.

Disclosure of Invention

Aiming at the risks of data loss, hardware damage, misoperation and the like of the existing equipment buttons, in order to achieve the aim of convenience and stability of the intelligent medical equipment, companies develop optimization of equipment key functions, the invention provides a circuit and a method for turning on and off the medical equipment, which aim at providing a circuit and a method for turning on and off the medical equipment according to actual requirements, the software is used for setting the delay time of delayed shutdown, so that the key delay time is controlled, the system performs necessary cleaning and closing operation while normally closing the running program, the integrity of the file system is maintained, the data damage is prevented, the equipment is ensured not to have unfinished background tasks or communicate with peripheral equipment when the equipment is shut down, and the stability and the reliability of the reset operation are improved.

The technical scheme of the invention is as follows: the switching on and switching off and resetting circuit of the medical instrument comprises a resetting key, wherein the switching on and switching off and resetting circuit comprises a power supply circuit, a controllable switching circuit, a key circuit, a voltage reducing circuit, a delay and control circuit, a resetting circuit and a main control circuit, wherein a power supply is respectively connected to the input ends of the controllable switching circuit and the key circuit, and the output end of the key circuit is respectively connected to the main control circuit, a first control end of the controllable switching circuit and a delay resetting circuit of the delay and control circuit; the output end of the controllable switch circuit is connected to a voltage-reducing circuit, and the voltage-reducing circuit is respectively connected to a main control chip, a reset circuit and a delay and control circuit of the main control circuit; the delay and control circuit is respectively connected with a main control chip of the main control circuit and a second control end of the controllable switch; the reset circuit is connected with the delay circuit and the control circuit and the main control chip at the same time; in the delay and control circuit, an inverter IV is arranged, one end of the inverter IV is provided with a noise reduction signal stabilizing circuit, the other end of the inverter IV is provided with a delay reset circuit, the noise reduction signal stabilizing circuit comprises a PMOS tube III and a triode IV, a base electrode and an emitter electrode of the triode IV are respectively connected with an IO port MAIN CON pin of a MAIN control circuit through a resistor fifteen and a resistor eighteen, the delay reset circuit comprises a triode V and a resistor-capacitor circuit II, a collector electrode of the triode V is connected with a REST pin of the MAIN control circuit through a resistor sixteen, the triode V is connected to a 5Y terminal on the inverter IV through a diode seven and a resistor seventeen, the resistor in the resistor-capacitor circuit II is connected with a diode five in parallel, one end of the resistor-capacitor circuit II is connected to a 6A terminal of the inverter IV, and the other end of the resistor-capacitor circuit II is connected to a KEY OPEN pin of the MAIN control circuit;

Further, the KEY circuit comprises a first reset KEY, one end of the first reset KEY is connected with a POWER-IN terminal IN the controllable switch circuit through a resistor five, and the other end of the first reset KEY is connected to a KEY OPEN terminal or pin IN the controllable switch circuit and the main control circuit;

further, the voltage reduction circuit comprises a first linear voltage stabilizer and a second linear voltage stabilizer, one ends of a fourth capacitor and a fifth capacitor are connected between the first linear voltage stabilizer and the second linear voltage stabilizer and are connected with a POWER supply voltage fifth, the other ends of the fourth capacitor and the fifth capacitor are grounded, one end of the first linear voltage stabilizer is connected with the second capacitor and one end of the third capacitor are simultaneously connected with a POWER end, the other ends of the second capacitor and the third capacitor are grounded, one end of the first capacitor and one end of the sixth capacitor are simultaneously connected with the POWER supply voltage, and the other ends of the first capacitor and the sixth capacitor are grounded;

Further, the controllable switch circuit comprises a PMOS tube, a first diode, a second diode and a third diode, wherein the input end of the first diode is connected with a POWER-IN terminal, the output end of the first diode is respectively connected with an eighth positive electrode of a capacitor, one end of a first resistor and a source electrode of the PMOS tube, the eighth negative electrode of the capacitor is grounded, the source electrode of the PMOS tube is connected with a drain electrode of the PMOS tube and is connected to a POWER terminal IN the voltage reducing circuit, the other end of the first resistor is connected to a grid electrode of the PMOS tube and is simultaneously connected to a collector electrode of the second transistor through the third resistor, the base electrode of the second diode and the negative electrode of the third diode are connected to the ground through the eighth resistor, the emitter electrodes of the second diode and the third diode are respectively connected to KEYOPEN and MAIN OPEN ends IN the MAIN control circuit at the positive electrodes through the fourth resistor and the sixth resistor;

further, a grid electrode of a PMOS tube III is connected to a collector electrode of a triode IV of the noise reduction signal stabilizing circuit, a source electrode of the PMOS tube III is connected with a power supply, the grid electrode is connected with the power supply through a resistor thirteen, an emitter electrode of the triode IV and the other end of a resistor eighteen are simultaneously grounded, a drain electrode of the PMOS tube III is connected to a 1A terminal on an inverter IV through a diode and one end of a resistor-capacitor circuit I, the other end of the resistor-capacitor circuit I is grounded, and the resistor-capacitor circuit I is a capacitor seventeen and a resistor eleven which are connected in parallel;

Further, the delay reset circuit comprises a resistor-capacitor circuit II, a diode seven and a triode five, the resistor-capacitor circuit II comprises a capacitor eighteen and a resistor ten, one ends of the capacitor eighteen and the resistor ten are connected to a 6A terminal of an inverter four, the other end of the capacitor eighteen is grounded, the resistor ten is connected with the diode five in parallel, and the other parallel end of the resistor ten is connected to a KEY OPEN pin in the main control circuit and is also connected with the resistor fourteen; the positive electrode of the diode seven is connected to the 5Y terminal of the inverter four, the negative electrode of the diode seven is connected to the emitter of the triode five through a resistor seventeen, the collector of the triode five is connected to the RSET pin in the main control circuit through a resistor sixteen, the emitting electrode of the triode five is grounded, the delay reset circuit further comprises a capacitor sixteen, one end of the capacitor sixteen is connected to the power supply voltage terminal of the inverter four, and the negative electrode of the capacitor sixteen is grounded;

further, the RESET circuit comprises a diode IV which is connected in parallel with a resistor nine, one end of the parallel circuit is connected with a power supply voltage VCC, the other end of the parallel circuit is connected with a capacitor fifteen, the parallel circuit is connected to a RESET pin in the main control circuit, and the other end of the capacitor fifteen is grounded;

Further, the master control circuit comprises a master control chip, the master control chip is a singlechip STM32F103, a crystal oscillator is arranged between pins 5 and 6 of the singlechip STM32F103, two ends of the crystal oscillator are respectively connected with one ends of a capacitor ten and a capacitor nine which are connected in parallel, the other ends of the capacitor ten and the capacitor nine are connected with one ends of a capacitor twelve and a capacitor eleven which are connected in parallel in series, the master control circuit is simultaneously connected to a pin 12 of the singlechip STM32F103, the other ends of the capacitor twelve and the capacitor eleven which are connected in parallel are simultaneously connected to a pin 13 and a resistor seven of the singlechip STM32F103, and the other ends of the resistor seven are connected with a power supply voltage; a capacitor fourteen is connected in series between pins 18 and 19 of the singlechip STM32F103, one end of a resistor twelve is connected in series on the number 28 of the singlechip STM32F103, and the other end of the resistor twelve is grounded; the capacitor nineteen is connected in series between pins 31 and 32 of the SCM 32F103, the capacitor thirteen is connected in series between pins 47 and 48, one end of a resistor II is connected to pin 60, the other end of the resistor II is grounded, and the capacitor seven is connected in series between pins 63 and 64.

The on-off and resetting method of the medical instrument utilizes the on-off and resetting circuit of the medical instrument, and the on-off and resetting method comprises the following steps of:

1) After the reset key I is pressed, the controllable switch circuit is conducted, and power is supplied to the main control chip through the voltage reduction circuit, so that the main control chip enters a working state;

2) The IO port MAIN CON in the MAIN control circuit outputs high level, the noise reduction signal stabilizing circuit in the delay and control circuit works, the triode IV and the PMOS tube III are conducted, the power supply voltage is input into the inverter IV, the high level is output through twice inversion to control the conduction of the controllable switch, and at the moment, no matter whether the reset key I is lifted, the equipment is in a starting state;

3) Lifting the equipment to normally start after the reset key is pressed down;

4) The RESET key is not lifted for a long time after being pressed down, a delay RESET circuit in the delay and control circuit works, and the triode is conducted in five ways, so that RESET is changed into low level, and the main control chip is RESET;

5) After the reset key I is released, the circuit discharges rapidly, so that the whole circuit system is ensured to recover to an initial state when the key is pressed again;

6) Pressing the reset key I again, and normally starting the device;

7) When the reset KEY is pressed down, the KEY OPEN pin outputs a high level, the MAIN control chip receives the high level and performs shutdown operation, the MAIN control chip outputs a low level signal, the left half circuit in the delay and control circuit works, the triode four and the PMOS tube are turned on and off, and the MAIN OPEN outputs a low level;

8) And after the reset key is lifted, the equipment is completely powered off and shut down.

The invention has the positive effects that: the input high voltage can be reduced to the voltage required by the device by arranging a voltage reduction circuit in the switching-on/off and reset circuit; the key circuit is arranged in the switching-on/switching-off and resetting circuit, so that the switching-off and resetting can be judged according to the time of pressing down the key; by arranging a controllable switch circuit in the switching-on/off and reset circuit, signal control can be implemented by using the KEY OPEN and the MAIN OPEN, when one of the two signals is at a high level, the triode II is conducted, the grid voltage of the PMOS tube I is smaller than the source voltage, and the PMOS tube I is conducted to supply power to the equipment; by setting a delay and control circuit in the switching-on/off and reset circuit, the threshold values of the noise reduction signal stabilizing circuit and the inverter IV can be utilized when the switching-on/off is performed, fluctuation generated by various interferences in the circuit is filtered out, the switching signal is stabilized, and the anti-interference capability is improved; the forced reset realizes the delay of the resistance capacitance circuit II by using the delay reset circuit and the threshold value of the inverter IV, can realize the reset operation by long keys, and can realize the quick software and hardware reset by pressing the reset when the system fails, does not respond or needs to be completely restarted by arranging the reset circuit in the switching on and shutting down and the reset circuit; the main control circuit is arranged in the switching-on/switching-off and resetting circuit, so that the control function is realized in addition to the integral control of the medical equipment, and the time of key pressing is mainly recorded in the switching-on/switching-off and resetting process, so that the controllable switch is controlled to execute the switching-on/switching-off operation; the invention uses the single key to control the on-off and the reset, and uses the inverter IV to stabilize and delay the signals, thereby realizing the adjustable on-off and reset time, reducing the possibility of misoperation and improving the anti-interference capability of the equipment. The signals are stabilized and delayed through the inverter IV, and the on-off and reset operations are realized by utilizing a single key. The user can realize the startup and shutdown by only touching one switch, so that the operation is more convenient and rapid. The reset function of the main control chip is triggered by long-time pressing in the switch area. A proper time threshold is set to prevent misoperation from triggering reset action, a delay reset circuit can ensure the stability and reliability of reset operation, the delay reset circuit can monitor the long time and accurately trigger the reset instruction. The time delay shutdown can be used for carrying out necessary cleaning and shutdown operations while normally shutting down an operating program, different time delay times can be set according to actual requirements, and the time delay shutdown is from a few seconds to a few minutes or even longer, so that a user can select proper time delay time to execute shutdown operations according to specific conditions, the integrity of a file system is maintained, data damage is prevented, incomplete background tasks or communication with peripheral equipment are avoided when equipment is shut down through the time delay shutdown, the user experience and stability of the medical instrument are improved, operation steps are simplified, the number of keys is reduced, the switching-on and switching-off functions are more intelligent and reliable, and the active reset risk of the equipment caused by misoperation is reduced.

Drawings

Fig. 1 is a schematic diagram of the connection between the circuits in the power-on/off and reset circuit.

Fig. 2 is a voltage step-down circuit diagram.

Fig. 3 is a key circuit diagram.

Fig. 4 is a circuit diagram of a controllable switch.

Fig. 5 is a delay and control circuit diagram.

Fig. 6 is a reset circuit diagram.

Fig. 7 is a master circuit diagram.

Fig. 8 is an overall circuit schematic.

Description of the reference numerals: capacitor one C1, capacitor two C2, capacitor three C3, capacitor four C4, capacitor five C5, capacitor six C6, capacitor seven C7, capacitor eight C8, capacitor nine C9, capacitor ten C10, capacitor eleven C11, capacitor twelve C12, capacitor thirteen C13, capacitor fourteen C14, capacitor fifteen C15, capacitor sixteen C16, capacitor seventeen C17, capacitor eighteen C18, capacitor nineteen C19, diode one D1, diode two D2, diode three D3, diode four D4, diode five D5, diode six D6, diode seven D7, PMOS tube one Q1, triode two Q2, PMOS tube three Q3, triode Q4, triode Q5, resistor one R1, resistor two R2, resistor three R3 and resistor four R4, five R5, six R6, seven R7, eight R8, nine R9, ten R10, eleven R11, twelve R12, thirteenth R13, fourteen R14, fifteen R15, sixteen R16, seventeen R17, eighteen R18, one reset button SW1, one-chip microcomputer STM32F103, linear voltage stabilizer U1, linear voltage stabilizer U2, four U4 inverters, supply voltage VCC, supply voltage five VCC5, crystal oscillator Y1, noise reduction signal stabilizing circuit 100 and delay reset circuit 200.

Detailed Description

The specific technical scheme of the invention is further described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of connection between various circuits in an on-off and reset circuit, including a reset key, where the on-off and reset circuit includes a power supply circuit, a controllable switch circuit, a key circuit, a voltage-reducing circuit, a delay and control circuit, a reset circuit and a main control circuit, where the power supply is connected to input ends of the controllable switch circuit and the key circuit, and output ends of the key circuit are connected to the main control circuit, a control end one of the controllable switch circuit, and a delay reset circuit 200 of the delay and control circuit; the output end of the controllable switch circuit is connected to a voltage-reducing circuit, and the voltage-reducing circuit is respectively connected to a main control chip, a reset circuit and a delay and control circuit of the main control circuit; the delay and control circuit is respectively connected with a main control chip of the main control circuit and a second control end of the controllable switch; the reset circuit is connected with the delay circuit and the control circuit and the main control chip at the same time; in the delay and control circuit, an inverter four U4 is arranged, one end of the inverter four U4 is provided with a noise reduction signal stabilizing circuit 100, the other end of the inverter four U4 is provided with a delay reset circuit 200, the noise reduction signal stabilizing circuit 100 comprises a PMOS (P-channel metal oxide semiconductor transistor) three Q3 and a triode four Q4, wherein the base electrode and the emitter electrode of the triode four Q4 are respectively connected with an IO port MAIN CON pin in a master control circuit through a resistor fifteen R15 and a resistor eighteen R18, the delay reset circuit 200 comprises a triode five Q5 and a resistor-capacitor circuit two, the collector electrode of the triode five Q5 is connected with a REST pin in the master control circuit through a resistor sixteen R16, the triode five Q5 is connected to a 5Y terminal on the inverter four U4 through a diode seventeen D7 and a resistor seventeen R17, the resistor-capacitor circuit two end is connected to a 6A terminal on the inverter four U4 through a resistor fifteen D5, and the other end of the resistor-capacitor circuit two is connected to a KEYOPEN pin in the master control circuit.

Fig. 2 is a voltage step-down circuit diagram, the voltage step-down circuit includes a first linear voltage stabilizer U1 and a second linear voltage stabilizer U2, one ends of a fourth capacitor C4 and a fifth capacitor C5 are connected between the first linear voltage stabilizer U1 and the second linear voltage stabilizer U2, one ends of the fourth capacitor C4 and the fifth capacitor C5 are grounded, one ends of the second capacitor C2 and the third capacitor C3 are connected with the POWER end at the same time, the other ends of the second capacitor C2 and the third capacitor C3 are grounded, one ends of the first capacitor C1 and the sixth capacitor C6 are connected with the POWER supply voltage VCC at the same time, and the other ends of the first capacitor C1 and the sixth capacitor C6 are grounded.

Fig. 3 is a KEY circuit diagram, wherein the KEY circuit comprises a reset KEY SW1, one end of the reset KEY SW1 is connected with a POWER-IN terminal IN the controllable switch circuit through a resistor five R5, and the other end of the reset KEY SW1 is connected to an idle switch circuit and a KEY OPEN terminal or pin on the main control chip.

Fig. 4 is a diagram of a controllable switch circuit, which includes a PMOS transistor Q1 and a diode D1, a diode D2, and a diode D3, wherein an input terminal of the diode D1 is connected to a POWER-IN terminal, an output terminal is connected to an anode of a capacitor octac 8, one end of a resistor R1, and a source of the PMOS transistor (P-channel metal oxide semiconductor transistor) Q1, a cathode of the capacitor octac 8 is grounded, a source of the PMOS transistor (P-channel metal oxide semiconductor transistor) Q1 is connected to a drain of the POWER source terminal IN the buck circuit, another end of the resistor R1 is connected to a gate of the PMOS transistor (P-channel metal oxide semiconductor transistor) Q1, and simultaneously, the input terminal of the resistor tri-R3 is connected to a collector of the transistor two Q2, the base of the transistor two Q2 is connected to a cathode of the diode D2 and a cathode of the diode tri-D3, and simultaneously, an emitter of the transistor two Q2 is grounded via the resistor octar 8, and the diode two D2 and the diode tri-D3 are connected to a cathode of the MAIN resistor four-bar 6 and a MAIN resistor four-bar 6 IN the buck circuit, respectively.

The principle of the controllable switch circuit is as follows: diode D1 is conductive in one direction, so that reverse connection of a power supply is prevented; the capacitor eight C8 can prevent the power supply voltage from being reduced due to suddenly increased load when the PMOS tube Q1 is conducted; the resistor I R1 and the resistor R3 form a voltage dividing circuit, when the diode II Q2 is not conducted, voltage division is not conducted, after the triode II Q2 is conducted, the resistor I R1 and the resistor R3 conduct voltage division, so that the PMOS (P-channel metal oxide semiconductor transistor) Q1 reaches a conducting condition, POWER is supplied to the POWER, the diode II D2 and the diode III D3 conduct electricity unidirectionally, interference between KEY OPEN and MAIN OPEN signals is prevented, the resistor IV R4 and the resistor VI R6 form a voltage dividing circuit with the resistor eighth R8 respectively, and the base voltage of the triode II Q2 meets the conducting condition of the triode II Q2.

Fig. 5 is a delay and control circuit diagram, the collector of the triode four Q4 of the noise reduction signal stabilizing circuit 100 is connected with the gate of the PMOS transistor three Q3, the source of the PMOS transistor three Q3 is connected with the power supply VCC, the gate is connected with the power supply VCC through the resistor thirteenth R13, the emitter of the triode four Q4 and the other end of the resistor eighteen R18 are simultaneously grounded, the drain of the PMOS transistor three Q3 is connected to the 1A terminal on the inverter four U4 through the diode D6 and one end of the resistor-capacitor circuit one, the other end of the resistor-capacitor circuit one is grounded, and the resistor-capacitor circuit one is the capacitor seventeen C17 and the resistor eleven R11 which are connected in parallel.

Referring to fig. 5, the noise reduction signal stabilizing circuit 100 principle is: when the MAIN CON high-level triode Q4 is conducted, the resistor eighteen R18 pulls down the resistor, so that the base electrode of the triode Q4 in an initial state is guaranteed to be low level, and the triode Q4 is turned off by default; the resistor fifteen R15 is used for limiting the current and protecting the triode Q4 from being damaged due to overlarge current; the resistor thirteen R13 provides default high level for the grid electrode of the PMOS tube three Q3, after the triode Q4 is conducted, the PMOS tube three Q3 is conducted, signals are input to the inverter four U4 after passing through the diode six D6, after inverting twice, the signals are connected to the controllable switch, the diode six D6 conducts electricity unidirectionally, current backflow is prevented, the capacitor seventeen C17 plays a role in continuous retention, voltage fluctuation is prevented, and the resistor R11 discharges the capacitor seventeen C17.

The delay reset circuit 200 comprises a resistor-capacitor circuit II, a diode seven D7 and a triode pentaQ 5, wherein the resistor-capacitor circuit II comprises a capacitor eighteen C18 and a resistor decaR 10, one ends of the capacitor eighteen C18 and the resistor decaR 10 are connected to a 6A terminal of the inverter quad U4, the other end of the capacitor eighteen C18 is grounded, the resistor decaR 10 is connected with the diode pentaD 5 in parallel, the other parallel end of the capacitor eighteen C18 is connected to a KEY OPEN pin in the main control circuit, meanwhile, the resistor fourteen R14 is also connected, the anode of the diode seven D7 is connected to a 5Y terminal of the inverter quad U4, the cathode of the diode seven D7 is connected to an emitter base electrode of the triode pentaQ 5 through the resistor seventeen R17, the collector electrode of the triode pentaQ 5 is connected to an RSET pin in the main control circuit through the resistor sixteen R16, the emitting electrode of the triode pentaQ 5 is grounded, the delay reset circuit 200 further comprises a capacitor sixteen C16, one end of the capacitor sixteen C16 is connected to a voltage power supply terminal of the inverter quad U4, and the cathode of the capacitor sixteen C16 is grounded.

The RESET circuit comprises a diode D4, the diode D4 is connected with a resistor nine R9 in parallel, one end of the parallel circuit is connected with a power supply voltage VCC, the other end of the parallel circuit is connected with a capacitor fifteenC 15, the capacitor fifteenC 15 is connected to a RESET pin of the main control chip, and the other end of the capacitor fifteenC 15 is grounded.

Fig. 6 is a reset circuit diagram in which the voltage of the capacitor is 0V in the initial state. After the power supply is powered up, the capacitor starts to charge slowly from 0V, which is determined by the RC delay time formed between the resistor and the capacitor. When the voltage of the capacitor reaches a threshold that triggers a reset, the single chip STM32F103 detects this condition through a comparator or other logic gate circuit. Upon detecting that the voltage reaches the threshold, the flip-flop will generate a reset signal that causes the reset module to revert to the known initial state. Diode four D4 rapidly discharges the capacitor when the supply voltage is 0.

In the delay reset circuit 200, KEY OPEN enters the inverter four U4 through a resistor-capacitor circuit formed by a resistor ten R10 and a capacitor eighteen C18, after reversing twice, a stable signal is output and input to the base electrode of the triode five Q5 to control the singlechip to reset, the diode seven D7 prevents current from flowing backward, and the resistor seventeen is the R17 current limiting resistor.

Fig. 7 is a diagram of a main control circuit, the main control circuit comprises a main control chip, the main control chip is a single chip microcomputer STM32F103, a crystal oscillator Y1 is arranged between pins 5 and 6 of the single chip microcomputer STM32F103, two ends of the crystal oscillator Y1 are respectively connected with one ends of a capacitor ten C10 and a capacitor nine C9 which are connected in parallel, one ends of a capacitor twelve C12 and a capacitor eleven C11 which are connected in parallel are connected in series with the other ends of the capacitor ten C10 and the capacitor nine C9, the other ends of the capacitor twelve C12 and the capacitor eleven C11 are connected to pins 12 of the single chip microcomputer STM32F103, the other ends of the capacitor twelve C12 and the capacitor eleven C11 are connected to pins 13 and a resistor seven R7 of the single chip microcomputer STM32F103, and the other ends of the resistor seven R7 are connected with a power supply voltage VCC; a capacitor fourteen C14 is connected in series between pins 18 and 19 of the singlechip STM32F103, one end of a resistor twelve R12 is connected in series on a pin 28 of the singlechip STM32F103, and the other end of the resistor twelve R12 is grounded; the capacitor nineteen pins 31 and 32 of the SCM 32F103 are connected in series, the capacitor thirteen C19 is connected in series between pins 47 and 48, one end of the resistor II R2 is connected to the pin 60, the other end of the resistor II R2 is grounded, and the capacitor seven C7 is connected in series between pins 63 and 64.

Fig. 8 is a schematic diagram of an overall circuit, and the on-off and reset method of the medical apparatus is as follows:

1) When a reset key SW1 is pressed down, KEYOPEN is equal to the voltage of POWER_IN, after the voltage is divided by a resistor four R4 and a resistor eight R8, a triode II Q2 is conducted, a PMOS tube I Q1 is conducted, POWER supplies POWER to a MAIN control chip singlechip through a voltage reducing circuit, the singlechip enters a working state, an IO port MAIN CON of the singlechip outputs a high level to conduct the triode Q4, a PMOS tube (P-channel metal oxide semiconductor transistor) three Q3 is conducted, the voltage of VCC is input to a 1A pin of an inverter four U4, the output of the VCC is connected to a 2A pin, a terminal 2Y pin outputs MAIN OPEN, the MAIN OPEN is a high level, and whether the triode II Q2 is lifted up or not is IN a conducting state, and the POWER-on is started;

2) When a reset KEY SW1 is pressed, the KEY OPEN controls the starting up and charges the capacitor eighteen C18 through a resistor ten R10;

3) After a reset key SW1 is pressed, the equipment is lifted up to be started normally;

4) When the voltage of the capacitor stone plate C18 reaches the threshold value of the inverter four U4, the terminal 6A in the inverter four U4 receives a high-level signal, the terminal 6Y outputs a low level, the terminal 6Y is connected to the terminal 5A, the terminal 5Y outputs a high level, the triode five Q5 is conducted, the RESET pin is changed into a low level, and the singlechip is RESET. After the key is released, the capacitor eighteen C18 discharges rapidly through the diode five D5 and the resistor fourteen R14, so that the whole circuit system is ensured to recover to an initial state when the key is pressed again;

6) Pressing a reset key SW1 again, and normally starting the device;

7) When a reset KEY SW1 is pressed, a KEY OPEN pin outputs a high level, when the MAIN control chip receives the high level, the MAIN control chip performs shutdown operation, a pin MAIN CON outputs a low level signal, a triode Q4 is turned off, a PMOS tube III is turned off, and a pin MAIN OPEN outputs a low level;

8) After the reset key SW1 is lifted, the equipment is completely powered off and shut down.

The invention has the positive effects that: the input high voltage can be reduced to the voltage required by the device by arranging a voltage reduction circuit in the switching-on/off and reset circuit; the key circuit is arranged in the switching-on/switching-off and resetting circuit, so that the switching-off and resetting can be judged according to the time of pressing down the key; by arranging a controllable switch circuit in the switching-on/off and reset circuit, signal control can be implemented by utilizing KEYOPEN and MAIN OPEN, when one of the two signals is at a high level, the triode II Q2 is conducted, the grid voltage of the PMOS pipe I Q1 is smaller than the source voltage, and the PMOS pipe I Q1 is conducted to supply power to the equipment; by setting a delay and control circuit in the switching-on/off and reset circuit, the threshold values of the noise reduction signal stabilizing circuit 100 and the four U4 inverters can be utilized when the switching-on/off is performed, fluctuation generated by various interferences in the circuit is filtered out, the switching signal is stabilized, and the anti-interference capability is improved; the forced reset utilizes the threshold values of the delay reset circuit 200 and the inverter four U4 to realize the delay of the resistance capacitance circuit II, the reset operation can be realized through a long key, and the reset circuit is arranged in the switching on/off and reset circuit, so that when the system fails, does not respond or needs to be completely restarted, the quick software and hardware reset can be realized by pressing down the reset; the main control circuit is arranged in the switching-on/switching-off and resetting circuit, so that the control function is realized in addition to the integral control of the medical equipment, and the time of key pressing is mainly recorded in the switching-on/switching-off and resetting process, so that the controllable switch is controlled to execute the switching-on/switching-off operation; the invention uses the single key to control the on-off and the reset, and uses the inverter four U4 to stabilize and delay the signals, thereby realizing the adjustable on-off and reset time, reducing the possibility of misoperation and improving the anti-interference capability of the equipment. The four U4 inverters stabilize and delay signals, and the single key is used for realizing the operation of starting and shutting down and resetting. The user can realize the startup and shutdown by only touching one switch, so that the operation is more convenient and rapid. The reset function of the main control chip is triggered by long-time pressing in the switch area. The time-delay reset circuit 200 can ensure the stability and reliability of the reset operation, and the time-delay reset circuit 200 can monitor the time for a long time and accurately trigger the reset instruction. The time delay shutdown can be used for carrying out necessary cleaning and shutdown operations while normally shutting down an operating program, different time delay times can be set according to actual requirements, and the time delay shutdown is from a few seconds to a few minutes or even longer, so that a user can select proper time delay time to execute shutdown operations according to specific conditions, the integrity of a file system is maintained, data damage is prevented, incomplete background tasks or communication with peripheral equipment are avoided when equipment is shut down through the time delay shutdown, the user experience and stability of the medical instrument are improved, operation steps are simplified, the number of keys is reduced, the switching-on and switching-off functions are more intelligent and reliable, and the active reset risk of the equipment caused by misoperation is reduced.

Claims (9)

1. The utility model provides a medical instrument's circuit that switches on and off and reset, includes reset button, its characterized in that: the switching-on/off and reset circuit comprises a power supply circuit, a controllable switch circuit, a key circuit, a voltage reduction circuit, a delay and control circuit, a reset circuit and a main control circuit, wherein the power supply is respectively connected to the input ends of the controllable switch circuit and the key circuit, and the output end of the key circuit is respectively connected to the main control circuit, a first control end of the controllable switch circuit and the delay reset circuit (200) of the delay and control circuit; the output end of the controllable switch circuit is connected to a voltage-reducing circuit, and the voltage-reducing circuit is respectively connected to a main control chip, a reset circuit and a delay and control circuit of the main control circuit; the delay and control circuit is respectively connected with a main control chip of the main control circuit and a second control end of the controllable switch; the reset circuit is connected with the delay circuit and the control circuit and the main control chip at the same time; in the delay and control circuit, an inverter IV (U4) is arranged, a noise reduction signal stabilizing circuit (100) is arranged at one end of the inverter IV (U4), a delay reset circuit (200) is arranged at the other end of the inverter IV (U4), the noise reduction signal stabilizing circuit (100) comprises a PMOS tube III (Q3) and a triode IV (Q4), wherein the base electrode and the emitter electrode of the triode IV (Q4) are respectively connected with an IO port MAIN CON pin of a master control circuit through a resistor fifteen (R15) and a resistor eighteen (R18), the delay reset circuit (200) comprises a triode V (Q5) and a resistor capacitor circuit II, the collector electrode of the triode V (Q5) is connected with a REST pin of the master control circuit through a resistor sixteen (R16), the triode V (Q5) is connected to a 5Y terminal on the inverter IV (U4) through a diode seven (D7) and a resistor seventeen (R17), one end of the resistor capacitor circuit II is connected with a resistor EN terminal on the master control circuit 6A of the inverter IV (U4), and the other end of the resistor capacitor circuit II is connected with a resistor EN terminal on the master control circuit II.

2. The circuit for switching on and switching off and resetting a medical device according to claim 1, wherein: the KEY circuit comprises a reset KEY I (SW 1), one end of the reset KEY I (SW 1) is connected with a POWER-IN terminal IN the controllable switch circuit through a resistor five (R5), and the other end of the reset KEY I (SW 1) is connected to a KEY OPEN terminal or pin IN the controllable switch circuit and the main control circuit.

3. The circuit for switching on and switching off and resetting a medical device according to claim 1, wherein: the voltage reducing circuit comprises a first linear voltage stabilizer (U1) and a second linear voltage stabilizer (U2), one ends of a capacitor IV (C4) and a capacitor V (C5) are connected between the first linear voltage stabilizer and the second linear voltage stabilizer and are connected with a POWER supply voltage V (VCC 5), the other ends of the capacitor IV (C4) and the capacitor V (C5) are grounded, one ends of the capacitor II (C2) and the capacitor III (C3) are connected with a POWER end at the same time, the other ends of the capacitor II (C2) and the capacitor III (C3) are grounded, one ends of the capacitor I (C1) and the capacitor VI (C6) are connected with the POWER supply voltage V (VCC) at the same time, and the other ends of the capacitor I (C1) and the capacitor VI (C6) are grounded.

4. The circuit for switching on and switching off and resetting a medical device according to claim 1, wherein: the controllable switch circuit comprises a PMOS tube (Q1) and a diode I (D1), a diode II (D2) and a diode III (D3), wherein the input end of the diode I (D1) is connected with a POWER-IN terminal, the output end of the diode I (D1) is respectively connected with the positive electrode of a capacitor eight (C8), one end of a resistor I (R1) and the source electrode of the PMOS tube (Q1), the negative electrode of the capacitor eight (C8) is grounded, the source electrode of the PMOS tube (Q1) is connected with the drain electrode of the PMOS tube to be connected with the POWER terminal IN the voltage reducing circuit, the other end of the resistor I (R1) is connected with the grid electrode of the PMOS tube (Q1), meanwhile, the base electrode of the triode II (Q2) is connected with the negative electrode of the diode II (D2) and the diode III (D3), the emitting electrode of the triode II (Q2) is grounded through the resistor eight (R8), and the emitting electrode of the diode II (D2) is respectively connected with the positive electrode of the triode II (D2) and the positive electrode of the diode III (D3) through the four resistors (R4) and the negative electrode of the OPEN 6 IN the MAIN control circuit and the OPIN 6 respectively.

5. The circuit for switching on and switching off and resetting a medical device according to claim 1, wherein: the grid electrode of a PMOS tube III (Q3) is connected to the collector electrode of a triode IV (Q4) of the noise reduction signal stabilizing circuit (100), the source electrode of the PMOS tube III (Q3) is connected with a power supply (VCC), the grid electrode is connected with the power supply (VCC) through a resistor thirteen (R13), the other end of the emitter electrode of the triode IV (Q4) and a resistor eighteen (R18) is simultaneously grounded, the drain electrode of the PMOS tube III (Q3) is connected to the 1A terminal on a phase inverter IV (U4) through a diode (D6) and one end of a resistor-capacitor circuit I, the other end of the resistor-capacitor circuit I is grounded, and the resistor-capacitor circuit I is a capacitor seventeen (C17) and a resistor eleven (R11) which are connected in parallel.

6. The circuit for switching on and switching off and resetting a medical device according to claim 1, wherein: the delay reset circuit (200) comprises a resistor-capacitor circuit II, a diode seven (D7) and a triode five (Q5), the resistor-capacitor circuit II comprises a capacitor eighteen (C18) and a resistor ten (R10), one ends of the capacitor eighteen (C18) and the resistor ten (R10) are connected to a 6A terminal of a triode four (U4), the other end of the capacitor eighteen (C18) is grounded, the resistor ten (R10) is connected with a diode five (D5) in parallel, the other parallel end of the capacitor eighteen (C18) is connected to a KEY OPEN pin in the master control circuit, meanwhile, the anode of the diode seven (D7) is connected to a 5Y terminal of a phase inverter four (U4), the cathode of the diode seven (D7) is connected to an emitter of the triode five (Q5) through a resistor seventeen (R17), the collector of the triode five (Q5) is connected to a RSET pin in the master control circuit through a resistor sixteen (R16), the emitting electrode of the triode five (Q5) is grounded, and the delay reset circuit 200 comprises a sixteen capacitor (C16) and a sixteen capacitor (C16) is connected to one end of the power supply voltage cc.

7. The circuit for switching on and switching off and resetting a medical device according to claim 1, wherein: the RESET circuit comprises a diode IV (D4), the diode IV (D4) is connected with a resistor nine (R9) in parallel, one end of the parallel circuit is connected with a power supply voltage VCC, the other end of the parallel circuit is connected with a capacitor fifteen (C15), the parallel circuit is simultaneously connected to a RESET pin in the main control circuit, and the other end of the capacitor fifteen (C15) is grounded.

8. The circuit for switching on and switching off and resetting a medical device according to claim 1, wherein: the master control circuit comprises a master control chip, the master control chip is a singlechip STM32F103, a crystal oscillator (Y1) is arranged between pins 5 and 6 of the singlechip STM32F103, two ends of the crystal oscillator (Y1) are respectively connected with one ends of a capacitor ten (C10) and a capacitor nine (C9) which are connected in parallel, one ends of a capacitor twelve (C12) and a capacitor eleven (C11) which are connected in parallel are connected in series, the other ends of the capacitor ten (C10) and the capacitor nine (C9) are connected to pins 12 of the singlechip STM32F103 at the same time, and the other ends of the capacitor twelve (C12) and the capacitor eleven (C11) which are connected in parallel are connected to pins 13 and a resistor seven (R7) of the singlechip STM32F103 at the same time, wherein the other ends of the resistor seven (R7) are connected with a power supply Voltage (VCC); a capacitor fourteen (C14) is connected in series between pins 18 and 19 of the singlechip STM32F103, one end of a resistor twelve (R12) is connected in series on the number 28 of the singlechip STM32F103, and the other end of the resistor twelve (R12) is grounded; the capacitor nineteen (C19) is connected in series between pins 31 and 32 of the SCM 32F103, the capacitor thirteen (C13) is connected in series between pins 47 and 48, one end of a resistor II (R2) is connected to pin 60, the other end of the resistor II (R2) is grounded, and the capacitor seven (C7) is connected in series between pins 63 and 64.

9. A method for turning on/off and resetting a medical device, using the circuit for turning on/off and resetting a medical device according to any one of claims 1 to 8, characterized in that: the on-off and reset methods are as follows:

1) After a reset key one (SW 1) is pressed, the controllable switch circuit is conducted, and power is supplied to the main control chip through the voltage reduction circuit, so that the main control chip enters a working state;

2) The IO port MAIN CON in the MAIN control circuit outputs high level, the noise reduction signal stabilizing circuit (100) in the delay and control circuit works, the triode IV (Q4) and the PMOS tube III (Q3) are conducted, the power supply Voltage (VCC) is input into the inverter IV (U4), the high level is output through two inversions to control the conduction of the controllable switch, and at the moment, no matter whether the reset key one (SW 1) is lifted or not, the equipment is in a starting state;

3) After a reset key one (SW 1) is pressed, the equipment is lifted up to be started normally;

4) The RESET key one (SW 1) is not lifted for a long time after being pressed, a delay RESET circuit (200) in the delay and control circuit works, a triode five (Q5) is conducted, RESET is changed into low level, and the main control chip is RESET;

5) After the reset key one (SW 1) is released, the circuit discharges rapidly, so that the whole circuit system is restored to the initial state when the reset key one (SW 1) is pressed again;

6) Resetting the key one (SW 1) again, and starting the device normally;

7) When a reset KEY I (SW 1) is pressed, a KEY OPEN pin outputs a high level, when the MAIN control chip receives the high level, the MAIN control chip performs shutdown operation, the MAIN control chip outputs a low level signal, a left half part of circuits in a delay and control circuit work, a triode IV (Q4) and a PMOS tube III (Q3) are turned on and off, and a MAIN OPEN outputs a low level;

8) After the reset key one (SW 1) is lifted, the device is completely powered off and shut down.