CN117524131A - Gate driving circuit and display panel - Google Patents
Gate driving circuit and display panel Download PDFInfo
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- CN117524131A CN117524131A CN202310346194.XA CN202310346194A CN117524131A CN 117524131 A CN117524131 A CN 117524131A CN 202310346194 A CN202310346194 A CN 202310346194A CN 117524131 A CN117524131 A CN 117524131A
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- 238000005192 partition Methods 0.000 claims abstract description 32
- 230000005540 biological transmission Effects 0.000 claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims description 24
- 230000008054 signal transmission Effects 0.000 claims description 5
- 230000011664 signaling Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 21
- 201000005569 Gout Diseases 0.000 description 15
- 238000000034 method Methods 0.000 description 4
- 101100348341 Caenorhabditis elegans gas-1 gene Proteins 0.000 description 2
- 101100447658 Mus musculus Gas1 gene Proteins 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100447665 Mus musculus Gas2 gene Proteins 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The embodiment of the application provides a gate driving circuit and a display panel, the gate driving circuit includes a gate driving unit that multistage cascade set up, the gate driving unit includes input module, drop-down control module, first output module, partition control module, second output module and drop-down module. The first output module is used for outputting the own hierarchical transmission signal; the partition control module is used for controlling the output of the current-stage scanning signal; the second output module is used for outputting the scanning signal of the current stage, and further controlling the output of the scanning signal of the current stage on the basis of ensuring the normal downloading of the level transmission signal, so that the partition driving display is realized, and the display effect of the display panel is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a gate driving circuit and a display panel.
Background
The array substrate row driving, namely, the grid row scanning driving signal circuit is manufactured on the array substrate by utilizing the existing thin film transistor liquid crystal display array manufacturing process, so that the grid progressive scanning driving mode is realized.
The traditional liquid crystal display panel is scanned line by line, the line scanning signals of the display are sequentially turned on, the images are scanned line by line, for a high-resolution product, the scanning on time distributed on each line is shortened, the high-resolution product is larger in load, pixel charging deficiency is easy to be caused, and color mixing abnormality of the display images is easy to be caused when gray scale changes between adjacent sub-frame images are larger.
Therefore, how to provide a gate driving circuit capable of implementing a partition driving display to improve the display effect of the display panel is a problem to be solved.
Disclosure of Invention
An object of the embodiment of the application is to provide a gate driving circuit and a display panel, wherein the gate driving circuit can realize partition driving display and improve the display effect of the display panel.
In one aspect, an embodiment of the present application provides a gate driving circuit, including a gate driving unit disposed in a multistage cascade, where the gate driving unit includes an input module, a pull-down control module, a first output module, a partition control module, a second output module, and a pull-down module; the input module is electrically connected with the forward scanning signal end, the upper two-stage transmission signal end and the first node, and is used for pulling up the potential of the first node; the pull-down control module is electrically connected with the forward scanning signal end, the lower two-stage clock signal end, the reverse scanning signal end, the upper two-stage clock signal end, the first global signal end, the lower two-stage transmission signal end, the reference low-level signal end, the first node, the second node and the third node, and is used for controlling the potential of the second node; the first output module is electrically connected with the first node, the current stage clock signal end and the current stage transmission signal end, and is used for outputting the current stage transmission signal; the partition control module is electrically connected with the first control signal end, the first node and the fourth node, and is used for controlling the output of the current-stage scanning signal; the second output module is electrically connected with the fourth node, the current stage clock signal end and the current stage scanning signal end, and is used for outputting the current stage scanning signal; the pull-down module is used for pulling down the electric potentials of the first node, the current level transmission signal end and the current level scanning signal end.
Optionally, in some embodiments of the present application, the first output module includes a first transistor, a gate of the first transistor is electrically connected to the first node, a first electrode of the first transistor is electrically connected to the current stage clock signal terminal, and a second electrode of the first transistor is electrically connected to the current stage signal terminal.
Optionally, in some embodiments of the present application, the first output module further includes a second transistor, a gate of the second transistor is electrically connected to the reference high signal terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the gate of the first transistor.
Optionally, in some embodiments of the present application, the partition control module includes a third transistor, a gate of the third transistor is electrically connected to the first control signal terminal, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to a fourth node.
Optionally, in some embodiments of the present application, the partition control module further includes a fourth transistor, a gate of the fourth transistor is electrically connected to the second control signal terminal, a first electrode of the fourth transistor is electrically connected to the reference low level signal terminal, and a second electrode of the fourth transistor is electrically connected to the fourth node.
Optionally, in some embodiments of the present application, the first control signal terminal is used for inputting a first control signal, and the second control signal terminal is used for inputting a second control signal, and a potential of the first control signal is opposite to a potential of the second control signal.
Optionally, in some embodiments of the present application, the second output module includes a fifth transistor, a gate of the fifth transistor is electrically connected to the fourth node, a first electrode of the fifth transistor is electrically connected to the current stage clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the current stage scan signal terminal.
Optionally, in some embodiments of the present application, the second output module further includes a sixth transistor, a gate of the sixth transistor and a first electrode of the sixth transistor are electrically connected to the second global signal terminal, and a second electrode of the sixth transistor is electrically connected to the current stage scan signal terminal.
Optionally, in some embodiments of the present application, the gate driving unit further includes: the device comprises a first capacitor, a second capacitor, an input module, a pull-down control module and a pull-down module; one end of the first capacitor is electrically connected with the first node, and the other end of the first capacitor is electrically connected with the reference low-level signal end; one end of the second capacitor is electrically connected with the second node, and the other end of the second capacitor is electrically connected with the reference low-level signal end; the input module comprises a seventh transistor, the grid electrode of the seventh transistor is electrically connected with the upper two-stage signal transmission end, the first electrode of the seventh transistor is electrically connected with the forward scanning signal end, and the second electrode of the seventh transistor is electrically connected with the first node; the pull-down control module comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, wherein the grid electrode of the eighth transistor is electrically connected with the forward scanning signal end, the first electrode of the eighth transistor is electrically connected with the lower two-stage clock signal end, and the second electrode of the eighth transistor is electrically connected with the third node; the grid electrode of the ninth transistor is electrically connected with the reverse scanning signal end, the first electrode of the ninth transistor is electrically connected with the upper two-stage clock signal end, and the second electrode of the ninth transistor is electrically connected with the third node; the grid electrode of the tenth transistor is electrically connected with the third node, the first electrode of the tenth transistor is electrically connected with the first global signal end, and the second electrode of the tenth transistor is electrically connected with the second node; the grid electrode of the eleventh transistor is electrically connected with the signal end of the next two-stage transmission, the first electrode of the eleventh transistor is electrically connected with the reverse scanning signal end, and the second electrode of the eleventh transistor is electrically connected with the first node; the grid electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the second node, and the second electrode of the twelfth transistor is electrically connected with the reference low-level signal end; the pull-down module comprises a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, wherein the grid electrode of the thirteenth transistor, the grid electrode of the fourteenth transistor and the grid electrode of the fifteenth transistor are electrically connected with the second node; a first electrode of the thirteenth transistor is electrically connected to the first node; a first electrode of the fourteenth transistor is electrically connected with the current-stage signal transmission end, and a first electrode of the fifteenth transistor is electrically connected with the current-stage scanning signal end; the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor and the second electrode of the fifteenth transistor are all electrically connected to the reference low-level signal terminal.
In another aspect, the present application provides a display panel including the gate driving circuit as described above.
In the gate driving circuit and the display panel provided by the embodiment of the application, the first output module, the partition control module and the second output module are arranged in the gate driving unit, and the first output module is used for outputting the hierarchical transmission signal; the partition control module is used for controlling the output of the current-stage scanning signal; the second output module is used for outputting the scanning signal of the current stage, and further controlling the output of the scanning signal of the current stage on the basis of ensuring the normal downloading of the level transmission signal, so that the partition driving display is realized, and the display effect of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a gate driving unit in the gate driving circuit shown in FIG. 1;
FIG. 3 is a first circuit schematic of the gate driving unit provided in FIG. 2;
fig. 4 is a first driving timing diagram of a gate driving circuit according to an embodiment of the present disclosure;
FIG. 5 is a second circuit schematic of the gate driving unit provided in FIG. 2;
FIG. 6a is a schematic diagram of a second driving timing diagram of the gate driving circuit according to the embodiment of the present disclosure;
FIG. 6b is a second driving timing diagram of a display panel according to the embodiment of the present disclosure;
FIG. 7 is a third circuit schematic of the gate driving unit provided in FIG. 2;
fig. 8 is a third driving timing diagram of the gate driving circuit according to the embodiment of the present application;
fig. 9 is a fourth driving timing diagram of the gate driving circuit according to the embodiment of the present application;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 11 is a schematic view of a partition of the display panel provided in fig. 10.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The embodiment of the application provides a gate drive circuit and display panel, and this gate drive circuit is through setting up the output of regional control module in order to control this level scanning signal, and then has realized the regional drive and has shown, is favorable to promoting display panel's display effect. The following will describe in detail. The following description of the embodiments is not intended to limit the preferred embodiments. In addition, in the description of the present application, the term "comprising" means "including but not limited to". The terms "first," "second," "third," and the like are used merely as labels, and are used for distinguishing between different objects and not for describing a particular sequential order.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application. As shown in fig. 1, the gate driving circuit provided in the embodiment of the present application includes a multi-stage cascade gate driving unit. In fig. 1, the cascaded 1 st to 3 n-th gate driving units are taken as an example, and the 1 st to n-th, n+1-th to 2 n-th, 2n+1-th to 3 n-th gate driving units are divided into three gate driving unit groups 10.
The 1 st to nth stages only sequentially output the signal of the stage, but do not output the scanning signal of the stage under the control of the first control signal GON; the n+1st to 2n-th and 2n+1st to 3n-th stages sequentially output the present-stage transmission signal and output the present-stage scanning signal under the control of the first control signal GON.
Referring to fig. 2, fig. 2 is a schematic diagram of a gate driving unit in the gate driving circuit provided in fig. 1. As shown in fig. 2, the embodiment of the present application provides a gate driving unit, where the gate driving unit includes an input module 101, a pull-down control module 102, a first output module 103, a partition control module 104, a second output module 105, and a pull-down module 106, a first capacitor C1, and a second capacitor C2;
the input module 101 is electrically connected to the forward scanning signal terminal U2D, the upper two-stage signal terminal STN (n-2), and the first node Q, and the input module 101 is configured to pull up the potential of the first node Q.
The pull-down control module 102 is electrically connected to the forward scanning signal terminal U2D, the lower two-stage clock signal terminal CK (n+2), the reverse scanning signal terminal D2U, the upper two-stage clock signal terminal CK (n-2), the first global signal terminal Gas1, the lower two-stage transmission signal terminal STN (n+2), the reference low-level signal terminal VGL, the first node Q, the second node P, and the third node K, and the pull-down control module 102 is configured to control the potential of the second node P.
The first output module 103 is electrically connected with the first node Q, the clock signal terminal CK (n) of the present stage, and the signal terminal STN of the present stage, and the first output module 103 is configured to output the signal of the present stage;
the partition control module 104 is electrically connected to the first control signal terminal GON, the first node Q, and the fourth node S, and the partition control module 104 is configured to control output of the current level scanning signal.
The second output module 105 is electrically connected to the fourth node S, the local clock signal terminal CK (n), and the local scan signal terminal Gout, and the second output module 105 is configured to output the local scan signal.
The pull-down module 106 is configured to pull down the potentials of the first node Q, the second node P, the current-stage transmission signal terminal STN, the current-stage scanning signal terminal Gout, and the reference low-level signal terminal VGL.
One end of the first capacitor C1 is electrically connected to the first node Q, and the other end of the first capacitor C1 is electrically connected to the reference low level signal terminal VGL.
One end of the second capacitor C2 is electrically connected to the second node P, and the other end of the second capacitor C2 is electrically connected to the reference low level signal terminal VGL.
The gate driving circuit provided by the application is characterized in that a first output module 103, a partition control module 104 and a second output module 105 are arranged in a gate driving unit, wherein the first output module 103 is used for outputting a current hierarchical transmission signal; the partition control module 104 is used for controlling the output of the current level scanning signal; the second output module 105 is configured to output the present stage scanning signal, and further control output of the present stage scanning signal on the basis of ensuring normal downloading of the stage scanning signal, so as to realize partition driving display, and facilitate improving display effect of the display panel.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of a first circuit of the gate driving unit provided in fig. 2. As shown in fig. 3, the embodiment of the present application provides a gate driving unit 100, where the gate driving unit 100 includes an input module 101, a pull-down control module 102, a first output module 103, a partition control module 104, a second output module 105, and a pull-down module 106;
specifically, the first output module 103 includes a first transistor T1 and a second transistor T2, where a first electrode of the first transistor T1 is electrically connected to the current stage clock signal terminal CK (n), and a second electrode of the first transistor T1 is electrically connected to the current stage signaling terminal STN; the grid electrode of the second transistor T2 is electrically connected with a reference high-level signal end VGH; the first electrode of the second transistor T2 is electrically connected to the first node Q, and the second electrode of the second transistor T2 is electrically connected to the gate of the first transistor T1.
Specifically, the partition control module 104 includes a third transistor T3, a gate of the third transistor T3 is electrically connected to the first control signal terminal GON, a first electrode of the third transistor T3 is electrically connected to the first node Q, and a second electrode of the third transistor T3 is electrically connected to the fourth node S.
Specifically, the second output module 105 includes a fifth transistor T5, where a gate of the fifth transistor T5 is electrically connected to the fourth node S, a first electrode of the fifth transistor T5 is electrically connected to the current stage clock signal terminal CK (n), and a second electrode of the fifth transistor T5 is electrically connected to the current stage scan signal terminal Gout.
One end of the first capacitor C1 is electrically connected with the first node Q, and the other end of the first capacitor C1 is electrically connected with the reference low-level signal end VGL; the first capacitor C1 is used for pulling down the potential of the first node Q in a non-signal output stage;
the input module 101 includes a seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the upper two-stage signal transmission terminal STN (n-2), a first electrode of the seventh transistor T7 is electrically connected to the forward scan signal terminal U2D, and a second electrode of the seventh transistor T7 is electrically connected to the first node Q.
The pull-down control module 102 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12, where a gate of the eighth transistor T8 is electrically connected to the forward scan signal terminal U2D, a first electrode of the eighth transistor T8 is electrically connected to the next two-stage clock signal terminal CK (n+2), and a second electrode of the eighth transistor T8 is electrically connected to the third node K; the grid electrode of the ninth transistor T9 is electrically connected with the reverse scanning signal end D2U, the first electrode of the ninth transistor T9 is electrically connected with the upper two-stage clock signal end CK (n-2), and the second electrode of the ninth transistor T9 is electrically connected with the third node K; the gate of the tenth transistor T10 is electrically connected to the third node K, the first electrode of the tenth transistor T10 is electrically connected to the first global signal terminal Gas1, and the second electrode of the tenth transistor T10 is electrically connected to the second node P; the grid electrode of the eleventh transistor T11 is electrically connected with the next two-stage transmission signal end STN (n+2), the first electrode of the eleventh transistor T11 is electrically connected with the reverse scanning signal end, and the second electrode of the eleventh transistor T11 is electrically connected with the first node Q; the gate of the twelfth transistor T12 is electrically connected to the first node Q, the first electrode of the twelfth transistor T12 is electrically connected to the second node P, and the second electrode of the twelfth transistor T12 is electrically connected to the reference low-level signal terminal VGL.
The pull-down module 106 includes a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15, wherein the gate of the thirteenth transistor T13, the gate of the fourteenth transistor T14, and the gate of the fifteenth transistor T15 are electrically connected to the second node P; a first electrode of the thirteenth transistor T13 is electrically connected to the first node Q; a first electrode of the fourteenth transistor T14 is electrically connected to the current stage signal terminal STN, and a first electrode of the fifteenth transistor T15 is electrically connected to the current stage scanning signal terminal Gout; the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the second electrode of the fifteenth transistor T15 are all electrically connected to the reference low level signal terminal VGL.
One end of the second capacitor C2 is electrically connected with the second node P, and the other end of the second capacitor C2 is electrically connected with the reference low-level signal end VGL; when the clock signal terminal CK (n) of the present stage changes from high level to low level, and at this time, since the second node P is high level, the thirteenth transistor T13 is in an on state, the output of the low level signal by the clock signal terminal CK (n) of the present stage will pull the second node P down to a certain extent, and due to the storage effect of the second capacitor C2, the second node P will decrease to low level in a straight line after a delay time when the output of the low level signal by the clock signal terminal CK (n) of the present stage.
Referring to fig. 4, fig. 4 is a gate according to an embodiment of the present applicationA first driving timing diagram of the pole driving circuit. As shown in fig. 4, the first control signal terminal GON corresponding to the 1 st to 3 n-th gate driving units inputs a high level signal, and the scan signal terminal Gout corresponding to the 1 st to 3 n-th gate driving units sequentially outputs the scan signal (G) 1 ,G 2 ,G n-1 ,G n... G 2n... G 3n ) The method comprises the steps of carrying out a first treatment on the surface of the The first control signal terminal GON corresponding to the 3n+1 to 4n gate driving units inputs a low level signal, and the present stage scan signal terminal Gout corresponding to the 3n+1 to 4n gate driving units outputs a present stage scan signal (G 3n+1... G 4n ) Is a low level signal.
Referring to fig. 5, fig. 5 is a schematic diagram of a second circuit of the gate driving unit provided in fig. 2. As shown in fig. 5, the embodiment of the present application provides a gate driving unit 200, where the gate driving unit 200 is different from the gate driving unit 100 in that the partition control module 104 in the gate driving unit 200 further includes a fourth transistor T4, a gate of the fourth transistor T4 is electrically connected to the second control signal terminal GOFF, a first electrode of the fourth transistor T4 is electrically connected to the reference low level signal terminal VGL, and a second electrode of the fourth transistor T4 is electrically connected to the fourth node S. This arrangement is advantageous in that the potential of the fourth node S is pulled down in time after the third transistor T3 is turned off, preventing erroneous output.
In this embodiment of the present application, the first control signal terminal GON is used for inputting a first control signal, the second control signal terminal GOFF is used for inputting a second control signal, and the potential of the first control signal is opposite to the potential of the second control signal. By the arrangement, the output of the scanning signal of the current stage can be controlled under the control of the first control signal, and when the first control signal is a low-level signal, the second control signal is high-level, the fourth transistor T4 is conducted, and the potential of the fourth node S can be pulled down in time.
In the embodiment of the present application, other structures in the gate driving unit 200 are the same as those in the gate driving unit 100, so that the description thereof is omitted here.
Referring to fig. 6a and 6b, fig. 6a is a schematic diagram showing a second driving timing diagram of a gate driving circuit according to an embodiment of the present applicationThe method comprises the steps of carrying out a first treatment on the surface of the Fig. 6b is a second driving timing diagram of the display panel according to the embodiment of the present application. As shown in fig. 6a, the first control signal terminal GON corresponding to the 1 st to nth stage gate driving units inputs a low level signal and the second control signal terminal GOFF inputs a high level signal, and the current stage scan signal terminal Gout corresponding to the 1 st to nth stage gate driving units outputs a current stage scan signal (G 1... G n ) Is a low level signal; the first control signal terminal GON corresponding to the n+1th to 4 n-th gate driving units inputs a high level signal and the second control signal terminal GOFF inputs a low level signal, and the scan signal terminal Gout corresponding to the n+1th to 4 n-th gate driving units sequentially outputs a high level scan signal (G) n+1... G 4n )。
As shown in fig. 6b, the first control signal terminal GON corresponding to the 1 st to 3 n-th gate driving units inputs a high level signal and the second control signal terminal GOFF inputs a low level signal, and the scanning signal terminal Gout corresponding to the 1 st to 3 n-th gate driving units sequentially outputs a high level scanning signal (G) 1... G 3n ) The method comprises the steps of carrying out a first treatment on the surface of the The first control signal terminal GON corresponding to the 3n+1 to 4n gate driving units inputs a low level signal and the second control signal terminal GOFF inputs a high level signal, and the present stage scan signal terminal Gout corresponding to the 3n+1 to 4n gate driving units outputs a present stage scan signal (G 3n+1... G 4n ) Is a low level signal.
Referring to fig. 7, fig. 7 is a schematic circuit diagram of a third circuit of the gate driving unit provided in fig. 2. As shown in fig. 7, the embodiment of the present application provides a gate driving unit 300, where the gate driving unit 300 is different from the gate driving unit 100/200 in that the second output module 105 in the gate driving unit 300 further includes a sixth transistor T6, the gate of the sixth transistor T6 and the first electrode of the sixth transistor T6 are electrically connected to the second global signal terminal Gas2, and the second electrode of the sixth transistor T6 is electrically connected to the current stage scanning signal terminal Gout.
In the embodiment of the present application, other structures of the display panel 300 are the same as those of the display panel 100/200, and thus are not described herein.
Referring to FIG. 8, FIG. 8 is the presentThe third driving timing chart of the gate driving circuit provided in the embodiment is applied. As shown in fig. 8, the first control signal terminal GON corresponding to the 1 st to nth stage gate driving units simultaneously inputs high level signals and the second control signal terminal GOFF inputs low level signals, and the scanning signal terminal Gout corresponding to the 1 st to nth stage gate driving units simultaneously outputs high level scanning signals (G 1... G n ) The current level scan signal (G 1... G n ) The output duration is equal to the scanning time of a row of pixel units; the first control signal terminal GON corresponding to the n+1th to 4 n-th gate driving units sequentially inputs high level signals and the second control signal terminal GOFF inputs low level signals, and the scan signal terminal Gout corresponding to the n+1th to 4 n-th gate driving units sequentially outputs high level scan signals (G) n+1... G 4n )。
Referring to fig. 9, fig. 9 is a fourth driving timing diagram of the gate driving circuit according to the embodiment of the present application. As shown in fig. 9, the driving timing of the gate driving circuit includes a precharge stage and an image display stage, in the precharge stage t1, the first control signal terminal GON corresponding to the 1 st to nth stage gate driving units simultaneously inputs a high level signal and the second control signal terminal GOFF inputs a low level signal, and the present stage scanning signal terminal Gout corresponding to the 1 st to nth stage gate driving units simultaneously outputs a present stage scanning signal (G 1... G n ) The current level scan signal (G 1... G n ) The duration of the output is equal to the scanning time of the pixel units of n rows.
In the image display stage t2, the first control signal terminal GON corresponding to the n+1th to 4 n-th gate driving units sequentially inputs high-level signals and the second control signal terminal GOFF inputs low-level signals, and the scanning signal terminal Gout corresponding to the n+1th to 4 n-th gate driving units sequentially outputs high-level scanning signals (G) n+1... G 4n )。
Referring to fig. 10, fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the disclosure. As shown in fig. 10, an embodiment of the present application provides a display panel 400 including the gate driving circuit 100/200/300 as described above. Specifically, the display panel 400 has a display area AA and a non-display area NA disposed around the display area AA;
the display area AA includes a plurality of pixel units P, a plurality of data lines D and a plurality of scan lines G, wherein the plurality of data lines D are perpendicularly crossed with the plurality of scan lines G, each pixel unit P is electrically connected with a data line D and a scan line G, the plurality of pixel units P electrically connected with the data line D form a pixel unit column, and the plurality of pixel units P electrically connected with the scan line G form a pixel unit row, wherein the data line D is used for inputting data signals to the pixel units P.
Referring to fig. 11, fig. 11 is a schematic diagram illustrating a partition of the display panel provided in fig. 10. As shown in fig. 11, the display area AA may include a plurality of sub-display areas a/B/C/D arranged in a direction close to the driving chip IC. The number and division of the sub-display areas can be adjusted according to the need of those skilled in the art, and the present application is not limited herein.
Specifically, the gate driving circuit provided by the application can realize the partition driving display of each sub-display area A/B/C/D, and can precharge according to different partitions, so that the charging bottleneck is improved, and further, higher resolution can be achieved.
In the gate driving circuit and the display panel provided in the embodiments of the present application, the first output module 103, the partition control module 104 and the second output module 105 are disposed in the gate driving unit, and the first output module 103 is configured to output the present level transmission signal; the partition control module 104 is used for controlling the output of the current level scanning signal; the second output module 105 is configured to output the present stage scanning signal, and further control output of the present stage scanning signal on the basis of ensuring normal downloading of the stage scanning signal, so as to realize partition driving display, and facilitate improving display effect of the display panel.
The foregoing has described in detail a gate driving circuit and a display panel provided in embodiments of the present application, and specific examples have been applied herein to illustrate the principles and implementations of the present application, where the foregoing examples are provided to assist in understanding the methods and core ideas of the present application; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the ideas of the present application, the contents of the present specification should not be construed as limiting the present application in summary.
Claims (10)
1. The grid driving circuit is characterized by comprising a grid driving unit which is arranged in a multistage cascade manner, wherein the grid driving unit comprises an input module, a pull-down control module, a first output module, a partition control module, a second output module and a pull-down module;
the input module is electrically connected with the forward scanning signal end, the upper two-stage transmission signal end and the first node, and is used for pulling up the potential of the first node;
the pull-down control module is electrically connected with the forward scanning signal end, the lower two-stage clock signal end, the reverse scanning signal end, the upper two-stage clock signal end, the first global signal end, the lower two-stage transmission signal end, the reference low-level signal end, the first node, the second node and the third node, and is used for controlling the potential of the second node;
the first output module is electrically connected with the first node, the current stage clock signal end and the current stage transmission signal end, and is used for outputting the current stage transmission signal;
the partition control module is electrically connected with the first control signal end, the first node and the fourth node, and is used for controlling the output of the current-stage scanning signal;
the second output module is electrically connected with the fourth node, the current stage clock signal end and the current stage scanning signal end, and is used for outputting the current stage scanning signal;
the pull-down module is used for pulling down the electric potentials of the first node, the current level transmission signal end and the current level scanning signal end.
2. The gate drive circuit of claim 1, wherein the first output module comprises a first transistor, a gate of the first transistor is electrically connected to the first node, a first electrode of the first transistor is electrically connected to the local clock signal terminal, and a second electrode of the first transistor is electrically connected to the local signaling signal terminal.
3. The gate drive circuit of claim 2, wherein the first output module further comprises a second transistor, a gate of the second transistor is electrically connected to a reference high signal terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the gate of the first transistor.
4. The gate driving circuit of claim 1, wherein the partition control module comprises a third transistor, a gate of the third transistor is electrically connected to the first control signal terminal, a first electrode of the third transistor is electrically connected to the first node, and a second electrode of the third transistor is electrically connected to a fourth node.
5. The gate drive circuit of claim 4, wherein the partition control module further comprises a fourth transistor, a gate of the fourth transistor is electrically connected to the second control signal terminal, a first electrode of the fourth transistor is electrically connected to the reference low level signal terminal, and a second electrode of the fourth transistor is electrically connected to the fourth node.
6. The gate driving circuit according to claim 5, wherein the first control signal terminal is used for inputting a first control signal, the second control signal terminal is used for inputting a second control signal, and a potential of the first control signal is opposite to a potential of the second control signal.
7. The gate driving circuit of claim 1, wherein the second output module comprises a fifth transistor, a gate of the fifth transistor is electrically connected to the fourth node, a first electrode of the fifth transistor is electrically connected to the current stage clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the current stage scan signal terminal.
8. The gate drive circuit of claim 7, wherein the second output module further comprises a sixth transistor, the gate of the sixth transistor and the first electrode of the sixth transistor are electrically connected to the second global signal terminal, and the second electrode of the sixth transistor is electrically connected to the current stage scan signal terminal.
9. The gate drive circuit of claim 1, wherein the gate drive unit further comprises: the device comprises a first capacitor, a second capacitor, an input module, a pull-down control module and a pull-down module;
one end of the first capacitor is electrically connected with the first node, and the other end of the first capacitor is electrically connected with the reference low-level signal end;
one end of the second capacitor is electrically connected with the second node, and the other end of the second capacitor is electrically connected with the reference low-level signal end;
the input module comprises a seventh transistor, the grid electrode of the seventh transistor is electrically connected with the upper two-stage signal transmission end, the first electrode of the seventh transistor is electrically connected with the forward scanning signal end, and the second electrode of the seventh transistor is electrically connected with the first node;
the pull-down control module comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, wherein the grid electrode of the eighth transistor is electrically connected with the forward scanning signal end, the first electrode of the eighth transistor is electrically connected with the lower two-stage clock signal end, and the second electrode of the eighth transistor is electrically connected with the third node; the grid electrode of the ninth transistor is electrically connected with the reverse scanning signal end, the first electrode of the ninth transistor is electrically connected with the upper two-stage clock signal end, and the second electrode of the ninth transistor is electrically connected with the third node; the grid electrode of the tenth transistor is electrically connected with the third node, the first electrode of the tenth transistor is electrically connected with the first global signal end, and the second electrode of the tenth transistor is electrically connected with the second node; the grid electrode of the eleventh transistor is electrically connected with the signal end of the next two-stage transmission, the first electrode of the eleventh transistor is electrically connected with the reverse scanning signal end, and the second electrode of the eleventh transistor is electrically connected with the first node; the grid electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the second node, and the second electrode of the twelfth transistor is electrically connected with the reference low-level signal end;
the pull-down module comprises a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, wherein the grid electrode of the thirteenth transistor, the grid electrode of the fourteenth transistor and the grid electrode of the fifteenth transistor are electrically connected with the second node; a first electrode of the thirteenth transistor is electrically connected to the first node; a first electrode of the fourteenth transistor is electrically connected with the current-stage signal transmission end, and a first electrode of the fifteenth transistor is electrically connected with the current-stage scanning signal end; the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor and the second electrode of the fifteenth transistor are all electrically connected to the reference low-level signal terminal.
10. A display panel comprising a gate driving circuit according to any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310346194.XA CN117524131A (en) | 2023-03-31 | 2023-03-31 | Gate driving circuit and display panel |
| PCT/CN2023/134007 WO2024198424A1 (en) | 2023-03-31 | 2023-11-24 | Gate driving circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310346194.XA CN117524131A (en) | 2023-03-31 | 2023-03-31 | Gate driving circuit and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN117524131A true CN117524131A (en) | 2024-02-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310346194.XA Pending CN117524131A (en) | 2023-03-31 | 2023-03-31 | Gate driving circuit and display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117524131A (en) |
| WO (1) | WO2024198424A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996367B (en) * | 2014-04-18 | 2017-01-25 | 京东方科技集团股份有限公司 | Shifting register, gate drive circuit and display device |
| CN107993620B (en) * | 2017-11-17 | 2020-01-10 | 武汉华星光电技术有限公司 | GOA circuit |
| CN108010498A (en) * | 2017-11-28 | 2018-05-08 | 武汉华星光电技术有限公司 | A kind of GOA circuits and liquid crystal panel, display device |
| CN113362771A (en) * | 2021-06-28 | 2021-09-07 | 武汉华星光电技术有限公司 | Gate drive circuit and display device |
| CN114170987B (en) * | 2021-12-09 | 2022-11-08 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
| CN114974114B (en) * | 2022-05-26 | 2024-10-25 | 合肥京东方卓印科技有限公司 | Display driving circuit, method, display panel, preparation method and device thereof |
-
2023
- 2023-03-31 CN CN202310346194.XA patent/CN117524131A/en active Pending
- 2023-11-24 WO PCT/CN2023/134007 patent/WO2024198424A1/en unknown
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| WO2024198424A1 (en) | 2024-10-03 |
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