CN117331873A - Method, system and storage medium for automatically distributing I2C address - Google Patents
Method, system and storage medium for automatically distributing I2C address Download PDFInfo
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- CN117331873A CN117331873A CN202311184055.8A CN202311184055A CN117331873A CN 117331873 A CN117331873 A CN 117331873A CN 202311184055 A CN202311184055 A CN 202311184055A CN 117331873 A CN117331873 A CN 117331873A
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- 238000003860 storage Methods 0.000 title claims description 6
- 230000006854 communication Effects 0.000 claims abstract description 24
- 238000004891 communication Methods 0.000 claims abstract description 23
- 230000004044 response Effects 0.000 claims abstract description 11
- 230000007246 mechanism Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 description 4
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- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
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- 238000009826 distribution Methods 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a method for automatically distributing I2C addresses, which comprises the following steps: a STATUS signal line is added on the I2C bus; initializing a host module, wherein a main control chip in the host module performs I2C interface initialization, and after the initialization is completed, begins to poll a STATUS signal on a bus; the slave device is initialized, connected into slave device, and starts to initialize, and after the slave device is initialized, the STATUS signal is pulled down; the interface is initialized, the main control chip initiates communication to the default address, the host searches the address table for the available address after the response is successful, and the new address is written into the I2C address register of the slave device through the I2C. The beneficial effects of the invention are as follows: the dynamic allocation mechanism of the I2C address can be realized by adding a STATUS signal on the bus, and the method has strong expansibility and high adaptability.
Description
Technical Field
The invention relates to the field of communication, in particular to a method and a system for automatically distributing I2C addresses.
Background
In a general application scenario, I2C is generally used for a master control chip to read data from a slave. The addresses of these slaves are in most cases configured with their I2C addresses by resistors configured at the time of hardware design. Sometimes, however, the slave is connected to the master in a manner that the small-sized card is externally connected. When in use, users access different numbers of boards according to the demands, and even dynamically increase or decrease. In this case, it is not practical to configure I2C addresses for the master of the board by hardware due to limitations in the production of small boards. Because it is not possible to produce one specific platelet for each I2C address. Meanwhile, if different burning firmware is instead brushed to realize that different slaves allocate different I2C addresses without hardware configuration, it is also impractical because it is impossible to brush one specific firmware for each I2C address.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a method for automatically distributing I2C addresses, which can realize a dynamic distribution mechanism of the I2C addresses by adding STATUS signals on a bus, and has strong expansibility and high adaptability.
The technical scheme adopted for solving the technical problems is as follows: a method of automatically assigning an I2C address, the method comprising:
a STATUS signal line is added on the I2C bus;
initializing a host module, wherein a main control chip in the host module performs I2C interface initialization, and after the initialization is completed, begins to poll a STATUS signal on a bus;
the slave device is initialized, connected into slave device, and starts to initialize, and after the slave device is initialized, the STATUS signal is pulled down;
the interface is initialized, the main control chip initiates communication to the default address, the host searches the address table for the available address after the response is successful, and the new address is written into the I2C address register of the slave device through the I2C.
In the above method, the host module initializes the I2C interface to a default address when initializing.
In the above method, the STATUS signal STATUS is high when the slave device is not connected to the master module.
In the above method, the slave device may be accessed only when the STATUS signal in the master module is at a high level.
In the above method, the slave module may initialize the I2C interface to a default address when initializing.
In the above method, the address sent by the host module matches with the address of the slave device, and the slave device replies in a reply bit.
A system for automatically assigning I2C addresses comprises a host module and a slave module, wherein the host module is connected with the slave module.
In the system, the host module and the slave module are both provided with I2C interfaces.
In the above system, the master control chip is disposed on the master module and the slave module.
A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the method of automatically assigning I2C addresses.
The beneficial effects of the invention are as follows: the dynamic allocation mechanism of the I2C address can be realized by adding a STATUS signal on the bus, and the method has strong expansibility and high adaptability.
Drawings
FIG. 1 is a flow chart of a method for automatically assigning I2C addresses according to the present invention.
FIG. 2 is a schematic diagram of a system for automatically assigning I2C addresses according to the present invention.
FIG. 3 is a schematic diagram of a system for automatically assigning I2C addresses according to the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
The conception, specific structure, and technical effects produced by the present invention will be clearly and completely described below with reference to the embodiments and the drawings to fully understand the objects, features, and effects of the present invention. It is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and that other embodiments obtained by those skilled in the art without inventive effort are within the scope of the present invention based on the embodiments of the present invention. In addition, all the coupling/connection relationships referred to in the patent are not direct connection of the single-finger members, but rather, it means that a better coupling structure can be formed by adding or subtracting coupling aids depending on the specific implementation. The technical features in the invention can be interactively combined on the premise of no contradiction and conflict.
Referring to fig. 1, the present invention discloses a method for automatically allocating an I2C address, specifically, the method includes:
a STATUS signal line is added on the bus;
initializing a host, initializing an I2C interface by a main control chip, and starting to poll a STATUS signal on a bus after the initialization is completed;
the slave is initialized, the slave is accessed, the slave starts to initialize, and the STATUS signal is pulled down after the slave is initialized;
the interface is initialized, the main control chip initiates communication to the default address, the host searches the address table for the available address after the response is successful, and the new address is written into the I2C address register of the slave through the I2C.
Inside the host there is an I2C address table containing addresses 0x10-0xf 0. Because a STATUS signal line is added on the bus, the dynamic allocation of the I2C address can be realized through the STATUS signal line.
When the host is initialized, the slave will default its own address to 0xF1. After the main board in the whole machine is electrified, the whole machine starts to enter a host initialization stage, and firstly, the main control chip initializes the I2C interface to enable the I2C interface to be initialized to a default value; then the master control chip starts to poll the STATUS signal on the bus, and the slave is not connected to the master at this time, so the STATUS signal is high, and when the STATUS signal is high, the slave can be connected to the master.
After the slave is connected to the host, the whole machine starts to enter the slave initialization stage, because after the slave is connected to the host, the slave can be electrified from the host interface, and then the slave starts to initialize, and is in the slave initialization stage. In the slave initialization phase, the STATUS signal is also high. When slave initialization is complete, the STATUS signal is pulled low, which is low.
When the STATUS signal is low level, the whole machine enters an interface initialization stage, and when the interface is initialized, the main control chip initiates communication to a default address (namely 0xF 1) of the slave machine through I2C and waits for response. When the response is successful, the host searches the address table for an available address. The interface initialization is then completed by writing a new address to the I2C address register 0xAD of the device through I2C. The I2C bus is a two-wire half duplex serial bus, divided into a data line (SDA) and a clock line (SCL). The communication time division is divided into a host slave, after the host sends a start signal, a 7-bit address and a 1-bit read-write bit are sent in eight clock cycles (here, the address in the form of 7 bits is commonly used), and then the host waits for whether the slave responds (ACK) or not. The slave continuously detects whether the address sent by the host matches with the slave or not at the stage, and responds if the address matches with the slave. Because the addresses of the slave devices in the scheme are default values which are agreed when the slave devices are just inserted, when the host detects that a new device is accessed through a STATUS signal, communication is initiated according to the default addresses. At this point, the slave chipcards that have been assigned addresses will not answer, because their addresses are not default addresses, and therefore only the newly accessed slave chipcards will answer. After the response, the host continues to configure the small card according to the address to assign a new I2C address to the new small card. After the round of communication is finished, the address of the small card is changed from the original default address to the newly allocated address.
After the complete machine completes the initialization of the host, the initialization of the slave and the initialization of the interface, the host also periodically polls the slave devices which complete the initialization, if the slave devices are lost, the addresses of the slave devices become unused, and the new devices can reuse the addresses. According to the characteristics of the I2C communication, after the host sends out an address, if the address matches with the address of the slave, the slave device responds in a response bit. The host periodically traverses the addresses already allocated here and should normally receive a response. If one address does not receive the response, the slave corresponding to the address is abnormal or not in place. The address is set to unused if no reply is received by the host, and can be used when a new slave device is accessed.
The present solution is illustrated by some specific examples below:
in some embodiments, (1) assume that the host has four interfaces according to this scheme, and when the host is powered on and started, the host starts to complete initialization, and after the initialization of the host is completed, each interface is not accessed from the slave device.
(2) Then the user accesses the first slave device, and the slave device obtains the power supply through the interface to initialize itself.
(3) After initialization, the STATUS signal is pulled down, and at the moment, the host senses the STATUS signal change and initiates communication on the I2C bus. The address of the communication is the default address 0xF1 (the value is determined according to the requirement when the communication is actually applied).
(4) The address of the slave device is also a default address, so that the slave device can respond to the communication initiated by the host.
(5) The host starts writing to the register address and the value that needs to be written to that register. The register address is the address register of the slave small card. The written value is the new I2C address allocated by the master to the slave.
(6) And after the communication is finished, the slave equipment changes the address of the slave equipment into the address allocated by the communication host, and releases the STATUS signal.
In another embodiment:
(1) at this point the host has access to and has assigned a new address if a slave device.
(2) Then the user accesses a slave device on the basis of the above, at this time, the slave device obtains a power supply through the interface to initialize itself, and the slave device completes initialization.
(3) After initialization is completed, the newly accessed slave device pulls down the STATUS signal, at this time, the host senses the STATUS signal change, the STATUS signal changes from high level to low level, the host initiates communication on the I2C bus, and the communication address is a default address which is agreed.
(4) The address of the new slave device is the default address and thus will respond to the current host initiated communication, whereas the previous slave device has been assigned the new address and thus will not respond to the current communication.
(5) The host writes the register address and corresponding value.
(6) And after the communication is finished, the new slave equipment changes the self address into the address allocated by the communication, and releases the STATUS signal.
(7) And repeating the process all the time, and finally completing the allocation of the I2C addresses to all the accessed slave devices.
The scheme also discloses a system for automatically distributing the I2C address, in particular to the system which comprises a host module 10 and a slave module 20, wherein the host module 10 is connected with the slave module 20 to complete the distribution of the I2C address of the slave equipment accessed in the slave module 20.
Specifically, a main board is disposed in the host module 10, a main control chip is disposed on the main board, and GND, VCC, I c_scl, i2c_sda and STATUS pins are disposed on the main control chip. Wherein GND is a ground pin, VCC is a power pin, and the slave equipment obtains a required power supply from the main board through the VCC pin.
I2c_scl is serial clock line SCL, mainly responsible for generating synchronization pulse wave; i2c_sda is a serial data line responsible for transmitting serial data between devices.
The I2C bus is a shared bus system, and thus a plurality of I2C devices can be connected to the system. Devices connected to the bus in the I2C may act as both master and slave devices. The master is responsible for controlling the communication, sending data and generating the required synchronization clock by initializing/terminating the data transfer, and the slave waits for a command from the master and responds to the receipt of the command. And the synchronous clock signal can only be generated by the master device. When the bus is idle, the SDA and SCL are in high level state, when the host is about to communicate with a certain slave, a start condition is sent first, then the slave address and read-write control bit are sent, and when the data transmission is finished, the host sends a stop condition. Each byte transmitted is 8 bits, with the high order preceding and the low order following. ( SDA is a bidirectional data line and SCL is a clock line SCL. The data is specially sent on the I2C bus, the most significant bit is sent first, the host sends out a starting signal, the SDA jumps from high level to low level during SCL high level, and then the host sends out one byte of data. After the data transmission is completed, the host sends out a stop signal, and the SDA jumps from a low level to a high level during the high level of the SCL. )
When the SCL is high, the SDA jumps from high to low to start transmitting data, and the level on the SDA is allowed to change only during the period when the SCL line is low in the data transmission process. The first byte sent by the host is the slave address, the upper 7 bits represent the address, the lowest bit is R/W read-write control bit, 1 represents the read operation, and 0 represents the write operation. Response signal-every time one byte of data is transferred, the receiver needs to reply one ACK (acknowledge). And sending the ACK by the slave when writing data, and sending the ACK by the host when reading data. When the host reads the last byte, a NACK may be sent followed by an end of credit. The data, which is 8 bits each, may be sent after the slave address is sent, depending on the slave, and then starts to transmit data, and the number of bytes of the data is not limited. After the start signal, both SDA and SCL are first low, SDA is first high when data is to be transmitted, and then SCL jumps high again before data transmission can take place. Repeating the start signal, wherein the host computer can transmit data with different slaves or can send a start signal when switching read-write operation is needed in one communication process. And when the SCL is high, the SDA jumps from low level to high level to finish transmitting data.
Wherein i2c_scl requires a configuration pull-up of the signal in the master module 10 and no pull-up in the slave module 20. The i2c_sda also requires that the signal be configured to be pulled up in the master module 10 and not in the slave module 20.
STATUS is a STATUS signal, and the main control chip in the host module 10 senses the STATUS through the signal, and then the signal is pulled up weakly, so that the host module 10 is in an input mode. The slave module pulls down the signal indicating that access permission is waiting when the slave device first accesses, and then releases the signal when the I2C address is allocated.
A plurality of I2C interfaces are provided on the host module 10, wherein each I2C interface is provided with the above GND, VCC, I c_scl, i2c_sda, and STATUS pins, through which the slave device is connected to the host module 10.
The slave module 20 is provided with slave equipment, a main control chip and an I2C interface are also arranged in the slave equipment, and the slave equipment is connected with the host module 10 through the I2C interface; the slave module 20 is further provided with an LED lamp, the LED lamp is connected with a main control chip in the slave module 20, and the distribution state of the I2C address can be displayed through the LED lamp.
The present solution also discloses a computer readable storage medium for automatically assigning an I2C address, the computer readable storage medium storing computer executable instructions for causing a computer to perform a method as described for automatically assigning an I2C address.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.
Claims (10)
1. A method for automatically assigning an I2C address, the method comprising:
a STATUS signal line is added on the I2C bus;
initializing a host module, wherein a main control chip in the host module performs I2C interface initialization, and after the initialization is completed, begins to poll a STATUS signal on a bus;
the slave device is initialized, connected into slave device, and starts to initialize, and after the slave device is initialized, the STATUS signal is pulled down;
the interface is initialized, the main control chip initiates communication to the default address, the host searches the address table for the available address after the response is successful, and the new address is written into the I2C address register of the slave device through the I2C.
2. The method of claim 1, wherein the host module initializes the I2C interface to a default address.
3. The method of claim 1, wherein the STATUS signal is high when no slave device is connected to the host module.
4. A method of automatically assigning I2C addresses according to claim 3, wherein the slave device is only accessible when the STATUS signal in the master module is high.
5. The method of claim 1, wherein the slave module initializes the I2C interface to a default address.
6. The method of claim 1, wherein the address from the host module matches the address of the slave device, and the slave device responds in a reply bit.
7. A system for automatically assigning an I2C address, the system comprising a host module and a slave module, the host module being connected to the slave module.
8. The system for automatically assigning I2C addresses of claim 7, wherein said master module and said slave module are each provided with an I2C interface.
9. The system for automatically assigning I2C addresses of claim 7, wherein said master and slave modules are each provided with a master chip.
10. A computer readable storage medium storing computer executable instructions for causing a computer to perform the method of automatically assigning I2C addresses as claimed in any one of claims 1 to 6.
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| CN202311184055.8A CN117331873A (en) | 2023-09-12 | 2023-09-12 | Method, system and storage medium for automatically distributing I2C address |
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| CN202311184055.8A CN117331873A (en) | 2023-09-12 | 2023-09-12 | Method, system and storage medium for automatically distributing I2C address |
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