CN117337419A

CN117337419A - DDR subsystem dynamic power management using statistical control

Info

Publication number: CN117337419A
Application number: CN202180098371.6A
Authority: CN
Inventors: 骆浩斌
Original assignee: Zeku Technology Shanghai Corp Ltd
Current assignee: Weiguang Co ltd
Priority date: 2021-05-21
Filing date: 2021-05-21
Publication date: 2024-01-02
Also published as: WO2022245371A1

Abstract

New tools and techniques are provided for dynamic power management using statistical control. A system includes a Double Data Rate (DDR) physical interface (physical interface, PHY) and a memory controller. Based on the power and latency characteristics of the individual low power modes, the memory controller may identify the low power modes that meet the aggregate system latency requirements. The memory controller may determine that the time slot is idle to ensure a minimum probability ρ of achieving power savings by entering a low power mode ₀ . For statistical assumption ρ.gtoreq.ρ ₀ A statistical check of the low power mode is performed, where ρ is the potential probability that the slot is idle. The low power mode may be entered based on the results of the statistical test.

Description

DDR subsystem dynamic power management using statistical control

Cross Reference to Related Applications

Portions of the application of this patent document contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office patent files or patent records, but otherwise reserves all copyright rights whatsoever.

Technical Field

The present disclosure relates generally to methods, systems, and apparatus for power management of dynamic random access memory (dynamic random access memory, DRAM), and more particularly to methods, systems, and apparatus for power management of DRAM subsystems using statistical control.

Background

As power usage and efficiency of mobile devices become more important, modern dynamic random access memory (dynamic random access memory, DRAM) devices are increasingly optimized for use in mobile environments. Low Power DRAM (LPDRAM) devices, such as Low Power Double Data Rate (LPDDR) Synchronous DRAM (SDRAM), have been developed to handle power management and control schemes for memory array power consumption. However, the problem of inefficiency and power consumption bottlenecks remains with DDR subsystems that control access to DRAM devices, including, for example, DDR memory controllers and DDR physical interfaces (PHYs).

Methods, systems, and apparatus for dynamic power management for DDR subsystems are thus provided.

Disclosure of Invention

New tools and techniques are provided for dynamic power management using statistical control. A system includes a Double Data Rate (DDR) physical interface (physical interface, PHY) and a memory controller. Based on the power and latency characteristics of the individual low power modes, the memory controller may identify the low power modes that meet the aggregate system latency requirements. The memory controller may determine a minimum probability ρ that the slot is idle ₀ To ensure energy savings by entering a low power mode. For statistical assumption ρ.gtoreq.ρ ₀ A statistical check of the low power mode is performed, where ρ is the potential probability that the slot is idle. The low power mode may be entered based on the results of the statistical test.

According to an embodiment, the present invention provides a method. The method includes obtaining, by a storage controller, aggregate system latency requirements of a storage system, the storage system including the storage controller. The method further includes determining, by the memory controller, a power characteristic and a delay characteristic of a low power mode of the memory system,wherein the power characteristic comprises power consumption in the low power mode and idle active power consumption, and wherein the delay characteristic comprises a total delay to enter and exit the low power mode. The method further includes determining, by the memory controller, whether the total latency of the low power mode is less than or equal to an aggregate system latency requirement. The method further includes, in response to determining that the total latency of the low power mode is less than or equal to the aggregate system latency requirement, determining ρ by the memory controller ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy savings is achieved by entering a low power mode. The method also includes, for statistical assumptions ρ+.ρ ₀ A statistical check of the low power mode is performed by the memory controller, where ρ is associated with the probability that the slot is idle. The method further includes causing, by the memory controller, the memory system to enter a low power mode based on a result of the statistical test.

According to another embodiment, the invention provides an apparatus comprising a processor. The apparatus also includes a non-transitory computer readable medium in communication with the processor. Encoded in the non-transitory computer-readable medium is a set of instructions executable by the processor to: acquiring an aggregate system delay requirement of a storage system; determining a power characteristic and a delay characteristic of a low power mode of the storage system, wherein the power characteristic comprises power consumption in the low power mode and power required to leave the low power mode, and wherein the delay characteristic comprises a total delay to enter and exit the low power mode; determining whether the total delay of the low power mode is less than or equal to an aggregate system delay requirement; in response to determining that the total delay of the low power mode is less than or equal to the aggregate system delay requirement: determining ρ based on power characteristics ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy saving by entering a low power mode; for statistical assumption ρ.gtoreq.ρ ₀ Performing a statistical test of the low power mode, wherein ρ is associated with a probability that the slot is idle; the storage system is caused to enter a low power mode based on the results of the statistical test.

According to yet another embodiment, the present invention provides a storage subsystem comprisingA double data rate physical interface (DDR PHY) to communicate with the memory device. The memory subsystem also includes a memory controller coupled to the DDR PHY. The storage controller includes a processor and a non-transitory computer readable medium in communication with the processor having encoded therein a set of instructions executable by the processor to: acquiring an aggregate system delay requirement of the storage system through the storage controller, wherein the aggregate system delay requirement is the minimum delay required by all clients of the storage system; determining, by a storage controller, a power characteristic and a delay characteristic of a low power mode of the storage system, wherein the power characteristic comprises power consumption in the low power mode and power required to leave the low power mode, and wherein the delay characteristic comprises a total delay to enter and exit the low power mode; determining, by the memory controller, whether the total latency of the low power mode is less than or equal to an aggregate system latency requirement; determining ρ based on the power characteristics by the memory controller in response to determining that the total delay of the low power mode is less than or equal to the aggregate system delay requirement ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy saving by entering a low power mode; for statistical assumption ρ.gtoreq.ρ ₀ Performing, by the memory controller, a statistical check of the low power mode, wherein ρ is associated with a probability that the slot is idle; based on the results of the statistical test, the storage system is caused to enter a low power mode by the storage controller. It is understood that other embodiments exist.

Drawings

A further understanding of the nature and advantages of certain embodiments may be realized by reference to the remaining description and the drawings wherein like reference numerals are used to describe similar components. In some examples, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to a sub-label, it is intended to describe all such multiple similar components.

FIG. 1 is a schematic diagram of a storage system for dynamic power management using statistical control, in accordance with various embodiments;

FIG. 2 is a schematic diagram of a memory controller for dynamic power management using statistical control, in accordance with various embodiments;

FIG. 3 is a schematic diagram of Low Power Mode (LPM) control logic for implementing dynamic power management using statistical control, in accordance with various embodiments;

FIG. 4 is a schematic diagram of a double data rate physical interface (DDR PHY) for dynamic power management using statistical control, in accordance with various embodiments;

FIG. 5 is a flow chart of a method of dynamic power management using a statistically controlled Double Data Rate (DDR) subsystem, in accordance with various embodiments;

FIG. 6 is a flow chart of a statistical verification method for dynamic power management of DDR subsystems, in accordance with various embodiments.

Detailed Description

Various embodiments provide tools and techniques for dynamic power management using statistical control.

In one aspect, a method for dynamic power management using statistical control is provided. The method includes obtaining, by a storage controller, aggregate system latency requirements of a storage system. The method may continue by the memory controller determining a power characteristic and a latency characteristic of a low power mode of the memory system, wherein the power characteristic includes power consumption in the low power mode and power required to leave the low power mode, and wherein the latency characteristic includes a total latency of entering and exiting the low power mode. The method further includes determining, by the memory controller, whether the total latency of the low power mode is less than or equal to an aggregate system latency requirement. In response to determining that the total latency of the low power mode is less than or equal to the aggregate system latency requirement, the method may further include determining ρ by the memory controller ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy saving by entering a low power mode, and for statistical assumptions ρ+.ρ ₀ A statistical test of the low power mode is performed by the memory controller. For example, ρ is the potential probability that the slot is idle, and ρ itself is not related to the number of samples. The statistical test is used to estimate whether the probability exceeds the calculated ρ for each Low Power Mode (LPM) ₀ 。

The method may continue by causing, by the memory controller, the memory system to enter a low power mode based on the results of the statistical test.

In some examples, the statistical test may be a Z test (Z-test), and wherein performing the statistical test includes performing the Z test. Performing the Z-check may include performing a Z-check based on ρ and ρ ₀ A Z-value (Z-score) of the low power mode is determined, and a Z-value threshold that meets the confidence level threshold is determined based on the confidence level threshold. The result of the statistical test may be an indication of whether the Z value is greater than or equal to a Z value threshold, wherein the low power mode is entered in response to determining that the Z value is greater than or equal to the Z value threshold.

In another example, determining the Z-value may further include determining a total number n of samples to collect based on the confidence level threshold and initializing a shift register of length n. The method may further include, at a sampling rate of 1/t _s Obtaining a sample, wherein t _s Is the duration of the total delay set to the low power mode (e.g., the delay to enter and exit the low power mode), where a sample is an indication of whether one or more lines of the memory system are idle, and every time duration t _s Writing a value of the sample to a shift register, the value indicating whether one or more lines of the memory system are idle at a current time, wherein the value is at intervals of time t _s Is updated and written to the shift register until the shift register is full, wherein the values in the shift register are shifted such that the oldest value in the shift register passes every time period t _s Is rewritten. The method may continue by determining a total number of samples of the most recent n samples for which one or more lines of the storage system are idle, where ρ is a potential probability that the slot is idle.

In some examples, the method may further include monitoring activity of one or more lines of a Double Data Rate (DDR) Physical (PHY) interface bus, and determining an activity state of the one or more lines of the DDR PHY interface bus, wherein the activity state indicates whether the one or more lines are idle. In some examples, entering the low power mode further includes causing, by the memory controller, at least one of the DDR PHY interface and the memory controller to enter the low power mode.

In another aspect, an apparatus for dynamic power management using statistical control is provided. The apparatus may include a processor and a non-transitory computer readable medium in communication with the processor having encoded therein a set of instructions executable by the processor to perform various functions. The set of instructions may be executable by the processor to obtain aggregate system latency requirements of the storage system and determine a power characteristic and a latency characteristic of a low power mode of the storage system, wherein the power characteristic comprises power consumption in the low power mode and power required to leave the low power mode, and wherein the latency characteristic comprises a total latency of entering and exiting the low power mode. Based on the above, it may be determined whether the total delay of the low power mode is less than or equal to the aggregate system delay requirement. Responsive to determining that the total delay of the low power mode is less than or equal to the aggregate system delay requirement, ρ may be determined based on the power characteristics ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy savings is achieved by entering a low power mode. The instructions may also be executed to determine, for statistical assumptions ρ+.ρ ₀ A statistical test of the low power mode is performed, wherein p is associated with a potential probability that the slot is idle, and the memory system is caused to enter the low power mode based on a result of the statistical test.

In some examples, the statistical test may be a Z test. To perform the Z-check, the instruction set may also be executable by the processor to determine a Z-value for the low power mode based on ρ and ρ0, and to determine a Z-value threshold that meets the confidence level threshold based on the confidence level threshold. The result of the statistical test may be an indication of whether the Z value is greater than or equal to a Z value threshold, wherein the low power mode is entered in response to determining that the Z value is greater than or equal to the Z value threshold.

In other examples, the set of instructions may be further executable by the processor to determine a total number n of samples to collect based on a confidence level threshold. Based on the above determination, the processor may also initialize a shift register of length n at a sampling rate of 1/t _s Obtaining a sample, wherein t _s Is the duration of the total delay set to low power mode, whichIn which the samples are an indication of whether one or more lines of the storage system are free, and every time period t _s Writing a value of the sample to a shift register, the value indicating whether one or more lines of the memory system are idle at a current time, wherein the value is at intervals of time t _s Is updated and written to the shift register until the shift register is full, wherein the values in the shift register are shifted such that the oldest value in the shift register passes every time period t _s Is rewritten. A total number of samples of the most recent n samples for which one or more lines of the storage system are idle may be determined, where ρ is a potential probability that the slot is idle.

In some examples, the set of instructions may be further executable by the processor to monitor activity of one or more lines of the DDR PHY interface bus and determine an activity state of the one or more lines of the DDR PHY interface bus, wherein the activity state indicates whether the one or more lines are idle.

In yet another aspect, a system for dynamic power management using statistical control is provided. The system includes a double data rate physical interface (DDR PHY) in communication with the memory device, and a memory controller coupled to the DDR PHY. The memory controller may also include a processor and a non-transitory computer-readable medium in communication with the processor having encoded therein a set of instructions executable by the processor to perform various functions. For example, the set of instructions may be executable by a processor to obtain, by a storage controller, an aggregate system latency requirement of the storage system, wherein the aggregate system latency requirement is a minimum latency required by all clients of the storage system. The instructions are further executable by the processor to determine, by the memory controller, a power characteristic and a latency characteristic of a low power mode of the memory system, wherein the power characteristic includes power consumption in the low power mode and power required to leave the low power mode, and wherein the latency characteristic includes a total latency of entering and exiting the low power mode. Based on the above, it may be determined by the memory controller whether the total latency of the low power mode is less than or equal to the aggregate system latency requirement. In response to determining that the total delay of the low power mode is less than or equal to the aggregate system Delay requirements, ρ may be determined by the memory controller based on the power characteristics ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy savings is achieved by entering a low power mode. The instructions may also be executable by the processor to, for statistical assumptions ρ+.ρ ₀ A statistical test of the low power mode is performed by the memory controller, and the memory system is caused to enter the low power mode by the memory controller based on a result of the statistical test.

In some examples, the statistical test may be a Z test. To perform the Z-check, the instruction set may also be executable by the processor to determine a Z-value for the low power mode based on ρ and ρ0, and to determine a Z-value threshold that meets the confidence level threshold based on the confidence level threshold. The result of the statistical test may be an indication of whether the Z value is greater than or equal to a Z value threshold, wherein the low power mode is entered in response to determining that the Z value is greater than or equal to the Z value threshold. In some examples, performing the Z-check may further include determining, by the memory controller, a Z-value for the low power mode based on ρ and ρ0, and determining, by the memory controller, a Z-value threshold that meets the confidence level threshold based on the confidence level threshold. The result of the statistical test may be an indication of whether the Z value is greater than or equal to a Z value threshold, wherein the low power mode is entered in response to determining that the Z value is greater than or equal to the Z value threshold.

In some examples, the instructions may also be executable by the processor to determine a total number n of samples to collect based on a confidence level threshold by the memory controller, initialize a shift register of length n by the memory controller, and sample rate 1/t by the DDR PHY _s Obtaining a sample, wherein t _s Is the duration of the total delay set to the low power mode, where a sample is an indication of whether one or more lines of the storage system are idle. The instructions may also be executable to cause the memory controller to perform operations for every time period t _s Writing a value of the sample to a shift register, the value indicating whether one or more lines of the memory system are idle at a current time, wherein the value is at intervals of time t _s Is updated and written to the shift register until the shift register is full, wherein the values within the shift register are shifted such thatEvery time a time period t elapses for the oldest value in the register _s Is rewritten. A total number of samples of the most recent n samples for which one or more lines of the storage system are idle may be determined, where ρ is associated with a probability that the slot is idle.

In other examples, the instructions may also be executable to monitor, by the memory controller, activity of one or more lines of a DDR PHY interface (DDR PHY interface, DFI) bus, and determine, by the memory controller, an activity state of the one or more lines of the DFI bus, wherein the activity state indicates whether the one or more lines of the DFI bus are idle. In still other examples, causing, by the memory controller, the memory system to enter the low power mode may further include causing, by the memory controller, at least one of the DDR PHY and the memory controller to enter the low power mode.

The various aspects and features of some embodiments are summarized above, and some embodiments are shown in more detail below to enable those skilled in the art to practice them. The depicted examples are meant to be examples only, and should not be taken as limiting the scope of the invention.

In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that other embodiments may be practiced without these specific details. In other instances, some structures and devices are shown in block diagram form. While various features are described herein as being ascribed to different embodiments, it will be appreciated that features described for one embodiment may be incorporated with other embodiments as well. Likewise, on the other hand, one or more features of any embodiment should not be considered essential to every embodiment of the present application, and other embodiments of the present application may omit these features.

Unless otherwise indicated, all numbers used herein to describe quantities, dimensions, and other numbers are to be understood as being modified by the term "about" in all instances. In this application, the use of the terms "and" or "means" and/or "unless specifically indicated otherwise, all the singular is intended to include the plural as well. Furthermore, the use of the term "including" in various expressions should be understood as non-exclusive. Also, unless explicitly stated otherwise, terms such as "element" or "component" encompass elements and components comprising one unit as well as elements and components comprising a plurality of units.

Various embodiments are described herein, including software products and computer-implemented methods, that represent tangible, specific improvements to the art, including but not limited to power management of storage systems. In other aspects, some embodiments can improve the functionality of the storage device itself through more efficient LPM management techniques.

If all of the abstract concepts are presented in various embodiments, these concepts may be implemented by a device, software, system, and method (e.g., steps or operations) having novel functionality, such as using a statistical control framework to dynamically manage power modes of storage devices and/or storage subsystems, as described herein.

FIG. 1 is a schematic diagram of a storage system 100 for dynamic power management using statistical control, in accordance with various embodiments. The system 100 includes a memory device 120 and a DDR subsystem 145. The DDR subsystem 145 includes a memory controller 105, a DDR physical interface (PHY) 115, and a clock generator 135, the memory controller 105 further includes an LPM control 110. Memory device 120 includes a memory array 125, a clock input circuit 130, an address command input circuit 135, and an input/output (I/O) circuit 140. It should be noted that fig. 1 schematically illustrates various components of a storage system 100, and that modifications to the storage system 100 are possible in accordance with various embodiments.

DDR subsystem 145 may include a storage subsystem that enables a host device (e.g., one or more processing cores of a system on chip (SoC), processor, or other integrated circuit (integrated circuit, IC)) to communicate with storage device 120. Accordingly, in some embodiments, DDR subsystem 145 includes DDR controller 105 and DDR PHY 115. In other embodiments, the DDR subsystem may include a clock generator 135. The memory controller 105 may also include an LPM control block 110. The memory controller 105 may be coupled to a DDR PHY 115, the DDR PHY 115 being a physical interface between the memory controller 105 and the memory device 120. Thus, DDR PHY 115 may, in turn, be coupled to memory device 120. The clock generator 135 may be coupled to the memory controller 105 and the DDR PHY 115.

According to the illustration, memory device 120 may include a clock input circuit 130, an address command input circuit 135, and an I/O circuit 140, address command input circuit 135 and I/O circuit 140 may also be coupled to memory array 125. In some embodiments, DDR PHY 115 may be coupled to one or more of clock input circuit 130, address command input circuit 135, and I/O circuit 140 via one or more corresponding buses. In some examples, one or more respective buses may collectively be referred to as a portion of a DFI bus, communicating via a DFI protocol as known to those skilled in the art. The clock input circuit 130, address command input circuit 135, and I/O circuit 140 may be used to control access to the memory array 125 by decoding command and address information (e.g., row and column address signals) and controlling the data flow to and from the DDR PHY 115.

[1] In various embodiments, storage device 120 may comprise a Synchronous Dynamic Random Access Memory (SDRAM) device. In some examples, SDRAM devices may include, but are not limited to, low power double data rate (low power doubledata rate, LPDDR) devices, such as LPDDR2, LPDDR3, LPDDR4x, and LPDDR5. Memory device 120 may be used to receive signals from memory controller 105 through DDR subsystem 145. The memory device 120 may thus be used to receive various command, address information, and control signals from the DDR PHY 115 of the DDR subsystem 145. The memory device 120 may also be used to receive data from the DDR subsystem 145 to be written to the memory array 125 and to send data to the DDR subsystem 145 to be used by the host device. Signals input from DDR PHY 115 may include, for example, clock signals (CK), clock enable (CKE) received via control lines and/or clock lines, various commands and addresses on one or more command/address (C/A) lines (e.g., a C/A bus), and data signals (DQ, DQS, DQM) on various data lines. The memory array 125 may thus be an array of memory cells, which may include, for example, volatile memory cells (e.g., dynamic random-access memory (DRAM) memory cells, low-power DRAM (low-power DRAM memory) memory cells, and static random-access memory (SRAM) memory cells), nonvolatile memory cells (e.g., flash memory cells), or other types of memory cells.

Thus, in various embodiments, DDR subsystem 145 may be used to enable memory controller 105 to communicate with memory device 120, as well as enable memory controller 105 to send data to memory array 125 and receive data from memory array 125. The memory controller 105 is a dedicated digital circuit that manages data written to the memory device 120 and data read from the memory device 120. The memory controller 105 also provides control signals and other commands that control the operation of the memory device 120, including operation at various LPMs. The LPM of the DRAM may include, for example, but not limited to, standby and fast low power states, light sleep and deep sleep states, power-down states (including precharge power down and deep power down), and self-refresh modes (including partial array self-refresh, temperature compensated self-refresh, and other self-refresh modes). Thus, memory controller 105 may be used to send commands to place memory device 120 in various DRAM LPMs.

In some embodiments, the memory controller 105 may be a dedicated memory controller 105 external to a host processor or SoC. Alternatively, in some embodiments, the memory controller 105 may be an on-chip/on-chip memory controller (e.g., an integrated memory controller). An example of the memory controller 105 is described in more detail below with reference to FIG. 2. In some embodiments, the storage controller 105 may receive commands and requests (read and write) for data from a host device. Memory controller 105 may also be used to receive a clock signal from clock generator 135. The clock generator 135 may also provide a clock signal to the DDR PHY 115. Accordingly, the clock generator 135 may provide clock signals to the memory controller 105 and the DDR PHY 115 for use as various internal clock signals.

The memory controller 105 may then process these commands to be sent to the DDR PHY 115. In some embodiments, the output of the memory controller to the DDR PHY 115 may be transmitted through a DFI, e.g., using a DFI protocol. The DFI may include lines for transmitting clock signals (e.g., CK, CKE), command/address information (C/a), and data signals (DQ, DQS, DQM). In other embodiments, the DFI may also include a low-power interface (LPI), through which the memory controller 105 may transmit commands and control signals (e.g., commands to enter/exit the LPM) that control the operation of the DDR PHY 115 to the DDR PHY 115. Memory controller 105 is described in more detail below with reference to FIG. 2, and DDR PHY 115 is described in more detail below with reference to FIG. 4.

Thus, in various embodiments, similar to memory device 120, DDR subsystem 145 may also include one or more LPMs. The LPM of DDR subsystem 145 may include, for example, but is not limited to, a standby state, a sleep state, and a power-off state. In each of the various LPM modes of DDR subsystem 145, different approaches may be used to reduce the power consumption of the various components of DDR subsystem 145. For example, the LPM may cause some components, such as delay-locked loop (DLL) and phase-locked loop (PLL), to perform power gating and/or clock gating. Thus, power gating includes blocking (e.g., shutting down, blocking, or disconnecting) a power supply (e.g., a voltage supply) of one or more components and/or portions of circuitry of DDR PHY 115 and/or memory controller 105. Clock gating may refer to the process of blocking clock signals provided to DDR PHY 115 and/or memory controller 105.

Accordingly, the memory controller 105 may be used to manage the power used by the DDR subsystem 145 by entering and exiting the LPM. In some embodiments, the memory controller 100 may also include an LPM control 110. For example, the LPM control 110 may include logic implemented in hardware, software, or a combination of hardware and software to implement an LPM control algorithm. In a hardware implementation, for example, LPM control 110 may be implemented as a circuit, such as an IC, a field programmable gate array (field programmable gate array, FPGA), or the like. In other embodiments, the LPM control 110 may also include a software implementation. Accordingly, the LPM control 110 may be a non-transitory computer-readable medium including a set of computer-readable instructions that may be executed by the storage controller 105. The LPM control 110 logic is described in more detail below in conjunction with fig. 3.

Conventional LPM management methods of DDR subsystem 145 rely on static, predefined timeout values (e.g., time-of-idle) to determine when and what level of LPM to enter. The traditional LPM management method has low efficiency and cannot adapt to real-time activity and load conditions. The LPM control logic 110 thus performs an LPM management dynamic approach, using real-time statistical predictions of system activity to select an LPM. In various embodiments, the LPM control algorithm may be a statistical control algorithm, as will be described below.

In some embodiments, the statistical control algorithm may include a control algorithm based on a Z-test. To perform the Z-check based algorithm, the first time period, e.g., the idle time period, may be divided into time slots of fixed time length. Thus, the first time period may be divided into a plurality of time slots N. The length of the time slot can be noted as t _s The total delay in entering and waking/activating from the associated LPM may be noted as t _a . For example, the term "total delay" refers to a delay associated with entering and exiting the LPM, wherein the delay (t _a ) The delay into the LPM is typically shorter but not negligible. As an example, exiting the LPM generally involves a transition from the LPM to an active idle state (active idle state). In some examples, t _a May be a delay associated with waking up individual components of the memory device 120, the DDR subsystem 145, such as the memory controller 105 and/or the DDR PHY 115, or a combination of the memory device 120, the memory controller 105, and/or the DDR PHY 115. t is t _a Can be based on LPM variation, each LPM having a specific t _a 。

In various embodiments, a timer is used to track idle states. For example, the timer may be implemented as part of the DDR subsystem. When the system is not in an idle state, the timer maintains its current value and pauses counting (i.e., counting The value of the timer is the total idle duration of the last idle period). When the system enters an idle state, the value of the timer is reset (e.g., set to 0) and the timer begins to count. The timer stops at its current value when the system transitions from the idle state to the active state. During the whole system initialization, the timer value is set to 0. In some embodiments, performing polling for each LPM using a timer may be implemented as follows. When the system transitions from the idle state to the active state, for each possible LPM, if the sample has not been updated, it is ensured that a bad time slot is recorded in the sliding log window of that LPM. The log status of the LPM is then updated. When the system is in an idle state and the idle timer is counting, for each LPM, every t passes if the DDR controller itself is still able to log _a Logging occurs over time. Otherwise, the process is re-executed until the system can log, and how many t's have elapsed is calculated _a Duration, and corresponding number of time slots updated accordingly.

If a given time slot is a bad time slot, meaning that the system should be in or being in an awake state (e.g., active state) in the given time slot, the power penalty (denoted as P _loss ) Not greater than t _a P _i . By way of example, P _i Refers to the idle power of the system, defined as the power consumption of the system when it is idle and not using any LPM (sometimes also referred to as idle active power). In other words, the power penalty will be at most the time it takes to enter and exit the LPM and the idle active power P _i Is a product of (a) and (b). If a good time slot, this means that the system is idle, the power gain P obtained by operating in TPM _gain Is t _s (P _i -P _l ) Wherein P is _l Is the power consumed in the corresponding LPM.

Based on the above, the objective is to determine the power gain P in the long term _gain Whether or not it will be greater than the power cost P _loss . Considering ρ as the probability that the slot is good (e.g., idle), the total power gain can be expressed as:

ρP _gain –(1-ρ)P _loss

(1)

Thus, if:

then a total power positive gain will be achieved.

Slot t _s Is set to be equal to the total delay t _a Equal, the following equation for the total power positive gain can be obtained:

wherein, for a given LPM, the minimum probability of obtaining a good time slot for a positive gain of total power is denoted ρ ₀ This can be derived from the following equation:

in view of the above, the null hypothesis (H ₀ ) Can be expressed as H ₀ :ρ≥ρ ₀ Alternative hypothesis H ₁ Denoted as H ₁ :ρ<ρ ₀ . That is, the null hypothesis is that entering the LPM saves power. Thus, for each LPM, a statistical test of zero hypotheses may be performed to determine whether a confidence level threshold into the respective LPM is met at a given time. An appropriate confidence level threshold may be selected depending on the application requirements. In some embodiments, a higher confidence level threshold may result in less power being saved in order to maintain low latency and high performance (e.g., less aggressive (less aggressively) into the LPM), while a lower confidence level threshold may result in more power being saved at the cost of performance (e.g., more aggressive into the LPM).

In one example, the confidence level threshold may be selected to be 95%. In other embodiments, other higher or lower confidence level thresholds may be selected and used. For example, in some embodiments, a confidence level threshold of greater than 95% may be usedFor example 99%. In other embodiments, a confidence level threshold of less than 95%, such as 90%, may be used. When using a 95% confidence level threshold, the test indicates if the probability ρ is greater than ρ ₀ With a confidence of 95% or higher, there will be a confidence of 95% or higher for entering a given LPM (e.g., entering in a given slot where the Z value is calculated) that more power is saved than for maintaining an active idle state.

This may be referred to as statistical hypothesis testing. The statistical hypothesis test in which the test statistic approximates a normal distribution is called a Z test. Thus, in various embodiments, the LPM control 110 logic may include instructions that execute or cause the memory controller 105 to control whether to enter a corresponding LPM based on a statistical test (e.g., without limitation, a Z-test). For example, to perform a Z-check, the following equation may be determined:

where Z is a standard value (e.g., Z value),is the sample mean (e.g., the number of good slots divided by the total number of sample slots), ρ ₀ Used as the expected value of T, s is the standard deviation of the sample. In this case, < >>May be p determined through a sliding window of n samples. In some embodiments, the number of samples may be determined as a function of the confidence level threshold. That is, the number of samples required increases with increasing confidence level threshold. In some embodiments, the number of n samples may exceed the number required to meet the confidence level threshold. In some examples, the number of n samples may be greater than or equal to 50.

The standard deviation s of the samples can be estimated as follows:

thus, the standard value (Z value) can be determined through a sliding window of n samples. The Z-value threshold may then be determined based on the confidence level threshold. For example, to meet a confidence level threshold of 95%, Z.gtoreq.1.65 may be required. In other embodiments, other kinds of statistical checksum methods may be used. For example, in some embodiments, a T-test/T value may be used.

Accordingly, the LPM control 110 logic may be used to determine or cause the memory controller 105 to determine a Z-value for each LPM. This process is described in more detail below in conjunction with fig. 5. The aggregate system delay requirement may be determined first. Based on the aggregate system delay requirement, it may be determined whether the overall delay of the LPM meets the aggregate system delay requirement. In some embodiments, the aggregate system delay requirement may be an aggregate voting delay requirement (aggregated voted latency requirement). For example, the aggregate vote delay requirement may be the delay requirements of all clients of the DDR subsystem. In this context, the clients of DDR subsystem 145 may include any processing core that shares access to memory device 120 through DDR subsystem 145. Thus, the components of the host device described above (e.g., one or more processing cores of the SoC) may be considered clients of DDR subsystem 145.

The power characteristics and delay characteristics of one or more LPMs may then be determined by memory controller 105 and/or LPM control 110 logic. The LPM whose delay characteristics (e.g., total delay) exceed the aggregate system delay requirement is restricted from selection. Then, for each LPM whose delay characteristics do not exceed the aggregate system delay requirement, its corresponding Z-value may be determined as previously described. For example, for each LPM, the corresponding P for a given LPM may be based on _i 、P _l 、t _s And t _a To determine the corresponding p and p ₀ 。

To determine ρ for a given LPM, every t may be _s Collect n samples (e.g., 50 samples), t _s Corresponding to the total delay, which includes the incoming delay and the wake-up delay t of the corresponding LPM _a . In some embodiments, the LPM control 110 logic mayTo sample the status of one or more buses of the memory system 100 and/or to query the memory controller 105 for the status of one or more buses. For example, the one or more buses may include, but are not limited to, a DFI or other buses and lines, such as a C/a bus, data lines, and/or control lines between DDR PHY 115 and memory device 120. In some examples, it may be determined whether the dfi_ctrlupd_req signal is asserted, which may indicate that the control, read, and write interfaces of the DFI are idle. In other embodiments, other DFI parameters may be used, such as PHY-related parameters indicating the number of periods of idle time on the DFI control line. In still other embodiments, activity of one or more lines of the DFI bus, such as activity of control lines of the DFI bus, may be monitored. Monitoring activity may include, for example, determining an activity state of one or more lines of the DFI bus. The active state may, for example, indicate that one or more lines are idle, or that one or more lines are in use (e.g., active).

If ρ based on LPM ₀ The corresponding Z-value exceeds the Z-value threshold, LPM control 110 may set the LPM and/or cause memory controller 105 to cause the DDR subsystem and/or one or more components of memory device 120 to enter the LPM. The LPM control 110 may then also determine whether there are additional LPMs that meet the aggregate system delay requirement, and determine a Z value for each additional LPM. In some embodiments, the Z-value of the LPM may be determined in ascending order of delay and power saving characteristics. For example, the Z value of the least aggressive (LPM) may be calculated first, with the least aggressive LPM having the lowest overall delay and the least power savings. Once it is determined to enter the LPM, it may then be determined whether to enter a more aggressive LPM, i.e., a higher overall delay, more power saving LPM. Alternatively, the Z-values of the LPM are calculated in descending order of delay and power saving characteristics. For example, the Z-value of the most aggressive (most aggressive) LPM may be calculated first, with the most aggressive LPM having the highest overall delay and more power savings. If the aggressive LPM is not entered, a determination may be made as to whether to enter a less aggressive LPM. In still other embodiments, the Z values of one or more LPMs may be determined simultaneously, with the LPM control 110 determining that full is entered The most aggressive LPM that is sufficient for the corresponding Z-value threshold. In some embodiments, if no LPM meets the Z-value threshold, DDR subsystem 145 and/or memory device 120 may remain in an active idle state.

In various embodiments, the LPM may include an LPM of DDR subsystem 145, an LPM of memory device 120, or an LPM of both DDR subsystem 145 and memory device 120. Accordingly, the LPM control 110 may be used to perform statistical control of the LPM of the DDR subsystem 145 and/or the memory device 120. The implementation of the LPM control 110 is described in more detail below in conjunction with fig. 5 and 6.

FIG. 2 is a schematic diagram 200 of a memory controller 205 for dynamic power management using statistical control, in accordance with various embodiments. Memory controller 205 includes control and timing block 210, command queue 215, data control block 220, address logic 225, LPM control 230, initialization control 235, and refresh control 240. It is noted that FIG. 2 schematically illustrates various components of the memory controller 205, and that modifications to the memory controller 205 are possible in accordance with various embodiments.

In various embodiments, control and timing block 210 may be coupled to command queue 215, address logic 225, LPM control 230, initialization control 235, and refresh control 240. Control and timing block 210 may include, but is not limited to, command decoders and logic for generating appropriate command and control signals, and timing circuitry and logic for providing clock/clock enable signals. The control and timing block may also include logic for decoding address data and/or for extracting address data for decoding via address logic 225. In some embodiments, command queue 215 may receive a plurality of commands from one or more clients (e.g., one or more processing cores of a host device/SoC device). The command queue 215 may queue commands. The control and timing block 210 may thus translate commands from the command queue 215 into sequences of commands and control signals required by the memory device. The control and timing block 210 may also implement a look-ahead function to optimize efficiency and throughput.

In other embodiments, control and timing block 210 may be used to generate appropriate commands and control signals for memory device startup, initialization, and reset as generated by initialization control 235. The refresh control 240 may generate or cause the control and timing block 210 to generate memory array refresh commands and control signals. As described above in connection with fig. 1, the LPM control 230 may be used to dynamically manage the LPM by selecting the LPM using real-time statistical predictions of system activity. The control blocks 230, 235, 240 may include, but are not limited to, control logic implemented as hardware, software executable by a processing core storing the control 205, or a combination of hardware and software.

The data control 220 may be used to control the data stream received from the client and to be written to memory, as well as the data stream received from the memory requested by the client. Thus, in various embodiments, data control 220 may include control logic and circuitry to manage the flow of data. For example, data control 220 may include one or more read buffers and one or more write buffers for storing data, and may also include control logic for asserting the DQ, DQS, and DQM signals as appropriate.

In various embodiments, the LPM control 230 may thus monitor activity (e.g., monitor idle state/activity) of one or more of the data lines, C/a lines, and control lines (e.g., DFI bus) of the memory controller 205. In some embodiments, the status of various lines may be requested and received from the control and timing block 210. The status of various buses and/or lines may be polled/sampled at a rate corresponding to the overall delay of each LPM. The sampled data may then be stored as a sliding window of n samples by the LPM control 230.

In some embodiments, the LPM may be the LPM of the storage controller 205 when it is determined to enter the LPM. As described above, the LPM of the memory controller 205 may include entering one or more low power states in which all or a portion of the memory controller is selectively power-gated and/or clock-gated. For example, in some embodiments, one or more of the control and timing block 210, the command queue 215, the data control 220, the address logic 225, or the control blocks 230, 235, 240 may be power gated during the deep power down state. In other embodiments, for some LPMs, the clock signal CLK for the internal clock signal may be down-converted and/or gated to reduce performance and/or defer activity within the memory controller 205.

In some embodiments, the sliding window may be configured as a shift register in hardware and/or software, as described below in connection with fig. 3. Accordingly, fig. 3 is a schematic diagram of LPM control logic 300 for implementing dynamic power management for statistical control, in accordance with various embodiments. The LPM control logic may include a shift register 305, the shift register 305 including N flip-flops (305A-305N) and Z verification logic 310. It should be noted that fig. 3 schematically illustrates various components of the LPM control logic 300, and that modifications to the LPM control logic 300 are possible in accordance with various embodiments.

In various embodiments, the output of shift register 305 may be provided to Z-check logic 310 at each clock timing unit (clock tick). In this example, the clock signal is set to 1/t of the frequency of a given LPM _a . As the previous example, the number of triggers n may correspond to the number of samples stored in a sliding window (e.g., a sliding window of n samples). Thus, in various embodiments, the LPM control logic 300 may initialize a shift register of n sample lengths. In some embodiments, the number of samples n may be preset for all LPMs or individual LPMs. In other embodiments, the number of samples n may be dynamically set at one or more LPMs. In one example, n may be preset to 50.

As described above, shift register 305 and Z-check logic 310 may be implemented as hardware and/or software logic. In some embodiments, shift register 305 may thus be initialized to a shift register of length n, may be a hardware shift register, and/or may be initialized in software. Similarly, Z-check logic 310 may be implemented in hardware as digital circuitry and/or software algorithms. In some embodiments, shift register 305 and Z-check logic 310 may both be implemented in hardware, both be implemented in software, or a combination of software and hardware.

In various embodiments, the data written to the first flip-flop 305A may be the current state of a memory system (e.g., one or more of the data lines, C/A lines, and control lines of a memory device or DFI bus). In some embodiments, if the storage system is idle, a value of 1 may be written to the flip-flop (and the previously stored value shifted to the later flip-flops 305B-305N). Thus, the Z-check logic 310 may be used to determine the total number of samples n, as well as the total number of free slots in the sliding window. The outputs of flip-flops 305A-305N may be output in parallel to Z-check logic 310. The Z-check logic may then determine the total number of "good" slots (e.g., free slots), i.e., the sum of the numbers of all bits Q1-Qn. Based on this number and the total number of samples n, Z-check logic 310 may determine ρ for a given LPM. Based on these values, the Z-check logic 310 may also determine the Z-value of the window of the last 50 samples, as described above in connection with fig. 1. Accordingly, the Z-check logic 310 may also be used to obtain aggregate system latency requirements, latency characteristics and power characteristics of individual LPMs, and confidence level thresholds for all clients of the DDR subsystem and/or storage device to determine a Z-value threshold. If the Z value meets or exceeds the Z value threshold, Z-check logic 310 may set the DDR subsystem and/or memory device to the corresponding LPM.

FIG. 4 is a schematic diagram 400 of a DDR PHY 405 for dynamic power management using statistical control, in accordance with various embodiments. DDR PHY 405 may include a clock/power management block 410, command/address control 420, and data control 430. The clock/power management block 410 may include one or more PLLs 415. The command/address control 420 may include one or more DLLs 425. The data control 430 may include one or more DLLs 435.DDR PHY 405 may also include an input-output buffer (I/O pad) 440. It is noted that fig. 4 schematically illustrates various components of DDR PHY 405, modifications to DDR PHY 405 being possible in accordance with various embodiments.

In various embodiments, clock/power management block 410 may be used to receive and process clock signals CK and CKE, and may also receive signals on LPI to handle power management of DDR PHY 405. As described above, the clock/power management block 410 may include logic that is applied to hardware and/or software. Similarly, the command/address control block 420 may be used to receive command/address signals from the command/address lines of the DFI bus. The command/address control block 420 may be used to receive command/address signals from the memory controller and further process signals received by the device to be stored. The command/address control 420 may include logic implemented in hardware and/or software, such as command buffers, tuning circuitry, and the like. Similarly, data control block 430 may include logic implemented in hardware and/or software and includes data to be written to/read from a storage device, data buffers, and other data processing logic (e.g., read/write balancing (read/write leveling), etc.). The signal to be output to the memory device may be transmitted through the input-output buffer 440.

According to various embodiments, DDR PHY 405 may receive commands and/or control signals through the LPI to enter the LPM based on the memory controller and/or the LPM control logic determining to enter the LPM. The clock/power management block 410 may read the LPI to enter a particular LPM. As described above, the LPM of the DDR PHY may include entering one or more low power states in which all or a portion of the components are selectively power-gated and/or clock-gated. For example, in some embodiments, each of PLL 415, DLL 425, and/or DLL 435 may be power-gated during deep power down states. In other words, in some LPMs, the clock signal CLK for the internal clock signal may be down-converted and/or gated to reduce performance and/or defer activity within the DDR PHY. In some LPMs, input-output buffer 440 may also be power gated or power removed.

FIG. 5 is a flow diagram of a method 500 of dynamic power management of a DDR subsystem using statistical control in accordance with various embodiments. The method 500 begins at block 505 with determining an aggregate system delay requirement. As described above, the storage controller may be used to determine aggregate system latency requirements based on each client of the storage device. In some examples, the aggregate system delay requirement may be an aggregate voting delay requirement.

At block 510, the method 500 continues with determining power characteristics and delay characteristics of the one or more LPMs. In some embodiments, the power characteristics and delay characteristics of one or more LPMs may be determined by a memory controllerAnd/or the LPM control logic, e.g., from an onboard data store or an external database. Thus, in various embodiments, the power characteristics and delay characteristics of the LPM may be preprogrammed into a memory system (e.g., DDR subsystem or LPM control logic) based on the disclosed manufacturing data. As an example, the power characteristics may include a determination of LPM power usage and idle active power. The delay characteristics of the LPM may include a total delay including an incoming delay and a wake-up delay t _a Or the time it takes to initialize/wake up from the LPM. As described above, the LPM may include a DDR subsystem and/or an LPM of a memory device.

At decision block 515, the method continues with determining whether the LPM delay characteristic (e.g., wake-up delay) is less than the aggregate system delay requirement. For a given LPM, if it is determined that the total delay exceeds the aggregate system delay requirement, the LPM may no longer be considered. The method 500 may include determining power characteristics and delay characteristics of a next LPM at block 510. Then at decision block 515, a determination is repeated as to whether the LPM meets the aggregate system delay requirement. Thus, one or more LPMs having a total delay less than or meeting the aggregate system delay requirement may be identified. In some embodiments, such determination of one or more LPMs may be made serially, as described. In other embodiments, such determination of one or more LPMs may be made in parallel.

If it is determined that the total delay is less than or meets the aggregate system delay requirement, the method 500 continues at block 520 with determining a minimum probability ρ of good time slots required to save power ₀ . As described above, ρ may be determined based on the power characteristics of a given LPM ₀ . In some embodiments, ρ may be calculated for a single LPM ₀ While in other embodiments, ρ of multiple LPMs may be determined in parallel ₀ 。

At block 525, the method 500 continues to calculate a given ρ of the LPM ₀ Z values of (3). In various embodiments, the Z-test may be completed for one or more LPMs. For example, n samples may be collected over n time slots. Length t of time slot _s May be set equal to the total delay including the incoming delay and wake-up delay t of the corresponding LPM for which the Z-value is calculated _a . May be based on good time slotsThe number of (e.g., free slots) calculates ρ.

At decision block 530, the method 500 continues with determining whether the Z value of the LPM is greater than a Z value threshold. As described above, the Z-value threshold may be determined by a confidence level threshold. In one example, the 95% confidence level threshold may correspond to a Z value threshold of 1.65. If the Z value of the LPM is greater than or equal to the Z value threshold, the method 500 continues with setting the LPM at block 535. For example, setting the LPM may include sending command and/or control signals to cause the memory system or a component of the memory system (e.g., a DDR subsystem and/or memory device, or a combination of sub-components of a DDR subsystem and/or memory device) to enter the LPM. If the Z value does not meet the Z value threshold, the system may be allowed to remain in an active idle state. The method 500 may continue at decision block 540 with checking whether there are additional LPMs to check and determine the Z value. Thus, if there is another LPM that has not yet been checked, the method 500 may repeat the determination of the power characteristics and delay characteristics of the remaining LPMs at block 510.

The process of performing the Z-test is described in more detail below. FIG. 6 is a flow diagram of a statistical verification method 600 for dynamic power management of DDR subsystems, in accordance with various embodiments. The method 600 begins at block 605 with determining the number n of samples to collect. As described above, in some embodiments, the number of samples n to collect may be determined based at least in part on a confidence level threshold required for the Z-test.

At block 610, the method 600 continues with initializing a shift register of length n. As described above, the shift register may be implemented in software or hardware. Thus, initializing the shift register may include initializing a hardware register to be filled with samples corresponding to states of one or more lines of the DFI bus and/or one or more lines of the C/a bus, control bus, and/or data bus connected to the memory device. In a software register implementation, the memory controller may be used to instantiate a shift register of length n, or to instantiate a rolling counter of the last 50 samples of idle state of the system, DDR subsystem, and/or memory device.

At block 615, the method 600 may continue to determine a duration of the sampling time for the given LPM (e.g E.g. length t of time slot _s ). In some embodiments, the length of the time slot may be set to the total delay of the individual LPMs. At block 620, every t _s Sampling, or at a sampling rate of 1/t _s Sampling is performed. As described above, one or more lines of the DFI bus or one or more lines of several buses connected to the memory device may be sampled to determine if one or more lines are idle. Alternatively, the storage controller may be queried to determine the condition of one or more lines.

At block 625, the condition of the line may be written as a new value for the shift register. In some embodiments, the condition is not updated during one state. In some embodiments, the idle state may correspond to a logic high level, while the low value may be set to a logic low level. In some embodiments, writing of new data values to the shift register may continue until the shift register is full, before the Z value is calculated. Once the shift register is full, at each clock cycle (e.g., every t _s ) New values are added while the oldest value is overwritten and pushed out of the shift register. In this way the shift register acts as a sliding window of the last n samples.

At block 630, method 600 may include determining a sum of each bit of the shift register. In this way, the total number of "good" slots (e.g., free slots) or the number of recent samples n may be determined. In some examples, the sum may continue to be updated as each new value is written to the shift register.

Based on the sum, a Z-value of the LPM may be determined, block 635. For example, in some embodiments, the probability that a given time slot will be "good" may be determined (e.g., ρ is determined) based on the sum of the total number of good time slots, and knowing the number of samples n. Based on ρ, and know ρ ₀ The Z-value of the LPM may be determined. As described above, the Z-test may be repeated for each LPM that meets the latency requirements of the aggregate system.

The terms "machine-readable medium" and "computer-readable medium" as used herein refer to any medium that participates in providing data that causes a machine to operation in a fashion. In an embodiment implemented using computer or hardware system 500, different computer-readable media may be involved in providing instructions/code to processor 510 for execution and/or may be used to store and/or carry such instructions/code (e.g., as signals). In many implementations, the computer-readable medium is a non-transitory, physical, and/or tangible storage medium. In some embodiments, a computer readable medium may take many forms, including but not limited to, non-volatile media, and the like. Non-volatile media includes, for example, optical and/or magnetic disks, such as storage device(s) 525. Volatile media includes, but is not limited to, dynamic memory, such as working memory 535. In some alternative embodiments, the computer-readable medium may take the form of a transmission medium including, but not limited to, coaxial cable, copper wire, and fiber optics, including the wires that comprise bus 505, and the various components of communication subsystem 530 (and/or the medium by which communication subsystem 530 provides for communication with other devices). In an alternative set of embodiments, transmission media can also take the form of waves (including, but not limited to, radio waves, acoustic and/or light waves, such as those generated during radio wave and infrared data communications).

While certain features and aspects have been described with respect to some embodiments, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, software components, and/or any combination thereof. Further, while, for ease of description, the different methods and processes described herein may be described with respect to particular structural and/or functional components, the methods provided by the various embodiments are not limited to any particular structural and/or functional architecture, but may be implemented on any suitable hardware, firmware, and/or software configuration. Similarly, although some functionality may reside in some system components, unless the context dictates otherwise, this functionality may be distributed among different other system components according to several embodiments.

Moreover, although the processes of the methods and processes described herein are described in a particular order for ease of description, different processes may be reordered, added, and/or omitted according to different embodiments unless otherwise specified herein. Furthermore, a process described with respect to one method or process may be combined in other described methods or processes; likewise, system components described with respect to one system may be organized in alternate structural architectures and/or incorporated into other described systems according to a particular structural architecture. Thus, while various embodiments with or without some features have been described for ease of describing and illustrating some aspects of those embodiments, various components and/or features described herein with respect to a particular embodiment may be substituted, added and/or subtracted from other described embodiments unless otherwise specified herein. Thus, while several embodiments are described above, it will be understood that the invention is intended to cover all modifications and equivalents within the scope of the following claims.

Claims

1. A method, comprising:

acquiring an aggregate system delay requirement of a storage system through a storage controller, wherein the storage system comprises the storage controller;

determining, by the memory controller, a power characteristic and a latency characteristic of a low power mode of the memory system, wherein the power characteristic includes power consumption in the low power mode and idle active power consumption, and wherein the latency characteristic includes a total latency of entering and exiting the low power mode;

determining, by the memory controller, whether the total latency of the low power mode is less than or equal to the aggregate system latency requirement;

in response to determining that the total delay of the low power mode is less than or equal to the aggregate system delay requirement:

determining ρ by the memory controller ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy savings by entering the low power mode;

for statistical assumption ρ.gtoreq.ρ ₀ Performing, by the memory controller, a statistical check of the low power mode, wherein ρ is associated with a probability that the slot is idle; and

and based on the result of the statistical test, causing the storage system to enter the low power mode by the storage controller.

2. The method of claim 1, further comprising:

in response to determining that the total delay of the low power mode is greater than the aggregate system delay requirement, it is determined whether the total delay of a next low power mode is less than or equal to the aggregate system delay requirement.

3. The method of claim 1, wherein the statistical test is a Z test, and wherein performing the statistical test comprises:

based on ρ and ρ ₀ Determining a Z value of the low power mode; and

a Z-value threshold that meets the confidence level threshold is determined based on the confidence level threshold.

4. The method of claim 3, wherein the result of the statistical test is an indication of whether the Z-value is greater than or equal to the Z-value threshold, and wherein, based on the result of the statistical test, causing the storage system to enter the low power mode comprises:

responsive to determining that the Z value is greater than or equal to the Z value threshold, causing the storage system to enter the low power mode.

5. A method according to claim 3, wherein determining the Z value comprises:

determining a total number n of samples to be collected based on the confidence level threshold;

initializing a shift register with a length of n;

At a sampling rate of 1/t _s Obtaining a sample, wherein t _s Is a duration of the total delay set to the low power mode, wherein the sample is an indication of whether one or more lines of the storage system are idle;

at the time period t when the storage system can record the log _s During which a value of the sample is written to the shift register, the value indicating whether the one or more lines of the memory system are idle at a current time, wherein the value is at intervals of the duration t _s Is updated and written to the shift register until the shift register is full, wherein the values within the shift register are shifted such that each time the time period t passes _s The oldest value in the shift register is overwritten; and

a total number of samples of the most recent n samples for which the one or more lines of the storage system are free is determined.

6. The method of claim 5, wherein obtaining the sample comprises:

monitoring activity of one or more lines of a double data rate Physical (PHY) interface bus; and

an active state of the one or more lines of the double data rate PHY interface bus is determined, wherein the active state indicates whether the one or more lines are idle.

7. The method of claim 1, wherein causing, by the storage controller, the storage system to enter the low power mode comprises:

at least one of a double data rate physical interface and the memory controller is brought into the low power mode by the memory controller.

8. An apparatus, comprising:

a processor; and

a non-transitory computer readable medium in communication with the processor, the non-transitory computer readable medium having encoded therein a set of instructions executable by the processor to:

acquiring an aggregate system delay requirement of a storage system;

determining a power characteristic and a delay characteristic of a low power mode of the storage system, wherein the power characteristic comprises power consumption in the low power mode and power required to leave the low power mode, and wherein the delay characteristic comprises a total delay to enter and exit the low power mode;

determining whether the total delay of the low power mode is less than or equal to the aggregate system delay requirement;

determining ρ based on the power characteristics ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy savings by entering the low power mode;

for statistical assumption ρ.gtoreq.ρ ₀ Performing a statistical test of the low power mode, wherein ρ is associated with a probability that a slot is idle; and

and based on the result of the statistical test, causing the storage system to enter the low power mode.

9. The apparatus of claim 8, wherein the set of instructions is further executable by the processor to:

in response to an indication that the total delay for the low power mode is greater than the aggregate system delay requirement, determining whether the total delay for a next low power mode is less than or equal to the aggregate system delay requirement.

10. The apparatus of claim 8, wherein performing the statistical test further comprises performing a Z-test, wherein the set of instructions is further executable by the processor to:

determining a Z value for the low power mode based on ρ and ρ0;

determining a Z-value threshold that meets a confidence level threshold based on the confidence level threshold; and

wherein the result of the statistical test is an indication of whether the Z-value is greater than or equal to the Z-value threshold, wherein the low power mode is entered in response to determining that the Z-value is greater than or equal to the Z-value threshold.

11. The apparatus of claim 10, wherein the set of instructions is further executable by the processor to:

initializing a shift register with a length of n;

every said time period t _s Writing a value of the sample to the shift register, the value indicating whether the one or more lines of the memory system are idle at a current time, wherein the value is at intervals of the duration t _s Is updated and written to the shift register until the shift register is full, wherein the values within the shift register are shifted such that each time the time period t passes _s The oldest value in the shift register is overwritten; and

a total number of samples of the most recent n samples for which the one or more lines of the storage system are idle is determined, wherein ρ is associated with a probability that a slot is idle.

12. The apparatus of claim 11, the set of instructions further executable by the processor to:

Monitoring activity of one or more lines of the double data rate PHY interface bus; and

13. A storage subsystem, comprising:

a double data rate physical interface (DDR PHY) to communicate with the memory device;

a memory controller coupled to the DDR PHY, the memory controller comprising:

a processor; and

acquiring an aggregate system delay requirement of a storage system through the storage controller, wherein the aggregate system delay requirement is the minimum delay required by all clients of the storage system;

determining, by the memory controller, a power characteristic and a latency characteristic of a low power mode of the memory system, wherein the power characteristic includes power consumption in the low power mode and power required to leave the low power mode, and wherein the latency characteristic includes a total latency of entering and exiting the low power mode;

determining ρ based on the power characteristics by the memory controller ₀ Wherein ρ is ₀ Is the minimum probability that a slot is idle to ensure energy savings by entering the low power mode;

through the memory controller, ρ is larger than ρ for statistical assumption ₀ Performing a statistical test of the low power mode,

wherein ρ is associated with the probability that the slot is idle; and

and enabling, by the memory controller, the memory system to enter the low power mode based on a result of the statistical test.

14. The storage subsystem of claim 13, wherein the set of instructions is further executable by the processor to:

responsive to an indication that the total delay for the low power mode is greater than the aggregate system delay requirement, determining, by the memory controller, whether the total delay for a next low power mode is less than or equal to the aggregate system delay requirement.

15. The storage subsystem of claim 13, wherein performing the statistical test further comprises performing a Z-test, wherein the set of instructions is further executable by the processor to:

determining, by the memory controller, a Z value for the low power mode based on ρ and ρ0;

determining, by the storage controller, a Z-value threshold that meets the confidence level threshold based on the confidence level threshold; and

16. The storage subsystem of claim 15, wherein the set of instructions is further executable by the processor to:

determining, by the storage controller, a total number n of samples to collect based on the confidence level threshold;

initializing a shift register with a length of n by the memory controller;

at a sampling rate of 1/t through the DDR PHY _s Obtaining a sample, wherein t _s Is a duration of the total delay set to the low power mode, wherein the sample is an indication of whether one or more lines of the storage system are idle;

Through the memory controller, every the time period t _s Writing a value of the sample to the shift register, the value indicating whether the one or more lines of the memory system are idle at a current time, wherein the value is at intervals of the duration t _s Is updated and is subjected toWriting the shift register until the shift register is full, wherein values within the shift register are shifted such that each time the time period t passes _s The oldest value in the shift register is overwritten; and

determining, by the memory controller, a total number of samples of the most recent n samples for which the one or more lines of the memory system are idle, wherein ρ is associated with a probability that a slot is idle.

17. The storage subsystem of claim 15, wherein the confidence level threshold is 95%.

18. The storage subsystem of claim 15, wherein the total number of samples n is at least 50.

19. The storage subsystem of claim 13, wherein the set of instructions is further executable by the processor to:

monitoring, by the memory controller, activity of one or more lines of a DDR PHY interface (DFI) bus; and

An active state of the one or more lines of the DFI bus is determined by the memory controller, wherein the active state indicates whether the one or more lines of the DFI bus are idle.

20. The storage subsystem of claim 13, wherein causing, by the storage controller, the storage system to enter the low power mode further comprises:

at least one of the DDR PHY and the memory controller is brought into the low power mode by the memory controller.