CN117318694A

CN117318694A - Transmitting circuit and digital isolator

Info

Publication number: CN117318694A
Application number: CN202311207602.XA
Authority: CN
Inventors: 陈奇辉; 盛云
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2023-09-19
Filing date: 2023-09-19
Publication date: 2023-12-29
Anticipated expiration: 2043-09-19
Also published as: CN117318694B

Abstract

The invention discloses a transmitting circuit and a digital isolator, wherein the transmitting circuit comprises: a digital transmitter including a first end and a second end coupled to ground; a high-side selection circuit including a first terminal, a second terminal, and a third terminal coupled to the first terminal of the digital transmitter; a current loop including a first terminal coupled to the first circuit input terminal, a second terminal coupled to the first terminal of the high-side selection circuit; and/or includes a third terminal coupled to the second circuit input terminal, a fourth terminal coupled to the second terminal of the high-side selection circuit. The transmitting circuit and the digital isolator provided by the invention can adapt to the working environment of bidirectional signal input, keep a current loop from being influenced by leakage current, and keep stable signal current input by a high-side selection circuit and stable chip working current.

Description

Transmitting circuit and digital isolator

Technical Field

The present invention relates to the field of isolation technologies, and in particular, to a transmitting circuit and a digital isolator.

Background

Digital isolators, or digital isolation units or digital isolation chips, are commonly used in industrial plant environments to ensure proper signal transmission between two systems. In one specific embodiment, the digital input from the switch and the sensor is received, processed and isolated, and then output to the back end. In this process, the above-mentioned digital input conditions, especially the input direction and voltage, are difficult to grasp and control on the digital isolator side, so that the reverse digital input signal is lost, the packaging cost is increased, and the problems of high voltage input requirements, system power accumulation and high heating power are difficult to adapt.

In the prior art, the selection of digital signals and common ground input is realized by arranging the switching circuit comprising the switching tube, so that the corresponding input end of the transmitting circuit can always keep the coupling relation with the corresponding signals, but because the switching circuit is arranged between the signal input and the digital transmitter, the correspondingly generated leakage current can flow through a current loop in the transmitter, thereby causing unstable working current of a chip and particularly influencing the signal output on one side of the transmitting circuit.

Disclosure of Invention

The invention aims to provide a transmitting circuit which solves the technical problems that a digital isolation circuit is difficult to adapt to a bidirectional high-voltage input environment and the working current of a chip is unstable in the prior art.

It is an object of the present invention to provide a digital isolator.

In order to achieve one of the above objects, an embodiment of the present invention provides a transmitting circuit including: a digital transmitter including a first end and a second end coupled to ground; a high-side selection circuit including a first terminal, a second terminal, and a third terminal coupled to the first terminal of the digital transmitter; the high-side selection circuit is configured to select and couple one of its first and second ends coupled to the digital signal to its third end; a current loop including a first terminal coupled to the first circuit input terminal, a second terminal coupled to the first terminal of the high-side selection circuit, configured to maintain a signal current output from the second terminal thereof constant when the first terminal thereof is coupled to the digital signal; and/or includes a third terminal coupled to the second circuit input terminal, a fourth terminal coupled to the second terminal of the high-side selection circuit, configured to keep the signal current output from the fourth terminal constant when the third terminal thereof is coupled to the digital signal.

In order to achieve one of the above objects, an embodiment of the present invention provides a digital isolator, which includes a receiving circuit, an isolation capacitor, and a transmitting circuit according to any one of the above embodiments.

Compared with the prior art, the transmitting circuit provided by the invention can keep that the first end side of the digital transmitter always receives the digital signal by arranging the high-side selection circuit, so that the transmitting circuit can adapt to the working environment of bidirectional signal input; the current loop is arranged between the high-side selection circuit and the circuit input end, so that the current loop is not influenced by leakage current generated at the high-side selection circuit, and the stability of signal current output to one side of the high-side selection circuit can be maintained, so that the stability of chip working current is maintained.

Drawings

Fig. 1 is a schematic diagram of a digital isolator according to an embodiment of the present invention.

Fig. 2 is a circuit configuration diagram of a transmission circuit according to an embodiment of the present invention.

Fig. 3 is a circuit configuration diagram of a digital transmitter of a transmission circuit according to an embodiment of the present invention.

Fig. 4 is a circuit configuration diagram of a high-side selection circuit of a transmission circuit according to an embodiment of the present invention.

Fig. 5 is a circuit configuration diagram of a high-side selection circuit of a transmission circuit according to another embodiment of the present invention.

Fig. 6 is a circuit configuration diagram of a low-side selection circuit of a transmission circuit according to an embodiment of the present invention.

Fig. 7 is a circuit configuration diagram of a low-side selection circuit of a transmission circuit according to another embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.

It should be noted that the term "comprises," "comprising," or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

An embodiment of the present invention provides a digital isolator 100 as shown in fig. 1, which is used for implementing isolation and signal transmission between two systems, wherein the two systems can be specifically an electromechanical system such as a detection site and a control system such as an industrial controller, so that two sides with different working environment requirements can be protected, and normal signal transmission and control can be ensured. The digital isolator 100 provided by the invention comprises a receiving circuit 12, an isolation capacitor 11 and a transmitting circuit 13. The transmitting circuit 13 is used for receiving an input signal from one side of the electromechanical system, the isolation capacitor 11 is used for preventing faults caused by direct coupling of the electromechanical system to the control system, and the receiving circuit 12 is used for receiving signals from the transmitting circuit 13 and the isolation capacitor 11, realizing communication and transmitting the signals to one side of the control system.

As further shown in fig. 1 and 2, an embodiment of the present invention provides a transmitting circuit 13, which may be mounted in the digital isolator 100, or may be mounted in another industrial controller, or any component disposed between two systems for implementing isolation and digital signal transmission.

The transmitting circuit 13 may include, in particular, a digital transmitter 200, a high-side selection circuit 300, and a current loop 400.

The digital transmitter 200 includes a first end 201 and a second end 202; the second terminal 201 of the digital transmitter 200 is coupled to ground. In one embodiment, the coupling to the common ground COM may be through the low-side selection circuit 500.

The high-side selection circuit 300 includes a first terminal VDDS1, a second terminal VDDS2, and a third terminal VDDS; the third terminal VDDS of the high-side selection circuit 300 is coupled to the first terminal 201 of the digital transmitter 200.

The high-side selection circuit 300 is configured to: one of the first terminal VDDS1 of the high-side selection circuit 300 and the second terminal VDDS2 of the high-side selection circuit 300 is selected to be coupled to the digital signal Input and is coupled to the third terminal VDDS of the high-side selection circuit 300. In this way, the first end 201 of the digital transmitter 200 is always coupled to the digital signal Input, so that the working condition of bidirectional signal Input can be adapted.

In a first embodiment, the current loop 400 includes a first end 411 and a second end 412; a first terminal 411 of the current loop 400 is coupled to the first circuit input 11 and a second terminal 412 of the current loop 400 is coupled to the first terminal VDDS1 of the high-side selection circuit 300.

The current loop 400 is configured to maintain a signal current output by the second end 412 of the current loop 400 constant when the first end 411 of the current loop 400 is coupled to the digital signal Input. Thus, the current flowing through the current loop 400 can be kept constant, and the leakage current on the side of the high-side selection circuit 300 is prevented from influencing the working current of the chip.

In a second embodiment, the current loop 400 includes a third terminal 421 and a fourth terminal 422; the third terminal 421 of the current loop 400 is coupled to the second circuit input 12, and the fourth terminal 422 of the current loop 400 is coupled to the second terminal VDDS2 of the high-side selection circuit 300.

The current loop 400 is configured to keep the signal current correspondingly output by the fourth terminal 422 of the current loop 400 constant when the third terminal 421 of the current loop 400 is coupled to the digital signal Input. Thus, the current flowing through the current loop 400 can be kept constant, and the leakage current on the side of the high-side selection circuit 300 is prevented from influencing the working current of the chip.

In one embodiment, the transmitting circuit provided by the present invention is configured as in the first and second embodiments described above. Thus, the signal current output to the high-side selection circuit 300 can be kept constant no matter the first circuit Input terminal 11 is coupled to the digital signal Input or the second circuit Input terminal 12 is coupled to the digital signal Input, so that the working current of the chip is kept stable in the whole process under the bidirectional Input scene, and the performance of the transmitting circuit is maintained.

In addition, since the current loop 400 is disposed between the high-side selection circuit 300 and the first circuit input terminal 11 and/or the second circuit input terminal 12, the input current of the current loop 400 itself can be kept stable, and the error of the internal sensing device can be prevented.

In the first embodiment, the current loop 400 includes a first terminal 411 coupled to the first circuit input 11 and a second terminal 412 coupled to the first terminal VDDS1 of the high-side selection circuit 300.

The current loop 400 comprises a first current loop 41. The first current loop 41 includes a first operational amplifier OPA1, a first resistor R1, and a first sense circuit Rsense1.

The first sense resistor Rsense1 is coupled between the first end 411 of the current loop 400 and the output terminal of the first operational amplifier OPA 1. The first resistor R1 is coupled between the first terminal 411 of the current loop 400 and a first terminal (e.g., a non-inverting input terminal) of the first operational amplifier OPA 1. A second terminal (e.g., an inverting input) of the first operational amplifier OPA1 is coupled to an output terminal of the first operational amplifier OPA1 to form a second terminal 412 of the current loop 400.

When the first circuit Input terminal 11 is coupled to the digital signal Input, the first current loop 41 makes the working current of the chip flow through the first sensing resistor Rsense1, so that the stability of the working current of the chip in this state can be effectively maintained. Specifically, the bias current flowing through the first resistor R1 is constant, the voltage across the first sense resistor Rsense1 is constant through the feedback adjustment of the first operational amplifier OPA1, the bias current flowing through the first sense resistor Rsense1 is constant, so the signal current output at the second end 412 of the current loop 400 is constant and is equal to the sum of the current flowing through the first resistor R1 and the current flowing through the first sense resistor Rsense 1.

Compared with the prior art, the configuration of the current loop has no temperature coefficient of the working current, the performance is not affected by the ambient temperature, and the voltage drop across the first sensing resistor Rsense1 can be adjusted by the resistance value of the first resistor R1 and the bias current of the first resistor R1. In one embodiment, the voltage drop across the first sense resistor Rsense1 may be reduced to reduce the start-up voltage of the digital transmitter 200.

Further, as shown in fig. 1 to 3, the digital transmitter 200 includes a bandgap reference source 21; the first terminal 211 of the bandgap reference source 21 is coupled to the third terminal VDDS of the high-side selection circuit 300. The bandgap reference source 21 is used for providing a bandgap reference voltage VREF; the bandgap reference source 21 outputs a bandgap reference voltage VREF from its second terminal 212.

The transmission circuit 13 further includes a third operational amplifier OPA3, a first switching tube M1, a third resistor R3, a third switching tube M3, and a ninth resistor R9.

A first end of the first switching tube M1 is coupled to a first end (e.g., a non-inverting input) of the first operational amplifier OPA 1; the third resistor R3 is coupled between the second end of the first switch tube M1 and ground. The first end of the third switching tube M3 is coupled to the third end VDDS of the high-side selection circuit 300; the ninth resistor R9 is coupled between the second end of the third switching tube M3 and ground. A first end (e.g., a non-inverting input) of the third operational amplifier OPA3 is coupled to the second end 212 of the bandgap reference source 21; a second terminal (e.g., an inverting input terminal) of the third operational amplifier OPA3 is coupled to a second terminal of the third switching tube M3. The output end of the third operational amplifier OPA3 is coupled to the control end of the first switching tube M1; the output of the third operational amplifier OPA3 is coupled to the control terminal of the third switching tube M3.

Thus, the first switching tube M1 and the third switching tube M3 are used for constructing a current mirror; the voltage at two ends of the third resistor R3 can be made to be the bandgap reference voltage VREF provided by the bandgap reference source 21 through the feedback adjustment of the third operational amplifier OPA3, so as to provide a constant bias current for the first resistor R1 through the first switching tube M1; wherein the bias current is equal in value to the ratio of the bandgap reference voltage VREF to the resistance of the third resistor R3.

The first switching tube M1 is an N-channel field effect tube; the first end of the first switching tube M1 is the drain electrode of the N-channel field effect tube, the second end of the first switching tube M1 is the source electrode of the N-channel field effect tube, and the control end of the first switching tube M1 is the grid electrode of the N-channel field effect tube.

The third switching tube M3 is an N-channel field effect tube; the first end of the third switching tube M3 is the drain electrode of the N-channel field effect tube, the second end of the third switching tube M3 is the source electrode of the N-channel field effect tube, and the control end of the third switching tube M3 is the grid electrode of the N-channel field effect tube.

In the second embodiment, the current loop 400 includes a third terminal 421 coupled to the second circuit input 12 and a fourth terminal 422 coupled to the second terminal VDDS2 of the high-side selection circuit 300.

The current loop 400 includes a second current loop 42. The second current loop 42 includes an operational amplifier OPA2, a second resistor R2, and a second sense circuit Rsense2.

The second sensing resistor Rsense2 is coupled between the third terminal 421 of the current loop 400 and the output terminal of the second operational amplifier OPA 2. The second resistor R2 is coupled between the third terminal 421 of the current loop 400 and a first terminal (e.g., a non-inverting input terminal) of the second operational amplifier OPA 2. A second terminal (e.g., an inverting input) of the second operational amplifier OPA2 is coupled to an output of the second operational amplifier OPA2 to form a fourth terminal 422 of the current loop 400.

When the second circuit Input 12 is coupled to the digital signal Input, the second current loop 42 makes the working current of the chip flow through the second sensing resistor Rsense2, so that the stability of the working current of the chip in this state can be effectively maintained. Specifically, the bias current flowing through the second resistor R2 is constant, the voltage across the second sense resistor Rsense2 is constant through the feedback adjustment of the second operational amplifier OPA2, the bias current flowing through the second sense resistor Rsense2 is constant, so the signal current output at the fourth end 422 of the current loop 400 is constant, and is equal to the sum of the current flowing through the second resistor R2 and the current flowing through the second sense resistor Rsense 2.

Compared with the prior art, the voltage drop across the second sensing resistor Rsense2 can be adjusted by the value of the second resistor R2 and the bias current of the second resistor R2. In one embodiment, the voltage drop across the second sense resistor Rsense2 may be reduced to reduce the start-up voltage of the digital transmitter 200.

The transmission circuit 13 further includes a third operational amplifier OPA3, a second switching tube M2, a fourth resistor R4, a third switching tube M3, and a ninth resistor R9.

A first end of the second switching tube M2 is coupled to a first end (e.g., a non-inverting input) of the second operational amplifier OPA 2; the fourth resistor R4 is coupled between the second end of the second switching tube M2 and ground. The first end of the third switching tube M3 is coupled to the third end VDDS of the high-side selection circuit 300; the ninth resistor R9 is coupled between the second end of the third switching tube M3 and ground. A first end (e.g., a non-inverting input) of the third operational amplifier OPA3 is coupled to the second end 212 of the bandgap reference source 21; a second terminal (e.g., an inverting input terminal) of the third operational amplifier OPA3 is coupled to a second terminal of the third switching tube M3. The output end of the third operational amplifier OPA3 is coupled to the control end of the second switching tube M2; the output of the third operational amplifier OPA3 is coupled to the control terminal of the third switching tube M3.

Thus, the second switching tube M2 and the third switching tube M3 are used for constructing a current mirror; the voltage at two ends of the fourth resistor R4 can be made to be the bandgap reference voltage VREF provided by the bandgap reference source 21 through the feedback adjustment of the third operational amplifier OPA3, so as to provide a constant bias current for the second resistor R2 through the second switching tube M2; wherein the bias current is equal in value to the ratio of the bandgap reference voltage VREF to the resistance of the fourth resistor R4.

The second switching tube M2 is an N-channel field effect tube; the first end of the second switching tube M2 is the drain electrode of the N-channel field effect tube, the second end of the second switching tube M2 is the source electrode of the N-channel field effect tube, and the control end of the second switching tube M2 is the grid electrode of the N-channel field effect tube.

In one embodiment, the transmitting circuit 100 provided by the present invention may be configured as the first embodiment and the second embodiment.

In one embodiment, the first current loop 41 and the second current loop 42 may have the same configuration. The first switching tube M1 and the second switching tube M2 may have the same configuration; the third resistor R3 and the fourth resistor R4 may have the same configuration.

As shown in fig. 3 in combination with fig. 1 and 2, the digital transmitter 200 includes a bandgap reference source 21. The bandgap reference source 21 includes a first end 211 and a second end 212. The first terminal 211 of the bandgap reference source 21 is coupled to the third terminal VDDS of the high-side selection circuit 300.

The bandgap reference source 21 is used for generating a bandgap reference voltage VREF as an input to the aforementioned third operational amplifier OPA3 and the later-described isolation comparison circuit 22.

In one embodiment, the Bandgap reference source 21 includes a first low dropout linear regulator LDO1 and a Bandgap reference voltage source Bandgap connected in series between a first end 211 of the Bandgap reference source 21 and a second end 212 of the Bandgap reference source 21. The first low dropout linear regulator LDO1 is used for providing a stabilized supply voltage required by a band gap reference voltage source Bandgap; the Bandgap reference voltage source Bandgap is used for outputting the Bandgap reference voltage VREF.

The digital transmitter 200 includes an isolation comparison circuit 22. The isolation comparison circuit 22 includes a first terminal 221, a second terminal 222, a third terminal 223, and an output terminal 220. The first terminal 221 of the isolation comparing circuit 22 is coupled to the third terminal VDDS of the high-side selecting circuit 300; a second terminal 22 of the isolation comparison circuit 22 is coupled to ground; the third terminal 223 of the isolation comparison circuit 22 is coupled to the second terminal 212 of the bandgap reference source 21.

The isolation comparing circuit 22 is configured to output a high level to enable a transmission driving circuit 23 described later when the voltage at the third terminal VDDS of the high-side selecting circuit 300 exceeds a threshold value set according to the bandgap reference voltage VREF (in particular, a threshold value set by resistance voltage division).

In one embodiment, the isolation comparison circuit 22 includes a hysteresis comparator CMP, a fifth resistor R5, and a sixth resistor R6. The output terminal of the hysteresis comparator CMP is coupled to a first terminal vddwk of the transmission driving circuit 23 described later; a second terminal (e.g., an inverting input) of the hysteresis comparator CMP is coupled to the second terminal 212 of the bandgap reference source 21. The fifth resistor R5 is coupled between the third terminal VDDS of the high-side selection circuit 300 and the first terminal (e.g., the non-inverting input terminal) of the hysteresis comparator CMP. The sixth resistor R6 is coupled between the first end of the hysteresis comparator CMP and ground.

The isolation comparing circuit 22 can set the condition of inverting the output terminal level by dividing the voltage by the fifth resistor R5 and the sixth resistor R6.

The digital transmitter 200 includes a transmission driving circuit 23. The transmission driving circuit 22 includes a first terminal vddwk, a second terminal CLK, a first output terminal 231, and a second output terminal 232. The first terminal vddiok of the transmit driver circuit 22 is coupled to the output terminal 220 of the isolation comparator circuit 22; the second terminal CLK of the transmit driver circuit 22 is coupled to the third terminal VDDS of the high-side select circuit 300.

The transmission driving circuit 23 is configured to output a differential signal; the transmission driving circuit 23 outputs a high-frequency clock signal in a differential form in response to the high-frequency oscillation clock, and provides driving capability.

In one embodiment, the transmission driving circuit 23 includes an AND gate AND, an inverter INV, AND a buffer BUF. The AND gate AND comprises a first end, a second end AND an output end; a first terminal of the AND gate AND is coupled to the output 220 of the isolation comparison circuit 22; the second terminal of the AND gate AND is coupled to the third terminal VDDS of the high-side selection circuit 300. The buffer BUF is coupled between the output of the AND gate AND the first output 231 of the transmission driving circuit 23. The inverter INV is coupled between the output of the AND gate AND the second output 232 of the transmission driving circuit 23.

In one embodiment, the digital transmitter 200 further includes a second low dropout linear regulator LDO2 and an oscillator OSC. The second LDO2 is used for generating a stable power supply voltage required by the oscillator OSC; the oscillator OSC is used for generating a high-frequency oscillation clock. The second low dropout linear regulator LDO2 and the oscillator OSC are sequentially connected in series between the third terminal VDDS of the high-side selection circuit 300 and the second terminal CLK of the transmission driving circuit 23.

In one embodiment, digital transmitter 200 further includes high pass filter circuit 24. The high-pass filter circuit 24 is for delivering the output of the transmission drive circuit 23 and providing a low-resistance bias voltage.

In a specific example, the high-pass filter circuit 24 includes a first capacitor C1 and a seventh resistor R7. The first capacitor C1 is coupled between the first output 231 of the transmission driving circuit 23 and the first circuit output TXP of the transmission circuit 13. The seventh resistor R7 is coupled between the second circuit input 12 and the first circuit output TXP.

When the digital signal Input is turned off, the transmission driving circuit 23 is not powered and presents a high-impedance state, and when the multi-channel data transmission is realized, the high-impedance state output of the transmission driving circuit 23 is interfered by the output of other transmission channels which work normally. While this specific example is based on the setting of the seventh resistor R7, the disturbance current can be effectively absorbed, and erroneous output caused by disturbance can be avoided.

In another specific example, the high-pass filter circuit 24 includes a second capacitor C2 and an eighth resistor R8. The second capacitor C2 is coupled between the second output 232 of the transmitting driving circuit 23 and the second circuit output TXN of the transmitting circuit 13. The eighth resistor R8 is coupled between the second circuit input terminal 12 and the second circuit output terminal TXN.

When the digital signal Input is turned off, the specific example is based on the setting of the seventh resistor R8, and the disturbance current can be effectively absorbed, so that erroneous output caused by disturbance can be avoided.

In a preferred embodiment, the transmitting circuit 13 provided in the present invention has the configurations of the two specific embodiments, so as to adapt to multi-channel transmission and solve the problem of crosstalk between channels.

As shown in fig. 1, 2 and 4, 5, the current loop 400 comprises a first input 411, a second input 412, a third input 421 and a fourth input 422. Wherein a first end 411 of the current loop 400 is coupled to the first circuit input 11; a second terminal 412 of the current loop 400 is coupled to the first terminal VDDS1 of the high-side selection circuit 300; a third terminal 421 of the current loop 400 is coupled to the second circuit input 12; the fourth terminal 422 of the current loop 400 is coupled to the second terminal VDDS2 of the high-side selection circuit 300. The current loop 400 includes the first current loop 41 and the second current loop 42 described above.

In one embodiment, the high-side selection circuit 300 includes a first high-side switching tube PM1, a first high-side voltage regulator tube Z1, a second high-side switching tube PM2, and a second high-side voltage regulator tube Z2.

The first high-side switching tube PM1 includes a first terminal 311, a second terminal 312, a control terminal 310, and a first body diode D1. The first end 311 of the first high-side switching tube PM1 is coupled to the second end 412 of the current loop 400; the second end 312 of the first high-side switch tube PM1 is coupled to the first end 201 of the digital transmitter 200. An input terminal of the first body diode D1 is coupled to the first terminal 311 of the first high-side switching tube PM 1; the output of the first body diode D1 is coupled to the substrate of the first high-side switching tube PM 1.

The first high-side switch tube PM1 is a P-channel field effect tube; the first end of the first high-side switch tube PM1 is the drain electrode of the P-channel field effect tube, the second end of the first high-side switch tube PM1 is the source electrode of the P-channel field effect tube, and the control end of the first high-side switch tube PM1 is the grid electrode of the P-channel field effect tube.

The first high-side regulator Z1 includes an input terminal and an output terminal. The input terminal of the first high-side regulator Z1 is coupled to the control terminal 310 of the first high-side switching tube PM1 and the fourth terminal 422 of the current loop 400, respectively, to form the second terminal VDDS2 of the high-side selection circuit 300; the output of the first high-side regulator Z1 is coupled to the first terminal 201 of the digital transmitter 200 to form the third terminal VDDS of the high-side selection circuit 300.

The breakdown voltage of the first high-side voltage stabilizing tube Z1 is greater than the threshold voltage of the first high-side switching tube PM 1.

The second high-side switching tube PM2 includes a first terminal 321, a second terminal 322, a control terminal 320, and a second body diode D2. The first end 321 of the second high-side switching tube PM2 is coupled to the fourth end 422 of the current loop 400; the second terminal 322 of the second high-side switch tube PM2 is coupled to the first terminal 201 of the digital transmitter 200. The input terminal of the second body diode D1 is coupled to the first terminal 321 of the second high-side switching tube PM 2; the output of the second body diode D1 is coupled to the substrate of the second high-side switching tube PM 2.

The second high-side switch tube PM2 is a P-channel field effect tube; the first end of the second high-side switch tube PM2 is the drain electrode of the P-channel field effect tube, the second end of the second high-side switch tube PM2 is the source electrode of the P-channel field effect tube, and the control end of the second high-side switch tube PM2 is the grid electrode of the P-channel field effect tube.

The second high-side regulator Z2 includes an input terminal and an output terminal. The input terminal of the second high-side regulator Z2 is coupled to the control terminal 320 of the second high-side switching tube PM2 and the second terminal 422 of the current loop 400, respectively, to form the first terminal VDDS1 of the high-side selection circuit 300; the output of the second high-side regulator Z2 is coupled to the first terminal 201 of the digital transmitter 200 to form the third terminal VDDS of the high-side selection circuit 300.

The breakdown voltage of the second high-side voltage stabilizing tube Z2 is greater than the threshold voltage of the second high-side switching tube PM 2.

When the first circuit Input 11 is at a high level (e.g., digital signal Input), the second circuit Input 12 is at a low level (e.g., common ground COM), the first terminal VDDS1 of the high side selection circuit 300 is at a high level, the second terminal VDDS2 of the high side selection circuit 300 is at a low level, and the first body diode D1, the first high side regulator Z1 and the resistor connected in series therewith are turned on. When the voltage drop of the first high-side voltage regulator Z1 is greater than the threshold voltage of the first high-side switch tube PM1, the first high-side switch tube PM1 is turned on to couple the first terminal VDDS1 of the high-side selection circuit 300 to the third terminal VDD of the high-side selection circuit 300.

When the first circuit Input 11 is at a low level (e.g., the common ground COM) and the second circuit Input 12 is at a high level (e.g., the digital signal Input), the first terminal VDDS1 of the high side selection circuit 300 is at a low level, the second terminal VDDS2 of the high side selection circuit 300 is at a high level, and the second body diode D2, the second high side regulator Z2 and the resistor connected in series therewith are turned on. When the voltage drop of the second high-side voltage stabilizing tube Z2 is greater than the threshold voltage of the second high-side switching tube PM2, the second high-side switching tube PM2 is turned on, and the second terminal VDDS2 of the high-side selection circuit 300 is coupled to the third terminal VDD of the high-side selection circuit 300.

In this way, the effect of coupling one of the first end VDDS1 and the second end VDDS2 coupled to the digital signal Input to the third end VDD is achieved.

In another embodiment, as shown in fig. 1, 2 and 5, the high side selection circuit 300' further includes a first high side driving pipe PM3 and a second high side driving pipe PM4.

The first high-side driving transistor PM3 includes a first terminal 331, a second terminal 332, a control terminal 330, and a third body diode D3. The first end 331 of the first high side drive tube PM3 is coupled to the fourth end 422 of the current loop 400; the second end 332 of the first high-side drive tube PM3 is coupled to the control end 310 of the first high-side switch tube PM1 and the first end 201 of the digital transmitter 200, respectively; the control terminal 330 of the first high-side driver PM3 is coupled to the input terminal of the first high-side regulator Z1. The input terminal of the third body diode D3 is coupled to the first terminal 331 of the first high-side driving transistor PM 3; the output of the third body diode D3 is coupled to the substrate of the first high-side drive transistor PM 3.

The first high-side driving tube PM3 is used to drive the control end 310 of the first high-side switching tube PM1 to accelerate the turn-on speed of the high-side selection circuit 300'.

The first high-side driving tube PM3 is a P-channel field effect tube; the first end of the first high-side driving tube PM3 is the drain electrode of the P-channel field effect tube, the second end of the first high-side driving tube PM3 is the source electrode of the P-channel field effect tube, and the control end of the first high-side driving tube PM3 is the grid electrode of the P-channel field effect tube.

The breakdown voltage of the first high-side regulator tube Z1 is greater than the threshold voltage of the first high-side driving tube PM 3.

The second high side driving transistor PM4 includes a first terminal 341, a second terminal 342, a control terminal 340, and a fourth body diode D4. The first end 341 of the second high-side driver tube PM4 is coupled to the second end 412 of the current loop 400; the second end 342 of the second high-side drive tube PM4 is coupled to the control end 320 of the second high-side switch tube PM2 and the first end 201 of the digital transmitter 200, respectively; the control terminal 340 of the second high-side driver PM4 is coupled to the input terminal of the second high-side regulator Z2. An input terminal of the fourth body diode D4 is coupled to the first terminal 341 of the second high-side driving pipe PM 4; the output of the fourth body diode D4 is coupled to the substrate of the second high-side drive tube PM 4.

The second high-side driving tube PM4 is used to drive the control end 320 of the second high-side switching tube PM2 to accelerate the turn-on speed of the high-side selection circuit 300'.

The second high-side driving tube PM4 is a P-channel field effect tube; the first end of the second high-side driving tube PM4 is the drain electrode of the P-channel field effect tube, the second end of the second high-side driving tube PM4 is the source electrode of the P-channel field effect tube, and the control end of the second high-side driving tube PM4 is the grid electrode of the P-channel field effect tube.

The breakdown voltage of the second high-side regulator tube Z2 is greater than the threshold voltage of the second high-side driving tube PM 4.

When the first circuit Input 11 is at a high level (e.g., digital signal Input), the second circuit Input 12 is at a low level (e.g., common ground COM), the first terminal VDDS1 of the high side selection circuit 300 is at a high level, the second terminal VDDS2 of the high side selection circuit 300 is at a low level, and the first body diode D1, the first high side regulator Z1 and the resistor connected in series therewith are turned on. When the voltage drop of the first high-side voltage stabilizing tube Z1 is larger than the threshold voltage of the first high-side driving tube PM3, the first high-side driving tube PM3 is conducted; when the voltage drop of the resistor at the control end 310 side of the first high-side switch tube PM1 is greater than the threshold voltage of the first high-side switch tube PM1, the first high-side switch tube PM1 is turned on to couple the first end VDDS1 of the high-side selection circuit 300 to the third end VDD of the high-side selection circuit 300.

When the first circuit Input 11 is at a low level (e.g., the common ground COM) and the second circuit Input 12 is at a high level (e.g., the digital signal Input), the first terminal VDDS1 of the high side selection circuit 300 is at a low level, the second terminal VDDS2 of the high side selection circuit 300 is at a high level, and the second body diode D2, the second high side regulator Z2 and the resistor connected in series therewith are turned on. When the voltage drop of the second high-side voltage stabilizing tube Z2 is greater than the threshold voltage of the second high-side driving tube PM4, the second high-side driving tube PM4 is turned on; when the voltage drop of the resistor at the control end 320 side of the second high-side switch tube PM2 is greater than the threshold voltage of the second high-side switch tube PM2, the second high-side switch tube PM2 is turned on to couple the second end VDDS2 of the high-side selection circuit 300 to the third end VDD of the high-side selection circuit 300. Therefore, an effect of coupling one of the first terminal VDDS1 and the second terminal VDDS2 coupled to the digital signal Input to the third terminal VDD is achieved.

As shown in fig. 1, 2, 6 and 7, the transmitting circuit 13 further includes a low-side selecting circuit 500.

The low side selection circuit 500 includes a first terminal 501, a second terminal 502, and a third terminal GND. A first terminal 501 of the low side selection circuit 500 is coupled to the first circuit input 11; a second terminal 502 of the low-side selection circuit 500 is coupled to the second circuit input 12; the third terminal GND of the low-side selection circuit 500 is coupled to the second terminal 202 of the digital transmitter 200.

The low-side selection circuit 500 is configured to; one of the first terminal 501 of the low-side selection circuit 500 and the second terminal 502 of the low-side selection circuit 500 is selected to be coupled to the common ground COM and is coupled to the third terminal GND of the low-side selection circuit 500. In this way, the second end 202 of the digital transmitter 200 is always coupled to the common ground COM, which can adapt to the condition of bi-directional signal input and can be shared to save pins.

Specifically, the bi-directional high voltage input is converted to a unidirectional high voltage output by the high side selection circuit 300 and the low side selection circuit 500 to power the digital transmitter 200. Because the high-side selection circuit 300 and the low-side selection circuit 500 share a common pin for COM input between different channels, the number of pins of the multi-channel product is effectively reduced, and the packaging cost is reduced.

The current loop 400 comprises a first input 411, a second input 412, a third input 421 and a fourth input 422. Wherein a first end 411 of the current loop 400 is coupled to the first circuit input 11; a second terminal 412 of the current loop 400 is coupled to the first terminal VDDS1 of the high-side selection circuit 300; a third terminal 421 of the current loop 400 is coupled to the second circuit input 12; the fourth terminal 422 of the current loop 400 is coupled to the second terminal VDDS2 of the high-side selection circuit 300. The current loop 400 includes the first current loop 41 and the second current loop 42 described above.

In one embodiment, the low-side selection circuit 500 includes a first low-side switching tube NM1, a first low-side voltage regulator tube Z3, a second low-side switching tube NM2, and a second low-side voltage regulator tube Z4.

The first low-side switching tube NM1 includes a first terminal 511, a second terminal 512, a control terminal 510, and a fifth body diode D5. The first end 511 of the first low-side switching tube NM1 is coupled to the first circuit input 11; the second terminal 512 of the first low-side switching tube NM1 is coupled to the second terminal 202 of the digital transmitter 200. The output terminal of the fifth body diode D5 is coupled to the first terminal 511 of the first low-side switching tube NM 1; the input terminal of the fifth body diode D5 is coupled to the substrate of the first low-side switching tube NM 1.

The first low-side switching tube NM1 is an N-channel field effect tube; the first end of the first low-side switching tube NM1 is the drain electrode of the N-channel field effect tube, the second end of the first low-side switching tube NM1 is the source electrode of the N-channel field effect tube, and the control end of the first low-side switching tube NM1 is the grid electrode of the N-channel field effect tube.

The first low-side regulator Z3 includes an input terminal and an output terminal. The output terminal of the first low-side regulator Z3 is coupled to the control terminal 510 of the first low-side switching tube NM1 and the fourth terminal 422 of the current loop 400, respectively, to the second terminal VDDS2 of the high-side selection circuit 300; an input terminal of the first low-side regulator Z3 is coupled to the second terminal 202 of the digital transmitter 200 to form the third terminal GND of the low-side selection circuit 500.

The breakdown voltage of the first low-side voltage stabilizing tube Z3 is greater than the threshold voltage of the first low-side switching tube NM 1.

The second low-side switching tube NM2 includes a first terminal 521, a second terminal 522, a control terminal 520, and a sixth body diode D6. The first end 521 of the second low-side switching tube NM2 is coupled to the second circuit input 12; a second terminal 522 of the second low-side switching tube NM2 is coupled to the second terminal 202 of the digital transmitter 200. The output terminal of the sixth body diode D6 is coupled to the first terminal 521 of the second low-side switching tube NM 2; the input terminal of the sixth body diode D6 is coupled to the substrate of the second low-side switching transistor NM 2.

The second low-side switching tube NM2 is an N-channel field effect tube; the first end of the second low-side switching tube NM2 is the drain electrode of the N-channel field effect tube, the second end of the second low-side switching tube NM2 is the source electrode of the N-channel field effect tube, and the control end of the second low-side switching tube NM2 is the grid electrode of the N-channel field effect tube.

The second low-side regulator Z4 includes an input terminal and an output terminal. The output terminal of the second low-side regulator Z4 is coupled to the control terminal 520 of the second low-side switching tube NM2 and the second terminal 422 of the current loop 400, respectively, to the first terminal VDDS1 of the high-side selection circuit 300; an input terminal of the second low-side regulator Z4 is coupled to the second terminal 202 of the digital transmitter 200 to form the third terminal VDDS of the low-side selection circuit 500.

The breakdown voltage of the second low-side voltage stabilizing tube Z4 is greater than the threshold voltage of the second low-side switching tube NM 2.

When the first circuit Input 11 is at a low level (e.g., the common ground COM) and the second circuit Input 12 is at a high level (e.g., the digital signal Input), the first terminal VDDS1 of the high side selection circuit 300 is at a low level, the second terminal VDDS2 of the high side selection circuit 300 is at a high level, and the fifth body diode D5, the first low side regulator Z3 and the resistor connected in series therewith are turned on. When the voltage drop of the first low-side voltage stabilizing tube Z3 is greater than the threshold voltage of the first low-side switching tube NM1, the first low-side switching tube NM1 is turned on, and the first terminal 501 of the low-side selecting circuit 500 is coupled to the third terminal GND of the low-side selecting circuit 500.

When the first circuit Input 11 is at a high level (e.g., digital signal Input), the second circuit Input 12 is at a low level (e.g., common ground COM), the first terminal VDDS1 of the high side selection circuit 300 is at a high level, the second terminal VDDS2 of the high side selection circuit 300 is at a low level, and the sixth body diode D6, the second low side regulator Z4 and the resistor connected in series therewith are turned on. When the voltage drop of the second low-side voltage stabilizing tube Z4 is greater than the threshold voltage of the second low-side switching tube NM2, the second low-side switching tube NM2 is turned on, and the second terminal 502 of the low-side selecting circuit 500 is coupled to the third terminal GND of the low-side selecting circuit 500.

In this way, an effect of coupling one of the first terminal 501 and the second terminal 502 thereof, which is coupled to the common ground COM, to the third terminal GND is achieved.

In another embodiment, as shown in fig. 1, 2 and 7, the low side selection circuit 500' further includes a first low side driving tube NM3 and a second low side driving tube NM4.

The first low-side driving transistor NM3 includes a first terminal 531, a second terminal 532, a control terminal 530, and a seventh body diode D7. A first end 531 of the first low side drive pipe NM3 is coupled to a fourth end 422 of the current loop 400; the second terminal 532 of the first low-side drive tube NM3 is coupled to the control terminal 510 of the first low-side switch tube NM1 and the second terminal 202 of the digital transmitter 200, respectively; the control terminal 530 of the first low-side driving transistor NM3 is coupled to the output terminal of the first low-side regulator Z3. The output terminal of the seventh body diode D7 is coupled to the first terminal 531 of the first low-side drive transistor NM 3; an input terminal of the seventh body diode D7 is coupled to the substrate of the first low-side drive transistor NM 3.

The first low-side driving transistor NM3 is used to drive the control terminal 510 of the first low-side switching transistor NM1, so as to speed up the turn-on speed of the low-side selecting circuit 500'.

The first low-side driving tube NM3 is an N-channel field effect tube; the first end of the first low-side driving tube NM3 is the drain electrode of the N-channel field effect tube, the second end of the first low-side driving tube NM3 is the source electrode of the N-channel field effect tube, and the control end of the first low-side driving tube NM3 is the grid electrode of the N-channel field effect tube.

The breakdown voltage of the first low-side regulator tube Z3 is greater than the threshold voltage of the first low-side drive tube NM 3.

The second low-side driving transistor NM4 includes a first terminal 541, a second terminal 542, a control terminal 540, and an eighth body diode D8. The first end 541 of the second low-side drive tube NM4 is coupled to the second end 412 of the current loop 400; the second terminal 542 of the second low-side driving transistor NM4 is coupled to the control terminal 520 of the second low-side switching transistor NM2 and the second terminal 202 of the digital transmitter 200, respectively; the control terminal 540 of the second low-side driving transistor NM4 is coupled to the output terminal of the second bottom regulator Z4. An output terminal of the eighth body diode D8 is coupled to the first terminal 541 of the second low-side drive tube NM 4; an input terminal of the eighth body diode D8 is coupled to the substrate of the second low-side drive transistor NM 4.

The second low-side driving transistor NM4 is used to drive the control terminal 520 of the second low-side switching transistor NM2, so as to speed up the turn-on speed of the low-side selecting circuit 500'.

The second low-side driving tube NM4 is an N-channel field effect tube; the first end of the second low-side driving tube NM4 is the drain electrode of the N-channel field effect transistor, the second end of the second low-side driving tube NM4 is the source electrode of the N-channel field effect transistor, and the control end of the second low-side driving tube NM4 is the grid electrode of the N-channel field effect transistor.

The breakdown voltage of the second low-side regulator tube Z4 is greater than the threshold voltage of the second low-side drive tube NM 4.

When the first circuit Input 11 is at a low level (e.g., the common ground COM) and the second circuit Input 12 is at a high level (e.g., the digital signal Input), the first terminal VDDS1 of the high side selection circuit 300 is at a low level, the second terminal VDDS2 of the high side selection circuit 300 is at a high level, and the fifth body diode D5, the first low side regulator Z3 and the resistor connected in series therewith are turned on. When the voltage drop of the first low-side voltage stabilizing tube Z3 is larger than the threshold voltage of the first low-side driving tube NM3, the first low-side driving tube NM3 is conducted; when the voltage drop of the resistor at the control end 510 side of the first low-side switching tube NM1 is greater than the threshold voltage of the first low-side switching tube NM1, the first low-side switching tube NM1 is turned on, and the first end 501 of the low-side selection circuit 500 is coupled to the third end GND of the low-side selection circuit 500.

When the first circuit Input 11 is at a high level (e.g., digital signal Input), the second circuit Input 12 is at a low level (e.g., common ground COM), the first terminal VDDS1 of the high side selection circuit 300 is at a high level, the second terminal VDDS2 of the high side selection circuit 300 is at a low level, and the sixth body diode D6, the second low side regulator Z4 and the resistor connected in series therewith are turned on. When the voltage drop of the second low-side voltage stabilizing tube Z4 is larger than the threshold voltage of the second low-side driving tube NM4, the second low-side driving tube NM4 is conducted; when the voltage drop of the resistor at the control end 520 side of the second low-side switching tube NM2 is greater than the threshold voltage of the second low-side switching tube NM2, the second low-side switching tube NM2 is turned on to couple the second end 502 of the low-side selecting circuit 500 to the third end GND of the low-side selecting circuit 500. Therefore, an effect of coupling one of the first and second terminals 501 and 502 coupled to the common ground COM to the third terminal GND is achieved.

In summary, the transmitting circuit and the digital isolator provided by the invention can keep that the first end side of the digital transmitter always receives the digital signal by arranging the high-side selecting circuit, so that the transmitting circuit can adapt to the working environment of bidirectional signal input; the current loop is arranged between the high-side selection circuit and the circuit input end, so that the current loop is not influenced by leakage current generated at the high-side selection circuit, and the stability of signal current output to one side of the high-side selection circuit can be maintained, so that the stability of chip working current is maintained.

It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.

The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.

Claims

1. A transmitting circuit, comprising:

a digital transmitter including a first end and a second end coupled to ground;

a high-side selection circuit comprising a first terminal (VDDS 1), a second terminal (VDDS 2), and a third terminal (VDDS) coupled to the first terminal of the digital transmitter; the high-side selection circuit is configured to select and couple one of its first and second ends coupled to the digital signal to its third end;

A current loop comprising a first terminal (411) coupled to a first circuit Input (11), a second terminal (412) coupled to a first terminal of the high-side selection circuit, configured to keep constant a signal current output by the second terminal when the first terminal thereof is coupled to the digital signal (Input); and/or comprises a third terminal (421) coupled to the input of the second circuit, a fourth terminal (422) coupled to the second terminal of the high-side selection circuit, configured to keep the signal current output from the fourth terminal constant when its third terminal is coupled to the digital signal.

2. The transmitting circuit of claim 1, wherein the current loop comprises a first end (411) coupled to the first circuit input, a second end (412) coupled to the first end of the high-side selection circuit;

the current loop comprises a first current loop (41) comprising a first operational amplifier (OPA 1), a first resistor (R1) and a first sense resistor (Rsense 1); the first sense resistor is coupled between a first end (411) of the current loop and an output of the first operational amplifier; the first resistor is coupled between a first end (411) of the current loop and a first end of the first operational amplifier; the second end of the first operational amplifier is coupled to a second end (412) whose output forms the current loop.

3. The transmitting circuit according to claim 2, characterized in that the digital transmitter comprises a bandgap reference source (21) having a first terminal (211) coupled to a third terminal (VDDS) of the high-side selection circuit; the transmitting circuit further comprises a third operational amplifier (OPA 3), a first switching tube (M1), a third resistor (R3), a third switching tube (M3) and a ninth resistor (R9); a first end of the first switching tube is coupled to a first end of the first operational amplifier, and the third resistor is coupled between a second end of the first switching tube and ground; a first end of the third switching tube is coupled to a third end (VDDS) of the high-side selection circuit, and the ninth resistor is coupled between a second end of the third switching tube and ground; the first end of the third operational amplifier is coupled to the second end (212) of the bandgap reference source, the second end is coupled to the second end of the third switching tube, and the output end is coupled to the control end of the first switching tube and the control end of the third switching tube.

4. The transmitting circuit of claim 1, wherein the current loop comprises a third terminal (421) coupled to the second circuit input, a fourth terminal (422) coupled to the second terminal of the high-side selection circuit;

The current loop comprises a second current loop (42) comprising a second operational amplifier (OPA 2), a second resistor (R2) and a second sense resistor (Rsense 2); the second sense resistor is coupled between a third terminal (421) of the current loop and an output terminal of the second operational amplifier; -the second resistor (R2) is coupled between a third terminal (421) of the current loop and a first terminal of the second operational amplifier; the second operational amplifier has its second end coupled to its output end forming a fourth end (422) of the current loop.

5. The transmitting circuit according to claim 4, characterized in that the digital transmitter comprises a bandgap reference source (21) having a first terminal (211) coupled to a third terminal (VDDS) of the high-side selection circuit; the transmitting circuit further comprises a third operational amplifier (OPA 3), a second switching tube (M2), a fourth resistor (R4), a third switching tube (M3) and a ninth resistor (R9); the first end of the second switching tube is coupled to the first end of the second operational amplifier, and the fourth resistor is coupled between the second end of the second switching tube and ground; a first end of the third switching tube is coupled to a third end (VDDS) of the high-side selection circuit, and the ninth resistor is coupled between a second end of the third switching tube and ground; the first end of the third operational amplifier is coupled to the second end (212) of the bandgap reference source, the second end is coupled to the second end of the third switching tube, and the output end is coupled to the control end of the second switching tube and the control end of the third switching tube.

6. The transmitting circuit of claim 1, wherein the digital transmitter further comprises:

a bandgap reference source (21) comprising a second terminal (212), and a first terminal (211) coupled to a third terminal (VDDS) of the high-side selection circuit;

an isolation comparison circuit (22) comprising an output (220), and a first terminal (221) coupled to a third terminal (VDDS) of the high-side selection circuit, a second terminal (222) coupled to ground, a third terminal (223) coupled to a second terminal (212) of the bandgap reference source;

a transmit drive circuit (23) comprising a first output (231), a second output (232), and a first terminal (vddwk) coupled to the output (220) of the isolation comparison circuit, and a second terminal (CLK) coupled to the third terminal (VDDS) of the high-side selection circuit.

7. The transmitting circuit of claim 6, wherein the digital transmitter further comprises a high pass filter circuit (24), the high pass filter circuit comprising:

a first capacitor (C1) coupled between the first output (231) of the transmit driver circuit and the first circuit output (TXP) of the transmit circuit, a seventh resistor (R7) coupled between the second circuit input (12) and the first circuit output (TXP); and/or the number of the groups of groups,

A second capacitor (C2) coupled between the second output (232) of the transmit driver circuit and the second circuit output (TXN) of the transmit circuit, and an eighth resistor (R8) coupled between the second circuit input (12) and the second circuit output (TXN).

8. The transmitting circuit of claim 6, wherein the Bandgap reference source comprises a first low dropout linear regulator (LDO 1) and a Bandgap reference voltage source (Bandgap) connected in series between a first end (211) thereof and a second end (212) thereof;

the isolation comparison circuit comprises a hysteresis Comparator (CMP), a fifth resistor (R5) and a sixth resistor (R6), wherein the output end of the hysteresis comparator is coupled to the first end (VDDOK) of the transmission driving circuit, and the second end of the hysteresis comparator is coupled to the second end (212) of the band gap reference source; the fifth resistor (R5) is coupled between the third terminal (VDDS) of the high-side selection circuit and the first terminal of the hysteresis comparator, and the sixth resistor is coupled between the first terminal of the hysteresis comparator and ground;

the transmission driving circuit includes an AND gate (AND), an Inverter (INV), AND a Buffer (BUF); the AND gate includes a first terminal coupled to an output terminal (220) of the isolation comparison circuit, a second terminal coupled to a third terminal (VDDS) of the high-side selection circuit; the buffer is coupled between the output end of the AND gate and the first output end (231) of the transmission driving circuit, and the inverter is coupled between the output end of the AND gate and the second output end (232) of the transmission driving circuit;

The digital transmitter further includes a second low dropout linear regulator (LDO 2) and an Oscillator (OSC) connected in series between a third terminal (VDDS) of the high side selection circuit and a second terminal (CLK) of the transmit driver circuit.

9. The transmitting circuit of claim 1, wherein the current loop comprises a first terminal (411) coupled to the first circuit input, a second terminal (412) coupled to the first terminal of the high-side selection circuit, a third terminal (421) coupled to the second circuit input, a fourth terminal (422) coupled to the second terminal of the high-side selection circuit;

the high-side selection circuit includes:

a first high-side switching tube (PM 1) comprising a control terminal (310), a first body diode (D1), and a first terminal (311) coupled to a second terminal (412) of the current loop, a second terminal (312) coupled to a first terminal (201) of the digital transmitter; an input end of the first body diode is coupled to a first end of the first high-side switching tube, and an output end of the first body diode is coupled to a substrate of the first high-side switching tube;

a first high-side regulator tube (Z1) comprising an input coupled to a control terminal (310) of the first high-side switching tube and a fourth terminal (422) of the current loop, respectively, and an output coupled to a first terminal (201) of the digital transmitter;

A second high side switching tube (PM 2) comprising a control terminal (320), a second body diode (D2), and a first terminal (321) coupled to a fourth terminal (422) of the current loop, a second terminal (322) coupled to a first terminal (201) of the digital transmitter; the input end of the second body diode is coupled to the first end of the second high-side switching tube, and the output end of the second body diode is coupled to the substrate of the second high-side switching tube;

a second high-side regulator tube (Z2) comprising an input coupled to the control terminal (320) of the second high-side switching tube and the second terminal (412) of the current loop, respectively, and an output coupled to the first terminal (201) of the digital transmitter.

10. The transmitting circuit of claim 9, wherein the high-side selection circuit comprises:

a first high-side drive tube (PM 3) comprising a third body diode (D3), and a first end (331) coupled to a fourth end (422) of the current loop, a second end (332) coupled to a control end (310) of the first high-side switch tube and a first end (201) of the digital transmitter, respectively, a control end (330) coupled to an input end of the first high-side regulator tube (Z1); -an input of the third body diode (D3) is coupled to a first end (331) of the first high-side drive tube, an output is coupled to a substrate of the first high-side drive tube;

A second high-side drive tube (PM 4) comprising a fourth body diode (D4), and a first terminal (341) coupled to a second terminal (412) of the current loop, a second terminal (342) coupled to a control terminal (320) of the second high-side switch tube and a first terminal (301) of the digital transmitter, respectively, a control terminal (340) coupled to an input terminal of the second high-side regulator tube (Z2); an input terminal of the fourth body diode (D4) is coupled to a first terminal (341) of the second high-side drive tube and an output terminal is coupled to a substrate of the second high-side drive tube.

11. The transmission circuit according to claim 1, characterized in that the transmission circuit further comprises:

a low-side selection circuit (500) comprising a first terminal (501) coupled to the first circuit input (11), a second terminal (502) coupled to the second circuit input (12), a third terminal (GND) coupled to the second terminal (202) of the digital transmitter; the low-side selection circuit is configured to select and couple one of its first (501) and second (502) terminals coupled to a common ground to its third terminal (GND).

12. The transmitting circuit of claim 11, wherein the current loop includes a first terminal (411) coupled to the first circuit input, a second terminal (412) coupled to the first terminal of the high-side selection circuit, a third terminal (421) coupled to the second circuit input, and a fourth terminal (422) coupled to the second terminal of the high-side selection circuit;

The low-side selection circuit (500) includes:

a first low-side switching tube (NM 1) comprising a control terminal (510), a fifth body diode (D5), and a first terminal (511) coupled to said first circuit input (11), a second terminal (512) coupled to the second terminal (202) of the digital transmitter; an output terminal of the fifth body diode (D5) is coupled to a first terminal (511) of the first low-side switching tube, and an input terminal is coupled to a substrate of the first low-side switching tube;

a first low-side regulator tube (Z3) comprising an output coupled to a control terminal (510) of the first low-side switching tube and a fourth terminal (422) of the current loop, respectively, and an input coupled to a second terminal (202) of the digital transmitter;

a second low-side switching tube (NM 2) comprising a control terminal (520), a sixth body diode (D6), and a first terminal (521) coupled to said second circuit input (12), a second terminal (522) coupled to the second terminal (202) of the digital transmitter; an output terminal of the sixth body diode (D6) is coupled to a first terminal (521) of the second low-side switching tube, and an input terminal is coupled to a substrate of the second low-side switching tube;

a second low-side regulator tube (Z4) comprising an output coupled to the control terminal (520) of the second low-side switching tube and the second terminal (412) of the current loop, respectively, and an input coupled to the second terminal (202) of the digital transmitter.

13. The transmitting circuit of claim 12, wherein the low-side selection circuit comprises:

a first low-side drive tube (NM 3) comprising a seventh body diode (D7), and a first end (531) coupled to a fourth end (422) of the current loop, a second end (532) coupled to a control end (510) of the first low-side switch tube and a second end (202) of the digital transmitter, respectively, a control end (530) coupled to an output end of the first low-side regulator tube (Z3); an output of the seventh body diode (D7) is coupled to the first end (531) of the first low-side drive pipe, and an input is coupled to the substrate of the first low-side drive pipe;

a second low-side drive tube (NM 4) comprising an eighth body diode (D8), and a first terminal (541) coupled to the second terminal (412) of the current loop, a second terminal (542) coupled to the control terminal (520) of the second low-side switch tube and the second terminal (202) of the digital transmitter, respectively, and a control terminal (540) coupled to the output terminal of the second low-side regulator tube (Z4); an output of the eighth body diode (D8) is coupled to a first end (541) of the second low-side drive tube and an input is coupled to the second low-side driven substrate.

14. A digital isolator comprising a receiving circuit, an isolation capacitor, and a transmitting circuit as claimed in any one of claims 1 to 13.