CN117291145A - Verification method and system of system on chip and electronic device - Google Patents
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Abstract
The application relates to a verification method, a verification system and an electronic device of a system on a chip, wherein the verification method comprises the following steps: generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequencer code and a reference model code which are logically corresponding to each other; simulating the system on chip based on the embedded C code and the sequencer code to obtain target simulation data; generating reference data based on the reference model code; comparing the target simulation data with the reference data, and obtaining a target verification result aiming at the system-on-chip based on the comparison result; according to the embodiment, the embedded C codes are introduced into the test vector, and verification of the system-level functions above the bus is realized besides verifying each function IP module in the system-on-chip, so that the problem of low verification efficiency of the system-on-chip in the related technology is solved, and the verification efficiency of the system-on-chip is improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit verification, and in particular, to a method, a system, and an electronic device for verifying a system on a chip.
Background
With the rapid development of semiconductor technology, the design and manufacture of Integrated Circuits (ICs), particularly the design and manufacture of system on a chip (SoC), is becoming more and more complex, and verification is becoming a key element in the integrated circuit industry.
The main purpose of verification is to verify whether the functions of all aspects of the chip meet the design requirements, wherein the establishment of a verification platform and the writing of test vectors are the core of chip verification. By constructing a verification platform, a verification environment capable of interacting with the design to be tested is constructed, excitation constraint is applied to the design to be tested by using the test vector, and verification is further implemented. In the prior art, a verification platform is generally constructed by using a general verification theory UVM (Universal Verification Methodology) introduced in 2011, and a test vector for verification is independently written by a verification engineer in combination with specific requirements. However, the conventional chip verification method is usually performed for each functional module in the chip, but the verification method for the system on chip is not perfect enough, so that verification is difficult to be directly realized from the system level, and the writing difficulty of the test vector is high, so that the verification efficiency is low.
Aiming at the problem of low verification efficiency of a system on a chip in the related art, no effective solution is proposed at present.
Disclosure of Invention
In this embodiment, a method, a system and an electronic device for verifying a system on a chip are provided, so as to solve the problem of low verification efficiency of the system on a chip in the related art.
In a first aspect, in this embodiment, there is provided a method for verifying a system on a chip, including:
generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequence generator code and a reference model code, and the logic of the embedded C code, the logic of the sequence generator code and the logic of the reference model code are corresponding;
simulating a design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested, wherein the design to be tested is a system on chip;
generating reference data based on the reference model code;
and comparing the target simulation data with the reference data, and obtaining a target verification result aiming at the design to be tested based on a comparison result.
In some embodiments, the generating the test vector for verification according to the preset parameter configuration file and the code template file includes:
acquiring parameter configuration information based on the parameter configuration file;
acquiring an embedded C template, a sequencer template and a reference model template based on the code template file;
generating the embedded C code based on the embedded C template and the parameter configuration information;
generating the sequencer code based on the sequencer template and the parameter configuration information;
and generating the reference model code based on the reference model template and the parameter configuration information.
In some embodiments, the simulating the design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested includes:
generating an excitation signal based on the sequencer code;
and under the action of the excitation signal, operating the embedded C code based on the design to be tested to obtain the target simulation data generated by operation.
In a second aspect, in this embodiment, there is provided a verification system of a system on a chip, the verification system including a test vector generation component, an external signal component, and a verification control component, wherein:
the test vector generation component is used for generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequencer code and a reference model code, and the logic of the embedded C code, the logic of the sequencer code and the logic of the reference model code are corresponding;
the external signal component is used for simulating a design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested; generating reference data based on the reference model code; wherein the design to be tested is a system on chip;
the verification control component is used for comparing the target simulation data with the reference data and obtaining a target verification result aiming at the design to be tested based on a comparison result.
In some of these embodiments, the verification system further comprises a top-level design component; the top layer design component is connected with the external signal component and the verification control component;
the top layer design component is used for providing a signal interface, a system clock and a reset signal; and for instantiating each of the components in the verification system;
the top-level design component is implemented based on classes in the UVM verification methodology.
In some embodiments thereof, the test vector generation component includes a first acquisition module, a second acquisition module, a first generation module, a second generation module, and a third generation module, wherein:
the first acquisition module is used for acquiring parameter configuration information based on the parameter configuration file;
the second acquisition module is used for acquiring an embedded C language template, a sequencer template and a reference model template based on the code template file;
the first generation module is used for generating the embedded C code based on the embedded C language template and the parameter configuration information;
the second generating module is used for generating the sequence generator code based on the sequence generator template and the parameter configuration information;
the third generation module is used for generating the reference model code based on the reference model template and the parameter configuration information.
In some of these embodiments, the external signal component comprises a proxy module comprising a sequencer, a driver, a monitor, and a reference model, wherein:
the sequencer is used for generating an excitation transaction according to the sequencer code and transmitting the excitation transaction to the driver;
the driver is used for converting the excitation transaction into the excitation signal and sending the excitation signal to the design to be tested;
the monitor is used for collecting a response signal from the design to be tested, converting the response signal into a response transaction and sending the response transaction to the verification control component;
the reference model is used for generating a reference transaction based on the reference model agent and sending the reference transaction to the verification control component.
In some of these embodiments, the verification control component includes a scoreboard;
the score board is used for comparing the target simulation data in the response signal with the reference data in the reference transaction, and obtaining the target verification result according to a comparison result.
In a third aspect, in this embodiment, there is provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the verification method of the system-on-chip described in the first aspect when the processor executes the computer program.
In a fourth aspect, in this embodiment, there is provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the verification method of the system-on-chip described in the first aspect.
Compared with the related art, the verification method of the system on chip provided in the embodiment generates a test vector for verification according to the preset parameter configuration file and the code template file, wherein the test vector comprises an embedded C code, a sequencer code and a reference model code, and the logic of the embedded C code, the sequencer code and the reference model code correspond to each other; simulating a to-be-tested design based on the embedded C code and the sequencer code to obtain target simulation data of the to-be-tested design, wherein the to-be-tested design is a system on chip; generating reference data based on the reference model code; the target simulation data and the reference data are compared, and a target verification result aiming at the design to be tested is obtained based on the comparison result, so that the problem of low verification efficiency of the system on chip in the related technology is solved, and the verification efficiency of the system on chip is improved.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a hardware configuration block diagram of a terminal of the verification method of the system-on-chip of the present embodiment;
fig. 2 is a flowchart of a verification method of the system on chip of the present embodiment;
FIG. 3 is a flow chart of a test vector generation method for system-on-chip verification of the present embodiment;
fig. 4 is a schematic structural diagram of a verification system of the system-on-chip of the present embodiment;
FIG. 5 is a schematic diagram of the structure of the test vector generation module of the present embodiment;
fig. 6 is a schematic structural diagram of a verification platform to which the verification method of the system-on-chip of the present embodiment is applied.
Detailed Description
For a clearer understanding of the objects, technical solutions and advantages of the present application, the present application is described and illustrated below with reference to the accompanying drawings and examples.
Unless defined otherwise, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and the like in this application are not intended to be limiting in number, but rather are singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used in the present application, are intended to cover a non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this application, merely distinguish similar objects and do not represent a particular ordering of objects.
The method embodiments provided in the present embodiment may be executed in a terminal, a computer, or similar computing device. For example, running on a terminal, fig. 1 is a block diagram of the hardware structure of the terminal of the verification method of the system-on-chip of the present embodiment. As shown in fig. 1, the terminal may include one or more (only one is shown in fig. 1) processors 102 and a memory 104 for storing data, wherein the processors 102 may include, but are not limited to, a microprocessor MCU, a programmable logic device FPGA, or the like. The terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and is not intended to limit the structure of the terminal. For example, the terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to the verification method of the system-on-chip in the present embodiment, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-described method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. The network includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
In this embodiment, a verification method of a system on chip is provided, fig. 2 is a flowchart of the verification method of the system on chip of this embodiment, and as shown in fig. 2, the flowchart includes the following steps:
step S201, generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequence generator code and a reference model code, and logic of the embedded C code, the sequence generator code and the reference model code correspond to each other.
Specifically, the test vectors are a set of test inputs, execution conditions, and expected results written for an integrated circuit design to be verified, i.e., a design under test (Design Under Test, simply DUT), according to design requirements and design principles, for verifying whether the design under test meets the design requirements. The verification method provided by the embodiment can efficiently generate the test vector, and the test vector comprises three parts, namely an embedded C code, a sequencer code and a reference model code. And (3) pre-writing a code template file, and generating an embedded C code, a sequence generator code and a reference model code by an automatic script program according to the embedded C template, the sequence generator template and the reference model template in the code template and combining parameter configuration information in the parameter configuration file. The embedded C code is written by a C language or an embedded assembly language, has a complete embedded architecture and an automatic compiling file (Makefile), can finish program generation and construction by a single command, and generates a target file required by simulation loading.
Step S202, based on the embedded C code and the sequencer code, simulating the design to be tested to obtain target simulation data of the design to be tested, wherein the design to be tested is a system on chip.
Specifically, the present embodiment uses a complete System on Chip (SoC) as a design to be tested for verification, where the System on Chip includes a System reset management unit, a System clock management unit, a System power consumption management unit, a central processing unit, a bus matrix, a storage unit, and a plurality of functional IP modules, where the central processing unit is connected to the storage unit and the functional IP module unit through the bus matrix. And applying excitation to the design to be tested by the embedded C code and the sequencer code in the test vector together to obtain simulation operation data of the design to be tested under excitation, namely target simulation data.
Related art generally implements verification on a system on chip based on a general verification methodology (Universal Verification Methodology, abbreviated as UVM), where UVM is a verification platform development framework based on a SystemVerilog library, and a verification engineer can use reusable components thereof to construct a functional verification environment with a standardized hierarchical structure and an interface, which is currently the most advantageous verification method.
The verification based on UVM uses the sequence signal generated by the sequence generator as excitation, the signal is transmitted to each functional IP module of the system on chip through a bus, and then each functional IP module is used as a design to be tested to respectively verify the module level. For example, a universal asynchronous receiver/Transmitter (UART) module in a system-on-chip is verified with a bus signal and an external I/O signal as stimuli. However, such verification methods can only verify the functional IP block itself, and cannot verify the portion above the bus in the system-on-chip. In this embodiment, after the embedded C code in the test vector is instantiated, the signal input excitation transmitted through the bus is not needed, but the embedded C code can directly run on the whole system on chip, so that excitation can be applied to each part of the system on chip, and on the basis of the verification function IP module, the embedded C code also covers the system level units and functions such as the central processor unit, the bus matrix connection and the like above the bus in the system on chip.
Step S203, generating reference data based on the reference model code.
Specifically, the reference model code generates reference data, which is an ideal expected result of a designer on the design under test running under test vector stimulus, by simulating the logic behavior of the design under test.
Step S204, comparing the target simulation data with the reference data, and obtaining a target verification result for the design to be tested based on the comparison result.
Specifically, by comparing the target simulation data with the reference data, the degree of conformity between the design to be tested and the design requirement can be judged, and the higher the similarity between the target simulation data and the reference data is, the more the design to be tested meets the design requirement, and further, the target verification result aiming at the design to be tested can be obtained by specifically quantifying the similarity between the target simulation data and the reference data in combination with the set quantification standard.
Through the steps S201 to S204, a test vector for verification is generated according to a preset parameter configuration file and a code template file, wherein the test vector includes an embedded C code, a sequencer code and a reference model code, and the logic of the embedded C code, the sequencer code and the reference model code correspond to each other; simulating a to-be-tested design based on the embedded C code and the sequencer code to obtain target simulation data of the to-be-tested design, wherein the to-be-tested design is a system on chip; generating reference data based on the reference model code; comparing the target simulation data with the reference data, and obtaining a target verification result aiming at the design to be tested based on the comparison result; according to the embodiment, the embedded C codes are introduced into the test vector, and after being instantiated, the embedded C codes directly act on the whole system on chip, and besides verifying each function IP module in the system on chip, verification of system-level functions such as a central processor unit over a bus and bus matrix connection is realized, so that the problem of low verification efficiency of the system on chip in the related art is solved, and the verification efficiency of the system on chip is improved.
Fig. 3 is a flowchart of a test vector generation method for system-on-chip verification in the present embodiment, as shown in fig. 3, in some embodiments, based on the above step S201, a test vector for verification is generated according to a preset parameter configuration file and a code template file, which may specifically include:
step S301, acquiring parameter configuration information based on a parameter configuration file; acquiring an embedded C template, a sequencer template and a reference model template based on the code template file; step S302, generating an embedded C code based on the embedded C template and the parameter configuration information; step S303, generating a sequence generator code based on the sequence generator template and the parameter configuration information; step S304, generating a reference model code based on the reference model template and the parameter configuration information.
The code template file is a pre-written atomic code template, and contains code segments aiming at specific functional IP modules, and all the systems on a chip using the same functional IP module can be verified by using the corresponding code segments. The atomic code templates include an embedded C template, a sequencer template, and a reference model template. The sequencer templates describe how to generate one or more transactions, supporting various logical code blocks of the System Verilog grammar; describing how to generate one or more transactions with reference to a model template, supporting various logical code blocks of a System Verilog grammar; systemVerilog is an industry standard language that combines hardware description language (Hardware Description Language, abbreviated HDL) with modern high level verification language (HVL) to integrate object oriented programming, dynamic threading, and inter-thread communications.
The embedded C-template implements each code segment capable of performing an independent operation, each code segment having a correspondence to a transaction described in the sequencer. In addition, the self-owned transaction class and the driver class are defined in the atomic code template; the driver may translate the transaction object into a signal or vice versa.
The parameter configuration file takes xml specification as a basic format to respectively describe parameter configuration information required by a column generator template, a reference model template and an embedded C template; the sequencer parameter configuration information comprises the type of the transaction to be generated and the matched parameters thereof; the reference model description comprises the types of the transactions needing to be generated and matched parameters thereof; the embedded C code description comprises a code segment to be generated and a matching parameter thereof; in addition, the sequencer templates and the embedded C templates have common configuration parameters, and the number and types of the parameters are not fixed.
The form of the parameter configuration information may include: integer, 32 bit integer, generally used for cycle number description, communication data length description, etc.; floating point, single precision floating point numbers, are commonly used as computational data, etc.; random numbers, randomly generated 32-bit integers, are generally used for generating communication data or generating register configuration values; binary parameters, which are generally used for logic judgment parameters; character strings, namely Chinese and English character string information; data packets, i.e. single parameters formed by a combination of various elementary data types.
Generating an embedded C code based on the embedded C template and the parameter configuration information by running an automatic script program; generating a sequencer code based on the sequencer template and the parameter configuration information; generating a reference model code based on the reference model template and the parameter configuration information; and copying the generated three types of verification codes into the designated vector preservation path according to the vector name and the related naming rule. Wherein the automation script program is implemented by a mainstream interpreted language, and is not specifically limited herein.
Preferably, in one embodiment, the configuration field information in the parameter configuration file is obtained by using an xml file manager; further, checking whether the original subcode template mark information in the configuration file field is matched with the command parameters, and if the original subcode template mark information is not matched with the command parameters, generating failure; analyzing a sequencer template, a reference model template and an embedded C template; positioning the template content of each atomic code segment according to the template keywords; generating a sequencer code, a reference model code, and an embedded C code for the sequencer template, the reference model template, and the embedded C template, respectively.
Specifically, according to the atomic code segment information in the parameter setting information, a corresponding template code is found, and the parameter field content is replaced according to the parameter keywords; the atomic code segment in the parameter setting information has a repeat key (repeat), and repeatedly generates the code segment according to the repeat times; when the parameters are randomly configured, the desired content is randomly generated using a random function. After all the atom code information in each atom template file generates an atom code, storing the newly generated file into a temporary directory and a file; after all the atomic template files finish code generation, the generated files are copied into a test vector path appointed by the command line parameters in a unified mode according to industry naming rules.
Further, in some embodiments, according to the step S202, based on the embedded C code and the sequencer code, the simulation is performed on the design to be tested to obtain target simulation data of the design to be tested, which may specifically include:
based on the sequencer code, generating an excitation signal, which can be converted into an excitation transaction by invoking a driver class; under the action of the excitation signal, the embedded C code is operated based on the design to be tested, and the target simulation data generated by operation is obtained.
Also provided in the present embodiment is a verification system of a system on chip, fig. 4 is a schematic structural diagram of the verification system of the system on chip of the present embodiment, as shown in fig. 4, the verification system includes a test vector generation component 41, an external signal component 42, and a verification control component 43, wherein:
the test vector generation component 41 is configured to generate a test vector for verification according to a preset parameter configuration file and a code template file, where the test vector includes an embedded C code, a sequencer code, and a reference model code, and logic of the embedded C code, the sequencer code, and the reference model code correspond to each other;
the external signal component 42 is used for simulating the design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested; generating reference data based on the reference model code; wherein the design to be tested is a system on chip;
the verification control component 43 is configured to compare the target simulation data with the data under test, and obtain a target verification result for the design under test based on the comparison result.
In addition, the verification system also includes a top-level design component; the top layer design component is connected with the external signal component and the verification control component; the top layer design component is used for providing a signal interface, a system clock and a reset signal; also used for each component in the example certification system; the top-level design component is implemented based on classes in the UVM verification methodology. For example, the class responsible for instantiating and connecting all functional components derives from the environmental class UVM _env in UVM.
Further, fig. 5 is a schematic structural diagram of a test vector generating component of the present embodiment, and as shown in fig. 5, the test vector generating component includes a first obtaining module 51, a second obtaining module 52, a first generating module 53, a second generating module 54, and a third generating module 55, where:
the first obtaining module 51 is configured to obtain parameter configuration information based on the parameter configuration file; the second obtaining module 52 is configured to obtain an embedded C language template, a sequencer template, and a reference model template based on the code template file; the first generation module 53 is configured to generate an embedded C code based on the embedded C language template and the parameter configuration information; the second generating module 54 is configured to generate a sequencer code based on the sequencer template and the parameter configuration information; the third generation module 55 is configured to generate a reference model code based on the reference model template and the parameter configuration information.
Further, the external signal component of the present embodiment includes a proxy module including a sequencer, a driver, a monitor, and a reference model, wherein:
the sequencer is used for generating an excitation transaction according to the sequencer code and transmitting the excitation transaction to the driver; the driver is used for converting the excitation transaction into an excitation signal and sending the excitation signal to the design to be tested; the monitor is used for collecting a response signal from the design to be tested, converting the response signal into a response transaction, and sending the response transaction to the verification control component; the reference model is used to generate a reference transaction based on the reference model proxy and send the reference transaction to the validation control component.
Further, the verification control assembly comprises a score board; the score board is used for comparing the target simulation data in the response signal with the reference data in the reference transaction and obtaining a target verification result according to the comparison result.
The above-described respective modules may be functional modules or program modules, and may be implemented by software or hardware. For modules implemented in hardware, the various modules described above may be located in the same processor; or the above modules may be located in different processors in any combination.
In particular, fig. 6 is a schematic structural diagram of a verification platform applying the verification method of the system-on-chip of the present embodiment, and as shown in fig. 6, the verification platform includes a control UVC, an external signal UVC, and a design under test; the UVC control comprises a score board, a virtual sequence generator and parameter configuration; the external signal UVC comprises an input agent and an output agent, the input agent comprises a sequencer, a driver and a monitor, and the output agent has the same structure as the input agent; the design to be tested comprises a memory and a peripheral interface. Wherein UVC refers to the component interacting with external signals based on the USB Video Class protocol.
As shown by the arrow in fig. 6, the embedded C code and the software assembly environment are loaded into the memory of the design under test; the peripheral interface in the design to be tested sends the signal of the design to be tested to an external signal UVC, and the external signal UVC sends the transaction to control UVC; the virtual sequence generator in the UVC is controlled to send the verification sequence to the external signal UVC.
There is also provided in this embodiment an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Alternatively, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequence generator code and a reference model code, and the logic of the embedded C code, the logic of the sequence generator code and the logic of the reference model code are corresponding;
s2, simulating a design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested, wherein the design to be tested is a system on chip;
s3, generating reference data based on the reference model code;
s4, comparing the target simulation data with the reference data, and obtaining a target verification result aiming at the design to be tested based on the comparison result.
It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.
In addition, in combination with the verification method of the system on chip provided in the above embodiment, a storage medium may be provided in this embodiment. The storage medium has a computer program stored thereon; the computer program, when executed by a processor, implements a method of authenticating a system on a chip of any of the above embodiments.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present application, are within the scope of the present application in light of the embodiments provided herein.
It is evident that the drawings are only examples or embodiments of the present application, from which the present application can also be adapted to other similar situations by a person skilled in the art without the inventive effort. In addition, it should be appreciated that while the development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as an admission of insufficient detail.
The term "embodiment" in this application means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A method of verifying a system-on-chip, comprising:
generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequence generator code and a reference model code, and the logic of the embedded C code, the logic of the sequence generator code and the logic of the reference model code are corresponding;
simulating a design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested, wherein the design to be tested is a system on chip;
generating reference data based on the reference model code;
and comparing the target simulation data with the reference data, and obtaining a target verification result aiming at the design to be tested based on a comparison result.
2. The method for verifying a system on a chip according to claim 1, wherein the generating a test vector for verification according to a preset parameter configuration file and a code template file comprises:
acquiring parameter configuration information based on the parameter configuration file;
acquiring an embedded C template, a sequencer template and a reference model template based on the code template file;
generating the embedded C code based on the embedded C template and the parameter configuration information;
generating the sequencer code based on the sequencer template and the parameter configuration information;
and generating the reference model code based on the reference model template and the parameter configuration information.
3. The method for verifying a system-on-chip according to claim 2, wherein the simulating the design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested comprises:
generating an excitation signal based on the sequencer code;
and under the action of the excitation signal, operating the embedded C code based on the design to be tested to obtain the target simulation data generated by operation.
4. A verification system of a system-on-chip, the verification system comprising a test vector generation component, an external signal component, and a verification control component, wherein:
the test vector generation component is used for generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequencer code and a reference model code, and the logic of the embedded C code, the logic of the sequencer code and the logic of the reference model code are corresponding;
the external signal component is used for simulating a design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested; generating reference data based on the reference model code; wherein the design to be tested is a system on chip;
the verification control component is used for comparing the target simulation data with the reference data and obtaining a target verification result aiming at the design to be tested based on a comparison result.
5. The system-on-chip verification system of claim 4, further comprising a top-level design component; the top layer design component is connected with the external signal component and the verification control component;
the top layer design component is used for providing a signal interface, a system clock and a reset signal; and for instantiating each of the components in the verification system;
the top-level design component is implemented based on classes in the UVM verification methodology.
6. The system-on-chip verification system of claim 4, wherein the test vector generation component comprises a first acquisition module, a second acquisition module, a first generation module, a second generation module, and a third generation module, wherein:
the first acquisition module is used for acquiring parameter configuration information based on the parameter configuration file;
the second acquisition module is used for acquiring an embedded C language template, a sequencer template and a reference model template based on the code template file;
the first generation module is used for generating the embedded C code based on the embedded C language template and the parameter configuration information;
the second generating module is used for generating the sequence generator code based on the sequence generator template and the parameter configuration information;
the third generation module is used for generating the reference model code based on the reference model template and the parameter configuration information.
7. The system-on-chip verification system of claim 6, wherein the external signal component comprises a proxy module comprising a sequencer, a driver, a monitor, and a reference model, wherein:
the sequencer is used for generating an excitation transaction according to the sequencer code and transmitting the excitation transaction to the driver;
the driver is used for converting the excitation transaction into an excitation signal and sending the excitation signal to the design to be tested;
the monitor is used for collecting a response signal from the design to be tested, converting the response signal into a response transaction and sending the response transaction to the verification control component;
the reference model is used for generating a reference transaction based on the reference model agent and sending the reference transaction to the verification control component.
8. The system-on-chip verification system of claim 7, wherein the verification control component comprises a scoreboard;
the score board is used for comparing the target simulation data in the response signal with the reference data in the reference transaction, and obtaining the target verification result according to a comparison result.
9. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of verification of a system on chip as claimed in any one of claims 1 to 3.
10. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the verification method of a system on chip of any one of claims 1 to 3.
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