CN117291145A - Verification method and system of system on chip and electronic device - Google Patents

Abstract

The present application relates to a system-on-chip verification method, system and electronic device, wherein the verification method includes: generating a test vector for verification based on a preset parameter configuration file and a code template file, wherein the test vector contains logic The corresponding embedded C code, sequencer code and reference model code; based on the embedded C code and sequencer code, simulate the on-chip system to obtain the target simulation data; based on the reference model code, generate reference data; The target simulation data is compared with the reference data, and the target verification results for the on-chip system are obtained based on the comparison results; this embodiment introduces embedded C code into the test vector, and in addition to verifying each functional IP module in the on-chip system, it also implements It verifies the system-level functions above the bus, thereby solving the problem of low verification efficiency of the system-on-chip in related technologies and improving the verification efficiency of the system-on-chip.

Description

System-on-chip verification method, system and electronic device

Technical field

The present application relates to the field of integrated circuit verification, and in particular to verification methods, systems and electronic devices for systems on a chip.

Background technique

With the rapid development of semiconductor technology, the design and manufacturing of integrated circuits (ICs), especially the design and manufacturing of systems on a chip (SoC), are becoming more and more complex, and verification has gradually become a key link in the integrated circuit industry.

The main purpose of verification is to check whether all aspects of the chip's functions meet the design requirements. Among them, the construction of the verification platform and the writing of test vectors are the core of chip verification. By building a verification platform, we build a verification environment that can interact with the design under test, and use test vectors to impose incentive constraints on the design under test, and then implement verification. In the existing technology, the Universal Verification Methodology (UVM) launched in 2011 is usually used to build a verification platform, and the test vectors used for verification are written independently by verification engineers based on specific needs. However, existing chip verification methods are usually conducted for each functional module in the chip, while the verification method for the system-on-chip is not perfect enough, making it difficult to directly implement verification from the system level, and it is difficult to write test vectors, which leads to verification problems. Less efficient.

Regarding the problem of low verification efficiency of system-on-chip in related technologies, no effective solution has been proposed yet.

Contents of the invention

This embodiment provides a system-on-chip verification method, system, and electronic device to solve the problem of low verification efficiency of system-on-chip in related technologies.

In the first aspect, this embodiment provides a system-on-chip verification method, including:

According to the preset parameter configuration file and code template file, a test vector for verification is generated, wherein the test vector contains embedded C code, sequencer code and reference model code. The embedded C code, all The logic of the sequence generator code and the reference model code corresponds;

Based on the embedded C code and the sequencer code, the design under test is simulated to obtain target simulation data of the design under test, where the design under test is a system on a chip;

Generate reference data based on the reference model code;

The target simulation data is compared with the reference data, and a target verification result for the design under test is obtained based on the comparison result.

In some embodiments, generating test vectors for verification based on preset parameter configuration files and code template files includes:

Obtain parameter configuration information based on the parameter configuration file;

Based on the code template file, obtain the embedded C template, sequencer template and reference model template;

Generate the embedded C code based on the embedded C template and the parameter configuration information;

Generate the sequencer code based on the sequencer template and the parameter configuration information;

The reference model code is generated based on the reference model template and the parameter configuration information.

In some embodiments, the design under test is simulated based on the embedded C code and the sequencer code to obtain target simulation data of the design under test, including:

generating an excitation signal based on the sequencer code;

Under the action of the excitation signal, the embedded C code is run based on the design to be tested, and the target simulation data generated by the operation is obtained.

In the second aspect, this embodiment provides a system-on-chip verification system, which includes a test vector generation component, an external signal component, and a verification control component, wherein:

The test vector generation component is used to generate a test vector for verification according to the preset parameter configuration file and code template file, wherein the test vector contains embedded C code, sequencer code and reference model code , the logic of the embedded C code, the sequencer code and the reference model code corresponds;

The external signal component is used to simulate the design under test based on the embedded C code and the sequencer code to obtain target simulation data of the design under test; and generate reference data based on the reference model code. ; Wherein, the design to be tested is a system on a chip;

The verification control component is used to compare the target simulation data and the reference data, and obtain a target verification result for the design under test based on the comparison result.

In some embodiments, the verification system further includes a top-level design component; the top-level design component connects the external signal component and the verification control component;

The top-level design components are used to provide signal interfaces, system clocks and reset signals; and are also used to instantiate each component in the verification system;

The top-level design components are implemented based on classes in the UVM verification methodology.

In some embodiments, the test vector generation component includes a first acquisition module, a second acquisition module, a first generation module, a second generation module and a third generation module, wherein:

The first acquisition module is used to acquire parameter configuration information based on the parameter configuration file;

The second acquisition module is used to acquire the embedded C language template, sequence generator template and reference model template based on the code template file;

The first generation module is used to generate the embedded C code based on the embedded C language template and the parameter configuration information;

The second generation module is used to generate the sequencer code based on the sequencer template and the parameter configuration information;

The third generation module is configured to generate the reference model code based on the reference model template and the parameter configuration information.

In some embodiments, the external signal component includes an agent module, which includes a sequencer, a driver, a monitor, and a reference model, where:

The sequencer is configured to generate a stimulus transaction according to the sequencer code and transmit the stimulus transaction to the driver;

The driver is used to convert the stimulus transaction into the stimulus signal, and send the stimulus signal to the design under test;

The monitor is used to collect response signals from the design under test, convert the response signals into response transactions, and send the response transactions to the verification control component;

The reference model is used to generate a reference transaction based on the reference model agent, and send the reference transaction to the verification control component.

In some of these embodiments, the verification control component includes a scoreboard;

The scoreboard is used to compare the target simulation data in the response signal with the reference data in the reference transaction, and obtain the target verification result according to the comparison result.

In a third aspect, this embodiment provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. The processor executes the computer program. The program implements the system-on-chip verification method described in the first aspect above.

In a fourth aspect, this embodiment provides a storage medium on which a computer program is stored. When the program is executed by a processor, the verification method of the system-on-chip described in the first aspect is implemented.

Compared with related technologies, the verification method of the system-on-chip provided in this embodiment generates a test vector for verification according to the preset parameter configuration file and code template file, where the test vector contains embedded C code , sequencer code and reference model code, the logic correspondence between the embedded C code, sequencer code and reference model code; based on the embedded C code and sequencer code, simulate the design under test and obtain the design under test Target simulation data, in which the design to be tested is an on-chip system; reference data is generated based on the reference model code; the target simulation data and the reference data are compared, and the target verification results for the design to be tested are obtained based on the comparison results, solving related technologies In order to solve the problem of low verification efficiency of the system on chip, the verification efficiency of the system on chip is improved.

The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more concise and understandable.

Description of drawings

The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:

Figure 1 is a hardware structure block diagram of a terminal of the verification method of the system-on-chip in this embodiment;

Figure 2 is a flow chart of the verification method of the system-on-chip of this embodiment;

Figure 3 is a flow chart of the test vector generation method for on-chip system verification in this embodiment;

Figure 4 is a schematic structural diagram of the verification system of the system-on-chip of this embodiment;

Figure 5 is a schematic structural diagram of the test vector generation component of this embodiment;

FIG. 6 is a schematic structural diagram of a verification platform applying the system-on-chip verification method of this embodiment.

Detailed ways

In order to understand the purpose, technical solutions and advantages of the present application more clearly, the present application is described and illustrated below in conjunction with the drawings and embodiments.

Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by a person with ordinary skills in the technical field to which this application belongs. In this application, "a", "an", "an", "the", "these" and other similar words do not indicate a quantitative limitation, and they may be singular or plural. The terms "comprising", "comprising", "having" and any variations thereof, as used in this application, are intended to cover a non-exclusive inclusion; for example, processes, methods and Systems, products, or devices are not limited to the steps or modules (units) listed, but may include steps or modules (units) not listed, or may include other steps or modules inherent to such processes, methods, products, or devices (unit). Words such as "connected", "connected", "coupled" and the like mentioned in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" mentioned in this application means two or more. "And/or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and/or B" can mean: A alone exists, A and B exist simultaneously, and B exists alone. Normally, the character "/" indicates that the related objects are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application only distinguish similar objects and do not represent a specific ordering of the objects.

The method embodiments provided in this embodiment can be executed in a terminal, computer or similar computing device. For example, when running on a terminal, FIG. 1 is a hardware structure block diagram of the terminal of the system-on-chip verification method of this embodiment. As shown in Figure 1, the terminal may include one or more (only one is shown in Figure 1) processors 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a microprocessor MCU or Processing device for programming logic devices such as FPGA. The above-mentioned terminal may also include a transmission device 106 and an input and output device 108 for communication functions. Persons of ordinary skill in the art can understand that the structure shown in Figure 1 is only illustrative, and it does not limit the structure of the above-mentioned terminal. For example, the terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than that shown in FIG. 1 .

The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the verification method of the system-on-chip in this embodiment. The processor 102 runs the computer program stored in the memory 104, thereby Execute various functional applications and data processing, that is, implement the above methods. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely relative to the processor 102, and these remote memories may be connected to the terminal through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.

Transmission device 106 is used to receive or send data via a network. The above-mentioned network includes the wireless network provided by the communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet wirelessly.

This embodiment provides a system-on-chip verification method. Figure 2 is a flow chart of the system-on-chip verification method in this embodiment. As shown in Figure 2, the process includes the following steps:

Step S201: Generate a test vector for verification based on the preset parameter configuration file and code template file. The test vector includes embedded C code, sequencer code and reference model code. The embedded C code, sequencer code and reference model code are included in the test vector. The logic corresponds to the processor code and reference model code.

Specifically, the test vector is a set of test inputs, execution conditions and expected results written for the integrated circuit design to be verified, that is, the Design Under Test (DUT), based on the design requirements and design principles. It is used for verification. Whether the design to be tested meets the design requirements. The verification method provided in this embodiment can efficiently generate a test vector, which includes three parts: embedded C code, sequencer code, and reference model code. Pre-write the code template file. Based on the embedded C template, sequencer template and reference model template in the code template, combined with the parameter configuration information in the parameter configuration file, the embedded C code, sequencer code and Reference model code. Among them, the embedded C code is written in C language or embedded assembly language, and has a complete embedded architecture and automated compilation file (Makefile). It can complete program generation and construction with a single command, and generate the target files required for simulation loading.

Step S202: Simulate the design under test based on the embedded C code and sequencer code to obtain target simulation data of the design under test, where the design under test is a system on a chip.

Specifically, this embodiment uses a complete system on chip (SoC for short) as the design to be tested. The system on chip includes a system reset management unit, a system clock management unit, a system power consumption management unit, and a central processor. unit, bus matrix, storage unit, and multiple functional IP modules, among which the central processor is connected to the storage unit and functional IP module unit through the bus matrix. The embedded C code and sequencer code in the test vector jointly apply stimulation to the design under test, and the simulation running data of the design under test under stimulation is obtained, that is, the target simulation data.

Related technologies are usually based on the Universal Verification Methodology (UVM) to implement the verification of on-chip systems. UVM is a verification platform development framework with the SystemVerilog class library as the main body. Verification engineers can use its reusable components to build The functional verification environment of standardized hierarchies and interfaces is currently the most advantageous verification method.

UVM-based verification uses the sequence signal generated by the sequencer as an excitation. The signal is transmitted to each functional IP module of the on-chip system through the bus. Each functional IP module is then used as the design to be tested, and module-level verification is performed separately. For example, bus signals and external I/O signals are used as stimuli to verify the Universal Asynchronous Receiver/Transmitter (UART) module in the system-on-chip. However, this type of verification method can only verify the functional IP module itself, but cannot verify the part above the bus in the system on chip. In this embodiment, after the embedded C code in the test vector is instantiated, it no longer needs the signal input stimulus transmitted through the bus. Instead, it can run directly on the entire on-chip system, so it can control each of the on-chip systems. Partially applying incentives, on the basis of verifying functional IP modules, it also covers system-level units and functions such as the central processing unit above the bus in the system-on-chip, bus matrix connections, etc.

Step S203: Generate reference data based on the reference model code.

Specifically, the reference model code generates reference data by simulating the logical behavior of the design under test. The reference data is the designer's ideal expected result for the design under test to run under test vector stimulation.

Step S204: Compare the target simulation data and the reference data, and obtain the target verification result for the design to be tested based on the comparison result.

Specifically, by comparing the target simulation data and the reference data, the degree of compliance between the design to be tested and the design requirements can be determined. The higher the similarity between the target simulation data and the reference data, the more the design under test meets the design requirements. Further, combined with Based on the set quantification standards, the similarity between the target simulation data and the reference data is specifically quantified, and the target verification results for the design under test can be obtained.

Through the above steps S201 to S204, a test vector for verification is generated according to the preset parameter configuration file and code template file, where the test vector includes embedded C code, sequencer code and reference model code. Embedded C The logic of the code, sequencer code and reference model code corresponds; based on the embedded C code and sequencer code, the design under test is simulated to obtain the target simulation data of the design under test, where the design under test is a system-on-chip; Based on the reference model code, reference data is generated; the target simulation data and the reference data are compared, and the target verification results for the design under test are obtained based on the comparison results; this embodiment introduces embedded C code into the test vector, and the embedded C code After being instantiated, it directly affects the entire on-chip system. In addition to verifying each functional IP module in the on-chip system, it also realizes the verification of system-level functions such as the central processing unit above the bus and the bus matrix connection, thus solving the problem. In the related art, the verification efficiency of the system on chip is low, and the verification efficiency of the system on chip is improved.

Figure 3 is a flow chart of the test vector generation method for on-chip system verification in this embodiment. As shown in Figure 3, in some embodiments, based on the above step S201, according to the preset parameter configuration file and code template file to generate test vectors for verification, which may include:

Step S301, obtain parameter configuration information based on the parameter configuration file; obtain the embedded C template, sequencer template and reference model template based on the code template file; Step S302, generate embedded C based on the embedded C template and parameter configuration information Code; step S303, generate sequence generator code based on the sequence generator template and parameter configuration information; step S304, generate reference model code based on the reference model template and parameter configuration information.

Among them, the code template file is a pre-written atomic code template, which contains code segments for specific functional IP modules. All on-chip systems that use the same functional IP module can use the corresponding code segments for verification. Atomic code templates include embedded C templates, sequencer templates, and reference model templates. The sequencer template describes how to generate one or more transactions and supports various logical code blocks of System Verilog syntax; the reference model template describes how to generate one or more transactions and supports various logical code blocks of System Verilog syntax; SystemVerilog is a An industry-standard language that combines Hardware Description Language (HDL) with modern high-level verification language (HVL), integrating features such as object-oriented programming, dynamic threads, and inter-thread communication.

The embedded C template implements each code segment that can complete independent operations, and each code segment has a corresponding relationship with the transaction described in the sequencer. In addition, the atomic code template defines and implements its own transaction class and driver class; the driver can convert transaction objects into signals, or signals into transaction objects.

The parameter configuration file uses the XML specification as the basic format and describes the parameter configuration information required by the column generator template, reference model template and embedded C template respectively; the sequence generator parameter configuration information includes the transaction type that needs to be generated and its matching parameters. ; The reference model description includes the transaction type that needs to be generated, and its matching parameters; the embedded C code description includes the code segment that needs to be generated, and its matching parameters; in addition, the sequencer template and the embedded C template have common configuration parameters, The number and type of parameters are not fixed.

The form of the above parameter configuration information can include: integer, 32-bit integer, generally used to describe the number of cycles, communication data length description, etc.; floating point, single-precision floating point number, generally used as calculation data, etc.; random number, random The generated 32-bit integers are generally used to generate communication data or register configuration values; binary parameters are generally used for logical judgment parameters; strings are Chinese and English string information; data packets are composed of various basic A single parameter formed by a combination of data types.

By running the automated script program, the embedded C code is generated based on the embedded C template and parameter configuration information; the sequence generator code is generated based on the sequencer template and parameter configuration information; the reference model is generated based on the reference model template and parameter configuration information Code; copy the generated three types of verification codes to the specified vector storage path according to the vector name and relevant naming rules. Among them, the automated script program is implemented by mainstream interpreted languages and is not specifically limited here.

Preferably, in one embodiment, an xml file manager is used to obtain the configuration field information in the parameter configuration file; further, check whether the atomic code template flag information in the configuration file field matches the command parameters. If they do not match, the generation fails; parsing Sequence generator template, reference model template and embedded C template template; locate the content of each atomic code segment template mentioned above according to the template keywords; generate sequence generator code, respectively for the sequence generator template, reference model template and embedded C template Reference model code as well as embedded C code.

Specifically, according to the atomic code segment information in the parameter setting information, the corresponding template code is found, and the parameter field content is replaced according to the parameter keyword; if the atomic code segment in the parameter setting information has repeated keywords (repeat), repeat according to the number of repetitions. Generate code snippets; when the parameters are randomly configured, use a random function to randomly generate the required content. When all the atomic code information in each atomic template file is completely generated into the atomic code, the newly generated files will be saved in temporary directories and files; when all the atomic template files have completed code generation, the generated files will be unified according to industry naming rules. Copy to the test vector path specified by the command line parameter.

Further, in some embodiments, according to the above step S202, based on the embedded C code and the sequencer code, the design under test is simulated to obtain the target simulation data of the design under test, which may specifically include:

Based on the sequencer code, the excitation signal is generated. By calling the driver class, the excitation transaction can be converted into; under the action of the excitation signal, the design under test runs the embedded C code to obtain the target simulation data generated by the operation.

This embodiment also provides a system-on-chip verification system. Figure 4 is a schematic structural diagram of the system-on-chip verification system in this embodiment. As shown in Figure 4, the verification system includes a test vector generation component 41, an external signal component 42 and verification control component 43, where:

The test vector generation component 41 is used to generate a test vector for verification according to the preset parameter configuration file and code template file, where the test vector contains embedded C code, sequence generator code and reference model code. The embedded C code Logical correspondence between code, sequencer code, and reference model code;

The external signal component 42 is used to simulate the design under test based on the embedded C code and sequencer code to obtain target simulation data of the design under test; and generate reference data based on the reference model code; wherein the design under test is a system on a chip;

The verification control component 43 is used to compare the target simulation data with the tested data, and obtain the target verification results for the design under test based on the comparison results.

In addition, the verification system also includes top-level design components; the top-level design components connect external signal components and verification control components; the top-level design components are used to provide signal interfaces, system clocks and reset signals; they are also used to instantiate each component in the verification system; the top-level design components Design components are implemented based on classes in the UVM verification methodology. For example, the class responsible for instantiating and connecting all functional components is derived from the environment class uvm_env in UVM.

Further, Figure 5 is a schematic structural diagram of the test vector generation component of this embodiment. As shown in Figure 5, the test vector generation component includes a first acquisition module 51, a second acquisition module 52, a first generation module 53, and a second generation module. module 54 and a third generation module 55, where:

The first acquisition module 51 is used to acquire parameter configuration information based on the parameter configuration file; the second acquisition module 52 is used to acquire the embedded C language template, sequence generator template and reference model template based on the code template file; the first generation module 53 Used to generate embedded C code based on the embedded C language template and parameter configuration information; the second generation module 54 is used to generate the sequence generator code based on the sequence generator template and parameter configuration information; the third generation module 55 is used to generate the sequence generator code based on the sequence generator template and parameter configuration information. Refer to the model template and parameter configuration information to generate reference model code.

Further, the external signal component of this embodiment includes an agent module. The agent module includes a sequencer, a driver, a monitor, and a reference model, where:

The sequencer is used to generate stimulus transactions based on the sequencer code and transmit the stimulus transactions to the driver; the driver is used to convert the stimulus transactions into stimulus signals and sends the stimulus signals to the design under test; the monitor is used to collect data from the device under test Designed response signals, convert the response signals into response transactions, and send the response transactions to the verification control component; the reference model is used to generate reference transactions based on the reference model agent, and send the reference transactions to the verification control component.

Further, the above-mentioned verification control component includes a scoreboard; the scoreboard is used to compare the target simulation data in the response signal with the reference data in the reference transaction, and obtain the target verification result based on the comparison result.

It should be noted that each of the above modules can be a functional module or a program module, and can be implemented by software or hardware. For modules implemented by hardware, each of the above-mentioned modules can be located in the same processor; or each of the above-mentioned modules can also be located in different processors in any combination.

In particular, Figure 6 is a schematic structural diagram of a verification platform that applies the verification method of the system-on-chip of this embodiment. As shown in Figure 6, the verification platform includes control UVC, external signal UVC, and the design to be tested; the control UVC includes scoring Board, virtual sequencer and parameter configuration; the external signal UVC includes an input agent and an output agent. The input agent includes a sequencer, driver and monitor. The output agent has the same structure as the input agent; the design under test includes memory and peripheral interfaces. Among them, UVC means that the component interacts with external signals based on the USB Video Class protocol.

As shown by the arrow in Figure 6, the embedded C code and software assembly environment are loaded into the memory of the design under test; the peripheral interface in the design under test sends the signal of the design under test to the external signal UVC, and the external signal UVC The transaction is sent to the control UVC; the virtual sequencer in the control UVC sends the verification sequence to the external signal UVC.

This embodiment also provides an electronic device, including a memory and a processor. The memory stores a computer program. The processor is configured to run the computer program to perform the steps in any of the above method embodiments.

Optionally, the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.

Optionally, in this embodiment, the above-mentioned processor may be configured to perform the following steps through a computer program:

S1, based on the preset parameter configuration file and code template file, generate a test vector for verification. The test vector contains embedded C code, sequencer code and reference model code. Embedded C code, sequencer code Logical correspondence between code and reference model code;

S2, based on the embedded C code and sequencer code, simulates the design under test to obtain the target simulation data of the design under test, where the design under test is a system-on-chip;

S3, based on the reference model code, generates reference data;

S4: Compare the target simulation data with the reference data, and obtain the target verification results for the design under test based on the comparison results.

It should be noted that for specific examples in this embodiment, reference may be made to the examples described in the above-mentioned embodiments and optional implementations, and details will not be described again in this embodiment.

In addition, in combination with the system-on-chip verification method provided in the above embodiment, a storage medium may also be provided in this embodiment for implementation. The storage medium stores a computer program; when the computer program is executed by the processor, any one of the system-on-chip verification methods in the above embodiments is implemented.

It should be understood that the specific embodiments described here are only used to explain this application and are not used to limit it. According to the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without performing creative work shall fall within the protection scope of this application.

Obviously, the accompanying drawings are only some examples or embodiments of the present application. For those of ordinary skill in the art, the present application can also be applied to other similar situations based on these drawings, but no creative effort is required. In addition, it can be understood that although the work done in this development process may be complex and lengthy, for those of ordinary skill in the art, certain designs and manufacturing based on the technical content disclosed in this application Or production and other changes are only routine technical means and should not be regarded as insufficient content disclosed in this application.

The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily intended to be identical embodiments, nor are they meant to be mutually exclusive, independent, or alternative to other embodiments. Those of ordinary skill in the art will understand, explicitly or implicitly, that the embodiments described in this application may be combined with other embodiments without conflict.

The above-mentioned embodiments only express several implementation modes of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of patent protection. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all fall within the protection scope of the present application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims (10)

1. A method of verifying a system-on-chip, comprising:

generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequence generator code and a reference model code, and the logic of the embedded C code, the logic of the sequence generator code and the logic of the reference model code are corresponding;

simulating a design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested, wherein the design to be tested is a system on chip;

generating reference data based on the reference model code;

and comparing the target simulation data with the reference data, and obtaining a target verification result aiming at the design to be tested based on a comparison result.

2. The method for verifying a system on a chip according to claim 1, wherein the generating a test vector for verification according to a preset parameter configuration file and a code template file comprises:

acquiring parameter configuration information based on the parameter configuration file;

acquiring an embedded C template, a sequencer template and a reference model template based on the code template file;

generating the embedded C code based on the embedded C template and the parameter configuration information;

generating the sequencer code based on the sequencer template and the parameter configuration information;

and generating the reference model code based on the reference model template and the parameter configuration information.

3. The method for verifying a system-on-chip according to claim 2, wherein the simulating the design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested comprises:

generating an excitation signal based on the sequencer code;

and under the action of the excitation signal, operating the embedded C code based on the design to be tested to obtain the target simulation data generated by operation.

4. A verification system of a system-on-chip, the verification system comprising a test vector generation component, an external signal component, and a verification control component, wherein:

the test vector generation component is used for generating a test vector for verification according to a preset parameter configuration file and a code template file, wherein the test vector comprises an embedded C code, a sequencer code and a reference model code, and the logic of the embedded C code, the logic of the sequencer code and the logic of the reference model code are corresponding;

the external signal component is used for simulating a design to be tested based on the embedded C code and the sequencer code to obtain target simulation data of the design to be tested; generating reference data based on the reference model code; wherein the design to be tested is a system on chip;

the verification control component is used for comparing the target simulation data with the reference data and obtaining a target verification result aiming at the design to be tested based on a comparison result.

5. The system-on-chip verification system of claim 4, further comprising a top-level design component; the top layer design component is connected with the external signal component and the verification control component;

the top layer design component is used for providing a signal interface, a system clock and a reset signal; and for instantiating each of the components in the verification system;

the top-level design component is implemented based on classes in the UVM verification methodology.

6. The system-on-chip verification system of claim 4, wherein the test vector generation component comprises a first acquisition module, a second acquisition module, a first generation module, a second generation module, and a third generation module, wherein:

the first acquisition module is used for acquiring parameter configuration information based on the parameter configuration file;

the second acquisition module is used for acquiring an embedded C language template, a sequencer template and a reference model template based on the code template file;

the first generation module is used for generating the embedded C code based on the embedded C language template and the parameter configuration information;

the second generating module is used for generating the sequence generator code based on the sequence generator template and the parameter configuration information;

the third generation module is used for generating the reference model code based on the reference model template and the parameter configuration information.

7. The system-on-chip verification system of claim 6, wherein the external signal component comprises a proxy module comprising a sequencer, a driver, a monitor, and a reference model, wherein:

the sequencer is used for generating an excitation transaction according to the sequencer code and transmitting the excitation transaction to the driver;

the driver is used for converting the excitation transaction into an excitation signal and sending the excitation signal to the design to be tested;

the monitor is used for collecting a response signal from the design to be tested, converting the response signal into a response transaction and sending the response transaction to the verification control component;

the reference model is used for generating a reference transaction based on the reference model agent and sending the reference transaction to the verification control component.

8. The system-on-chip verification system of claim 7, wherein the verification control component comprises a scoreboard;

the score board is used for comparing the target simulation data in the response signal with the reference data in the reference transaction, and obtaining the target verification result according to a comparison result.

9. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of verification of a system on chip as claimed in any one of claims 1 to 3.

10. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor implements the steps of the verification method of a system on chip of any one of claims 1 to 3.