CN117172184A

CN117172184A - Method, apparatus, device, storage medium and program product for generating printed circuit board layout

Info

Publication number: CN117172184A
Application number: CN202210580514.3A
Authority: CN
Inventors: 张子贤; 谭智荣; 宁富立; 黄帆; 张�浩
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-05-25
Filing date: 2022-05-25
Publication date: 2023-12-05

Abstract

Embodiments of the present disclosure provide methods, apparatus, devices, storage media and program products for generating printed circuit board layouts, relating to the field of electronics. In the method, a first set of layouts for laying out devices on a printed circuit board is generated based on censoring rules and parameter space searches; generating a second set of layouts based on simulation results of the physical properties of the first set of layouts; and generating at least one target layout from the second set of layouts based on the optimization rules. In this way, by comprehensively using the censoring rules, parameter space search, simulation of physical properties, and optimization rules, the target layout can be automatically generated without manually using multiple specialized tools for multiple iterative designs. In addition, based on the parameter space search, initial layouts meeting requirements can be generated as much as possible, so that the efficiency of generating target layouts is improved.

Description

Method, apparatus, device, storage medium and program product for generating printed circuit board layout

Technical Field

Embodiments of the present disclosure relate generally to the field of electronics, and more particularly to the field of electronic design automation (electronic design automation, EDA). More particularly, embodiments of the present disclosure relate to methods, apparatuses, devices, computer-readable storage media, and computer program products for generating printed circuit board (printed circuit board, PCB) layouts.

Background

In the design process of PCBs, it is necessary to generate a PCB layout capable of realizing functions required by a circuit designer based on a schematic circuit diagram or the like. In general, the PCB layout needs to be generated taking into account various factors such as the layout of external connections, the layout of internal electronic components, the layout of metal wirings and vias, electromagnetic protection, heat dissipation, etc. Excellent PCB layout can save production cost and achieve good circuit performance and heat dissipation performance.

However, because of the many influencing factors in generating a PCB layout, it generally takes a significant amount of time to make multiple adjustments and evaluations to generate a PCB layout that meets the target conditions.

Disclosure of Invention

Embodiments of the present disclosure provide a scheme for generating a printed circuit board layout.

In a first aspect of the present disclosure, a method of generating a printed circuit board layout is provided. The method comprises the following steps: generating a first set of layouts for layout of devices on the printed circuit board based on the censoring rules and the parameter space search; generating a second set of layouts based on simulation results of the physical properties of the first set of layouts; and generating at least one target layout from the second set of layouts based on the optimization rules.

In this way, by comprehensively using the censoring rules, parameter space search, simulation of physical properties, and optimization rules, the target layout can be automatically generated without manually using multiple specialized tools for multiple iterative designs. In addition, based on the parameter space search, initial layouts meeting requirements can be generated as much as possible, so that the efficiency of generating target layouts is improved.

In some embodiments of the first aspect, the censoring rules are determined based on at least one of: design requirements, design specifications, forbidden regions, and testability requirements.

In some embodiments of the first aspect, the censoring rules are represented in structured data.

In some embodiments of the first aspect, generating a first set of layouts for layout of devices on a printed circuit board based on the censoring rules and the parameter space search includes: determining a recommended layout area of the device based on the censoring rules; the first set of layouts for laying out the devices is determined using a depth-first algorithm based on the recommended layout area.

In some embodiments of the first aspect, the simulation includes at least one of: thermal simulation, electromagnetic simulation, and electromagnetic compatibility simulation.

In some embodiments of the first aspect, the thermal simulation comprises a simulation based on an equivalent coefficient of thermal expansion associated with a rate of wet expansion, humidity, a current temperature, and a material glassy temperature.

In some embodiments of the first aspect, the at least one target layout comprises a first target layout, and generating at least one target layout from the second set of layouts based on an optimization rule comprises: based on the optimization rules, the locations of the devices in a first layout in the second set of layouts are adjusted to generate the first target layout.

In some embodiments of the first aspect, the at least one target layout comprises a second target layout, and generating at least one target layout from the second set of layouts based on the optimization rules comprises: based on the optimization rules, a portion of a first layout in the second set of layouts and a portion of a second layout in the second set of layouts are combined to generate the second target layout.

In some embodiments of the first aspect, the method further comprises: utilizing a data structure for the device, the data structure including structural data indicative of a three-dimensional structure of the device and performance data indicative of a physical property of the device.

In a second aspect of the present disclosure, an apparatus for generating a printed circuit board layout is provided. The device comprises: a pre-layout unit configured to generate a first set of layouts for layout of devices on a printed circuit board based on the censoring rules and the parameter space search; a simulation unit configured to generate a second group of layouts based on simulation results of the physical properties of the first group of layouts; and an optimization unit configured to generate at least one target layout from the second set of layouts based on the optimization rules.

In some embodiments of the second aspect, the censoring rules are determined based on at least one of: design requirements, design specifications, forbidden regions, and testability requirements.

In some embodiments of the second aspect, the censoring rules are represented in structured data.

In some embodiments of the second aspect, the pre-layout unit is configured to: determining a recommended layout area of the device based on the censoring rules; the first set of layouts for laying out the devices is determined using a depth-first algorithm based on the recommended layout area.

In some embodiments of the second aspect, the simulation includes at least one of: thermal simulation, electromagnetic simulation, and electromagnetic compatibility simulation.

In some embodiments of the second aspect, the thermal simulation comprises a simulation based on an equivalent coefficient of thermal expansion associated with a rate of wet expansion, humidity, a current temperature, and a material glassy temperature.

In some embodiments of the second aspect, the at least one target layout comprises a first target layout, and the optimization module is configured to: based on the optimization rules, the locations of the devices in a first layout in the second set of layouts are adjusted to generate the first target layout.

In some embodiments of the second aspect, the at least one target layout comprises a second target layout, and the optimization module is configured to: based on the optimization rules, a portion of a first layout in the second set of layouts and a portion of a second layout in the second set of layouts are combined to generate the second target layout.

In some embodiments of the second aspect, the apparatus further comprises a data utilization unit configured to: utilizing a data structure for the device, the data structure including structural data indicative of a three-dimensional structure of the device and performance data indicative of a physical property of the device.

In a third aspect of the present disclosure, there is provided an electronic device comprising: at least one computing unit; at least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit cause the apparatus to implement the method provided by the first aspect.

In a fourth aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program, wherein the computer program is executed by a processor to implement the method provided in the first aspect.

In a fifth aspect of the present disclosure, there is provided a computer program product comprising computer executable instructions which, when executed by a processor, implement some or all of the steps of the method of the first aspect.

It will be appreciated that the electronic device of the third aspect, the computer storage medium of the fourth aspect or the computer program product of the fifth aspect provided above are each for performing the method provided by the first aspect. Therefore, the explanation or explanation concerning the first aspect is equally applicable to the third aspect, the fourth aspect, and the fifth aspect. The advantages achieved by the third, fourth and fifth aspects are referred to as advantages in the corresponding methods, and will not be described here.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

FIG. 1 illustrates a schematic diagram of an example environment in which some embodiments of the disclosure may be implemented;

fig. 2 illustrates a flowchart of a process of generating a PCB layout according to some embodiments of the present disclosure;

FIG. 3 illustrates a schematic diagram of a user interface for displaying a generated target layout, according to some embodiments of the present disclosure;

FIG. 4 illustrates a schematic diagram of a process of building a data structure for a device, according to some embodiments of the present disclosure;

fig. 5 illustrates a schematic block diagram of an apparatus for generating a PCB layout according to some embodiments of the present disclosure; and

FIG. 6 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As mentioned briefly above, it is often necessary to expend a significant amount of time to adjust and evaluate in order to generate a PCB layout that meets the target conditions. Currently, waterfall designs remain the dominant way to generate PCB layouts. Typically, the steps of schematic diagram determination, PCB layout generation, physical performance simulation, etc. are taken care of by different departments, and each department performs the job with a respective specialized tool. However, due to the lack of collaboration between different specialized tools, information from different specialized tools is difficult to use in a comprehensive manner. For example, it is difficult to query data from one professional tool to another and collaborative design of different professional tools is inefficient.

To at least partially address the above-mentioned problems, as well as other potential problems, various embodiments of the present disclosure provide a solution for generating a PCB layout. In general, according to various embodiments described herein, a first set of layouts for layout of devices on a PCB is first generated based on censoring rules and parameter space searches. A second set of layouts is generated based on simulation results of the physical properties of the first set of layouts. At least one target layout is generated from the second set of layouts based on the optimization rules.

In this way, by comprehensively using the censoring rules, parameter space search, simulation of physical properties, and optimization rules, the target layout can be automatically generated without manually using multiple specialized tools for multiple iterative designs. In addition, based on the parameter space search, the layout meeting the requirements can be generated as many as possible, so that the efficiency of generating the target layout is improved.

Various example embodiments of the disclosure are described below with reference to the accompanying drawings.

Fig. 1 illustrates a schematic diagram of an example environment 100 in which some embodiments of the disclosure may be implemented. As shown in fig. 1, based on the censoring rules 105 and the parameter space search 110, the pre-layout module 120 generates a first set of layouts 130. The first set of layouts 130 may include a plurality of layouts for laying out devices on the PCB. The device to be laid out may be a core device such as a chip. Additionally, the devices to be laid out may include some designated devices.

The censoring rules 105 may refer to requirements for the PCB layout that are determined based on historical data or a priori knowledge. In some embodiments, the censoring rules 105 may be determined based on design requirements. Design requirements may include thermal evaluation requirements, power integrity requirements, signal integrity requirements, special layout wiring requirements, and the like. Alternatively or additionally, the censoring rules 105 may be determined based on design specifications. In particular, the censoring rules 105 may indicate design specifications for the mechanical domain. For example, the design specifications may include specifications for a manufacturing-oriented design (design for manufacture, DFM), an assembly-oriented design (design for assembly, DFA), and the like. Alternatively or additionally, the censoring rules 105 may be determined based on the forbidden regions. The no-layout area may indicate an area on the PCB where layout devices and/or routing are to be inhibited. Alternatively or additionally, the censoring rules 105 may be determined based on testability requirements.

Based on the first set of layouts 130, the simulation module 140 generates a second set of layouts 150. The simulation module 140 may simulate the physical properties of the first set of layouts 130 and generate the second set of layouts 140 based on the simulation results. In some embodiments, the simulation module 140 may identify a layout in the first set of layouts 130 that meets the corresponding performance requirements to determine the second set of layouts 150. Alternatively or additionally, the simulation module 140 may adjust at least a portion of the layouts of the first set of layouts 130 based on the simulation results of the first set of layouts 130 to determine the second set of layouts 150.

Based on the second set of layouts 150, the optimization module 160 utilizes the optimization rules 170 to generate at least one target layout 180. The optimization rules 170 may be rules for optimizing the PCB layout determined based on historical data or a priori knowledge. For example, the optimization rules may indicate adjusting the location of a particular device. In some embodiments, the optimization module 160 can identify a layout from the second set of layouts 150 that meets a predetermined condition to determine at least one target layout 180. Alternatively, the optimization module 160 may determine the at least one target layout 180 by adjusting at least a portion of the layouts of the second set of layouts 150 based on the optimization rules 170.

It should be understood that fig. 1 is merely exemplary and not limiting. For example, the optimization rules 170 shown in FIG. 1 may be obtained by the optimization module 160 from an external database. Specific details of generating the at least one target layout 180 will be described in detail below.

Fig. 2 illustrates a flowchart of a process 200 of generating a PCB layout according to some embodiments of the present disclosure. Process 200 may be implemented by any suitable computing device, such as EDA software deployed on a computing device. Details of generating the PCB layout will be described below with reference to fig. 1.

At block 202, a first set of layouts 130 for laying out devices on a PCB is generated based on the censoring rules 105 and the parameter space search 110. As described above, the censoring rules 105 may be determined based on at least one of design requirements, design specifications, forbidden regions, and testability requirements. In some embodiments, the censoring rules may be represented by structured data. In this way, automated review of the layout may be achieved by the computing device.

In some embodiments, pre-layout module 120 may obtain censoring rules 105 from other modules. For example, the pre-layout module 120 may obtain design requirements in the form of structured data from an engineering form input module. The engineering form input module may receive an engineering requirements form provided by a single board hardware engineering and determine design requirements in terms of structured data based on the engineering requirements form. For example, the engineering form input module may determine that the heating power of a particular area on the PCB does not exceed a particular threshold based on the thermal evaluation requirements. Alternatively, the pre-layout module 120 may determine the design requirements in terms of structured data directly based on the engineering requirements form without other modules.

In some embodiments, the pre-layout module 120 may obtain the design specifications represented in structured data from a rule input and parsing module. The rule input and parsing module may determine constraint data during the production and manufacturing of the product based on the historical data as a design specification represented in structured data. Examples of design specifications may include: (1) In general, all components should be arranged on the same surface of the PCB, and only when the top layer component is too dense, some devices with limited height and small heat productivity, such as chip resistors, chip capacitors, chip ICs, etc., can be placed on the lower layer; (2) On the premise of ensuring the electrical performance, the elements are placed on the grid and are arranged in parallel or perpendicular to each other so as to be neat and attractive, and the elements are not allowed to overlap under the general condition; the arrangement of the elements is compact, and the elements should be distributed uniformly and the density is consistent on the whole layout; (3) The minimum spacing between adjacent pad patterns of different components on the PCB should be above 1 mm; (4) The distance from the edge of the PCB is generally not less than 2mm, the optimal shape of the PCB is rectangular, the length-width ratio is 3:2 or 4:3, and when the PCB surface rule is more than 200mm multiplied by 150mm, the mechanical strength born by the PCB is considered; (5) The positions of the functional circuit units are arranged according to the flow of the circuit, so that the layout is convenient for signal circulation, and the signals keep the consistent direction as far as possible; (6) The layout is performed around the core component of each functional unit, centering around it. The components should be arranged on the PCB uniformly, integrally and compactly, so as to reduce and shorten leads and connections among the components as much as possible; (7) The circuit operating at high frequency takes into account the distribution parameters between the components. The common circuit should make the components and parts parallel arrangement as much as possible, thus not only being beautiful, but also being easy to weld and easy to mass production.

For example, it may be determined based on historical data that the length, width, height of the PCB should be less than X1, X2, and X3, respectively. In this way, in a subsequent operation, the coordinates of the PCB may be automatically extracted from the layout and the dimensions of the PCB calculated, thereby examining whether the layout meets the design specifications indicating the maximum dimensions of the PCB. Alternatively, without other modules, the pre-layout module 120 may determine a design specification, such as a DFM design specification, expressed in structured data directly based on historical data.

In some embodiments, the pre-layout module 120 may obtain the forbidden area in terms of structured data from the forbidden area input module. For example, the keep-out area input module may receive data indicating an area (e.g., coordinates of a keep-out area) where layout and/or routing is to be kept out and determine the keep-out area in terms of structured data, such as a rectangular box defined by coordinates of a boundary.

In another example, the keep-out area input module may allow a user to input a maximum and/or minimum value of the z-axis of the printed circuit board to define the keep-out area in three-dimensional space. For example, the front, back, TOP (TOP), BOTTOM (botom), or no-load areas on the laminate of the printed circuit board may be indicated. In addition, the forbidden region input module may receive a forbidden region manually drawn by a user in three-dimensional space. Alternatively, without other modules, the pre-layout module 120 may determine the keep-out area in the structured data representation directly based on the indication of the keep-out area.

In some embodiments, the pre-layout module 120 may arrange the devices on the PCB based on the censoring rules 105 and the parameter space search 110 to automatically generate the first set of layouts 130 that conform to the censoring rules 105. The parameter space search 110 may refer to selecting parameters in the parameter space that indicate the location of each device to combine to generate a corresponding layout. The size of the parameter space may be determined based on the size of the printed circuit board, and the pitch of the parameters may vary according to the particular implementation.

For example, the position of each device may be indicated by 6 parameters, which may include coordinate data of the device on the X, Y, Z axis and the angle of rotation about the X, Y, Z axis. In this way, by choosing and combining parameters in the parameter space, all possible layouts can be generated. For example, one possible layout may be characterized in the following format: the method comprises the steps of (1) x1, y1, z1, rx1, ry1, rz1, [ x2, y2, z2, rx2, ry2, rz2 ] and … … ], wherein the subscript 1 identifies the first device, x1, y1, z1 respectively identifies the coordinate data of the first device on the X, Y, Z axis and the rotation angle of the first device about the X, Y, Z axis, the subscript 2 identifies the second device, x2, y2, z2 respectively identifies the coordinate data of the second device on the X, Y, Z axis and the rotation angle of the second device about the X, Y, Z axis, ry2, rz2 respectively.

In some embodiments, the pre-layout module 120 may first traverse the entire parameter space based on the parameter space search 110 to generate a set of overall layouts. On this basis, the pre-layout module 120 may screen the set of all layouts for layouts that meet the censoring rules 105 based on the censoring rules 105 to generate the first set of layouts 130.

Alternatively, the pre-layout module 120 may traverse at least a portion of the parameter space based on the censoring rules 105 to generate the first set of layouts 130. In some embodiments, pre-layout module 120 may determine a recommended layout area for a device to be laid out based on censoring rules 105. Based on the determined recommended layout region, the pre-layout module 120 may determine the first set of layouts 130 using a depth-first algorithm. For example, a recommended layout area of the device (e.g., an area other than a keep-out area or a specific area on the PCB) may be first determined based on the censoring rules 105. A depth-first search may be performed based on the recommended layout region of the device to generate the first set of layouts 130.

At block 204, a second set of layouts 150 is generated based on simulation results of the physical properties of the first set of layouts 130. As described above, the simulation module 140 may simulate the physical properties of the first set of layouts 130. In some embodiments, the simulation module 140 may perform at least one of thermal simulation, electromagnetic compatibility simulation.

In some embodiments, the physical properties of the first set of layouts 130 may be simulated using any suitable simulation method. For example, the mechanical calculations may be performed using open source software calculix, the thermal fluid calculations may be performed using open, and so on. In some embodiments, the laws of physics may be encapsulated to form a simulation algorithm. Any suitable mathematical method may be utilized to solve the simulation results. For example, a direct solution, an iterative solution, or the like may be used. For simulations of small scale, the solution can be performed by direct solution. For large-scale simulation, such as simulation of layout with more than 100 ten thousand grids, the simulation result can be solved iteratively. It should be understood that the scope of the disclosure is not limited herein.

In some embodiments, the simulation module 140 may perform thermal simulation based on the equivalent thermal expansion coefficient for the first set of layouts 130. For example, the expansion caused by moisture and the expansion caused by thermal stress may be superimposed so as to consider the combined effect of moisture and temperature on thermal expansion. In this way, chip explosion (also known as popcorn effect) caused by the thermal expansion of the chip during die bonding (e.g., reflow soldering) can be simulated, thereby helping to analyze thermal stress variations of the chip during bonding and determine bonding parameters to improve the bonding process.

In some embodiments, the equivalent coefficient of thermal expansion may be determined based on the rate of wet expansion, humidity, current temperature, and the glass transition temperature of the material to account for the combined effects of humidity and temperature on expansion. For example, the equivalent thermal expansion coefficient may be determined with reference to the following formula.

Wherein the alpha mark considers the equivalent thermal expansion coefficient of moisture and temperature factors, the beta mark the wet expansion rate, the C mark the humidity, the T ₁ Mark the current temperature, and T ₀ The glass temperature of the marking material. Thus, by utilizing an equivalent thermal expansion coefficient instead of a thermal expansion coefficient that only considers temperature factors, existing thermal simulation algorithms can be utilized to account for the combined effects of moisture and temperature on expansion.

In some embodiments, the simulation module 140 may identify a layout of the first set of layouts 130 that satisfies the target condition based on the simulation results to determine the second set of layouts 150. Alternatively, the simulation module 140 may adjust at least a portion of the layouts of the first set of layouts 130 based on the simulation results to determine the second set of layouts 150. For example, if the physical properties simulated for a layout do not meet the target conditions, the simulation module 140 may adjust the locations of devices in the layout. In particular, the simulation module 140 may automatically adjust the position of the device at predetermined intervals. In another example, the simulation module 140 may replace a particular device in the layout with another device. Additionally, the simulation module 140 may iteratively perform adjustments and simulations of the layout to determine a layout that meets the target condition to determine the second set of layouts 150. In this way, the second set of layouts 150, for which the physical properties meet the target conditions, may be automatically determined without manual adjustment by an engineer.

At block 206, at least one target layout 180 is generated from the second set of layouts 150 based on the optimization rules 170. As described above, the optimization rules 170 may be determined based on historical data and/or a priori knowledge. The optimization rules 170 may indicate one or more items to be inspected and the corresponding optimization schemes. The optimization scheme may indicate an optimization strategy or method that may be adopted when the item to be inspected does not meet the target condition. The optimization scheme may include optimization parameters such as adjusted spacing of locations of particular devices.

In some embodiments, the item to be inspected may include an item associated with the censoring rule 105. For example, as the simulation module 140 adjusts the locations of devices in the layout, the newly generated layout may no longer conform to the censoring rules 105. In this case, the optimization module 160 may again adjust the layout so that the newly generated layout complies with the censoring rules 105.

Examples of items to be inspected may include: (1) Whether the size of the circuit board is consistent with the processing size required by the drawing; (2) Whether the layout of the components is balanced, the arrangement is orderly, and whether the components are completely distributed; (3) Whether each layer has conflict or not, such as whether components, outer frames and layers needing private printing are reasonable or not; (4) Whether the commonly used components are convenient to use or not, such as a switch, a plug-in board inserting device, components which need to be replaced frequently, and the like; (5) Whether the distance between the heat-sensitive component and the heating component is reasonable or not; (6) whether or not the heat dissipation property is good; (7) whether the interference problem of the line needs to be considered.

The optimization module 160 may determine whether each layout in the second set of layouts 150 needs to be optimized based on the inspection results of the item to be inspected. In some embodiments, the optimization module 160 can identify a layout of the second set of layouts 150 for which the inspection results of the items to be inspected meet the corresponding target conditions to generate at least one target layout 180. In some embodiments, for layouts for which the inspection results of the items to be inspected in the second set of layouts 150 do not meet the corresponding target conditions, the optimization module 160 may adjust these layouts based on the optimization scheme indicated by the optimization rules 170 to generate at least one target layout 180.

In some embodiments, the optimization scheme may indicate the locations of devices in the adjustment layout. Alternatively or additionally, the optimization scheme may indicate a particular device in the alternative layout. For example, the optimization scheme may instruct a device similar to the particular device to be selected from a library of devices for replacement. Alternatively or additionally, the optimization scheme may indicate that specific portions of different layouts are combined. For example, the optimization scheme may instruct to combine the first portion of the first layout in the second set of layouts 150 and the second portion of the second layout in the second set of layouts 150 to generate a new layout as one target layout. It should be appreciated that the first layout and the second layout are merely exemplary, and that the optimization scheme may dictate any combination of a plurality of layouts to generate one target layout. In this way, based on the optimization rules 170, the optimization module 160 can extract dominant portions of the layouts of the second set of layouts 150 to combine, thereby improving performance of the generated at least one target layout 180.

It should be understood that process 200 is merely exemplary and that process 200 may include other actions or reduction actions as well. For example, the generated second set of layouts 150 may be reviewed again based on the review rules 105 to improve the quality of the generated at least one target layout 180.

In some embodiments, the process 200 may include outputting the generated at least one target layout 180 for subsequent operation. Alternatively or additionally, the process 200 may further include displaying the generated at least one target layout 180. The generated at least one target layout 180 may be displayed on a user interface.

Fig. 3 illustrates a schematic diagram of a user interface 300 according to some embodiments of the present disclosure. In addition to displaying the generated at least one target layout 180, the user interface 300 may also support other interactions with the user. As shown in fig. 3, the user interface 300 may include a toolbar, menu bar, property window, navigational tree, and the like. In the navigational tree 301, the user may query the information of the class, code, bit number, etc. of the devices in the layout. The user may also view information of the selected device by selecting a device in the navigational tree 301. For example, the information of the device may be shown in the property window on the right.

Additionally, the user interface 300 may also show inspection results based on the inspection rules 105 and/or inspection results based on the optimization rules 170. For example, the censoring rules 105 may include rules for device height that indicate that collision interference may occur during an assembly procedure if the device height exceeds a predetermined threshold. In this case, as shown in fig. 3, the inspection result 302 may show device information in which an interference phenomenon may occur to remind the user to replace the device or adjust the layout.

In some embodiments, process 200 further includes utilizing a data structure for the devices, which may include, for each device, structural data indicative of the three-dimensional structure of the device and performance data indicative of the physical properties of the device. The structural data may be data for representing a three-dimensional model. The structure data may be data in STL format, STEP format, IGES format, GLB format, GLTF format, OBJ format, JT format, or custom geometric format. Examples of performance data may include electrical data, mechanical data, thermal data, etc. of the device. By using a data structure that fuses multiple domains of data, the execution efficiency of computing device execution process 200 may be increased, thereby increasing the efficiency of generating at least one target layout 180.

In some embodiments, the structural data and performance data of the same device may be coupled together to build a data structure for the device to facilitate subsequent queries and invocations. For example, the structural and performance data of a device may be obtained and parsed and the structural and performance data of the same device coupled by a unique identifier of the device to form a data structure for the device.

Fig. 4 shows a schematic diagram of a process 400 of building a data structure for a device according to an embodiment of the disclosure. As shown in fig. 4, three-dimensional structural data 401 of a device may be acquired and parsed to obtain a structural topology representation 402 of the device. Two-dimensional electrical data 403 of the device may also be acquired and parsed to obtain an electrical topology representation 404 of the device. With the coupling algorithm 405, a data structure 406 for the device may be constructed. As shown in fig. 4, the device-specific data structure 406 may be indexed by structural elements to indicate a coupling relationship 406-1 between the structural data and the performance data. The device-specific data structure 406 may also be indexed by electrical elements to indicate a coupling relationship 406-2 between the structural data and the performance data. Fig. 4 also shows an exemplary device representation 407 that fuses three-dimensional structural information and two-dimensional electrical information. By constructing a multi-domain fusion data structure, real-time viewing of multi-domain data and cross-domain inspection and optimization can be achieved in a single EDA tool, thereby accelerating the efficiency of PCB layout design.

The process of generating the PCB layout is described above with reference to fig. 1 to 4. By comprehensively using the censoring rules, the parameter space search, the simulation of physical properties, and the optimization rules, the target layout can be automatically generated without manually using multiple specialized tools for multiple iterative designs. In addition, based on the parameter space search, the layout meeting the requirements can be generated as many as possible, so that the efficiency of generating the target layout is improved.

Example apparatus and apparatus

Fig. 5 shows a block diagram of an apparatus 500 for generating a PCB layout, the apparatus 500 may include a plurality of modules for performing corresponding steps in the process 200 as discussed in fig. 2, according to an embodiment of the disclosure. As shown in fig. 5, the apparatus 500 includes a pre-layout unit 510 configured to generate a first set of layouts for laying out devices on a PCB based on the censoring rules and the parameter space search. A simulation unit 520 configured to generate a second set of layouts based on simulation results of the physical properties of the first set of layouts; and an optimization unit 530 configured to generate at least one target layout from the second set of layouts based on an optimization rule. The pre-layout unit 510, the simulation unit 520, and the optimization unit 530 may implement some or all of the functions of the pre-layout module 120, the simulation module 140, and the optimization module 160 shown in fig. 1.

In some embodiments, the censoring rules are represented in structured data.

In some embodiments, the pre-layout unit 510 is configured to: determining a recommended layout area of the device based on the censoring rules; the first set of layouts for laying out the devices is determined using a depth-first algorithm based on the recommended layout area.

In some embodiments, the simulation includes at least one of: thermal simulation, electromagnetic simulation, and electromagnetic compatibility simulation.

In some embodiments, the thermal simulation includes a simulation based on an equivalent coefficient of thermal expansion that is associated with a wet expansion rate, a humidity, a current temperature, and a material glass transition temperature.

In some embodiments, the at least one target layout includes a first target layout, and the optimization module 530 is configured to: based on the optimization rules, the locations of the devices in a first layout in the second set of layouts are adjusted to generate the first target layout.

In some embodiments, the at least one target layout includes a second target layout, and the optimization module 530 is configured to: based on the optimization rules, a portion of a first layout in the second set of layouts and a portion of a second layout in the second set of layouts are combined to generate the second target layout.

In some embodiments, the apparatus 500 further comprises a data utilization unit configured to: utilizing a data structure for the device, the data structure including structural data indicative of a three-dimensional structure of the device and performance data indicative of a physical property of the device.

Fig. 6 shows a schematic block diagram of an example device 600 that may be used to implement embodiments of the present disclosure. The apparatus 600 may be used to implement the device 600. As shown, the device 600 includes a computing unit 601 that can perform various suitable actions and processes according to computer program instructions stored in a Random Access Memory (RAM) 603 and/or a Read Only Memory (ROM) 602 or computer program instructions loaded from the storage unit 608 into the RAM603 and/or the ROM 602. In RAM603 and/or ROM 602, various programs and data required for operation of device 600 may also be stored. The computing unit 601 and the RAM603 and/or the ROM 602 are connected to each other by a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

Various components in the device 600 are connected to the I/O interface 605, including: an input unit 606 such as a keyboard, mouse, etc.; an output unit 607 such as various types of displays, speakers, and the like; a storage unit 608, such as a magnetic disk, optical disk, or the like; and a communication unit 609 such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The computing unit 601 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 601 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as process 200. For example, in some embodiments, the process 200 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 600 via RAM and/or ROM and/or communication unit 609. One or more of the steps of process 200 described above may be performed when a computer program is loaded into RAM and/or ROM and executed by computing unit 601. Alternatively, in other embodiments, computing unit 601 may be configured to perform process 200 by any other suitable means (e.g., by means of firmware).

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof, and when implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions which, when loaded and executed on a server or terminal, fully or partially produce a process or function in accordance with embodiments of the present application. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer readable storage medium may be any available medium that can be accessed by a server or terminal or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape, etc.), an optical medium (such as a digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as a solid state disk, etc.).

Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims

1. A method of generating a printed circuit board layout, comprising:

Generating a first set of layouts for layout of devices on the printed circuit board based on the censoring rules and the parameter space search;

generating a second set of layouts based on simulation results of the physical properties of the first set of layouts; and

at least one target layout is generated from the second set of layouts based on the optimization rules.

2. The method of claim 1, wherein the censoring rules are determined based on at least one of:

design requirements, design specifications, forbidden regions, and testability requirements.

3. The method of any of claims 1-2, wherein the censoring rules are represented in structured data.

4. A method according to any one of claims 1 to 3, wherein generating a first set of layouts for layout of devices on a printed circuit board based on the censoring rules and the parameter space search comprises:

determining a recommended layout area of the device based on the censoring rules;

the first set of layouts for laying out the devices is determined using a depth-first algorithm based on the recommended layout area.

5. The method of any one of claims 1 to 4, wherein the simulation comprises at least one of:

thermal simulation, electromagnetic simulation, and electromagnetic compatibility simulation.

6. The method of claim 5, wherein the thermal simulation comprises a simulation based on an equivalent coefficient of thermal expansion associated with a rate of wet expansion, humidity, a current temperature, and a material glassy temperature.

7. The method of any of claims 1-6, wherein the at least one target layout comprises a first target layout, and generating at least one target layout from the second set of layouts based on optimization rules comprises:

based on the optimization rules, the locations of the devices in a first layout in the second set of layouts are adjusted to generate the first target layout.

8. The method of any of claims 1-6, wherein the at least one target layout comprises a second target layout, and generating at least one target layout from the second set of layouts based on optimization rules comprises:

based on the optimization rules, a portion of a first layout in the second set of layouts and a portion of a second layout in the second set of layouts are combined to generate the second target layout.

9. The method of any one of claims 1 to 8, further comprising:

utilizing a data structure for the device, the data structure including structural data indicative of a three-dimensional structure of the device and performance data indicative of a physical property of the device.

10. An apparatus for generating a printed circuit board layout, comprising:

a pre-layout unit configured to generate a first set of layouts for layout of devices on a printed circuit board based on the censoring rules and the parameter space search;

a simulation unit configured to generate a second group of layouts based on simulation results of physical properties of the first group of layouts; and

an optimization unit configured to generate at least one target layout from the second set of layouts based on an optimization rule.

11. The apparatus of claim 10, wherein the censoring rules are determined based on at least one of:

12. The apparatus of any of claims 10 to 11, wherein the censoring rules are represented in structured data.

13. The apparatus according to any one of claims 10 to 12, wherein the pre-layout unit is configured to:

14. The apparatus of any of claims 10 to 13, wherein the simulation comprises at least one of:

15. The apparatus of claim 14, wherein the thermal simulation comprises a simulation based on an equivalent coefficient of thermal expansion associated with a rate of wet expansion, humidity, a current temperature, and a material glassy temperature.

16. The apparatus of any of claims 10 to 15, wherein the at least one target layout comprises a first target layout, and the optimization module is configured to:

17. The apparatus of any of claims 10 to 15, wherein the at least one target layout comprises a second target layout, and the optimization module is configured to:

18. The apparatus according to any of claims 10 to 17, further comprising a data utilization unit configured to:

19. An electronic device, comprising:

at least one computing unit;

at least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit, cause the electronic device to perform the method of any one of claims 1-9.

20. A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method according to any of claims 1-9.

21. A computer program product comprising computer executable instructions which, when executed by a processor, implement the method according to any one of claims 1-9.