CN117174123A - Memory cell voltage level selection - Google Patents

Abstract

The application relates to memory cell voltage level selection. The method includes performing an amount of write operations associated with a four level cell QLC memory block over a period of time; determining that the time period exceeds a threshold time; designating the QLC memory block as dual mode; determining a voltage threshold level of a last successful read operation associated with the QLC memory block; and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

Description

Memory cell voltage level selection

Technical Field

Embodiments of the present disclosure relate generally to memory subsystems and, more particularly, to memory cell voltage level selection.

Background

The memory subsystem may include one or more memory devices that store data. The memory device may be, for example, a non-volatile memory device and a volatile memory device. In general, a host system may utilize a memory subsystem to store data at and retrieve data from a memory device.

Disclosure of Invention

One aspect of the present disclosure provides a method for memory cell voltage selection, wherein the method comprises: performing an amount of write operations associated with a four level cell (QLC) memory block in the memory device over a period of time; determining that the time period exceeds a threshold time; designating the QLC memory block as dual mode in response to determining that the time period exceeds the threshold time; determining, in response to the dual mode designation, a voltage threshold level of a last successful read operation associated with the QLC memory block; and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

Another aspect of the present disclosure provides an apparatus for memory cell voltage selection, wherein the apparatus comprises: a non-volatile memory comprising non-volatile memory blocks including Single Level Cell (SLC) memory blocks and Quad Level Cell (QLC) memory blocks; and a controller configured to: responsive to receiving signaling indicating an access request, writing data associated with performance of a memory operation to the SLC memory block; migrating the data from the SLC memory block to a respective QLC memory block of the QLC memory block over a period of time; determining that the time period exceeds a threshold time; designating the QLC memory block as dual mode in response to the determining that the time period exceeds the threshold time; determining a voltage threshold level of a last successful read operation associated with the QLC memory block; and setting the voltage threshold level to the read threshold level of at least a portion of the QLC memory block.

Another aspect of the present disclosure provides a system for memory cell voltage selection, wherein the system comprises: a memory subsystem comprising a non-volatile memory, the non-volatile memory comprising: a first subset of memory blocks including Single Level Cell (SLC) memory blocks or memory blocks configured as SLC memory blocks, and a second subset of memory blocks including four level cell (QLC) memory blocks; and a processing device coupled to the memory subsystem, the processing device to perform operations comprising: migrating data from the SLC memory block to an individual QLC memory block of the QLC memory block over a period of time; comparing the time period to a threshold time; designating the individual QLC memory blocks as dual modules in response to determining that the time period exceeds the threshold time; determining a voltage threshold level of a last successful read operation associated with the dual module; setting the voltage threshold level at the read threshold level of the last successful read operation associated with the dual module; and performing a read operation associated with at least a portion of the dual module at the read threshold level.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.

FIG. 1 illustrates an example computing system including a memory subsystem, according to some embodiments of the disclosure.

FIG. 2 illustrates an example diagram of a non-volatile memory device for memory cell voltage level selection, according to some embodiments of the disclosure.

FIG. 3 illustrates a flow chart for memory cell voltage level selection according to some embodiments of the present disclosure.

Fig. 4 is a flow chart corresponding to a method for memory cell voltage level selection in accordance with some embodiments of the present disclosure.

FIG. 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure relate to memory cell voltage level selection, and in particular, to memory subsystems that include selective memory cell voltage level components. The memory subsystem may be a storage system, a storage device, a memory module, or a combination of these. An example of a memory subsystem is a storage system such as a Solid State Disk (SSD). Examples of memory devices and memory modules are described below in connection with FIG. 1, among other places. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data for storage at the memory subsystem and may request that data be retrieved from the memory subsystem.

The memory device may be a non-volatile memory device. One example of a non-volatile memory device is a NAND memory device (also known as flash technology). Other examples of non-volatile memory devices are described below in connection with FIG. 1. A nonvolatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into Logical Units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is made up of a set of pages. Each page is made up of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a unit of a memory device for storing data, and may include a group of memory cells, a group of word lines, a word line, or individual memory cells. For some memory devices, a block (hereinafter also referred to as a "memory block") is the smallest area that is erasable. Pages cannot be erased individually and only the entire block can be erased.

Each of the memory devices may include one or more arrays of memory cells. Depending on the cell type, the cell may be written to store binary information for one or more bits and have various logic states related to the number of bits being stored. The logic states may be represented by binary values (e.g., "0" and "1") or a combination of such values. There are various types of cells, such as Single Level Cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC may store one bit of information and have two logic states.

Some NAND memory devices employ a floating gate architecture in which memory access is controlled based on relative voltage changes between the bit line and the word line. Other examples of NAND memory devices may employ replacement gate architectures that may include the use of word line layouts that may allow charge corresponding to data values to be captured within memory cells based on the characteristics of the material used to construct the word lines.

Due to various factors, data stored in the memory cells may become unreliable (e.g., lost). Memory cells (e.g., volatile memory cells) may be periodically refreshed (e.g., via block refresh) at a particular rate. Although periodically refreshing the memory cells may be sufficient (e.g., frequent enough) to maintain data integrity, in many cases, the memory cell charge may change due to various factors and/or the memory cells may wear over time. For example, leakage of charge from a memory cell may result in data loss. Charge leakage or charge loss can be manifested by a time-to-voltage shift in the memory block. As used herein, time Voltage Shift (TVS) generally refers to the change in measured voltage of a cell over time. The amount of charge leakage from a memory block may vary based on the duration of a previous memory operation (e.g., a previous write operation) associated with the memory block.

For example, a first memory block written at a first time may experience a greater degree of charge leakage than a second memory block written at a second time that is closer than the first time. Thus, the access voltage at which data associated with the first memory block may be successfully accessed may be different (e.g., lower) than the access voltage at which data associated with the second memory block may be successfully accessed. As used herein, successfully accessing data associated with a memory block refers to evaluating data having a given health characteristic value, such as an appropriate Raw Bit Error Rate (RBER), so that a host can discern the data with or without performing an error correction operation or other type of data remediation on the data. As used herein, RBER refers to a data quality metric that may be calculated after successfully decoding data (e.g., by comparing bits before and after successful decoding).

Various methods may store data in SLC memory blocks, followed by migration of the data to portions of individual QLC memory blocks. For example, data may be migrated from two SLC blocks into a portion, but not all, of individual QLC memory blocks at a given time. Data may then be migrated from the two SLC blocks into different portions of the individual QLC memory blocks at a later time. Writing data into a portion of a memory block, such as a QLC memory block, may provide performance advantages over writing an entire memory block at a given time. For example, after migrating data from SLC blocks, the SLC blocks may be released into a free block pool and thus available for other memory operations.

However, if the period of time between the initial migration of data to the first portion of the QLC memory block and the final migration of data is long enough, there may be different degrees of charge loss between the portions of the QLC memory block. Thus, the default voltage threshold level may not be applicable to different portions of the QLC memory block. Examples of default voltage threshold levels (e.g., default read thresholds) include device default read thresholds (e.g., predetermined value or values), read thresholds based on a desired final pass voltage (VpassR), and/or system managed read thresholds, as well as other possible types of default read thresholds.

Thus, when the difference in charge loss between the upper and lower stacks is substantial, employing the same default read threshold level for an entire physical memory block (e.g., an entire QLC memory block) (e.g., both the upper and lower stacks) may result in read failures and/or obtain data with undesirable health characteristics (e.g., large RBER). As used herein, a "physical block of memory cells" or "physical block" generally refers to a group of memory cells storing a charge corresponding to a data value and having an address (e.g., a physical block address) associated therewith. For example, the default read threshold level may be too high for memory cells in the lower stack (e.g., that experience a greater degree of charge loss than memory cells in the upper stack that were recently written) and may result in a read operation failure (that does not return some or all of the data stored in the memory cells and/or returns data having undesirable health characteristics such as large RBER). Failure of a read operation may degrade the performance of the memory subsystem. Performance degradation may be undesirable, particularly in critical applications and/or in applications where very high memory subsystem performance requirements are expected. Moreover, such performance degradation that may be exhibited in such approaches may be further exacerbated in mobile (e.g., smart phones, internet of things, etc.) memory deployments, where the amount of space available to accommodate the memory subsystem is limited as compared to traditional computing architectures.

Aspects of the present disclosure address the above and other drawbacks by: performing a quantity of write operations associated with a memory block (e.g., a QLC block) over a period of time; determining that the time period exceeds a threshold time; determining a voltage threshold level of a last successful read operation associated with the memory block; and setting a read threshold level of at least a portion of the memory block to a voltage threshold level of a last successful read operation, as detailed herein. That is, the methods herein account for differences in charge loss experienced by different portions of the QLC memory block due to corresponding differences in programming times of different portions of the QLC block.

For example, the methods herein may determine a voltage threshold level of a last successful read operation associated with a QLC memory block (e.g., a last successful read operation associated with a lower stack of QLC memory blocks), and may set a read threshold level of the QLC memory block (e.g., at least the lower stack) at the voltage threshold level of the last successful read operation. Setting the voltage threshold level of at least the lower stack of QLC memory blocks at the voltage threshold level of the last successful read operation may determine that a subsequent read operation is performed at the voltage threshold level of the last successful read operation, thereby mitigating the likelihood of a read failure or returning data having undesirable health characteristics (e.g., high RBER) that would otherwise result from performing a read operation at the default voltage threshold level.

The last successful read operation may be a successful initial read that yields successfully decoded (e.g., with or without error correction, etc.) data. However, in some cases, the last successful read operation may be a successful read retry operation that generates successfully decoded data and is performed at a different voltage than and after the failed initial read operation.

FIG. 1 illustrates an example computing system 100 including a memory subsystem 110, according to some embodiments of the disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

Memory subsystem 110 may be a storage device, a memory module, or a hybrid of storage devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal Flash Storage (UFS) drives, secure Digital (SD) cards, and Hard Disk Drives (HDD). Examples of memory modules include Dual Inline Memory Modules (DIMMs), small DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, an unmanned aerial vehicle, a train, an automobile, or other conveyance), an internet of things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or such computing device that includes memory and a processing device.

The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, host system 120 is coupled to different types of memory subsystems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory subsystem 110. As used herein, "coupled to … …" or "coupled with … …" generally refers to a connection between components that may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, host system 120 uses memory subsystem 110 to write data to memory subsystem 110 and to read data from memory subsystem 110.

Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, universal Serial Bus (USB) interfaces, fibre channel, serial Attached SCSI (SAS), small Computer System Interface (SCSI), double Data Rate (DDR) memory buses, dual Inline Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Double Data Rates (DDR)), open NAND Flash Interfaces (ONFI), double Data Rates (DDR), low Power Double Data Rates (LPDDR), or any other interface. A physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled with host system 120 through a PCIe interface, host system 120 may further utilize an NVM high speed (NVMe) interface to access components (e.g., memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Fig. 1 illustrates a memory subsystem 110 as an example. In general, the host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and/or volatile memory devices. Volatile memory devices, such as memory device 140, may be, but are not limited to, random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

Some examples of non-volatile memory devices, such as memory device 130, include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory may perform bit storage based on a change in bulk resistance in combination with the stackable cross-meshed data access array. In addition, in contrast to many flash-based memories, cross-point nonvolatile memories may perform write-in-place operations, where nonvolatile memory cells may be programmed without pre-erasing the nonvolatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of the memory devices 130, 140 may include one or more arrays of memory cells. One type of memory cell, such as a Single Level Cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC or any combination of these. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and/or a PLC portion of memory cells. The memory cells of memory device 130 may be grouped into pages, which may refer to the logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as Read Only Memory (ROM), phase Change Memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic Random Access Memory (MRAM), spin Transfer Torque (STT) -MRAM, conductive Bridging RAM (CBRAM), resistive Random Access Memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and Electrically Erasable Programmable Read Only Memory (EEPROM).

As described above, the memory component may be a memory die or a memory package that forms at least a portion of the memory device 130. In some embodiments, a block of memory cells may form one or more "superblocks. As used herein, a "superblock" generally refers to a set of data blocks that span multiple memory dies and are written in an interleaved manner. For example, in some embodiments, each of a plurality of interleaved NAND blocks can be deployed across a plurality of memory dies having multiple planes and/or pages associated therewith. In the context of the present disclosure, the terms "superblock," "block," "memory cell block," and/or "interleaved NAND block," and variations thereof, are used interchangeably.

The memory subsystem controller 115 (or simply controller 115) may communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and/or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., field Programmable Gate Array (FPGA), application Specific Integrated Circuit (ASIC), etc.), or other suitable processor.

The memory subsystem controller 115 may be a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including processing communications between the memory subsystem 110 and the host system 120.

In some embodiments, local memory 119 may include memory registers that store memory pointers, extracted data, and the like. Local memory 119 may also include Read Only Memory (ROM) for storing microcode. Although the example memory subsystem 110 in fig. 1 has been illustrated as including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

In general, memory subsystem controller 115 may receive commands or operations from host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve desired access to memory device 130 and/or memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical Block Addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access memory device 130 and/or memory device 140 and convert responses associated with memory device 130 and/or memory device 140 into information for host system 120.

In some embodiments, memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and/or memory device 140. For example, in some examples, memory device 140 may be DRAM and/or SRAM configured to operate as a cache for memory device 130. In such cases, the memory device 130 may be a NAND.

In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device that is the original memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAAND) device. Memory subsystem 110 may also include additional circuitry or components not illustrated.

Memory subsystem 110 may include a memory cell voltage level selection component 113. Although not shown in fig. 1 to not obscure the drawing, the memory cell voltage level selection component 113 can include various circuitry to facilitate aspects of media management, as detailed herein. In some embodiments, the memory cell voltage level selection component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and/or other logic circuitry that may allow the memory cell voltage level selection component 113 to coordinate and/or perform the operations described herein.

In some embodiments, the memory subsystem controller 115 includes at least a portion of the memory cell voltage level selection component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the memory cell voltage level selection component 113 is part of the memory subsystem 110, an application program, or an operating system.

In a non-limiting example, an apparatus (e.g., computing system 100) can include a memory cell voltage level selection component 113. Memory cell voltage level selection component 113 can reside on memory subsystem 110. As used herein, the term "residing on … …" means something physically located on a particular component. For example, the memory cell voltage level selection component 113 "residing on the memory subsystem 110" refers to a condition in which hardware circuitry comprising the memory cell voltage level selection component 113 is physically located on the memory subsystem 110. The term "residing on … …" may be used interchangeably herein with other terms such as "disposed on … …" or "located on … …".

The memory cell voltage level selection component 113 may be configured to perform a quantity of write operations associated with a four-level cell (QLC) memory block over a period of time, determining that the period of time exceeds a threshold time, as detailed herein. For example, a time period may extend from a time associated with programming a page (e.g., a first page) in a lower stack of memory blocks (migrating data into the page) to a time associated with programming a page (e.g., an upper page) in an upper stack of memory blocks.

The memory cell voltage level selection component 113 can be configured to designate a QLC memory block as dual mode. As used herein, a dual module refers to a block of memory cells having a period of time exceeding a threshold time that extends from a time associated with programming at least an initial page of the block of memory to a time associated with programming a last page in the block of memory. The memory cell voltage level selection component 113 can be configured to designate the QLC memory block as dual mode in response to determining that the period of time exceeds a threshold time, as detailed herein.

The memory cell voltage level selection component 113 can be configured to set a read threshold level of at least a portion (e.g., a lower stack) of a memory block (e.g., a QLC memory block) at a voltage threshold level of a last successful read operation. The memory cell voltage level selection component 113 can be configured to set a read threshold level of at least a portion of the QLC memory block at a voltage threshold level of a last successful read operation in response to designating the memory block as dual-module. For example, the read threshold level of the lower stack of QLC memory blocks may be set at the voltage level of the last successful read operation, rather than the default read threshold level, as detailed herein. In some embodiments, the voltage level of the last successful read operation may be below the default read threshold level. As mentioned, using a relatively lower voltage level for at least the lower stack for the last successful read operation may take into account the higher degree of charge loss experienced by the lower stack (e.g., relative to the degree of charge loss experienced by the last programmed upper stack). Thus, the methods herein may produce improved data with desirable health characteristics (e.g., RBER lower than RBER of the data if obtained using a default read threshold level).

FIG. 2 illustrates an example diagram of a non-volatile memory device 240 for selective memory cell voltage levels according to some embodiments of the disclosure. The diagram of fig. 2 illustrates aspects of performing memory cell voltage level selection for a memory subsystem having a block of memory cells, such as memory subsystem 110.

As used herein, nonvolatile memory refers to a device having a block of nonvolatile memory cells configured to store various bits per memory cell. The blocks of non-volatile memory cells (243-1, 243-2, 243-3 …, 243-N and 245-1, 245-2, 245-3, …, 245-N; collectively referred to herein as blocks 243, 245) in non-volatile memory device 240 may include blocks of non-volatile SLC, MLC, TLC, QLC and/or PLCs, among other possibilities.

For example, blocks 243, 245 in the non-volatile memory device 240 may include: a block of SLCs, wherein each SLC cell may store one bit of information; and a block of QLCs, where each QLC cell can store four bits of information. In some embodiments, blocks 243, 245 may include only combinations of SLC and QLC. As used herein, SLC block (or SLC memory block) refers to a block of memory cells that can each store only 1 bit of information per memory cell.

The first subset 242-1 of the non-volatile memory devices 240 may be SLCs and/or may be higher-level memory blocks that may be selectively configured to operate in a single-level mode, as detailed herein. In some embodiments, the first subset 242-1 may include a dedicated number of SLCs. However, in some embodiments, some or all of the first subset 242-1 may be composed of higher-level memory blocks (e.g., QLC blocks) that are selectively configured to operate in a single-level mode. For example, the free nonvolatile memory blocks of the nonvolatile memory device 240 may be selectively configured to operate in a single level mode. "free blocks" (e.g., open virtual blocks, physical blocks, and/or logical blocks) generally refer to memory blocks in which pages of the memory block have no data (are not programmed). The free nonvolatile memory blocks (i.e., free blocks) may be contained in a free block pool containing a plurality of free blocks. The use of free blocks may facilitate a fast configuration of free blocks operating in a single layer level mode as compared to the use of other blocks having data stored therein.

In some embodiments, media management operations such as garbage collection may be performed to add free blocks to a free block pool. "garbage collection operation" generally refers to the process of folding data from a victim block stripe into a new destination block stripe, with the intended purpose of data consolidation to free up memory resources for subsequent program/erase cycles. Folding may be performed to pack the valid data together (garbage collection), thereby freeing up more space for new writes, error avoidance, wear leveling, and recovering RAIN parity protection in the event of an error. As used herein, a "block stripe" generally refers to a logical grouping of blocks that share the same upper block number and that are accessible in parallel. The garbage collection operation may include reclaiming (e.g., erasing and making available for programming) memory blocks that have the most invalid pages among the blocks in the memory device. In some embodiments, garbage collection may include reclaiming memory blocks having more than a threshold amount (e.g., number) of invalid pages. However, if there are enough free memory blocks for the programming operation, then the garbage collection operation may not occur. Adding the block to the free block pool may occur in the absence of a host command (e.g., a host write operation and/or a host read operation to the memory subsystem). In this way, media management as detailed herein may occur independent of host commands and/or without any associated traffic through the bus or other connection between the host and the memory subsystem.

In some embodiments, selectively configuring free non-volatile memory blocks (from the free block pool) to operate in single level mode may occur until the number of first subsets 242-1 equals the target number of non-volatile memory blocks. As used herein, "target number" generally refers to a particular total number of blocks. In some embodiments, the target number may be equal to 16, 32, 48, 64, 80, 96, 110 blocks, among other possible values. The target number may be a value stored in a table (e.g., a lookup table) or otherwise stored or accessible by the memory subsystem. In any case, the selective single level memory operation component as detailed herein may be configured to compare the current block count to a target number, thereby determining a difference between the current block count and the target number. Accordingly, the idle blocks may continue to be configured to operate in the single-level mode until the current block count in the first subset of non-volatile memory blocks configured to operate in the single-level mode is equal to the target number. Maintaining a number of free blocks (e.g., a number of free TLC blocks and/or QLC blocks) in the pool of free blocks that is equal to or greater than the target number of blocks may allow the free blocks to be easily configured in a single layer level mode.

The second subset 242-2 may be configured in (or remain configured in accordance with) a multi-level memory mode, such as a QLC mode. For example, as illustrated in FIG. 2, the first subset 242-1 may be formed by blocks 243-1, 243-2, 243-3 …, 243-N, whereas the second subset 242-2 may be formed by blocks 245-1, 245-2, 245-3, …, 245-N, may be formed by non-volatile memory blocks. In various embodiments, the first subset 242-1 is formed of blocks 245-1, 245-2, 245-3, …, 245-N having respective block sizes (e.g., X/4 pages) that are smaller than the respective block sizes (X pages) of the second subset 242-2. In various embodiments, the page size (16 kilobytes) of the blocks of the first subset 242-1 is smaller than the page size (e.g., 64 kilobytes) of the blocks of the second subset 242-2. Although fig. 2 illustrates the first subset 242-1 and the second subset 242-2 as including a given number of memory blocks, the number of blocks in the first subset 242-1 and/or the second subset 242-2 may be different.

Data (as represented by element identifier 241) may be written to first subset 242-1. Data (as represented by element identifier 244) may then be migrated internally from first subset 242-1 to second subset 242-2, as detailed herein.

Each memory block in the first subset 242-1 may be assigned a block index number (e.g., a consecutive number, such as 0 … N-1) such that each of the blocks may be written consecutively for consecutive host write operations. For example, data associated with performance of a first memory operation may be written to a first block having a first block index value. Data may be written to pages in the first block in the first subset 242-1 until the last page in the first block is full. The data may then be written to a second block (having the next block value in the series of block index values) in the first subset 242-1. It is noted that in such cases, the first block index value and the second block index value may be consecutive block index values. This manner of writing data to SLC blocks of the first subset 242-1 may continue in one loop (e.g., such that each block is written to before additional writes (e.g., single-level caches) are performed to any given block in the first subset.

Data may be migrated from the first subset 242-1 to the second subset 242-2. Such internal migration (folding) may completely migrate data (e.g., migrate all data from the first portion 242-1 to the second portion 242-2) and thus may have a write magnification of 1 compared to multiple host write operations that were originally to write such data directly to the second subset of non-volatile memory blocks. In this way, data may be effectively and efficiently stored in the higher-level memory cells of the second subset 242-2 (e.g., QLC memory blocks), however, the write magnification may be reduced as compared to other methods that may attempt to write such data directly to the QLC blocks of the second subset 242-2.

In some embodiments, data may be migrated from the first subset 242-1 to fill some but not all of the blocks in the second subset 242-2. For example, data may be migrated to fill a first portion of block 245-1 in second subset 242-2 at a first time (e.g., lower stack 247-2), and then additional data may be migrated to fill a second portion of block 245-1 (e.g., upper stack 247-1).

In some embodiments, migration of data from SLC memory blocks of the first subset 242-1 includes migration of data from a plurality of SLC memory blocks into portions of corresponding (individual) QLC memory blocks of the second subset 242-2. That is, the plurality of SLC memory blocks may operate as a cache and may allow data to be migrated (e.g., folded) from the plurality of SLC blocks into portions of the respective QLC blocks. For example, data associated with two blocks (e.g., two SLC blocks) in the first subset 242-1 may be migrated to fill a portion (e.g., a lower stack) of blocks (e.g., QLC blocks) in the second subset 242-2 at a first time. Additional data associated with two additional blocks (e.g., two additional SLC blocks) in the first subset 242-1 may be migrated to fill a second portion (e.g., an upper stack) of blocks in the second subset 242-2 at a second time subsequent to the first time. Such incremental programming at the first time and the second time may have various performance advantages and/or simplify aspects related to data management. However, as mentioned, writing or migrating data at different times can result in the block experiencing different degrees of charge loss. For example, in the above example, memory cells associated with data in a second portion (e.g., an upper stack) of the blocks in the second subset 242-2 may experience less charge loss than memory cells associated with data in a first portion of the blocks, the data in the second portion migrating at a second time subsequent to the first time.

As mentioned, the various methods use the same read threshold level for a first portion (e.g., lower stack) and a second portion (e.g., upper stack) of a memory block (e.g., QLC block), despite the different charge losses. In other words, the various methods employ default voltage threshold levels that are the same for the entire block (e.g., the same for both the upper and lower stacks of memory blocks). However, when the difference in charge loss between the upper and lower pages is substantial, maintaining the default voltage threshold level to the read threshold level of the entire QLC memory block may result in a read failure and/or obtain data with undesirable health characteristics (e.g., large RBER). For example, the default voltage threshold level may be too high for memory cells in the lower stack (e.g., that experience a greater degree of charge loss than memory cells in the upper stack that were recently written) and may result in read failures and/or obtain data with undesirable health characteristics, such as data with a larger RBER. For example, the RBER associated with data in the first portion (e.g., lower stack) may be higher than the RBER associated with data in the first portion (e.g., upper stack). Thus, memory cell voltage level selection may be employed, as detailed herein.

Fig. 3 illustrates a flow chart 334 for memory cell voltage level selection in accordance with some embodiments of the present disclosure. At 336-1, data may be migrated from the plurality of SLC memory blocks to portions of individual QLC memory blocks over a period of time. For example, a first amount of data may be migrated from a first subset of SLC memory blocks (e.g., two SLC blocks) to a first portion of QLC blocks (e.g., a lower stack) at a first time. Subsequently, a second amount of data may be migrated from the second subset (e.g., two SLC blocks) to the second portion (e.g., the upper stack) of the QLC blocks at a second time subsequent to the first time. That is, in some embodiments, the QLC block may include an upper portion configured to store a first amount of data and a lower portion configured to store a second amount of data. In some embodiments, the upper stack may be equal to half the size of the QLC block and the lower stack may be equal to half the size of the QLC block. For example, for a 64 kilobyte QLC block, the upper stack may be 32 kilobytes and the lower stack may be 32 kilobytes, among other possible values.

At 336-2, the time period may be compared to a threshold time. The threshold time refers to the amount of time allowed between programming a given page (e.g., a first page) and another page (e.g., a last page) of a memory block (e.g., a QLC memory block). The threshold time may be equal to a given amount of time, such as a given amount of seconds, minutes, and/or hours, etc.

In response to determining that the programming time is less than or equal to the threshold time, flow may proceed to 336-3. At 336-3, the memory block may be designated as a normal memory block (e.g., a non-dual module). Thus, the memory subsystem may continue normal operation (e.g., permit read/write operations associated with the entire memory block at the default voltage threshold level). For example, the memory subsystem may use a default VpassR voltage threshold level for an entire memory block (e.g., both the lower and upper stacks of QLC memory blocks). A memory block may be designated as a normal memory block by adding identification information (e.g., logical and/or physical addresses, etc.) associated with the memory block to a normal block list. Other mechanisms are possible such as designating a memory block as a normal memory block by changing bits in a status register and/or storing various data in a memory block (e.g., a memory block designated as a normal memory block), etc.

In response to determining that the programming time exceeds the threshold time, flow may proceed to 336-4. At 336-4, the memory block may be designated as a dual module. For example, in some embodiments, a memory block may be designated as a dual module by adding identification information (e.g., logical and/or physical addresses, etc.) associated with the memory block to a dual module list. Other mechanisms for designating a memory block as dual mode and/or storing various data in a memory block (e.g., a memory block designated as dual mode memory block) by changing bits in a status register are possible. As mentioned, the dual mode designation indicates that a sufficient amount of time has elapsed between programming of the first portion and programming of the second portion of the memory block. Thus, the bimodal blocks may be prone to the first portion and the second portion experiencing varying degrees of charge loss, which may be addressed by employing memory cell voltage level selection, as detailed herein.

In some embodiments, designating a memory block as dual mode may be eliminated. For example, a memory block may be removed from the dual mode memory block list in response to determining that a read threshold level of the memory block is substantially equal to a default voltage threshold level, in response to the memory block being included in the dual mode memory block list for a threshold amount of time, in response to a memory operation (e.g., a write operation and/or an erase operation associated with the memory block), in response to an occurrence of a system condition, and/or in response to a system input, etc. For example, in response to the read threshold level of the memory block being substantially equal to the default voltage threshold level, the memory block may be removed from the dual mode memory block list.

At 336-5, a voltage level of a last successful read operation associated with the dual module may be determined. In some embodiments, a dual module is a QLC block that includes a first portion (e.g., a lower portion or lower stack) and a second portion (e.g., an upper portion or upper stack). In such embodiments, the voltage level of the last successful read operation associated with the first portion and/or the second portion may be determined. For example, a voltage level associated with the first portion (e.g., a read voltage level of a read operation) may be determined.

At 336-6, the read threshold level of the dual module may be set at the voltage threshold level of the last successful read operation associated with the dual module. For example, for a QLC block, the read threshold level of the lower and/or upper stack may be set at the voltage threshold level associated with the last successful read operation. In some embodiments, at least the read threshold level of the lower stack may be set at the voltage threshold level associated with the last successful read operation. For example, the read threshold level of the lower stack may be set at the voltage threshold level associated with the last successful read operation, and the read threshold level of the upper stack may be set to the default read threshold level. In such examples, the read threshold level of the lower stack may be lower than the default read threshold level of the upper stack (e.g., a VpassR-based read threshold).

At 336-7, a read operation may be performed at a read threshold level. As mentioned, the read threshold level may be lower than the default read threshold level. In response to receiving signaling indicating that the host initiated the read and/or the memory device initiated the read, a read operation may be performed at a read threshold level. In some embodiments, the read operation may be performed in response to receiving signaling that instructs the host to initiate the read. In some embodiments, the read operation may be performed in response to receiving signaling that instructs the memory device to initiate the read.

At 336-8, a determination may be made as to whether the read operation performed at the read threshold level was successful. For example, it may be determined whether data associated with a read operation was successfully decoded. Decoding may be performed by the host and/or by a component in the memory subsystem, such as by a processing resource. In response to determining that the data associated with the read operation was successfully decoded, the read operation may be determined to be successful. In response to determining that the data associated with the read operation was not successfully decoded, the read operation may be determined to be unsuccessful.

In response to determining that the read operation performed at the read threshold level was successful, flow may return to 336-7. That is, when a read operation is successful, a subsequent read operation may be performed at the same read threshold level. For example, the voltage threshold level associated with the last successful read operation may be maintained as the read threshold level of at least one subsequent read operation, such as at least one subsequent read operation associated with a QLC block (e.g., a lower stack of QLC blocks). After each subsequent read operation of the at least one subsequent read operation is performed, a determination may then be made at 336-8 as to whether the at least one subsequent read operation performed was successful.

In response to determining that the read operation performed at the read threshold level was unsuccessful, flow may proceed to 336-9. Thus, at 336-9, the read threshold level may be altered to a different read threshold level (e.g., an altered read threshold level). For example, the read threshold level of the QLC memory block may be altered before a subsequent read operation associated with the QLC memory block is performed. Altering the read threshold level before proceeding with a subsequent read operation may reduce the likelihood of an additional read operation or a subsequent read operation being unsuccessful. In some embodiments, the read threshold level may be altered by decreasing the read threshold level (to a lower threshold level relative to the read threshold level employed at 336-7). However, in some embodiments, the read threshold level may be increased (relative to the read threshold level employed at 336-7).

Fig. 4 is a flow chart corresponding to a method for memory cell voltage level selection in accordance with some embodiments of the present disclosure. The method 460 may be performed by processing logic that may comprise hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of the device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 460 is performed by the memory cell voltage level selection component 113 of fig. 1. Although shown in a particular order or sequence, the sequence of processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

At 461, a quantity of write operations associated with a memory block (e.g., a QLC memory block) may be performed over a period of time. For example, data may be migrated (e.g., folded) from a first subset of non-volatile memory blocks to a second subset of non-volatile memory blocks, as detailed herein. In response to writing a threshold amount of data (e.g., an amount of data equal to at least a portion of a page size of a block in the second subset) to the first subset of non-volatile memory blocks, the data may be migrated from the first subset of non-volatile memory blocks to the second subset of non-volatile memory blocks.

In some embodiments, the time period may extend from a first time of an initial write operation associated with data migration from an initial SLC block of the plurality of SLC blocks to a first page of the QLC block to a second time of a final write operation associated with data migration from a final SLC block of the plurality of SLC blocks to a final page of the QLC block. In some embodiments, the time period may extend from a first time associated with data migration to a lower stack of the QLC memory block to a second time associated with data migration to an upper stack of the QLC memory block.

The time period may be compared to a threshold time. For example, at 462, the time period may be compared to a threshold time to determine whether the time period exceeds the threshold time, as detailed herein.

At 463, the QLC block may be designated as dual mode (e.g., as dual mode), as detailed herein. At 464, a voltage threshold level for a last successful read operation associated with the QLC memory block may be determined, as detailed herein. As mentioned, the last successful read may be a successful initial read or a successful read retry performed after a failed initial read. At 463, a voltage threshold level of a last successful read operation associated with the QLC memory block may be determined in response to the dual mode designation. At 465, the read threshold level of the QLC memory block may be set at the voltage threshold level of the last successful read operation, as detailed herein.

FIG. 5 is a block diagram of an example computer system 500 in which embodiments of the present disclosure may operate. For example, fig. 5 illustrates an example machine of a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, computer system 500 may correspond to a host system (e.g., host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of fig. 1) or may be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to memory cell voltage level selection component 113 of fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, in the capacity of a server or client machine in a client-server network environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a network appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. In addition, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 500 includes a processing device 502, a main memory 504 (e.g., read Only Memory (ROM), flash memory, dynamic Random Access Memory (DRAM), such as Synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static Random Access Memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 502 may also be one or more special purpose processing devices, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. The processing device 502 is configured to execute the instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 to communicate over a network 520.

The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and/or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and/or the main memory 504 may correspond to the memory subsystem 110 of fig. 1.

In one embodiment, the instructions 526 include instructions to implement functionality corresponding to the selective component (e.g., the memory cell voltage level selection component 113 of FIG. 1). While the machine-readable storage medium 524 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to apparatus for performing the operations herein. Such an apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the methods. The structure of various of these systems will be presented as set forth in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer).

In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage medium, optical storage medium, flash memory device, etc. In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims (15)

1. A method (460) for memory cell voltage selection, the method comprising:

performing a quantity of write operations associated with a four level cell QLC memory block (242-2) in the memory device (240) over a period of time;

Determining that the time period exceeds a threshold time;

designating the QLC memory block as dual mode in response to determining that the time period exceeds the threshold time;

determining, in response to the dual mode designation, a voltage threshold level of a last successful read operation associated with the QLC memory block; and

A read threshold level of at least a portion of the QLC memory block is set at the voltage threshold level of the last successful read operation.

2. The method of claim 1, further comprising performing a subsequent read operation associated with the QLC memory block at the voltage threshold level of the last successful read operation.

3. The method as recited in claim 2, further comprising:

determining that data associated with the subsequent read operation was successfully decoded; and

In response to determining that the data associated with the subsequent read operation is successfully decoded, the voltage threshold level is maintained at the read threshold level of at least one additional read operation associated with the QLC memory block.

4. The method as recited in claim 2, further comprising:

determining that data associated with the subsequent read operation was not successfully decoded; and

In response to determining that the data associated with the subsequent read operation was not successfully decoded, the read threshold level of the QLC memory block is altered prior to performing additional read operations associated with the QLC memory block.

5. The method of claim 4, further comprising altering the read threshold level to an altered read threshold level that is less than the voltage threshold level.

6. The method of any one of claims 1-5, further comprising performing a plurality of write operations to write data from a Single Level Cell (SLC) memory block (242-1) to the QLC memory block for the period of time, wherein the period of time extends from a first time of an initial write operation associated with data migration from an initial SLC block of the SLC block to a first page of the QLC block to a second time of a final write operation associated with data migration from a final SLC block of the SLC block to a final page of the QLC block.

7. The method of any of claims 1-5, designating the QLC memory block as a normal block in response to determining that the time period is less than or equal to the threshold time.

8. The method of claim 7, in response to designating the QLC memory block as a normal block, maintaining a default voltage threshold level as the read threshold level for the entire QLC memory block, wherein the default voltage threshold level is a device default read threshold, a read threshold based on a desired final pass voltage (VpassR), or a system managed read threshold.

9. An apparatus (100) for memory cell voltage selection, the apparatus comprising:

a non-volatile memory (140, 240) comprising non-volatile memory blocks (243, 245) including single level cell SLC memory blocks (242-1) and four level cell QLC memory blocks (242-2); and

A controller (115) configured to:

in response to receiving signaling indicating an access request,

writing data (241) associated with performance of a memory operation to the SLC memory block;

migrating the data from the SLC memory block to a respective QLC memory block of the QLC memory block over a period of time;

determining that the time period exceeds a threshold time;

designating the QLC memory block as dual mode in response to the determining that the time period exceeds the threshold time;

Determining a voltage threshold level of a last successful read operation associated with the QLC memory block; and

The voltage threshold level is set to the read threshold level of at least a portion of the QLC memory block.

10. The apparatus of claim 9, wherein the migration of the data from the SLC memory blocks further comprises migrating data (244) from a plurality of SLC memory blocks into portions of the respective QLC memory blocks.

11. The apparatus of any one of claims 9-10, wherein the signaling instructs a host to initiate a read or a memory device to initiate a read.

12. The apparatus of any of claims 9-10, wherein designating the memory block as a dual module further comprises adding information indicative of the memory block to a dual module list, and further comprising removing the memory block from the dual module list in response to determining that the read threshold level of the memory block is substantially equal to a default voltage threshold level.

13. A system (100) for memory cell voltage selection, the system comprising:

a memory subsystem (100) comprising a non-volatile memory (240), the non-volatile memory comprising: a first subset of memory blocks including single level cell SLC memory blocks or memory blocks configured as SLC memory blocks (242-1), and a second subset of memory blocks including four level cell QLC memory blocks (242-2); and

-a processing means (117) coupled to the memory subsystem, the processing means for performing operations comprising:

migrating data from the SLC memory block to an individual QLC memory block of the QLC memory block over a period of time;

comparing the time period to a threshold time;

designating the individual QLC memory blocks as dual modules in response to determining that the time period exceeds the threshold time;

determining a voltage threshold level of a last successful read operation associated with the dual module;

setting the voltage threshold level at the read threshold level of the last successful read operation associated with the dual module; and

A read operation associated with at least a portion of the dual module is performed at the read threshold level.

14. The system of claim 13, wherein the QLC block further comprises an upper portion (247-1) configured to store a first amount of data, and a lower portion (247-2) configured to store a second amount of data.

15. The system of claim 14, further comprising:

performing a read operation associated with the lower portion of the QLC block at the read threshold level; and

A read operation associated with the upper portion of the QLC block is performed at a default read threshold level.