CN117081960B

CN117081960B - Data transmission performance testing method and device, electronic equipment and storage medium

Info

Publication number: CN117081960B
Application number: CN202311333052.6A
Authority: CN
Inventors: 郭国峰; 许宏珍; 祝磊; 王梅
Original assignee: Shenzhen Huayun Information System Technology Co ltd
Current assignee: Shenzhen Huayun Information System Technology Co ltd
Priority date: 2023-10-16
Filing date: 2023-10-16
Publication date: 2023-12-22
Anticipated expiration: 2043-10-16
Also published as: CN117880142A; CN117081960A

Abstract

The embodiment of the application relates to a method and a device for testing data transmission performance, electronic equipment and a storage medium, wherein the method comprises the following steps: determining time information of target data in a target data sequence acquired by a PCIE terminal and/or a CPU terminal, and obtaining a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; the target data are collected by the PCIE end and then transmitted to a DMA (direct memory access) memory, so that the CPU end collects the target data from the DMA memory; determining statistics of the target time information sequence; and determining the data transmission performance of the PCIE terminal based on the statistical data, wherein the data transmission performance represents the performance of the PCIE terminal for data transmission relative to a preset reference terminal. Therefore, the test cost of the data transmission performance of the PCIE terminal can be reduced.

Description

Data transmission performance testing method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a method and apparatus for testing data transmission performance, an electronic device, and a storage medium.

Background

PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard), is a high-speed serial bus interface, is a bus type commonly used in modern computer systems, is widely applied to data connection transmission between peripheral devices and a CPU (Central Processing Unit ), and can provide higher bandwidth and lower transmission delay.

In applications requiring the performance of the very fast transmission, PCIE-DMA is often used as a data transmission mode between a device and a CPU, and the performance status of PCIE-DMA (Direct Memory Access ) transmission greatly affects the very fast performance status of the system. Because PCIE equipment and a CPU use different timestamp calculation modes, measurement of delay performance is difficult to uniformly calculate, so that performance evaluation of the traditional PCIE-DMA can only be tested through special equipment, and for many common users, the PCIE-DMA has high application cost and is difficult to popularize and apply.

Therefore, how to reduce the test cost of the data transmission performance of the PCIE end is a technical problem that is worth focusing on.

Disclosure of Invention

In view of this, in order to solve some or all of the above technical problems, embodiments of the present application provide a method, an apparatus, an electronic device, and a storage medium for testing data transmission performance.

In a first aspect, an embodiment of the present application provides a method for testing data transmission performance, where the method includes:

determining time information of target data in a target data sequence acquired by a PCIE terminal and/or a CPU terminal, and obtaining a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; the target data are collected by the PCIE end and then transmitted to a DMA (direct memory access) memory, so that the CPU end collects the target data from the DMA memory;

determining statistics of the target time information sequence;

and determining the data transmission performance of the PCIE terminal based on the statistical data, wherein the data transmission performance represents the performance of the PCIE terminal for data transmission relative to a preset reference terminal.

In one possible embodiment, the target time information in the target time information sequence is represented by a numerical value; and

the determining the statistics of the target time information sequence includes:

determining a time difference sequence based on the target time information sequence; the time difference in the time difference sequence represents the time difference of the CPU end and the PCIE end for collecting the same target data, or the time difference in the time difference sequence represents the time difference of the PCIE end for collecting the two target data, or the time difference in the time difference sequence represents the time difference of the CPU end for collecting the two target data;

Determining at least one of a first average value, a first median, a first maximum value, a first minimum value and a first interval ratio of the time difference sequence to obtain statistical data of the target time information sequence;

wherein the first interval ratio represents a ratio at which a time difference in the time difference sequence belongs to a first time difference interval.

In one possible embodiment, the determining a time difference sequence based on the target time information sequence includes:

determining the difference between the target time information and the previous target time information of the target time information in the target time information sequence aiming at the non-first target time information in the target time information sequence to obtain the time difference corresponding to the target time information;

the resulting sequence of time differences is determined as a time difference sequence.

In a possible implementation manner, the determining, based on the statistical data, the data transmission performance of the PCIE end includes:

determining whether the first average value belongs to a first numerical value interval or not to obtain first judging information;

determining whether the first median belongs to a second numerical value interval or not to obtain second judging information;

Determining whether delay jitter exists or not based on the first maximum value and the first minimum value, and obtaining third judging information;

determining a difference value between the first average value and the first maximum value or the first minimum value to obtain a target difference value;

determining whether the target difference value is smaller than or equal to a preset value to obtain fourth discrimination information;

and determining the data transmission performance of the PCIE terminal based on the first discrimination information, the second discrimination information, the third discrimination information, the fourth discrimination information and the first section ratio.

In one possible implementation manner, the determining the time information of the target data in the target data sequence acquired by the PCIE side and/or the CPU side, to obtain the target time information sequence includes:

determining time information of target data in a target data sequence acquired by a first CPU (central processing unit) end to obtain a first target time information sequence, wherein the target data acquired by the first CPU end is transmitted to a first DMA (direct memory access) memory through a first PCIE (peripheral component interface express) end;

determining time information of target data in a target data sequence acquired by a second CPU (central processing unit) end to obtain a second target time information sequence, wherein the target data acquired by the second CPU end is transmitted to a second DMA (direct memory access) memory through a second PCIE (peripheral component interface express) end, and the target time information in the first target time information sequence corresponds to the target time information in the second target time information sequence one by one; and

determining a first difference sequence of the first target time information sequence and the second target time information sequence, wherein the difference value in the first difference sequence is the difference value between the target time information in the first target time information sequence and the corresponding target time information in the second target time information sequence;

determining the statistical data of the first difference value sequence to obtain the statistical data of the target time information sequence; and

the determining, based on the statistical data, the data transmission performance of the PCIE terminal includes:

and determining the data transmission performance of the first PCIE terminal relative to the second PCIE terminal based on the statistical data.

In one possible embodiment, the determining the statistical data of the first difference sequence includes:

determining a second average value, a second median, a second maximum value, a second minimum value and a second interval ratio of the first difference sequence to obtain statistical data of the first difference sequence;

wherein the second interval ratio represents a ratio at which a difference in the first difference sequence belongs to a second difference interval; and

The determining, based on the statistical data, the data transmission performance of the first PCIE end relative to the second PCIE end includes at least one of:

determining the data transmission speed condition of the first PCIE terminal relative to the second PCIE terminal based on the second average value, the second median, the absolute value of the second average value, the absolute value of the second median and the second interval ratio;

and determining delay jitter conditions of data transmission of the first PCIE terminal relative to the second PCIE terminal based on the second maximum value, the second minimum value, the second average value and the second median.

In one possible implementation manner, the CPU side performs an acquisition operation according to a preset frequency to acquire target data; and

the determining the time information of the target data in the target data sequence acquired by the PCIE end and/or the CPU end, and obtaining the target time information sequence comprises the following steps:

determining the cycle times of the CPU terminal for collecting target data in a target data sequence to obtain a cycle times sequence, wherein the cycle times represent the times of executing the collecting operation during the period that the CPU terminal currently collects the target data and the CPU terminal last collects the target data;

Determining the cycle number sequence as the target time information sequence; and

and determining the data transmission performance of the PCIE terminal relative to the CPU terminal based on the statistical data.

determining time information of target data in a target data sequence acquired by a PCIE terminal, and obtaining a third target time information sequence;

determining time information of target data in the target data sequence acquired by a CPU (Central processing Unit) end to obtain a fourth target time information sequence; and

determining a second difference sequence of the fourth target time information sequence and the third target time information sequence, wherein the difference value in the second difference sequence is the difference value between the target time information in the third target time information sequence and the corresponding target time information in the fourth target time information sequence;

Determining the statistical data of the second difference value sequence to obtain the statistical data of the target time information sequence; and

and determining the data transmission delay of the PCIE terminal based on the statistical data.

In one possible implementation, the timestamp of the PCIE side and the timestamp of the CPU side are not in the same clock source.

In a second aspect, an embodiment of the present application provides a test apparatus for data transmission performance, where the apparatus includes:

the first determining unit is used for determining time information of target data in the PCIE terminal and/or the CPU terminal acquisition target data sequence to obtain a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; the target data are collected by the PCIE end and then transmitted to a DMA (direct memory access) memory, so that the CPU end collects the target data from the DMA memory;

a second determining unit configured to determine statistical data of the target time information sequence;

and the third determining unit is used for determining the data transmission performance of the PCIE terminal based on the statistical data, wherein the data transmission performance represents the performance of the PCIE terminal for data transmission relative to a preset reference terminal.

In a third aspect, an embodiment of the present application provides an electronic device, including:

a memory for storing a computer program;

and a processor, configured to execute the computer program stored in the memory, where the computer program is executed to implement the method of any embodiment of the method for testing data transmission performance of the first aspect of the present application.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as in any of the embodiments of the method for testing data transmission performance of the first aspect described above.

In a fifth aspect, embodiments of the present application provide a computer program comprising computer readable code which, when run on a device, causes a processor in the device to implement a method as in any of the embodiments of the method of testing data transmission performance of the first aspect described above.

According to the test method for the data transmission performance, which is provided by the embodiment of the application, the time information of the target data in the target data sequence acquired by the PCIE terminal and/or the CPU terminal can be determined, and the target time information sequence is obtained; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; and the target data is acquired by the PCIE terminal and then transmitted to a DMA (direct memory access) memory, so that the CPU (central processing unit) terminal acquires the target data from the DMA memory, then, the statistical data of the target time information sequence is determined so as to carry out statistical analysis on time information contained in the target time information sequence, and then, the data transmission performance of the PCIE terminal is determined based on the statistical data, wherein the data transmission performance represents the performance of the PCIE terminal for carrying out data transmission relative to a preset reference terminal so as to realize the test of the data transmission performance of the PCIE terminal. Therefore, the test of the data transmission performance of the PCIE terminal can be realized without depending on special equipment, and the test cost of the data transmission performance of the PCIE terminal can be reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.

The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 1 is a flow chart of a method for testing data transmission performance according to an embodiment of the present application;

fig. 2 is a flow chart of another method for testing data transmission performance according to an embodiment of the present application;

fig. 3A is a schematic flow chart of data interaction between a PCIE terminal and a CPU terminal according to a method for testing data transmission performance provided in an embodiment of the present application;

fig. 3B is a flowchart illustrating a method for testing data transmission performance according to another embodiment of the present application;

fig. 4 is a schematic structural diagram of a testing device for data transmission performance according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings, it being apparent that the described embodiments are some, but not all embodiments of the present application. It should be noted that: the relative arrangement of the parts and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless it is specifically stated otherwise.

It will be appreciated by those skilled in the art that terms such as "first," "second," and the like in the embodiments of the present application are used merely to distinguish between different steps, devices, or modules, and do not represent any particular technical meaning or logical sequence therebetween.

It should also be understood that in this embodiment, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.

It should also be appreciated that any component, data, or structure referred to in the embodiments of the present application may be generally understood as one or more without explicit limitation or the contrary in the context.

In addition, the term "and/or" in this application is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In this application, the character "/" generally indicates that the associated object is an or relationship.

It should also be understood that the description of the embodiments herein emphasizes the differences between the embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. For an understanding of the embodiments of the present application, the present application will be described in detail below with reference to the drawings in conjunction with the embodiments. It will be apparent that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In order to solve the technical problem of how to reduce the test cost of the data transmission performance of the PCIE terminal in the prior art, the present application provides a test method for the data transmission performance, which can reduce the test cost of the data transmission performance of the PCIE terminal.

Fig. 1 is a flow chart of a testing method for data transmission performance according to an embodiment of the present application. The method may be applied to one or more electronic devices such as FPGA (Field Programmable Gate Array), smart phone, notebook computer, desktop computer, portable computer, server, etc., and the execution subject of the method may be hardware or software.

As shown in fig. 1, the method specifically includes:

step 101, determining time information of target data in a target data sequence acquired by a PCIE terminal and/or a CPU terminal, and obtaining a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; and the target data are acquired by the PCIE terminal and then transmitted to a DMA (direct memory access) memory, so that the CPU terminal acquires the target data from the DMA memory.

In this embodiment, the PCIE device may be represented by a PCIE device. The CPU end can represent a CPU software end.

In practice, in some fields of data high-frequency interaction, PCIE devices such as FPGA boards are often used for quotation and transaction processing, and the processed data is transmitted to CPU software through DMA, where related data flows may be shown in fig. 3A, and fig. 3A is a schematic flow diagram of data interaction between a PCIE end and a CPU end, where the method for testing data transmission performance is related to the method provided by the embodiment of the present application.

Step one, the PCIE device (i.e., the PCIE end, device 1, device 2 in the illustrated example) processes data (i.e., the target data in the target data sequence), and requests to transmit the data to the corresponding DMA memory from the PCIE bus, where the PCIE bus implements a data transmission process, and transmits the data to the DMA memory.

And step two, if the CPU cache has a cache with a corresponding address, the system bus synchronizes the data into the CPU cache, and if the CPU cache does not exist, the step is not executed.

And step three, the CPU reads the data from the DMA memory, and if the data hits in the cache, the data is directly fetched from the cache.

And step four, if the data is not cached (cache miss, no cache or miss in the cache), the corresponding DMA memory data is requested from the DMA memory through a system bus application.

Step five, the CPU acquires the DMA data and enters corresponding business processing.

The target data in the target data sequence may be various data interacted between the PCIE terminal and the CPU terminal. The target data in the target data sequence may be arranged according to the sequence of data transmission from the PCIE end to the CPU end.

The time information may represent time when the PCIE side and/or the CPU side collect the target data in the target data sequence. For example, the time information may represent time when the PCIE terminal collects the target data in the target data sequence, may represent time when the CPU terminal collects the target data in the target data sequence, and may also represent time when the PCIE terminal and the CPU terminal collect the target data in the target data sequence.

The order of the time information in the target time information sequence may correspond to the order of the target data in the target data sequence.

Step 102, determining the statistics of the target time information sequence.

In the present embodiment, the above-described statistical data may be any one or more statistical data for the target time information series. As an example, the above-described statistical data may be an average, a median, a maximum, a minimum, a variance, a standard deviation, or the like of times represented by the respective target time information in the target time information sequence.

Step 103, determining the data transmission performance of the PCIE terminal based on the statistical data, where the data transmission performance represents the performance of the PCIE terminal for performing data transmission with respect to a preset reference terminal.

In this embodiment, the data transmission performance of the PCIE end may be determined based on the statistical data, where the preset reference end may be another PCIE end other than the PCIE end, or may be a CPU end configured to perform data interaction with the PCIE end. Data transmission capabilities may include at least one of: data transmission rate, data transmission delay, data transmission jitter, etc.

As an example, in the case that the statistical data includes an average value, if the average value belongs to a preset first interval, it may be determined that the frequency of transmission of the target data by the PCIE terminal is within a reasonable range.

As yet another example, in the case where the statistical data includes an average value and a maximum value (or a minimum value), if the difference between the average value and the maximum value (or the minimum value) is less than or equal to a preset value, it may be determined that the jitter of the PCIE side transmission target data is small.

In some optional implementations of this embodiment, the following manner may be adopted to determine time information of the PCIE side and/or the CPU side to collect the target data in the target data sequence, so as to obtain the target time information sequence:

determining time information of target data in a target data sequence acquired by a first CPU (Central processing Unit) end to obtain a first target time information sequence.

The first CPU may be any CPU.

The first target time information sequence may be a sequence of time information obtained by collecting target data in the target data sequence via the first CPU side.

The target data collected by the first CPU is transmitted to the first DMA memory through the first PCIE terminal.

The first PCIE peer may be a PCIE peer that is configured to transmit the target data to the first CPU peer.

The first DMA memory may be a DMA memory to which the first PCIE terminal collects the target data and then transmits the target data, that is, a DMA memory from which the first CPU terminal collects the target data.

And step two, determining time information of target data in the target data sequence acquired by the second CPU end, and obtaining a second target time information sequence.

The second CPU terminal may be any other CPU terminal different from the first CPU terminal.

The second target time information sequence may be a sequence of time information obtained by collecting target data in the target data sequence via the second CPU side.

And the target data acquired by the second CPU end are transmitted to a second DMA memory through a second PCIE end. The target time information in the first target time information sequence corresponds to the target time information in the second target time information sequence one by one.

The second PCIE peer may be a PCIE peer that is configured to transmit the target data to the second CPU peer.

The second DMA memory may be a DMA memory to which the second PCIE terminal collects the target data and then transmits the target data, that is, a DMA memory from which the second CPU terminal collects the target data.

On this basis, the statistics of the target temporal information sequence may be determined in the following way:

step one, a first difference sequence of the first target time information sequence and the second target time information sequence is determined.

The difference value in the first difference value sequence is the difference value between the target time information in the first target time information sequence and the corresponding target time information in the second target time information sequence.

As an example, if the first target time information sequence is "A1, B1, C1", and the second target time information sequence is "A2, B2, C2", the first difference sequence may be "A1-A2, B1-B2, C1-C2".

Step two, determining the statistical data of the first difference value sequence to obtain the statistical data of the target time information sequence.

Here, the above-mentioned statistical data may be any one or more statistical data for the first difference sequence. As an example, the above-mentioned statistical data may be the average, median, maximum, minimum, variance, standard deviation, etc. of the individual differences in the first sequence of differences.

Further, on this basis, the following manner may be adopted to determine, based on the statistical data, the data transmission performance of the PCIE side: and determining the data transmission performance of the first PCIE terminal relative to the second PCIE terminal (namely the preset reference terminal) based on the statistical data.

As an example, in the case where the statistical data includes an average value, if the average value is a positive value, it may be determined that the efficiency of transmitting the target data by the first PCIE terminal is lower than the efficiency of transmitting the target data by the second PCIE terminal; if the average value is negative, it may be determined that the efficiency of the first PCIE side for transmitting the target data is higher than the efficiency of the second PCIE side for transmitting the target data.

It can be understood that in the above alternative implementation manner, the comparison test of the data transmission performance of two different PCIE ends may be implemented by determining the difference sequence between the first target time information sequence and the second target time information sequence, so that the cost of the comparison test of the data transmission performance of the different PCIE ends may be reduced.

In some optional implementations of this embodiment, the statistical data of the first difference sequence may be determined in the following manner:

and a first step of determining a second average value, a second median, a second maximum value, a second minimum value and a second interval ratio of the first difference sequence to obtain statistical data of the first difference sequence.

Wherein the second interval ratio represents a ratio at which the difference value in the first difference sequence belongs to a second difference interval.

The second average may be an average of the individual differences in the first sequence of differences.

The second median may be the median of the individual differences in the first sequence of differences.

The second maximum value may be the maximum value of the individual differences in the first sequence of differences.

The second minimum value may be the minimum value of the individual differences in the first sequence of differences.

The second difference interval may be a predetermined difference interval.

Thus, the statistics of the first sequence of differences may include: a second average value, a second median value, a second maximum value, a second minimum value, and a second interval ratio.

Based on this, at least one of the following manners may be adopted to determine, based on the statistical data, data transmission performance of the first PCIE end relative to the second PCIE end:

in one aspect, the data transmission speed of the first PCIE terminal relative to the second PCIE terminal (i.e., the data transmission performance) is determined based on the second average value, the second median, the absolute value of the second average value, the absolute value of the second median, and the second interval ratio.

Here, the performance situation of the first PCIE end and the second PCIE end compared may be determined by the second average value and the second median, if the second average value and the second median are positive values, the first PCIE end is slower than the second PCIE end, and if the second average value and the second median are negative values, the first PCIE end is faster than the second PCIE end. The larger the absolute value of the second average value and the absolute value of the second median, the larger the difference between the first PCIE end and the second PCIE end is indicated.

The second interval ratio can be used for determining the ratio of the first PCIE end to the second PCIE end, so that the average value and the extremum (i.e., the maximum value or the minimum value) can be improved to a certain extent, which is insufficient in the statistical aspect. If the second interval ratio indicates that the number of the differences greater than 0 in the first difference sequence is greater than or equal to 80%, it indicates that the second PCIE end occupies 80% of the first PCIE end in a case of being faster than the first PCIE end, and the value can better reflect the fast and slow delay performance of the comparison between the second PCIE end and the first PCIE end.

In a second mode, a delay jitter condition (i.e., the above data transmission performance) of the data transmission of the first PCIE end relative to the second PCIE end is determined based on the second maximum value, the second minimum value, the second average value, and the second median.

Here, the second maximum value and the second minimum value may represent extremums of the comparison between the second PCIE end and the first PCIE end, if the extremums have a larger difference from the second average value and the second median, this indicates that the jitter is larger, the distribution is unbalanced, the average value may be affected by the extremums, and the comparison situation may be interfered by other factors.

In some optional implementations of this embodiment, the CPU side performs an acquisition operation according to a preset frequency to acquire the target data.

On the basis, the following mode can be adopted to determine the time information of the target data in the PCIE terminal and/or the CPU terminal acquisition target data sequence, so as to obtain the target time information sequence:

the first step, determining the circulation times of the target data in the target data sequence acquired by the CPU end, and obtaining the circulation times sequence.

The cycle number represents the number of times the CPU terminal performs the acquisition operation during the period when the CPU terminal acquires the target data at present and the last time the CPU terminal acquires the target data.

Here, the order of the respective cycle times in the sequence of cycle times may correspond to the order of the respective target data in the sequence of target data.

And secondly, determining the circulation times sequence as the target time information sequence.

Based on this, the following manner may be adopted to determine, based on the statistical data, the data transmission performance of the PCIE terminal: and determining the data transmission performance of the PCIE terminal relative to the CPU terminal (namely the preset reference terminal) based on the statistical data.

Here, by querying the number of cycles in the cycle number sequence, if the number of cycles is greater than 0, it is indicated that the CPU end can obtain data from the DMA memory at this time, the higher the number of cycles, the more waiting time, so as to analyze whether the PCIE end has a processing bottleneck, or if the data is paused at this time. When the CPU side processing and PCIE side upstream processing operate at the same DMA address, that is, the read-write is synchronous, the cycle number is 0, for example, at the moment when transmission is just started, or when PCIE side processing is slower than CPU side processing, the cycle number is increased, so that it can be distinguished where the performance bottleneck occurs.

It can be understood that the performance comparison analysis between the CPU ends at the PCIE end can be performed by the statistics of the cycle number sequence.

In some optional implementations of this embodiment, the following manner may be used to determine time information of the PCIE side and/or the CPU side to collect the target data in the target data sequence, so as to obtain the target time information sequence:

the first step, determining time information of target data in a target data sequence acquired by the PCIE terminal, and obtaining a third target time information sequence.

The third target time information sequence may be a sequence of time information obtained by collecting target data in the target data sequence via the PCIE terminal.

And step two, determining time information of the target data in the target data sequence acquired by the CPU end, and obtaining a fourth target time information sequence.

The fourth target time information sequence may be a sequence of time information obtained by collecting target data in the target data sequence via the CPU side.

step one, determining a second difference sequence between the fourth target time information sequence and the third target time information sequence.

The difference value in the second difference value sequence is the difference value between the target time information in the third target time information sequence and the corresponding target time information in the fourth target time information sequence.

As an example, if the third target time information sequence is "A1, B1, C1", and the fourth target time information sequence is "A2, B2, C2", the second difference sequence may be "A1-A2, B1-B2, C1-C2".

And step two, determining the statistical data of the second difference value sequence to obtain the statistical data of the target time information sequence.

Here, the statistical data of the second difference sequence may be any one or more statistical data for the second difference sequence. As an example, the above-mentioned statistical data may be the average, median, maximum, minimum, variance, standard deviation, etc. of the individual differences in the second sequence of differences.

Further, the following manner may be adopted to determine, based on the statistical data, the data transmission performance of the PCIE end: and determining the data transmission delay (namely the data transmission performance) of the PCIE terminal based on the statistical data.

It may be appreciated that in the above alternative implementation, the performance of the PCIE bus may be analyzed. Specifically, the transmission delay of a PCIE end at a certain moment can be evaluated through a device recording interval and a software end recording interval, and of course, the delay is a relative value, not the inherent performance of the PCIE end, but only reflects the relative value of transmitting a certain data at a certain moment, and the relative value may be affected by the load pressure and bus contention condition of the PCIE end at a certain moment, but the real-time condition of PCIE bus transmission can be fed back to a certain extent, and a certain decision basis can be provided for PCIE-DMA transmission system optimization. Therefore, even if the software timestamp and the device timestamp are not in the same clock source, the equation calculation cannot be performed, and the data transmission delay of the PCIE end can be determined based on the statistical data.

In some alternative implementations of the present embodiment, the software timestamp is not at the same clock source as the device timestamp.

It can be appreciated that the solution described in the above alternative implementation manner may implement the test of the data transmission performance of the PCIE end of the heterogeneous platform in the case that the software timestamp and the device timestamp are not in the same clock source.

Fig. 2 is a flow chart of another testing method for data transmission performance according to an embodiment of the present application. As shown in fig. 2, the method specifically includes:

step 201, determining time information of target data in a target data sequence acquired by a PCIE terminal and/or a CPU terminal, and obtaining a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; the target time information in the target time information sequence is represented by a numerical value; and the target data are acquired by the PCIE terminal and then transmitted to a DMA (direct memory access) memory, so that the CPU terminal acquires the target data from the DMA memory.

In practice, in some fields of data high-frequency interaction (such as financial fields), PCIE devices such as FPGA boards are often used for quotation and transaction processing, and the processed data is transferred to CPU software through DMA, where related data flows may be shown in fig. 3A, and fig. 3A is a schematic flow diagram of data interaction between a PCIE terminal and a CPU terminal related to a testing method for data transmission performance provided in an embodiment of the present application.

Step four, if the data is not cached (Cache miss, cache does not have Cache and miss), the corresponding DMA memory data is requested from the DMA memory through a system bus application;

The target time information in the target time information sequence is represented by a numerical value. For example, the target time information in the target time information sequence may be a time stamp of the target data collected by the CPU side, a time stamp of the target data collected by the PCIE side, or the number of times the collecting operation is performed during the period when the CPU side currently collects the target data and the CPU side last collects the target data (i.e., the number of cycles described above).

Step 202, determining a time difference sequence based on the target time information sequence; the time difference in the time difference sequence represents the time difference of the CPU end and the PCIE end for collecting the same target data, or the time difference in the time difference sequence represents the time difference of the PCIE end for collecting the two target data, or the time difference in the time difference sequence represents the time difference of the CPU end for collecting the two target data.

In this embodiment, in the case where the target time information sequence is obtained by determining the time information of the target data in the target data sequence acquired by the CPU terminal in step 201, the time difference in the time difference sequence may represent the time difference of the two target data acquired by the CPU terminal. In this case, the time difference sequence may be determined based on the target time information sequence in the following manner:

If the target time information sequence is "A _0r 、A _1r ……A _ir ", wherein A _ir Indicating the time of the CPU terminal collecting the target data, i+1 indicating the amount of target time information in the target time information sequence, then the time difference sequence may be "B _0r 、B _ir ……B _（i-1）r ”，B _（i-1）r Is equal to A _ir -A _（i-1）r 。

In step 201, in the case where the target time information sequence is obtained by determining the time information of the target data in the target data sequence collected by the PCIE terminal, the time difference in the time difference sequence may represent the time difference of the PCIE terminal for collecting the two target data. In this case, the time difference sequence may be determined based on the target time information sequence in the following manner:

if the target time information sequence is "A _0t 、A _1t ……A _it ", wherein A _it Indicating the time when the PCIE end collects the target data, i+1 indicates the number of target time information in the target time information sequence, then the time difference sequence may be "B _0t 、B _it ……B _（i-1）t ”，B _（i-1）t Is equal to A _it -A _（i-1）t 。

In step 201, in the case where the target time information sequence is obtained by determining the time information of the target data in the target data sequence collected by the PCIE terminal and the CPU terminal, the time difference in the time difference sequence may represent the time difference of the same target data collected by the CPU terminal and the PCIE terminal. In this case, the time difference sequence may be determined based on the target time information sequence in the following manner:

If the target time information sequence includes the first target time information sequence "A _0r 、A _1r ……A _ir "and second target time information sequence" A _0t 、A _1t ……A _it ", wherein A _ir Indicating the time of collecting target data by the CPU end, i+1 indicating the number of target time information in the target time information sequence, A _it Indicating the time for PCIE terminal to collect the target data, the time difference sequence may be "Chi A _1r， ɡA _2r， ɡA _{3r，……，} ɡA _nr ”，ɡA _nr Is equal to A _ir - A _it 。

Step 203, determining at least one of a first average value, a first median, a first maximum value, a first minimum value and a first interval ratio of the time difference sequence, and obtaining statistical data of the target time information sequence; wherein the first interval ratio represents a ratio at which a time difference in the time difference sequence belongs to a first time difference interval.

In this embodiment, the first average value may be an average value of the time difference series.

The first median may be a median of the time difference sequence.

The first maximum value may be the maximum value in the time difference sequence.

The first minimum value may be a minimum value of a time difference sequence.

The first time difference interval may be a predetermined time difference interval.

Step 204, determining data transmission performance of the PCIE terminal based on the statistical data, where the data transmission performance indicates performance of data transmission of the PCIE terminal with respect to a preset reference terminal.

In this embodiment, step 204 is substantially identical to step 103 in the corresponding embodiment of fig. 1, and will not be described herein.

In some alternative implementations of the present embodiment, the time difference sequence may be determined based on the target time information sequence in the following manner:

first, for non-first target time information in the target time information sequence, determining a difference between the target time information and previous target time information of the target time information in the target time information sequence, and obtaining a time difference corresponding to the target time information.

Then, the obtained sequence of each time difference composition is determined as a time difference sequence.

As an example, in the case where the target time information sequence is obtained by determining the manner in which the CPU side collects the time information of the target data in the target data sequence in step 201, the time difference in the time difference sequence may represent the time difference in which the two CPU sides collect the target data. In this case, the time difference sequence may be determined based on the target time information sequence in the following manner:

if the target time information sequence is "A _0r 、A _1r ……A _ir ", wherein A _ir Indicating the time of the CPU terminal collecting the target data, i indicating the amount of target time information in the target time information sequence, then the time difference sequence may be "B _0r 、B _ir ……B _（i-1）r ”，B _（i-1）r Is equal to A _ir -A _（i-1）r 。

As yet another example, in the case where the target time information sequence is obtained by determining the time information of the target data in the target data sequence by the PCIE terminal in step 201, the time difference in the time difference sequence may represent the time difference of the PCIE terminal for collecting the two target data. In this case, the time difference sequence may be determined based on the target time information sequence in the following manner:

if the target time information sequence is "A _0t 、A _1t ……A _it ", wherein A _it Indicating the time when the PCIE end collects the target data, i indicates the amount of the target time information in the target time information sequence, then the time difference sequence may be "B _0t 、B _it ……B _（i-1）t ”，B _（i-1）t Is equal to A _it -A _（i-1）t 。

It can be appreciated that in the above alternative implementation manner, the data transmission performance of the PCIE terminal may be tested at a lower cost by determining the difference between the target time information and the previous target time information of the target time information in the target time information sequence.

In some application scenarios in the above optional implementation manners, the following manner may be adopted to determine, based on the statistical data, data transmission performance of the PCIE terminal:

and a first step of determining whether the first average value belongs to a first numerical value interval to obtain first discrimination information.

The first determination information may indicate whether the first average value belongs to the first numerical range. The first numerical value interval may represent a preset numerical value interval.

And a second step of determining whether the first median belongs to a second numerical range or not to obtain second discrimination information.

The second discrimination information may indicate whether the first median belongs to the second numerical range. The second value interval may represent a preset value interval.

And thirdly, determining whether delay jitter exists or not based on the first maximum value and the first minimum value, and obtaining third judging information.

The third discrimination information may indicate whether or not there is delay jitter.

And step four, determining a difference value between the first average value and the first maximum value or the first minimum value to obtain a target difference value.

Wherein the target difference may represent a difference of the first average value and the first maximum value or the first minimum value.

And fifthly, determining whether the target difference value is smaller than or equal to a preset value, and obtaining fourth judging information.

The fourth discrimination information may indicate whether the target difference is less than or equal to a preset value.

And a sixth step of determining the data transmission performance of the PCIE end based on the first discrimination information, the second discrimination information, the third discrimination information, the fourth discrimination information, and the first section ratio.

As an example, in step 201, in the case that the target time information sequence is obtained by determining the manner that the CPU terminal collects the time information of the target data in the target data sequence, the method can intuitively reflect the frequency of transmitting the target data by the PCIE terminal, and analyze the frequency by the first average value, the first maximum value, the first minimum value, the first median and the first interval ratio, where the first average value and the first median can reflect whether the frequency of transmitting the target data by the PCIE terminal is in a reasonable range, and can represent the processing performance status of the device, whether the first maximum value and the first minimum value represent delay jitter, whether the difference between the first average value and the extremum (i.e., the first maximum value and the first minimum value) is smooth, and the excessive jitter amplitude indicate the potential problem of the processing of the device.

As another example, in the case that the target time information sequence is obtained by determining the manner that the PCIE terminal collects the time information of the target data in the target data sequence in step 201, the method can intuitively reflect whether the CPU terminal receives the record, and analyze the record by using a first average value, a first maximum value, a first minimum value, a first median, and a first interval ratio, where the first average value and the first median reflect whether the frequency of the CPU software (i.e., the CPU terminal) receiving the record is in a reasonable range, and can reflect the system processing performance status, whether the first maximum value and the first minimum value reflect delay jitter, whether the difference between the first average value and the extremum (i.e., the first maximum value and the first minimum value) is smooth, and the excessive jitter is too small and too large, which indicates the system processing potential problem. Can view B _ir Such as B _ir Far greater than the first average (e.g. B _ir A difference from the first average value being greater than or equal to a preset threshold value), and B at the first moments _it Without significant fluctuations, performance bottlenecks may be in the software processing or PCIE transport bottlenecks.

It should be noted that, in addition to the above descriptions, the present embodiment may further include the corresponding technical features described in the embodiment corresponding to fig. 1, so as to further achieve the technical effects of the method for testing the data transmission performance shown in fig. 1, and the detailed description is referred to in fig. 1, and is omitted herein for brevity.

According to the data transmission performance testing method provided by the embodiment of the application, the data transmission performance of the PCIE terminal is determined through at least one of the first average value, the first median, the first maximum value, the first minimum value and the first interval ratio of the time difference sequence. Therefore, the test of the data transmission performance of the PCIE terminal can be realized without depending on special equipment, and the test cost of the data transmission performance of the PCIE terminal can be reduced.

The following exemplary description of the embodiments of the present application is provided, but it should be noted that the embodiments of the present application may have the features described below, and the following description should not be construed as limiting the scope of the embodiments of the present application.

PCIE is a high-speed serial bus interface, is a bus type commonly used in modern computer systems, is widely applied to data connection transmission between peripheral equipment and a CPU, and can provide higher bandwidth and lower transmission delay.

In applications requiring the performance of the very fast transmission, PCIE-DMA is often used as a data transmission mode between the device and the CPU, and the performance of the PCIE-DMA greatly influences the performance of the very fast system. Because the device and the CPU use different timestamp calculation modes, it is difficult to uniformly calculate and realize the measurement of delay performance, so that the performance evaluation of the existing PCIE-DMA can only be tested by special equipment, and the application cost is high for many common users, and the popularization and application are difficult.

The method utilizes a plurality of technologies such as statistical analysis, big data mining, linear regression and the like, comprehensively evaluates PCIE-DMA transmission performance in a low cost, facilitates easy-to-use mode, finds performance bottleneck points, and optimizes the performance mining of the system.

In the prior art and scheme, the PCIE performance evaluation needs to rely on a dedicated device, and the PCIE transmission performance is measured by a dedicated hardware device, because of the specificity of PCIE hardware, accurate measurement cannot be performed by using a software mode, and system software also has no similar means.

The PCIE transmission performance can be intuitively reflected by a special equipment mode, but the equipment is high in price and cost and is not friendly to common users, and if the performance condition of the system can be tested by a convenient mode, the PCIE transmission performance is more easily accepted by the public.

In the fields of high-frequency transaction and the like, PCIE equipment such as an FPGA board is often used for quotation and transaction processing, processed data is transmitted to CPU software through DMA, and related data flow is shown in FIG. 3A.

In the process flow shown in fig. 3A, the processing performance of PCIE-DMA includes the time interval from sending data from the device to the memory to the CPU fetching from the memory to the memory, where the time is shown as T2-T1, but the time T1 and T2 are generated by different clock sources, and subtraction of the two is meaningless, so the time acquisition process of T2-T1 needs to be simulated by other means.

The method realizes observability and diagnosability of PCIE-DMA performance by fusing big data statistical analysis technology, and simultaneously can analyze the performance bottlenecks of PCIE equipment and CPU software to realize the performance comparison test of multi-manufacturer PCIE equipment. Fig. 3B is a flow chart of a testing method for data transmission performance according to an embodiment of the present application. The method realizes the delay performance detection of PCIE-DMA, and is completed through the steps of data acquisition, data statistics, analysis and deduction, and optimization and guidance.

Specifically, the method may comprise the steps of:

step one, data collection:

here, the relevant data of the device side (i.e. the PCIE side) and the CPU software side (i.e. the CPU side) may be collected, the data collected by the device side includes a record collection timestamp t, a record identifier d, and record relevant service data s, the data collected by the CPU software side includes a timestamp r when received, a cycle count j waiting for recording (i.e. the cycle count) has the fields described above, and each record value is marked with a, for example, the cycle count of line 2 is a _2j The relevant records are as follows:

A _0t A _0d A _0s A _0r A _0j

A _1t A _1d A _1s A _1r A _1j

A _2t A _2d A _2s A _2r A _2j

_{…………………………}

A _it A _id A _is A _ir A _ij

step two, statistics:

according to the collected data records, recording statistics of various different scenes are carried out, such as:

1) Equipment endPacket pitch statistics, which are the average (i.e., the first average), median (i.e., the first median), maximum (i.e., the first maximum), minimum (i.e., the first minimum), interval ratio (i.e., the first interval ratio), etc., of the packet pitches, sequence B is determined _it， Which takes the value equal to A _(i+1)t -A _it， Sorting is performed to obtain an average avg (B _it )=Maximum max (B _it ) Minimum value min (B _it ) Median (B) _it ) Interval ratio. Wherein i+1, n each represent the number of packets, i.e., the number of target data in the target data sequence.

2) Counting the interval of CPU software, calculating the average value (i.e. the first average value), the median (i.e. the first median), the maximum value (i.e. the first maximum value), the minimum value (i.e. the first minimum value), the interval ratio (i.e. the first interval ratio) and the like of the interval, and obtaining the sequence B _ir， It is equal to A _(i+1)r -A _ir， Sorting is performed to obtain an average avg (B _ir )=Maximum max (B _ir ) Minimum value min (B _ir ) Median (B) _ir ) Interval ratio. Where i+1, n denote the number of packets, i.e. the number of target data in the target data sequence.

3) Comparing and counting between different manufacturer devices (namely the first PCIE end and the second PCIE end), assuming that the record of manufacturer alpha is alpha A, the record of manufacturer beta is beta A, counting CPU time stamps finally falling to the ground, and comparing difference value alpha = alpha A-beta A to obtain a sequence { S A) _0r， ɡA _1r， ɡA _{2r，……，} ɡA _ir Average value (i.e. the second average value) avg (skin A) of this sequence _ir )=The maximum value (i.e., the second maximum value) max (@ a _ir ) Minimum value (i.e., the second minimum value) min (No. a _ir ) A median (i.e. the second median mentioned above) medium (grade a _ir ) The speed ratio (i.e., the second section ratio). Where i+1, n denote the number of packets, i.e. the number of target data in the target data sequence.

Step three, reasoning analysis:

based on the statistics, the collected and counted data can be analyzed, so that the system performance bottleneck is analyzed, decision basis is provided for system optimization, and the following functional analysis can be realized:

1) Visually reflecting the frequency at which the device generates records, by avg (B _it )、max(B _it )、min(B _it )、median(B _it ) Analysis was performed by the section ratio, avg (B _it )、median(B _it ) Reflecting whether the frequency of the record generated by the equipment is in a reasonable range, the processing performance status of the equipment can be represented, max (B _it )、min(B _it ) Whether the value shows delay jitter, whether the difference between the average value and the extreme value is smooth, whether the jitter is too large or too small and the jitter amplitude is too large or not indicate the equipment to treat the potential problem.

2) Intuitively reflects how fast the software receives the record, through avg (B _ir )、max(B _ir )、min(B _ir )、median(B _ir ) Analysis was performed by the section ratio, avg (B _ir )、median(B _ir ) Reflects whether the frequency of the CPU software receiving processing records is in a reasonable range, can embody the processing performance status of the system, and has the characteristics of max (B _ir )、min(B _ir ) Whether the value shows delay jitter, whether the difference between the average value and the extremum value is smooth, and too large and too small jitter and too large jitter amplitude are indicative of potential problems of the system treatment. Can view B _ir Such as B _ir Far greater than avg (B) _ir ) And B at the first few moments _it Without significant fluctuations, performance bottlenecks may be in the software processing or PCIE transport bottlenecks.

3) Realizes the performance comparison of manufacturers, and passes avg (by A) _ir )、max(ɡA _ir )、min(ɡA _ir )、median(ɡA _ir ) The ratio of the speed to the slow speed is analyzed, avg (Ag A) _ir )、median(ɡA _ir ) Reflecting the performance of the manufacturer comparison, if the values are positive, the manufacturer alpha is slower than the manufacturer beta, if the values are negative, the manufacturer alpha is faster than the manufacturer beta, and if the value is greater than the value 0, the difference between the two manufacturers is greater; max (breast A) _ir )、min(ɡA _ir ) The value represents the extreme value of comparison of two manufacturers, if the difference between the extreme value and the average value or the median is larger, the jitter is predicted to be larger, the distribution is unbalanced, the average value is possibly influenced by the extreme value, and the comparison condition is possibly interfered by other factors; the ratio of fast to slow reveals the ratio of fast to slow between manufacturers, and can improve the disadvantage of average value and extremum in statistics to a certain extent, for example, manufacturer alpha accounts for 80% faster than manufacturer beta, and the value can reflect the fast and slow delay performance compared by manufacturers.

4) And analyzing the performance comparison between the equipment and the software, and performing performance comparison analysis between the equipment and the software through the counted data. First, by querying cycle count A _ij Value, when A _ij >0, software can not obtain data from DMA memory, A _ij The higher the waiting time, the more time is needed, so that whether the equipment has a processing bottleneck or not can be analyzed, or the data is paused at the moment; finally, when the software process and the device upstream process operate at the same DMA address, i.e. read-write synchronization, such as at the time of the initial transfer, or the device process is slower than the software process, then the software process A is caused _ij From which it can be discerned that a performance bottleneck may occur.

5) Analyzing the performance of PCIE bus, and from the statistics, the software processing time A _ir Device processing time a _it +PCIE transmission delay P _i +DMA memory fetch latency D _i However, the software time stamp and the device time stamp are not in the same clock source, and cannot be calculated by equation, so the equation is not established, but the linear relationship can be determined by the packet interval, such as B _ir≈ B _it +P _i +D _i， Convert one down P _i≈ B _ir -B _it -D _i So P _i The value of (2) is represented by B _it、 B _it、 D _i To determine due to D _i And P _i Is synchronous, that is, is exactly P _i≈ B _ir -B _it， The delay of the PCIE transmission at a certain moment can be evaluated through the equipment recording interval and the software end recording interval, and of course, the delay is a relative value, not the inherent performance of the PCIE, but only the relative value of transmitting certain data at a certain moment is reflected, and the value is possibly influenced by the PCIE transmission load pressure and bus competition condition at a certain moment, but the real-time condition of PCIE bus transmission can be fed back to a certain extent, and a certain decision basis can be provided for optimizing a PCIE-DMA transmission system.

Here, the record identifier d and the record-related service data s may be used for data discrimination. Wherein the record identifier d may be a data identifier other than a time stamp. In practice, the same timestamp and/or record identification may not correspond to the same data (i.e., the traffic data s described above).

Thus, in some cases, the following manner may be employed to determine whether the same data is: first, it is determined whether two service data s correspond to the same record identifier. If the two service data s correspond to the same record identifier, it may be further determined whether the two service data s are identical. If the two service data s are identical, it can be determined that the two service data s are identical. If the two traffic data s are different, it can be determined that the two traffic data s are different. If the two service data s correspond to different record identifications, it can be directly determined that the two service data s are different.

Further, in the process of implementing vendor performance comparison, that is, in the case of determining the data transmission performance of the first PCIE end relative to the second PCIE end based on the statistical data, the same data may be used for testing. For example, determining time information of the first CPU end for collecting the target data a, b and c, and obtaining a first target time information sequence. And determining the time information of the same target data a, b and c collected by the second CPU end to obtain a second target time information sequence. Then, a first sequence of differences between the first target time information sequence and the second target time information sequence is determined. And then, determining the statistical data of the first difference value sequence to obtain the statistical data of the target time information sequence. And finally, determining the data transmission performance of the first PCIE terminal relative to the second PCIE terminal based on the statistical data. The accuracy of comparison test can be further improved by the aid of the vehicle.

It should be noted that, in addition to the above descriptions, the present embodiment may further include the technical features described in the above embodiments, so as to achieve the technical effects of the above-described method for testing data transmission performance, and specific reference is made to the above description, which is omitted herein for brevity.

The method for testing the data transmission performance provided by the embodiment of the application carries out PCIE-DMA performance detection in a software mode, and the PCIE-DMA performance detection method comprises the steps of data acquisition, data statistics, data analysis and optimization and guidance related methods. The data acquisition comprises record collection time stamps, record identification and record related business data, wherein the data collected by the CPU software end comprises time stamps during receiving, and the record information is related to the cycle count waiting record. The method supports the realization of the statistics of the package interval at the equipment end, can count the data such as the average value, the median, the maximum value, the minimum value, the interval ratio and the like of the package interval, and the realization of the statistics of the CPU software package interval, can count the data such as the average value, the median, the maximum value, the minimum value, the interval ratio and the like of the package interval, and also realizes a comparison statistics mode among equipment of different manufacturers, supports the comparison difference value among comparison manufacturers, and comprises the information of the average value, the median, the maximum value and the minimum value. The method and the technology for detecting the processing performance of the equipment by recording the generation frequency can diagnose the comparison condition of the performances of multiple manufacturers through the delay performance of the software processing of the receiving side and the performance condition of the statistical analysis system. And a method for comparing the performance speed between the analysis equipment and the software and a method for diagnosing the performance condition of the PCIE bus are also provided.

Fig. 4 is a schematic structural diagram of a testing device for data transmission performance according to an embodiment of the present application. The method specifically comprises the following steps:

a first determining unit 401, configured to determine that a PCIE side and/or a CPU side collect time information of target data in a target data sequence, so as to obtain a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; the target data are collected by the PCIE end and then transmitted to a DMA (direct memory access) memory, so that the CPU end collects the target data from the DMA memory;

a second determining unit 402, configured to determine statistics of the target time information sequence;

and a third determining unit 403, configured to determine, based on the statistical data, a data transmission performance of the PCIE peer, where the data transmission performance indicates a performance of data transmission of the PCIE peer with respect to a preset reference peer.

The data transmission performance testing apparatus provided in this embodiment may be a data transmission performance testing apparatus as shown in fig. 4, and may perform all the steps of the above-described data transmission performance testing method, so as to achieve the technical effects of the above-described data transmission performance testing method, and specific reference is made to the above-described related description, which is omitted herein for brevity.

As shown in fig. 5, the embodiment of the present application further provides an electronic device, which includes a processor 111, a communication interface 112, a memory 113, and a communication bus 114, where the processor 111, the communication interface 112, and the memory 113 perform communication with each other through the communication bus 114,

a memory 113 for storing a computer program;

in one embodiment of the present application, the processor 111 is configured to implement the method for testing data transmission performance provided in any one of the foregoing method embodiments when executing the program stored in the memory 113, where the method includes:

determining statistics of the target time information sequence;

The embodiment of the present application further provides a computer readable storage medium having stored thereon a computer program, which when executed by a processor, implements the steps of the method for testing data transmission performance provided in any one of the method embodiments described above, including:

Determining statistics of the target time information sequence;

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the respective embodiments or some parts of the embodiments.

It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for testing data transmission performance, the method comprising:

determining time information of target data in a target data sequence acquired by a PCIE terminal and/or a CPU terminal, and obtaining a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; the method comprises the steps that target data are collected through a PCIE end and then transmitted to a DMA (direct memory access) memory, so that a CPU (central processing unit) end collects the target data from the DMA memory; the time stamp of the PCIE end and the time stamp of the CPU end are not in the same clock source;

determining statistics of the target time information sequence;

2. The method according to claim 1, wherein the target time information in the target time information sequence is represented by a numerical value; and

3. The method of claim 2, wherein the determining a time difference sequence based on the target time information sequence comprises:

4. The method of claim 3, wherein the determining the data transmission performance of the PCIE peer based on the statistics comprises:

5. The method of claim 1, wherein the determining that the PCIE side and/or the CPU side collect time information of the target data in the target data sequence to obtain the target time information sequence includes:

6. The method of claim 5, wherein said determining statistics of said first sequence of differences comprises:

7. The method according to claim 1, wherein the CPU side performs an acquisition operation according to a preset frequency to acquire target data; and

8. The method of claim 1, wherein the determining that the PCIE side and/or the CPU side collect time information of the target data in the target data sequence to obtain the target time information sequence includes:

9. A test device for data transmission performance, the device comprising:

the first determining unit is used for determining time information of target data in the PCIE terminal and/or the CPU terminal acquisition target data sequence to obtain a target time information sequence; wherein, the target data in the target data sequence corresponds to the target time information in the target time information sequence one by one; the method comprises the steps that target data are collected through a PCIE end and then transmitted to a DMA (direct memory access) memory, so that a CPU (central processing unit) end collects the target data from the DMA memory; the time stamp of the PCIE end and the time stamp of the CPU end are not in the same clock source;

10. An electronic device, comprising:

a memory for storing a computer program;

a processor for executing a computer program stored in said memory, and which, when executed, implements the method of any of the preceding claims 1-8.

11. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of any of the preceding claims 1-8.