CN117033267B - Hybrid memory master controller and hybrid memory - Google Patents

Abstract

The embodiment of the application relates to the field of solid state disk application and discloses a hybrid storage main controller and a hybrid storage, wherein the hybrid storage main controller comprises a storage medium controller, the storage medium controller corresponds to a channel, and the channel corresponds to at least two storage media; wherein the storage medium controller controls data access of at least two storage media through corresponding channels. By setting at least two corresponding storage media under the same channel, one storage medium controller can control data access of the at least two storage media, and the expansibility and compatibility of the storage medium controller can be improved.

Description

Hybrid memory master controller and hybrid memory

Technical Field

The application relates to the field of solid state disk applications, in particular to a hybrid storage main controller and a hybrid storage.

Background

The solid state disk (Solid State Drives, SSD) is a hard disk made of a solid state electronic memory chip array, and the solid state disk comprises a control unit and a memory unit (a Flash memory chip or a DRAM memory chip). Flash memory (NAND Flash) is the primary storage medium for solid state disks.

At present, the hybrid storage comprises a hybrid structure of flash memory medium particles and SCM medium particles, however, the hybrid structure usually designs two independent medium controllers, namely the flash memory medium controller and the SCM medium controller, but because the flash memory medium controller and the SCM medium controller exist independently, only one medium particle exists in the same channel, and in consideration of capacity, a plurality of channels need to be expanded, so that hardware design resources are wasted.

Disclosure of Invention

The embodiment of the application aims to provide a hybrid storage main controller and a hybrid storage, which solve the problem of insufficient expansibility caused by corresponding one medium particle to the same channel at present, and improve the expansibility and compatibility of a storage medium controller.

In order to solve the technical problems, the embodiment of the application provides the following technical scheme:

in a first aspect, an embodiment of the present application provides a hybrid storage master controller, including:

a storage medium controller corresponding to one channel, the channel corresponding to at least two storage media;

wherein the storage medium controller controls data access of at least two storage media through corresponding channels.

In some embodiments, a hybrid storage master controller includes:

at least two storage medium controllers, each corresponding to one channel, each corresponding to at least two storage media;

wherein each storage medium controller controls data access of at least two storage media through a corresponding channel.

In some embodiments of the present invention, in some embodiments,

a storage medium controller comprising:

the command path module is used for the command interaction between the storage medium controller and the hardware module of the hybrid memory;

the data path module is used for data interaction between the storage medium controller and the hardware module of the hybrid memory;

the storage medium controller logic layer is connected with the command path module and the data path module and is used for processing logic layers of at least two medium protocol stacks, and each medium protocol stack corresponds to one storage medium one by one;

the storage medium controller physical layer is connected with the storage medium controller logic layer and is used for processing physical layer processing of medium time sequence operation;

and the IO function module of the storage medium controller is connected with the physical layer of the storage medium controller and is used for processing IO signals.

In some embodiments of the present invention, in some embodiments,

A storage medium controller logic layer, comprising:

the command interface module is used for analyzing the external command generated by the command access module to generate a medium control internal command and decomposing the medium control internal command into a medium protocol command;

the data interface module is used for analyzing the external data generated by the data path module to generate medium control internal data and decomposing the medium control internal data into medium protocol data;

the logic layer control module is connected with the command interface module and the data interface module and is used for receiving the medium protocol command sent by the command interface module and receiving the medium protocol data sent by the data interface module;

and each protocol stack logic module is used for generating an operation sequence corresponding to the medium protocol of the corresponding storage medium.

In some embodiments of the present invention, in some embodiments,

a logic layer control module comprising:

each protocol stack register group corresponds to one medium protocol one by one, and is used for storing control configuration parameters of the corresponding medium protocol;

The protocol stack control state machine is used for controlling the processing procedures of different medium protocol operation sequences;

and the logic layer protocol stack operation control module is used for carrying out protocol logic operation of the medium protocol.

In some embodiments of the present invention, in some embodiments,

a storage medium controller physical layer comprising:

each time sequence generation module corresponds to one medium protocol one by one, and each time sequence generation module is used for generating a time sequence control signal of a corresponding protocol medium;

and the physical layer control module is connected with each time sequence generation module and is used for switching management of at least two protocol time sequences.

In some embodiments of the present invention, in some embodiments,

the at least two time sequence generating modules comprise a first time sequence generating module and a second time sequence generating module, wherein the first time sequence generating module and the second time sequence generating module are both connected with the IO functional module of the storage medium controller, and the first time sequence generating module and the second time sequence generating module are used for sending time sequence control signals to the IO functional module of the storage medium controller.

In some embodiments of the present invention, in some embodiments,

a physical layer control module, comprising:

each DLL register set corresponds to one protocol time sequence one by one, and each DLL register set is used for storing control configuration parameters of the corresponding protocol time sequence;

The DLL control state machine is used for controlling the processing procedures of different protocol time sequences;

and the physical layer time sequence operation control module is used for performing time sequence operation of the protocol time sequence.

In some embodiments of the present invention, in some embodiments,

the storage medium controller logic layer and the storage medium controller physical layer are communicated through a DFI interface module;

wherein,

the storage medium controller logic layer includes a first DFI interface module, the storage medium controller physical layer includes a second DFI interface module, and the storage medium controller logic layer sends an operation sequence to the second DFI interface module through the first DFI interface module.

In some embodiments of the present invention, in some embodiments,

the hybrid storage main controller further includes:

an NVMe controller for processing NVMe protocol of the hybrid memory and the host;

a dynamic random access memory controller for controlling the dynamic random access memory;

and the data transmission module is used for data transmission between the NVMe controller and the storage medium controller.

In a second aspect, embodiments of the present application provide a hybrid memory, including:

the hybrid storage host controller of the first aspect;

at least two host ports, wherein each host port is configured to establish a separate access path between a host and a storage medium controller.

In some embodiments of the present invention, in some embodiments,

the at least two host ports include a first host port and a second host port,

the at least two storage media include an SSD storage medium and an SCM storage medium;

wherein,

a first host port for constructing an SSD access path for the host and the storage medium controller;

and a second host port for constructing SCM access paths of the host and the storage medium controller.

The beneficial effects of the embodiment of the application are that: in comparison with the prior art, the hybrid storage main controller and the hybrid storage provided by the embodiment of the application comprise a storage medium controller, wherein the storage medium controller corresponds to one channel, and the channel corresponds to at least two storage media; wherein the storage medium controller controls data access of at least two storage media through corresponding channels. By setting at least two corresponding storage media under the same channel, one storage medium controller can control data access of the at least two storage media, and the expansibility and compatibility of the storage medium controller can be improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a schematic structural diagram of a solid state hard disk hardware framework provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a solid state disk provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a host and a memory according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a memory hardware framework according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a hybrid memory according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a first hybrid storage host controller and channel provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of a second hybrid storage host controller and channel provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of a third hybrid storage host controller and channel provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of a storage medium controller according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a logical layer of a storage medium controller and a physical layer of the storage medium controller according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a logic layer control module according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a physical layer control module according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a protocol sequence and a protocol stack sequence according to an embodiment of the present application;

FIG. 14 is a schematic diagram of clock switching in a switching sequence according to an embodiment of the present disclosure;

fig. 15 is a flow chart of a protocol operation switching control method according to an embodiment of the present application;

fig. 16 is an overall flow chart of a protocol operation switching control method provided in the embodiment of the present application.

Reference numerals illustrate:

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In addition, technical features described below in the various embodiments of the present application may be combined with each other as long as they do not conflict with each other.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a solid state disk hardware frame provided in an embodiment of the present application;

As shown in fig. 1, the solid state disk (Solid State Drives, SSD) generally includes a solid state disk Controller, i.e., an SSD Controller (SSD Controller), a Connector (Connector), a flash memory array, a cache unit, and other peripheral units.

The solid state disk controller is used as a control operation unit for managing an SSD internal system;

among them, a Flash Array (NAND Flash Array), which is used as a storage unit for storing data, including user data and system data, generally presents a plurality of Channels (CH), and one Channel is independently connected to a group of Flash arrays, for example: channel 0, channels 1, … …, channel x are each independently connected to a set of flash memory arrays. It will be appreciated that Flash memory (NAND Flash) is characterized by the fact that it must be erased before writing, and that each Flash memory has a limited number of erases.

The cache unit is used for caching the mapping table and comprises a dynamic random access memory (Dynamic Random Access Memory, DRAM).

Wherein, connector (Connector) is used for connecting the host computer, for example: a PC or a server.

Other peripheral units include serial ports (Serial Peripheral Interface, SPI), sensors (Sensor), registers, universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), power chips, other interfaces, such as: JTAG interface, etc.

Referring to fig. 2 again, fig. 2 is a schematic structural diagram of a solid state disk according to an embodiment of the present application;

as shown in fig. 2, the solid state disk includes a flash memory medium and a solid state disk controller connected to the flash memory medium. The solid state disk is in communication connection with the host in a wired or wireless mode and is used for realizing data interaction.

The Flash memory medium, which is also called as Flash memory, flash memory or Flash particles, belongs to one type of memory device, is a nonvolatile memory, can store data for a long time even without current supply, and has storage characteristics equivalent to a hard disk, so that the Flash memory medium becomes the basis of the storage medium of various portable digital devices.

The structure of the memory cell is very similar to that of a common semiconductor transistor, the Flash memory medium (NAND Flash) is characterized in that the single transistor of the NAND Flash is added with a floating gate and a control gate, the floating gate is used for storing electrons, the surface of the floating gate is covered by a layer of silicon oxide insulator and is coupled with the control gate through a capacitor, when negative electrons are injected into the floating gate under the action of the control gate, the storage state of a single crystal of the NAND Flash is changed from '1' to '0', and when the negative electrons are removed from the floating gate, the storage state is changed from '0' to '1', and the insulator covered on the surface of the floating gate is used for trapping the negative electrons in the floating gate, so that data storage is realized. That is, the memory cells of NAND Flash are floating gate transistors, which are used to store data in the form of charges. The amount of charge stored is related to the magnitude of the voltage applied by the floating gate transistor.

One NAND Flash includes at least one Chip, each Chip is composed of a plurality of Block physical blocks, and each Block physical Block includes a plurality of Page pages. The Block physical Block is the minimum unit of the NAND Flash for executing the erasing operation, the Page is the minimum unit of the NAND Flash for executing the reading and writing operation, and the capacity of one NAND Flash is equal to the number of the Block physical Block and the number of Page pages contained in the Block physical Block and the capacity of one Page. Specifically, the flash memory medium can be classified into SLC, MLC, TLC and QLC according to different levels of voltages of memory cells.

The solid state disk controller, namely the master control, comprises a data converter, a processor, a buffer, a flash memory controller and an interface.

And the data converter is respectively connected with the processor and the flash memory controller and is used for converting binary data into hexadecimal data and converting hexadecimal data into binary data. Specifically, when the flash memory controller writes data to the flash memory medium, binary data to be written is converted into hexadecimal data by the data converter, and then written to the flash memory medium. When the flash memory controller reads data from the flash memory medium, hexadecimal data stored in the flash memory medium is converted into binary data by the data converter, and then the converted data is read from the binary data page register. The data converter may include a binary data register and a hexadecimal data register, among others. Binary data registers may be used to hold data converted from hexadecimal to binary, and hexadecimal data registers may be used to hold data converted from binary to hexadecimal.

The processor is respectively connected with the data converter, the buffer, the flash memory controller and the interface, wherein the processor can be connected with the data converter, the buffer, the flash memory controller and the interface through buses or other modes, and is used for running nonvolatile software programs, instructions and modules stored in the buffer, or used for providing an accessed interface and protocol, realizing a corresponding SAS/SATA target protocol end or NVMe protocol end, acquiring I/O instructions sent by the host, decoding and generating internal private data results and waiting for execution; or for taking care of the core processing of the flash translation layer (Flash translation layer, FTL) to implement any method embodiments of the present application.

The buffer is mainly used for buffering read/write instructions sent by the host and read data or write data obtained from the flash memory medium according to the read/write instructions sent by the host. The buffer is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs and modules. The buffer may include a storage program area that may store an operating system, an application program required for at least one function. In addition, the buffer may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the buffer may optionally include memory located remotely from the processor. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The buffer may be static random access memory (Static Random Access Memory, SRAM) or coupled memory (Tightly Coupled Memory, TCM) or double rate synchronous dynamic random access memory (Double DataRate Synchronous Dynamic Random Access Memory, DDR SRAM).

The flash memory controller is connected with the flash memory medium, the data converter, the processor and the buffer and is used for accessing the flash memory medium at the rear end and managing various parameters and data I/O of the flash memory medium; or, the interface and the protocol for providing access are used for realizing a corresponding SAS/SATA target protocol end or NVMe protocol end, acquiring an I/O instruction sent by the host, decoding and generating an internal private data result, and waiting for execution; or for taking care of the core processing of the flash translation layer (Flash translation layer, FTL).

The interface is connected with the host and the data converter, the processor and the buffer and is used for receiving data sent by the host or receiving data sent by the processor and realizing data transmission between the host and the processor, and the interface can be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCIe interface, an NGFF interface, a CFast interface, an SFF-8639 interface and an M.2 NVME/SATA protocol.

Referring to fig. 3 again, fig. 3 is a schematic diagram of a host and a memory according to an embodiment of the present disclosure;

as shown in fig. 3, the host includes a processor, a memory Controller (Memory Controller), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a storage class memory (Storage Class Memory, SCM), and an IO Controller (IO Controller).

Wherein, inside the host, the SCM is used as a cache of the DRAM, at this time, the memory controller is connected with the DRAM, and the DRAM is connected with the SCM; alternatively, the SCM is directly used as the memory, and at this time, the memory controller is directly connected to the SCM.

The memory comprises a memory controller, a SAS SSD, an NVMe SSD, an SCM or an HDD. At this time, the SCM is part of the memory, i.e., the SCM is juxtaposed with the SAS SSD, NVMe SSD, or HDD.

Referring to fig. 4 again, fig. 4 is a schematic structural diagram of a memory hardware framework according to an embodiment of the present application;

as shown in fig. 4, the memory hardware framework connects the SCM medium and the flash memory medium with the main controller through corresponding channels, for example: the SCM medium is connected with the main controller through an SCM medium channel, the flash memory medium is connected with the main controller through a flash memory channel, and the main controller is generally provided with two independent medium controllers which are an SCM medium controller and a flash memory medium controller respectively, wherein the SCM medium controller controls the data access of the SCM medium through the SCM medium channel, and the flash memory medium controller controls the data access of the flash memory medium through the flash memory channel.

However, in this arrangement, since the SCM media controller and the flash media controller are independent, only one media particle exists in the same channel, and considering the capacity problem of the memory, if the capacity of the memory is large, more channels need to be expanded at this time, which results in waste of hardware design resources.

In view of this, the embodiments of the present application provide a hybrid media host controller, by setting at least two storage media corresponding to the same channel, so that one storage media controller can control data access of at least two storage media, so as to improve expansibility and compatibility of the storage media controller.

Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of a hybrid memory according to an embodiment of the present application;

as shown in fig. 5, the hybrid memory 100 includes a hybrid memory host controller 10, a hybrid memory medium 20, a dynamic random access memory 30, and first and second host ports 401 and 402.

Wherein the hybrid storage main controller 10 is configured to access the hybrid storage medium 20 through a corresponding channel.

Wherein the hybrid storage media 20 are connected to the hybrid storage master controller 10, the hybrid storage media 20 are used for storing data, wherein each hybrid storage media 20 comprises at least two storage media, such as: SCM media and flash media.

The dynamic random access memory 30, i.e., dynamic random access memory (Dynamic Random Access Memory, DRAM), is used as a buffer for buffering read/write commands sent by the host and read data or write data obtained from the hybrid storage medium 20 according to the read/write commands sent by the host.

The first host port 401 is configured to communicate with a host in an underlying protocol, where the first host port 401 communicates with the host through a first communication protocol, for example: the first communication protocol is a PCIe interface protocol.

In the embodiment of the present application, the first host port 401 includes:

and the PCIe module includes a PCIe Controller (PCIe Controller), where the PCIe Controller is used as a port to interface with the host, and is configured to receive data sent by the host, and implement data transmission between the host and the hybrid memory 100. It is understood that the PCIe controller includes a PCIe interface.

Specifically, the first host port 401 is configured to process related operations of the PCIe protocol, for example: read and write operations based on PCIe protocols. It is understood that peripheral component interconnect express (peripheral component interconnect express, PCIe) is a high-speed short-range communication interface and is widely used in computers, test instruments, and the like. The main constituent elements of PCIe systems are Root nodes (Root), switch nodes (Switch), and end nodes (Endpoint).

The Root is responsible for managing all buses and nodes in the PCIe system and is a bridge for communication between a central processing unit (central processing unit, CPU) and an Endpoint in the PCIe system; the Switch is used as a data forwarding node and is connected with the Endpoint; endpoint is an end device, such as a Peripheral (Peripheral). In PCIe systems, communication cannot be directly performed between end points, and Root must be passed.

The first host port 401 further includes a physical layer (PHY).

The first host port 401 further comprises an NVMe module comprising an NVMe controller for handling relevant operations of the NVMe protocol, such as: access to NVMe pathway.

In the embodiment of the present application, the second host port 402 is similar to the first host port 401, and the second host port 402 also includes a PCIe controller, a physical layer, and an NVMe controller, where the first host port 401 and the second host port 402 share the NVMe controller, that is, NVMe supports two host interfaces.

In the embodiment of the present application, the first host port 401 and the second host port 402 are used to implement independent access paths of two storage media, for example: the hybrid storage medium includes a first storage medium and a second storage medium, the first host port 401 is used to implement an access path of the first storage medium, and the second host port 402 is used to implement an access path of the second storage medium.

Referring to fig. 6 again, fig. 6 is a schematic diagram of a first hybrid memory host controller and channels according to an embodiment of the present application;

as shown in fig. 6, the hybrid storage main controller 10 includes a storage medium controller 80, wherein the storage medium controller 80 corresponds to one channel corresponding to one hybrid storage medium 20 including at least two types of storage media, for example: the hybrid storage medium 20 includes a first storage medium 21 and a second storage medium 22.

Wherein the storage medium controller 80 is connected to the hybrid storage medium 20 through the channel such that the storage medium controller 80 interfaces with at least two storage media such that the storage medium controller 80 can control data access of at least two storage media of the hybrid storage medium 20, i.e., the storage medium controller 80 can control data access of each storage medium of the hybrid storage medium 20.

It will be appreciated that the number of first storage media 21, second storage media 22 in the hybrid storage medium 20 is set according to specific needs, for example: the first storage medium 21 is provided in two, and the second storage medium 22 is provided in two. It is understood that each storage medium is a media particle.

In the embodiment of the application, by setting at least two corresponding storage media under one channel, one storage medium controller can control the data access of the at least two storage media, so that the expansibility and compatibility of the storage medium controller are improved.

Further, the hybrid storage main controller includes:

at least two storage medium controllers, each corresponding to one channel, each corresponding to at least two storage media;

Wherein each storage medium controller controls data access of at least two storage media through a corresponding channel.

Specifically, referring to fig. 7 again, fig. 7 is a schematic diagram of a second hybrid storage host controller and channels according to an embodiment of the present application;

as shown in fig. 7, the hybrid storage main controller 10 includes a first storage medium controller 11 and a second storage medium controller 12, and the first storage medium controller 11 and the second storage medium controller 12 correspond to a first channel and a second channel, respectively.

The first storage medium controller 11 is connected to the hybrid storage medium 20 through a first channel, where the hybrid storage medium 20 includes a first storage medium 21 and a second storage medium 22, where the number of the first storage medium 21 and the second storage medium 22 in the same hybrid storage medium is set according to specific needs, for example: the first storage medium 21 is provided in two, and the second storage medium 22 is provided in two. It is understood that each storage medium is a media particle.

Similarly, the second storage medium controller 12 is connected to the corresponding hybrid storage medium through the second channel, where the hybrid storage medium corresponding to the second storage medium controller 12 also includes a first storage medium and a second storage medium, where the number of the first storage medium and the second storage medium in the same hybrid storage medium is set according to specific needs, for example: the first storage medium is provided in two, and the second storage medium is provided in two.

Further, referring to fig. 8, fig. 8 is a schematic diagram of a third hybrid memory host controller and channels according to an embodiment of the present application;

as shown in fig. 8, the hybrid storage main controller includes a plurality of storage medium controllers, each of which corresponds to one channel one by one, each of which corresponds to at least two types of storage media, and the number of each type of storage media is set according to specific needs, for example: the first storage medium controller corresponds to a first channel, and the first channel corresponds to a first storage medium and a second storage medium; the second storage medium controller corresponds to a second channel, and the second channel corresponds to the first storage medium and the second storage medium; the third storage medium controller corresponds to a third channel, and the third channel corresponds to the first storage medium and the second storage medium.

It should be noted that, the same channel in the embodiments of the present application may correspond to a plurality of storage media, for example: the first storage medium controller corresponds to a first channel, and the first channel corresponds to three storage media, namely a first storage medium, a second storage medium and a third storage medium; alternatively, the first channel corresponds to more than three types of storage media, and is not illustrated herein.

In the embodiment of the application, by arranging the plurality of storage medium controllers, each storage medium controller corresponds to one channel one by one, so that the plurality of channels can access the hybrid storage medium in parallel, and the read-write performance of the hybrid storage is improved.

Specifically, referring to fig. 9, fig. 9 is a schematic structural diagram of a storage medium controller according to an embodiment of the present application;

as shown in fig. 9, the storage medium controller 80 includes:

a command path module 81 for command interaction of the storage medium controller with the hardware module of the hybrid memory;

specifically, the command path module 81 is configured to take charge of a command interaction path between the storage medium controller 80 and an external module of the hybrid memory, for example: the storage medium controller 80 is responsible for interacting with the command messages of the processor or other hardware module, such as: and receiving and sending command messages and taking charge of command analysis and feedback information. In an embodiment of the present application, the other hardware modules include a data path hardware logic module (Data Path Processor) for controlling the transmission of the data blocks by transmitting messages when the data interaction is performed.

A data path module 82 for data interaction of the storage medium controller with the hardware module of the hybrid memory;

specifically, the data path module 82 is configured to take charge of a data interaction path between the storage medium controller 80 and an external module of the hybrid memory, for example: the external modules of the hybrid memory include a double rate synchronous dynamic random access memory (Double DataRate Synchronous Dynamic Random Access Memory, DDR SRAM) and other hardware modules, and the data path module 82 is used for taking charge of data interaction between the storage medium controller 80 and the external modules, including: receive and transmit data and are responsible for splitting and combining data packets.

In the embodiment of the present application, the command path module 81 and the data path module 82 are configured to construct at least two independent storage medium access paths, where each independent storage medium access path is used for a host to access a corresponding storage medium, for example: the hybrid storage medium includes a first storage medium and a second storage medium, where the first storage medium is an SCM storage medium, and the second storage medium is an SSD storage medium, that is, a flash memory medium, and then the command path module 81 and the data path module 82 of each storage medium controller 80 construct an independent SCM access path and an SSD access path based on the corresponding channels, where the SCM access path and the SSD access path are used by the host to access the SCM storage medium and the SSD storage medium, that is, the flash memory medium, respectively, for example: the first storage medium controller constructs an SCM access path and an SSD access path through its command path module and data path module and the first channel. It is understood that the SCM access path and the SSD access path each include a command path and a data path to enable command interaction and/or data interaction with the storage medium.

A logic layer 83 of the storage medium controller, configured to process logic layer processing of at least two media protocol stacks, where each media protocol stack corresponds to one storage medium;

specifically, the storage medium controller logic layer 83 is compatible with at least two media protocol stacks, and processes logic layer processing of at least two media protocol stacks, where each media protocol stack corresponds to one storage medium one by one.

A storage medium controller physical layer 84 for handling physical layer processing of medium timing operations and for handling physical layer processing of at least two medium timings, wherein each medium timing corresponds to one storage medium one-to-one;

specifically, the physical layer 84 of the storage medium controller is compatible with at least two media protocol sequences, and is used for physical layer processing responsible for media sequence operations, i.e. physical layer processing for processing media sequence operations of at least two media protocol stacks, and physical layer processing for processing at least two media sequences, wherein each media sequence operation corresponds to one media protocol stack, and each media sequence corresponds to one storage medium one by one.

It will be appreciated that the protocol stack is at the operational command level, such as: a write command includes a command code, an address code, and data, wherein the command code, the address code, and the data are transmitted in a sequential order. The protocol stack switch includes switch of different command sets, for example: some protocol address codes are 5 Bytes and some are 6 Bytes.

It will be appreciated that protocol timing is at the signal waveform level, such as: protocol timing includes clock frequencies at the signal waveform level or delay rules between signals. The protocol time sequence switching comprises switching of clock frequency or switching of delay rules between signals.

Specifically, referring to fig. 10 again, fig. 10 is a schematic structural diagram of a logical layer and a physical layer of a storage medium controller according to an embodiment of the present application;

as shown in fig. 10, the storage medium controller logic layer 83 includes:

the command interface module 831 is connected to the command path module and the logic layer control module, and is configured to parse the external command generated by the command path module to generate a medium control internal command, and decompose the medium control internal command into a medium protocol command.

Specifically, the command interface module 831 is configured to parse and escape the external command information of the upper command path module to form a medium control internal command, and then further decompose the medium control internal command into a command of a medium protocol layer. For example: an internal flash read command is decomposed into flash command codes "00" and "30" for delivery to the logical layer control module.

The data interface module 832 is connected to the data path module and the logic layer control module, and is configured to parse the external data generated by the data path module to generate internal data of the medium control, and decompose the internal data of the medium control into medium protocol data.

Specifically, the data interface module 832 is configured to parse and escape the external data composition format of the upper data path module to form a medium control internal data composition format, and then further decompose the external data composition format into data compositions of a medium protocol layer. For example: an internal flash write command is split into three pages of data components for transfer to the logical layer control module.

The logic layer control module 833 is connected to the command interface module 831 and the data interface module 832, and is configured to receive the media protocol command sent by the command interface module, and is configured to receive the media protocol data sent by the data interface module.

Specifically, the logic layer control module 833 is configured to take charge of switching management of at least two protocol stacks, and specifically, the switching management of the protocol stacks is implemented by controlling the switching of the state machine of the protocol stacks.

The storage medium controller logic layer 83 includes at least two protocol stack logic modules including a first protocol stack logic module and a second protocol stack logic module, where the first protocol stack logic module corresponds to a first storage medium, and the first protocol stack logic module is configured to generate an operation sequence corresponding to a medium protocol of the first storage medium; the second protocol stack logic module corresponds to a second storage medium, and the second protocol stack logic module is configured to generate an operation sequence corresponding to a media protocol of the second storage medium, for example: the at least two protocol stack logic modules are respectively:

The first protocol stack logic module 834, the connection logic layer control module 833 and the first DFI interface module 836 are configured to generate an operation sequence corresponding to a media protocol of the first storage medium.

The second protocol stack logic module 835 is connected to the logic layer control module 833 and the first DFI interface module 836, and is configured to generate an operation sequence corresponding to a media protocol of the second storage medium.

In this embodiment of the present application, the storage medium controller logic layer 83 includes at least two protocol stack logic modules, where each protocol stack logic module corresponds to one storage medium one by one, and each protocol stack logic module is configured to generate an operation sequence corresponding to a medium protocol of the corresponding storage medium, for example: the storage medium controller logic layer 83 includes two protocol stack logic modules, namely a first protocol stack logic module 834 and a second protocol stack logic module 835, where the first protocol stack logic module 834 corresponds to a first storage medium, the second protocol stack logic module 835 corresponds to a second storage medium, and the first protocol stack logic module 834 and the second protocol stack logic module 835 are respectively used to generate operation sequences corresponding to medium protocols of the first storage medium and the second storage medium.

It can be appreciated that the storage medium controller logic layer 83 may further include more than three protocol stack logic modules, which are not described in detail.

A first DFI interface module 836, coupled to the first protocol stack logic module 834 and the second protocol stack logic module 835, the first DFI interface module 836 configured to interface with a storage media controller physical layer, and in particular, the first DFI interface module 836 is coupled to a second DFI interface module of the storage media controller physical layer, configured to send an operation sequence to the second DFI interface module.

It should be noted that, the DFI interface module in the embodiment of the present application is used as an interface processing module between a standard logical layer and a physical layer, and no matter how many protocol stack logic modules are, the first DFI interface module 836 in the embodiment of the present application is connected to each protocol stack logic module to implement sending an operation sequence to the physical layer of the storage medium controller, where the operation sequence is an operation sequence meeting the protocol requirements.

In the embodiment of the application, different channels are corresponding to different storage medium controllers, so that independent access of the mixed storage medium is supported, the structure of the mixed storage main controller is optimized to be compatible with at least two mixed storage media, and storage media with different medium operation rates and time sequences can be supported under the same channel, so that the expansibility of the channels of the storage medium controllers is improved.

Referring to fig. 11 again, fig. 11 is a schematic structural diagram of a logic layer control module according to an embodiment of the present application;

as shown in fig. 11, the logic layer control module 833 includes:

the first protocol stack register set 8331 is connected to the protocol stack control state machine 8333 and the logic layer protocol stack operation control module 8334, and is used for storing control configuration parameters of the first media protocol.

The second protocol stack register set 8332 is connected to the protocol stack control state machine 8333 and the logic layer protocol stack operation control module 8334, and is configured to store control configuration parameters of the second medium protocol.

In this embodiment of the present application, the logic layer control module 833 includes at least two protocol stack register sets, each of which is connected to the protocol stack control state machine 8333 and the logic layer protocol stack operation control module 8334, where each of the protocol stack register sets corresponds to one media protocol one by one, and each of the protocol stack register sets is configured to store control configuration parameters of the media protocol corresponding to the protocol stack register set.

The protocol stack control state machine 8333 is connected to the first protocol stack register set 8331, the second protocol stack register set 8332 and the logic layer protocol stack operation control module 8334, and is used for controlling the processing procedures of different media protocol operation sequences.

Specifically, the protocol stack control state machine 8333 is configured to control the processing procedure of the different media protocol sequence operations, for example: switching of different protocol operation sequences.

Referring to fig. 13, fig. 13 is a schematic diagram of a protocol sequence and a protocol stack sequence according to an embodiment of the present application;

as shown in fig. 13, different protocols correspond to different protocol operation sequences, wherein the protocol stack sequences include different combinations of protocol stack operation sequences. The logic layer protocol stack operation control module 8334 is connected to the first protocol stack register set 8331, the second protocol stack register set 8332, and the protocol stack control state machine 8333, and is configured to perform protocol logic operation of the media protocol.

As shown in fig. 13, CEn represents a CHIP ENABLE signal (CHIP ENABLE, CE), where n refers to active low.

CLE represents a COMMAND LATCH ENABLE signal (CLE), which means that after the signal is enabled, the data representing the data bus represents a COMMAND code.

ALE represents an address latch ENABLE signal (ADDRESS LATCH ENABLE, ALE), meaning that after the signal is enabled, the data on the data bus represents an address code.

WEn represents a WRITE ENABLE signal (WE) indicating that after the signal is enabled, the data on the data bus may be flash latched, where n is active low.

REn/RE both represent a READ ENABLE signal (READ ENABLE, RE) that, after being enabled, the data on the data bus may be flash-driven normal, where REn and RE are both differential signal pairs and n is active low.

DQS/DQSn each represent a DATA STROBE signal (DATA STROBE) that is used as a sampling signal for reading and writing DATA, where DQS and DQSn are both differential signal pairs and n refers to active low.

I/O represents a data bus.

R/Bn represents bus available/Busy (Ready/Busy), where n means active low.

t _ADL Indicating the time of receipt of the address to data load (Address to Data Loading Time).

t _CALS The set-up Time (CLE/ALE Setup Time) of the CLE and ALE signals is indicated.

t _CDQSS Indicating the settling time (DQS Setup Time for data input mode start) for DQS to begin based on the data input pattern.

t _WPRE The cycle time (Write Preamble) of the Write Preamble is shown.

t _WPST Indicating the cycle time (Write post) of the Write post-amble.

t _WPSTH The retention time of the written postamble is indicated (Write Postamble Hold Time).

O1h represents a command code for operating the lower page.

8Oh represents one command code or operation code of a write (program) operation command pair.

Col addr 1/Col addr2 represents Column Address 1 (Columb Address 1), column Address 2 (Columb Address 2), respectively, wherein the entire Column Address addresses over 8 bits, and one transmission is 8 bits wide, thus being divided into Column addresses 1,2.

Row Address 1/Row Address 2/Row Address 3 represents Row Address 1 (Row Address 1), row Address 2 (Row Address 2), row Address 3 (Row Address 3), respectively, wherein the whole Row Address addresses over 8 bits, and one transmission is 8 bits wide, so the Row addresses are divided into Row addresses 1,2,3.

DO/D1/Dn represents Data0/1/2, namely Data0 transmitted, data 1 transmitted, data n transmitted, respectively, wherein each Data bit width is 8 bits.

1Ah represents one command code of the write (program) operation command pair.

O2h represents the command code of the page in operation.

Lower page represents the Lower page.

t _WB Indicating the time (WE High to Busy) at which the write operation enable signal goes High to Busy.

t _DCBSYW2 Indicating the time of busy data to cache in write cache mode (Data Cache Busy Time in Write Cache).

Specifically, the logical layer protocol stack operation control module 8334 is configured to perform a protocol logic operation according to the media protocol requirement in the current protocol state.

Specifically, the storage medium controller physical layer 84 includes:

the second DFI interface module 841 is connected to the first DFI interface module and the physical layer control module 842, and is configured to receive the operation sequence sent by the first DFI interface module.

It will be appreciated that the first DFI interface module and the second DFI interface module are each configured to define relevant signal and timing parameters and configurable functional parameters between the controller and the physical layer (PHY), and that the controller and the physical layer (PHY) are each independently designed, and thus have an interface at the logic layer of the controller and an interface at the physical layer (PHY).

It should be noted that, the first DFI interface module and the second DFI interface module include a first DFI interface and a second DFI interface, respectively, the DFI interfaces are used as interface standards for connecting the DDR controller and a DDR physical layer (DDR PHY), and the interface protocol includes operation commands corresponding to the memory, for example: a read command, a write command. The interface protocol includes a DFI standard protocol.

The physical layer control module 842 is connected to the second DFI interface module 841 and each timing generation module, for example: the first timing generation module 843 and the second timing generation module 844 are respectively connected for switching management of at least two protocol timings. The physical layer control module 842 controls the state machine to control the switching management of at least two protocol timings through a DLL.

Referring to fig. 12 again, fig. 12 is a schematic structural diagram of a physical layer control module according to an embodiment of the present application;

as shown in fig. 12, the physical layer control module 842 includes:

a first DLL register set 8421 connected to the DLL control state machine and the physical layer timing operation control module for storing control configuration parameters of the first protocol timing;

a second DLL register set 8422 is coupled to the DLL control state machine and the physical layer timing operation control module for storing control configuration parameters for the second protocol timing.

In this embodiment, the physical layer control module 842 includes at least two DLL register sets, where each DLL register set corresponds to one protocol timing, and each DLL register set is configured to store a control configuration parameter of the corresponding protocol timing.

A DLL control state machine 8423 is coupled to each DLL register set and to the physical layer timing operation control module for controlling the processing of the different protocol timings.

Specifically, the DLL control state machine is configured to control switching of different protocol timings, where the switching of the protocol timings includes: switching of clock frequencies, switching of delay rules between signals, etc. It is understood that a DLL refers to a Delay-locked Loop (DLL) that can be implemented by a Clock frequency measurement method (CFM, clock Frequency Measurement) or a Clock comparison method (CC).

The physical layer timing operation control module 8424 is connected to each DLL register set and the DLL control state machine 8423 for performing a timing operation of the protocol timing.

Specifically, the physical layer timing control module 8424 is configured to generate a timing operation that meets the requirements of the protocol medium in the current timing state.

In an embodiment of the present application, at least two timing generation modules include:

the first timing generation module 843 is coupled to the physical layer control module 842 for generating timing control signals for the first protocol medium.

The second timing generation module 844 is connected to the physical layer control module 842 and is configured to generate a timing control signal for the second protocol medium.

In the embodiment of the present application, the first timing generation module 843 includes a first timing control circuit, and the second timing generation module 844 includes a second timing control circuit. Wherein the first timing control circuit and the second timing control circuit each comprise a timing generation circuit, wherein the timing generation circuit is configured to generate the timing control signal.

The first timing generation module 843 and the second timing generation module 844 are connected to the storage medium controller IO functional module, and the first timing generation module and the second timing generation module are configured to send timing control signals to the storage medium controller IO functional module.

It will be appreciated that the timing control signal is responsible for controlling the correlation between signals, for example: the relationship between the CE signal and the clock signal is controlled, such as: the CE is enabled, and specifically, the CE needs to be enabled before a number of times of the rising edge of the clock. The timing control signal is input to the storage medium controller IO functional module, so that the storage medium controller IO functional module generates a corresponding IO signal based on the timing control signal. It will be appreciated that the storage medium controller IO function module stores an indication of the point in time when the detailed signal goes low to high.

In this embodiment of the present application, the physical layer of the storage medium controller includes at least two timing generation modules, each of the timing generation modules corresponds to one medium protocol one by one, and each of the timing generation modules is configured to generate a timing control signal of a protocol medium corresponding to the timing generation module, where the timing control signal is a timing control signal meeting a requirement of the medium protocol, so that timings of different storage media can be controlled.

Referring to fig. 14, fig. 14 is a schematic diagram of clock switching in a switching timing provided in an embodiment of the present application;

As shown in fig. 14, switching different timings can be achieved by DLL control state machines.

The storage medium controller IO function module 85 is configured to process the IO signal.

Specifically, the storage medium controller IO functional module 85 is connected to the storage medium controller physical layer 84, and is configured to be responsible for processing generation, reception, or judgment of an IO signal.

In an embodiment of the present application, a hybrid storage master controller is provided, where the hybrid storage master controller includes a storage medium controller, where the storage medium controller corresponds to a channel, and the channel corresponds to at least two storage media; wherein the storage medium controller controls data access of at least two storage media through corresponding channels. By setting at least two corresponding storage media under the same channel, one storage medium controller can control data access of the at least two storage media, and the expansibility and compatibility of the storage medium controller can be improved.

Referring to fig. 15 again, fig. 15 is a flow chart of a protocol operation switching control method according to an embodiment of the present application;

the method is applied to the hybrid storage medium controller in the embodiment, and the hybrid storage medium controller comprises a command path module, a data path module, a storage medium controller logic layer, a storage medium controller physical layer and a storage medium controller IO functional module.

As shown in fig. 15, the protocol operation switching control method includes:

step S1501: acquiring a protocol level operation instruction, wherein the protocol level operation instruction corresponds to an operation request;

specifically, the logical layer control module of the logical layer of the storage medium controller acquires an upper layer module, for example: and the command interface module is used for sending a protocol level operation instruction, wherein the protocol level operation instruction corresponds to an operation request, and the operation request comprises a write operation or a read operation.

In the embodiment of the present application, the protocol level operation instruction corresponds to a media protocol, for example: SCM media protocol, SSD media protocol. Wherein each media protocol corresponds to a protocol number one by one.

Step S1502: and adding the operation request into a processing queue of the state machine according to the protocol level operation instruction.

Specifically, according to the protocol number of the medium protocol corresponding to the protocol level operation instruction, whether the state machine needs to be switched is judged by combining with the protocol number corresponding to the currently running state machine, and an operation request is added into a processing queue of the state machine.

It is understood that the state machine refers to a finite state machine (Finite State Machine, FSM), which is composed of a state register and a combinational logic circuit, and is capable of performing state transition according to a preset state according to a control signal, and is a control center for coordinating related signal actions and completing specific operations.

Specifically, according to the protocol level operation instruction, adding the operation request into a processing queue of the state machine, including:

analyzing the protocol level operation instruction to obtain a first protocol number corresponding to the protocol level operation instruction, wherein the first protocol number corresponds to a target protocol state machine;

inquiring a second protocol number of a currently running state machine;

if the first protocol number is the same as the second protocol number, the operation request is added to a processing queue of the target protocol state machine.

In some embodiments of the present invention, in some embodiments,

the method further comprises the steps of:

if the first protocol number is different from the second protocol number, further judging whether the currently running state machine is in a switchable state or not;

if the currently running state machine is in a switchable state, the context of the currently running state machine is saved, the currently running state machine is switched to a target protocol state machine corresponding to the first protocol number, and an operation request is added into a processing queue of the target protocol state machine.

Specifically, referring to fig. 16 again, fig. 16 is an overall flow chart of a protocol operation switching control method provided in the embodiment of the present application;

as shown in fig. 16, the overall flow of the protocol operation switching control method includes:

Step S1601: acquiring a protocol level operation instruction issued by a command interface module;

specifically, the logic layer of the storage medium controller acquires a protocol level operation instruction issued by the command interface module, wherein the protocol level operation instruction corresponds to an operation request, and the operation request comprises a write operation or a read operation. Wherein the protocol level operation instruction corresponds to a media protocol, for example: SCM media protocol, SSD media protocol.

Step S1602: analyzing the protocol number in the protocol level operation instruction;

specifically, the protocol level operation instruction is analyzed to obtain the protocol number of the medium protocol corresponding to the protocol level operation instruction.

Step S1603: inquiring the protocol number of the currently running state machine;

specifically, the currently running state machine is determined, and the protocol number of the currently running state machine is queried.

Step S1604: whether the protocol number of the protocol level operation instruction is consistent with the protocol number of the currently running state machine or not;

specifically, assuming that the protocol number of the protocol level operation instruction is a first protocol number and the protocol number of the currently running state machine is a second protocol number, whether the first protocol number is consistent with the second protocol number is judged.

If the first protocol number is consistent with the second protocol number, the step S1608 is entered;

if the first protocol number is not identical to the second protocol number, the process proceeds to step S1605.

Step S1605: whether the currently running state machine is in a switchable state;

specifically, whether the currently running state machine is in a switchable state is judged, if the currently running state machine meets the preset condition, the state machine is determined to be in the switchable state, and at the moment, the logic layer protocol stack operation control module can be triggered to switch to another state machine for running.

Step S1606: storing the context of the currently running state machine;

specifically, if the protocol number of the protocol level operation instruction is different from the protocol number of the currently running state machine, and the currently running state machine is in a switchable state, the context of the currently running state machine is saved.

Step S1607: switching to a state machine corresponding to the target protocol number;

specifically, after the context of the currently running state machine is saved in the dynamic random access memory, the state machine is switched to a state machine corresponding to a target protocol number, wherein the target protocol number corresponds to the target protocol state machine, and the target protocol number refers to a protocol number of a protocol level operation instruction, namely a first protocol number.

Step S1608: and adding the current operation request into a processing queue of a state machine corresponding to the target protocol number.

Specifically, after switching to the state machine corresponding to the first protocol number, that is, the target protocol state machine, the current operation request is added to the processing queue of the target protocol state machine corresponding to the target protocol number, so that the target protocol state machine can process the operation request subsequently.

In an embodiment of the present application, by providing a protocol operation switching control method, which is applied to the hybrid memory of the above embodiment, the protocol operation switching control method includes: acquiring a protocol level operation instruction, wherein the protocol level operation instruction corresponds to an operation request; and adding the operation request into a processing queue of the state machine according to the protocol level operation instruction.

By adding the operation request corresponding to the protocol level operation instruction to the processing queue of the state machine, the protocol level operation instruction can be processed better.

The embodiments of the present application also provide a nonvolatile computer storage medium, where computer executable instructions are stored, where the computer executable instructions are executed by one or more processors, and may enable the one or more processors to perform the protocol operation switching control method in any of the method embodiments described above, for example, perform the protocol operation switching control method in any of the method embodiments described above.

In an embodiment of the present application, the non-transitory computer readable storage medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the non-volatile computer readable storage medium may include content that is subject to appropriate increases and decreases as required by jurisdictions and by jurisdictions in which such non-volatile computer readable storage medium does not include electrical carrier signals and telecommunications signals.

The apparatus or device embodiments described above are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., and include several instructions for up to a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method of each embodiment or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as above, which are not provided in details for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (7)

1. A hybrid storage master controller, the hybrid storage master controller comprising:

a storage medium controller corresponding to one channel, the channel corresponding to at least two types of storage media;

wherein the storage medium controller controls data access of at least two storage media through corresponding channels;

the storage medium controller includes:

a command path module for command interaction of the storage medium controller with a hardware module of the hybrid memory;

a data path module for data interaction of the storage medium controller with a hardware module of the hybrid memory;

the logic layer of the storage medium controller is connected with the command path module and the data path module and is used for processing logic layers of at least two medium protocol stacks, and each medium protocol stack corresponds to one storage medium one by one;

a storage medium controller physical layer connected with the storage medium controller logic layer for processing physical layer processing of medium time sequence operation;

the IO function module of the storage medium controller is connected with the physical layer of the storage medium controller and is used for processing IO signals;

The storage medium controller logic layer includes:

the command interface module is used for analyzing the external command generated by the command access module to generate a medium control internal command and decomposing the medium control internal command into a medium protocol command;

the data interface module is used for analyzing the external data generated by the data path module to generate medium control internal data and decomposing the medium control internal data into medium protocol data;

the logic layer control module is connected with the command interface module and the data interface module and is used for receiving a medium protocol command sent by the command interface module and receiving medium protocol data sent by the data interface module;

each protocol stack logic module is used for generating an operation sequence corresponding to a medium protocol of the corresponding storage medium;

the logic layer control module comprises:

each protocol stack register group corresponds to one medium protocol one by one, and is used for storing control configuration parameters of the corresponding medium protocol;

The protocol stack control state machine is used for controlling the processing procedures of different medium protocol operation sequences;

and the logic layer protocol stack operation control module is used for carrying out protocol logic operation of the medium protocol.

2. The hybrid storage master controller of claim 1 wherein,

the storage medium controller physical layer includes:

each time sequence generation module corresponds to one medium protocol one by one, and each time sequence generation module is used for generating a time sequence control signal of a corresponding protocol medium;

and the physical layer control module is connected with each time sequence generation module and is used for switching management of at least two protocol time sequences.

3. The hybrid storage master controller of claim 2 wherein,

the at least two time sequence generating modules comprise a first time sequence generating module and a second time sequence generating module, wherein the first time sequence generating module and the second time sequence generating module are both connected with the storage medium controller IO functional module, and the first time sequence generating module and the second time sequence generating module are used for sending the time sequence control signals to the storage medium controller IO functional module.

4. A hybrid storage master controller as defined in claim 2 or 3, wherein,

the physical layer control module includes:

each DLL register set corresponds to one protocol time sequence one by one, and each DLL register set is used for storing control configuration parameters of the corresponding protocol time sequence;

the DLL control state machine is used for controlling the processing procedures of different protocol time sequences;

and the physical layer time sequence operation control module is used for performing time sequence operation of the protocol time sequence.

5. The hybrid storage master controller of claim 1 wherein,

the storage medium controller logic layer and the storage medium controller physical layer are communicated through a DFI interface module;

wherein,

the storage medium controller logic layer comprises a first DFI interface module, the storage medium controller physical layer comprises a second DFI interface module, and the storage medium controller logic layer sends an operation sequence to the second DFI interface module through the first DFI interface module.

6. A hybrid memory, comprising:

the hybrid storage master controller of any one of claims 1-5;

at least two host ports, wherein each host port is configured to establish a separate access path between a host and a storage medium controller.

7. The hybrid memory as in claim 6, wherein,

the at least two host ports include a first host port and a second host port;

the at least two storage media include an SSD storage medium and an SCM storage medium;

wherein,

the first host port is used for constructing an SSD access path of the host and the storage medium controller;

the second host port is used for constructing an SCM access path of the host and the storage medium controller.