CN116938144A - Low-phase noise differential mode common mode resonance separated voltage-controlled oscillator - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B1/00—Details
- H03B1/04—Reducing undesired oscillations, e.g. harmonics
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
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Abstract
The application discloses a low phase noise differential mode common mode resonance separated voltage controlled oscillator, comprising: a transformer module and an active device module; the transformer module comprises a first inductor and a second inductor, wherein two end ports of the first inductor are respectively P1 and P2 ports of the transformer module, and two end ports of the second inductor are respectively P3 and P4 ports of the transformer module; the middle section of the first inductor is provided with a first tap, and the middle section of the second inductor is provided with a second tap; the first tap is connected with a power supply, and the second tap is grounded; the active device module comprises a first NMOS tube, a second NMOS tube, a differential tuning capacitor, a first common mode tuning capacitor and a second common mode tuning capacitor. Compared with the traditional feedback voltage-controlled oscillator, the application can realize differential mode resonance and common mode resonance on only one inductance area, realize the feedback amplification function of the transformer, and realize high common mode and differential mode isolation by separating the common mode and the differential mode capacitor.
Description
Technical Field
The application relates to the field of radio frequency chip design, in particular to a low-phase noise differential mode common mode resonance separated voltage-controlled oscillator.
Background
With the development of mobile communication, the data transmission speed is limited by low bandwidth caused by low frequency band. Therefore, in order to increase the transmission speed, high-order modulation such as 16-QAM,64-QAM, etc. is proposed. But this modulation method increases the phase noise performance requirements for a Voltage Controlled Oscillator (VCO) in the transceiver. In particular, in the CMOS process, CMOS has poor high-frequency performance, so it is challenging to design a voltage-controlled oscillator that meets modulation requirements, but due to the low power consumption, low cost and high yield of CMOS, CMOS is undoubtedly the best material for the civil chip. Thus, designing a low phase noise voltage controlled oscillator in CMOS is a challenge that must be overcome.
The prior art proposes many approaches to reduce the phase noise of CMOS VCO, but often cannot be truly used in industry due to its complexity and lack of robustness in practical use. The most classical technique which can be widely used in practice is the common mode resonance technique. This technique was proposed in 2001 by paper A FilteringTechnique to Lower LC Oscillator Phase Noise by providing a resonant cavity with a resonance at 2 times the fundamental frequency in the common mode path of the VCO, allowing the common mode path to see high impedance at the 2 nd harmonic frequency, thus reducing the loading of the LC resonator due to the tube entering the linear region. However, this technique has a very significant disadvantage in that the VCO requires two inductors, which increases the cost of production due to the large area required for the integration of the inductors on the chip. In 2017, the VCO was optimized by paper replit Common-Mode Resonance in LC Oscillators, and the VCO proposes to use a transformer to realize Common-mode and differential-mode resonance simultaneously, which overcomes the problem that one more inductor is consumed in 2001, but introduces another problem at the same time. Since the actual use of VCO requires capacitive tuning, we need to have its differential mode resonance at f0 and its common mode resonance at 2f0, the phase noise of the VCO can be optimized. It is also known that for differential mode resonance, the current in the differential mode path can flow through the differential mode capacitance and the common mode capacitance can be seen. Whereas for common mode resonance, the common mode path sees only the common mode capacitance. However, in this VCO, the common mode capacitance and the differential mode capacitance are placed at the same location, which means that when the VCO needs common mode tuning, the differential mode resonant frequency f0 is directly affected. Therefore, it has not found wide industrial application because it requires a complicated calibration process.
Meanwhile, the VCO is also affected due to the low voltage of the CMOS process nodePerformance. We can calculate from the well-known Lesson formula, L (Δw) = (FkTR/V) 2 0 Q 2 )*(w 0 /Δw) 2 It can be seen that V0 is its oscillation amplitude. It is known that conventional cross-coupled oscillators limit the phase noise value up to 2 times the amplitude of the supply voltage Vdd, i.e. low Vdd.
In view of the above needs and the drawbacks of the prior art, the present application provides a low-phase noise differential mode common mode resonant isolated voltage controlled oscillator.
Disclosure of Invention
The application provides a low-phase noise differential mode common mode resonance separated voltage-controlled oscillator, which only realizes differential mode resonance and common mode resonance on one inductance area, realizes a transformer feedback amplification function, improves oscillation amplitude of a VCO and isolation of a common mode and a differential mode, and ensures that the common mode differential mode can be respectively tuned, and frequency drift is very small.
The primary purpose of the application is to solve the technical problems, and the technical scheme of the application is as follows:
the first aspect of the present application provides a low phase noise differential mode common mode resonant isolated voltage controlled oscillator, comprising: a transformer module and an active device module; the transformer module comprises a first inductor L1 and a second inductor L2, two end ports of the first inductor L1 are respectively P1 and P2 ports of the transformer module, and two end ports of the second inductor L2 are respectively P3 and P4 ports of the transformer module.
Further, a first tap A is arranged at the middle section of the first inductor L1, and a second tap B is arranged at the middle section of the second inductor L2; the first tap A is connected with a power supply, and the second tap B is grounded; the active device module comprises a first NMOS tube, a second NMOS tube, a differential tuning capacitor Cd, a first common mode tuning capacitor Cs1 and a second common mode tuning capacitor Cs2.
Further, the P1 port of the transformer module is connected to the source of the second NMOS, the P2 port of the transformer module is connected to the source of the first NMOS, the P3 port of the transformer module is connected to the gate of the first NMOS and the drain of the second NMOS, and the P4 port of the transformer module is connected to the gate of the second NMOS and the drain of the first NMOS, respectively.
The drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are connected to the Nd end of the differential tuning capacitor Cd, and the Pd end of the differential tuning capacitor Cd is connected to the gate electrode of the first NMOS tube and the drain electrode of the second NMOS tube respectively; the source electrode of the first NMOS tube is connected to the Ps end of the first common mode tuning capacitor Cs1, the source electrode of the second NMOS tube is connected to the Ps end of the second common mode tuning capacitor Cs2, and the Ns ends of the first common mode tuning capacitor Cs1 and the second common mode tuning capacitor Cs2 are grounded.
Further, the first inductor L1 surrounds the second inductor L2, the first inductor L1 is a loop of inductor, the second inductor L2 is a two-loop inductor, the second inductor L2 includes a first branch and a second branch which are mutually intersected, one end of the first branch is a P3 port of the transformer module, the other end of the first branch is grounded through a second tap B, one end of the second branch is a P4 port of the transformer module, and the other end of the second branch is grounded through a second tap B; wherein the middle section of the first branch and the middle section of the second branch are intersected with each other.
Further, the differential tuning capacitor Cd includes nd+1 differential tuning capacitor Cd arrays connected in parallel, where any one of the differential tuning capacitor Cd arrays includes: the first inverter, the second inverter, the third NMOS tube, the first resistor, the second resistor, the first capacitor and the second capacitor; the structure of the differential tuning capacitor Cd array is specifically as follows: the external signal is input to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and is respectively connected to the source electrode of the third NMOS tube and the negative electrode of the first capacitor through the first resistor, and is respectively connected to the drain electrode of the third NMOS tube and the negative electrode of the second capacitor through the second resistor; the output end of the second inverter is connected to the grid electrode of the third NMOS tube; the positive electrode of the first capacitor is connected to the drain electrode of the first NMOS tube through the Pd end of the differential tuning capacitor Cd, and the positive electrode of the second capacitor is connected to the drain electrode of the second NMOS tube through the Nd end of the differential tuning capacitor Cd.
Further, the third NMOS tube is a differential mode switch NMOS tube, in the differential tuning capacitor Cd array of the Nth bit control word, the size of the third NMOS tube is (N+1) (W/L), the size of the capacitor is (N+1) Cd, and the size of the resistor is (N+1) R; wherein W represents the width and length of the differential mode switch NMOS tube, and L represents the channel length of the differential mode switch NMOS tube.
Further, the first common-mode tuning capacitor Cs1 and the second common-mode tuning capacitor Cs2 each include ns+1 common-mode tuning capacitors Cs connected in parallel, and a cm array, where any one of the common-mode tuning capacitors Cs, the cm array includes: a third capacitor and a fourth NMOS tube; the positive electrode of the third capacitor is connected to the common mode tuning capacitor Cs, the cm end Ps, the negative electrode of the third capacitor is connected to the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected to the common mode tuning capacitor Cs, the cm end Ns and the ground, and an external signal is input to the grid electrode of the fourth NMOS tube.
Further, the fourth NMOS is a common-mode switch NMOS, where the size of the fourth NMOS is (m+1) (W/L) and the capacitance is (m+1) Cs in the cm array of the common-mode tuning capacitor Cs of the mth control word; wherein W represents the width and length of the common mode switch NMOS tube, and L represents the channel length of the common mode switch NMOS tube.
Compared with the prior art, the technical scheme of the application has the beneficial effects that:
the application provides a low-phase noise differential mode common mode resonance separated voltage-controlled oscillator, which is based on a special transformer structure, so that a circuit has a very high differential mode coupling coefficient Kdm and a very small common mode coupling coefficient Kcm; by separating the common mode tuning capacitor Cs, cm and the differential mode tuning capacitor, very high common mode and differential mode isolation is realized, so that common mode differential modes can be tuned respectively, and the frequency drift is very small.
Drawings
Fig. 1 is a schematic diagram of a low phase noise differential mode common mode resonant isolated vco according to the present application.
FIG. 2 is a schematic diagram of a common mode tuning capacitor array according to the present application.
FIG. 3 is a schematic diagram of a differential mode tuning capacitor array according to the present application.
FIG. 4 is a schematic diagram of a differential mode signal path according to an embodiment of the present application.
FIG. 5 is a schematic diagram of common mode signal paths according to an embodiment of the present application.
FIG. 6 is an equivalent model of a differential-mode capacitive switch in an embodiment of the present application.
Fig. 7 is an equivalent common mode path in one embodiment of the application.
FIG. 8 is a diagram of simulation results in an embodiment of the present application.
FIG. 9 is a diagram of time domain simulation results in an embodiment of the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, without conflict, the embodiments of the present application and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, however, the present application may be practiced in other ways than those described herein, and therefore the scope of the present application is not limited to the specific embodiments disclosed below.
Example 1
As shown in fig. 1, the present application provides a low phase noise differential mode common mode resonant separation voltage controlled oscillator, comprising: a transformer module and an active device module; the transformer module comprises a first inductor L1 and a second inductor L2, two end ports of the first inductor L1 are respectively P1 and P2 ports of the transformer module, and two end ports of the second inductor L2 are respectively P3 and P4 ports of the transformer module.
Further, a first tap A is arranged at the middle section of the first inductor L1, and a second tap B is arranged at the middle section of the second inductor L2; the first tap A is connected with a power supply, and the second tap B is grounded; the active device module comprises a first NMOS tube, a second NMOS tube, a differential tuning capacitor Cd, a first common mode tuning capacitor Cs1 and a second common mode tuning capacitor Cs2.
Further, the P1 port of the transformer module is connected to the source of the second NMOS, the P2 port of the transformer module is connected to the source of the first NMOS, the P3 port of the transformer module is connected to the gate of the first NMOS and the drain of the second NMOS, and the P4 port of the transformer module is connected to the gate of the second NMOS and the drain of the first NMOS, respectively.
The drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are connected to the Nd end of the differential tuning capacitor Cd, and the Pd end of the differential tuning capacitor Cd is connected to the gate electrode of the first NMOS tube and the drain electrode of the second NMOS tube respectively; the source electrode of the first NMOS tube is connected to the Ps end of the first common mode tuning capacitor Cs1, the source electrode of the second NMOS tube is connected to the Ps end of the second common mode tuning capacitor Cs2, and the Ns ends of the first common mode tuning capacitor Cs1 and the second common mode tuning capacitor Cs2 are grounded.
Note that, cd connected to the drain terminals of M1 and M2 is a differential tuning capacitor Cd, and the specific structure thereof is shown in fig. 3, in which a capacitor array with nd+1 bits is included, so Cd may be simultaneously expressed as Cd [ Nd:0], and the structure thereof will be explained below by taking a control word 0 as an example.
Further, the differential tuning capacitor Cd includes nd+1 differential tuning capacitor Cd arrays connected in parallel, where any one of the differential tuning capacitor Cd arrays includes: the first inverter, the second inverter, the third NMOS tube, the first resistor, the second resistor, the first capacitor and the second capacitor; the structure of the differential tuning capacitor Cd array is specifically as follows: the external signal is input to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and is respectively connected to the source electrode of the third NMOS tube and the negative electrode of the first capacitor through the first resistor, and is respectively connected to the drain electrode of the third NMOS tube and the negative electrode of the second capacitor through the second resistor; the output end of the second inverter is connected to the grid electrode of the third NMOS tube; the positive electrode of the first capacitor is connected to the drain electrode of the first NMOS tube through the Pd end of the differential tuning capacitor Cd, and the positive electrode of the second capacitor is connected to the drain electrode of the second NMOS tube through the Nd end of the differential tuning capacitor Cd.
Further, the third NMOS tube is a differential mode switch NMOS tube, in the differential tuning capacitor Cd array of the Nth bit control word, the size of the third NMOS tube is (N+1) (W/L), the size of the capacitor is (N+1) Cd, and the size of the resistor is (N+1) R; wherein W represents the width and length of the differential mode switch NMOS tube, and L represents the channel length of the differential mode switch NMOS tube.
In a specific embodiment, the input of the first inverter receives an external signal Cd, dm [ Nd:0]. Assuming that the NMOS transistors in the array of control word 0 are sized (W/L), the capacitance is Cd, and the resistance is R, then the NMOS transistors in the array of control word 1 are sized 2 (W/L), the capacitance is 2Cd, and the resistance is 2R. Similarly, for the capacitor array of the nth control word, the NMOS transistor has a size of (n+1) (W/L), the capacitor of (n+1) Cd, and the resistor of (n+1) R. So designed, the differential mode capacitance can be adjusted according to the specific gravity of the binary control word.
Further, the first common-mode tuning capacitor Cs1 and the second common-mode tuning capacitor Cs2 each include ns+1 common-mode tuning capacitors Cs connected in parallel, and a cm array, where any one of the common-mode tuning capacitors Cs, the cm array includes: a third capacitor and a fourth NMOS tube; the positive electrode of the third capacitor is connected to the common mode tuning capacitor Cs, the cm end Ps, the negative electrode of the third capacitor is connected to the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected to the common mode tuning capacitor Cs, the cm end Ns and the ground, and an external signal is input to the grid electrode of the fourth NMOS tube.
Further, the fourth NMOS is a common-mode switch NMOS, where the size of the fourth NMOS is (m+1) (W/L) and the capacitance is (m+1) Cs in the cm array of the common-mode tuning capacitor Cs of the mth control word; wherein W represents the width and length of the common mode switch NMOS tube, and L represents the channel length of the common mode switch NMOS tube.
The common mode tuning capacitor Cs, cm is connected to the source terminals of M1 and M2. The specific structure is shown in FIG. 2, which contains Ns+1 arrays. Thus, cs, cm may be expressed as Cs, cm [ Ns:0], and it should be noted that there is a single common mode capacitor array Cs at the M1 source, cm [ Ns:0] and a single common mode capacitor array Cs at the M2 source, cm [ Ns:0].
In a specific embodiment, the structure is explained in terms of the control word Cs, cm < 0 >. A common mode capacitor array includes an NMOS tube and a capacitor Cs, the positive terminal of Cs is connected to the source terminal of the M1 or M2 tube and the negative terminal of Cs is connected to the drain terminal of the NMOS tube in the array, the source terminal of the NMOS tube is directly grounded. To achieve the same control word weight adjustment in binary as in differential mode capacitance. We also assume Cs, cm < 0 > NMOS transistor size (W/L), and capacitance size Cs. The capacitor array of the Mth control word has an NMOS transistor size of (M+1) (W/L) and a capacitor size of (M+1) Cs.
Example 2
Based on the above embodiment 1, with reference to fig. 4 to 7, this embodiment analyzes the differential mode and common mode current voltage signals of the circuit, respectively, to explain the working principle and advantages of the present application in detail.
In a specific embodiment, as shown in fig. 4, we can see that in the second inductor L2 formed by the transformers P4 and P3, the currents of the two turns are in phase, so that the coupling effect between the turns P4-P3 and the turns P2-P1 is enhanced, a higher differential mode coupling coefficient Kdm can be obtained, and the signal fed back to the source terminal of M1 from the drain terminal of M1 is in phase because the transformers are coupled by forward voltage, as shown in the signals at the ends P4 and P2 in fig. 4. As a result of the feedback, the source voltage of M1 may become lower than ground, and a negative voltage may be reached for part of the time during the oscillation period. The same thing happens at the M2 terminal as shown by the signals at the P3 and P1 terminals in fig. 4. Therefore, the output oscillation amplitude V0 can break through the limit of 2Vdd, and the oscillation amplitude is improved, so that the phase noise is optimized.
Further, how the effect of the common-mode capacitance on the differential-mode resonant frequency is reduced is described with reference to fig. 4, and as shown in fig. 2, the differential-mode current still flows through the common-mode capacitance Cs, cm, which is determined by the resonant formula of the VCO:
where Ld, ls denote differential mode self-inductance of turns P4-P3 and P2-P1 of the transformer, and Kdm denotes the differential mode coupling coefficient. Let n=ld/Ls. Then equation (1) can be rewritten as:
we can see that in equation (2), cd, dm and Cs, cm/N have the same effect on frequency (at the same location), so it can be understood that the effect of the common mode capacitance Cs, cm is reduced by a factor of N due to the isolation of the transformer. Therefore, the application has little influence on the differential mode by the common mode capacitance during common mode tuning.
In a specific embodiment, the common mode signal current is as shown in fig. 5, and in an ideal case, the common mode current does not pass through the differential mode capacitor Cd. However, in actual practice and manufacturing process, the differential mode capacitor generates a common mode parasitic capacitance to the ground due to the switching action, as shown in fig. 6. The parasitic common mode capacitance thereof is unavoidable from non-ideal characteristics. Further, the transformer behaves differently from the differential mode current when faced with the common mode current. The first and second turns of the P4-P3 turns are reversed at common mode current, and since the self-inductance of the first and second turns is substantially the same, the coupling of P4-P3 to P2-P1 is reduced very weakly, i.e. with a Kcm of about 0. At this time, by analyzing the equivalent common-mode network, as shown in fig. 7, the impedance Zcm of the common-mode path can be calculated specifically as:
wherein, Z1, Z2 and Z3 have no specific meaning, and are respectively as follows:
equation (3) provides a common mode impedance expression for the equivalent circuit shown in fig. 7, and since the common mode coupling coefficient Kcm of the transformer in the present application is about 0, the common mode path impedance Zcm can be reduced to:
as can be seen from equation (7), in the present application, zcm becomes a series connection of two resonant cavities, that is, ls and Cs, cm can be used alone to provide a common mode resonance effect of 2 times the resonance frequency, independent of devices such as Cd, dm at the drain end.
Further, i.e. its common mode resonance frequency is only dependent on Ls and Cs, cm. The application uses the special transformer (with larger differential mode coupling coefficient Kdm and extremely small common mode coupling coefficient Kcm), and the influence of the differential mode path on the common mode resonance frequency can be completely skimmed.
Note that the differential mode and the common mode are two different observation angles, and Ld becomes Ld, cm is the same when the common mode observation angle is used, ls becomes Ls, cm, ld, cm, and Ls, and cm is a value indicating that Ls is observed at the common mode angle. Similarly, ls and dm are obtained at the differential observation angle Ls. Thus, kcm and Kdm are:
the embodiment obtains two advantages through analysis of the differential mode signal: a) By means of a large differential transformer coupling coefficient, a large amplitude gain can be achieved, i.e. a larger oscillation amplitude can be obtained, which is advantageous for optimizing the phase noise performance (b) since the common-mode capacitance and the differential-mode capacitance are separated by the transformer. Therefore, we can calculate that the effect of the common mode capacitance on the differential mode resonant frequency is cut by the transformer.
By analyzing the common mode signal, the application can completely skim the influence of the device of the differential mode path on the common mode resonance frequency. In summary, the influence of the common mode on the differential mode is reduced by separating the capacitors at two sides through the transformer, and the influence of the differential mode on the common mode is skimmed through the extremely low common mode coupling coefficient Kcm. And the signal amplitude is increased through the feedback form of the transformer, so that the application has higher oscillation amplitude and better phase noise.
Example 3
Based on the above examples 1 and 2, the present example details the performance of the present application in connection with simulation verification in connection with fig. 8 to 9.
In a specific embodiment, cadence and Peakview software simulation verification is adopted, a transformer part of the transformer utilizes electromagnetic field simulation soft drop Peakview to extract a snp file, and the result of resonance frequency, phase noise and the like of the transformer is simulated by Cadence through PSS+Pnase simulation functions of the transformer. And gets its time domain waveform by the transmit simulation of Cadence.
The simulation circuit diagram of the application is shown in fig. 1, and the transformer consists of two turns of inductors and one turn of inductor. The two ports of the inductor are denoted as P1 on the right side and P2 on the left side; the two turns of the inductor are denoted P3 on the right and P4 on the left. Wherein one turn of the inductor encloses two turns of the inductor. Taps are provided between the one and two turns of inductance for grounding and power supply. And the active device part consists of two NMOS transistors, M1 and M2 in the figure. The specific connection mode is that the drain end of the M1 is connected to the P4 port of the transformer, and the source end of the M1 is connected to the P2 port of the transformer. And the drain terminal of M2 is connected to the P3 port of the transformer, and the source terminal of M2 is connected to the P1 port of the transformer. While Cd, dm and Cs, cm are not used as an array for simplicity, as a scan variable in Cadence simulation. The transformer extracts a pnp file of the transformer by using electromagnetic field simulation software Peakview and puts the pnp file into circuit diagram simulation to be simulated in a joint way. The simulation result of the circuit is shown in the seventh figure, and as can be seen from fig. 8, under different conditions of Cd and dm, the phase noise performance can be optimized by configuring proper Cs and cm, which is the result of common mode resonance. Its phase noise can be optimized by 8.3dB. It can also be seen that the offset caused by the differential mode oscillation frequency is very small when tuning the common mode capacitance Cs, cm, as shown in fig. 8. This demonstrates that the present application possesses very high common mode and differential mode isolation. Fig. 9 shows a time domain simulation waveform of the present application, and as can be seen from fig. 9, the source end waveform of the NMOS has abundant 2 nd harmonic waves, and the output amplitude of the NMOS can reach 2.642V which is 1.8 times of that of the conventional VCO at a supply voltage of 0.75V, and has very high oscillation amplitude. It can also be seen in the phase noise simulation of fig. 8 that the present application possesses very superior phase noise performance.
The drawings depict structural positional relationships and are merely illustrative, and are not to be construed as limiting the patent.
It is to be understood that the above examples of the present application are provided by way of illustration only and not by way of limitation of the embodiments of the present application. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are desired to be protected by the following claims.
Claims (10)
1. The utility model provides a low phase noise differential mode common mode resonance separation's voltage-controlled oscillator which characterized in that includes: a transformer module and an active device module; the transformer module comprises a first inductor L1 and a second inductor L2, wherein two end ports of the first inductor L1 are respectively P1 and P2 ports of the transformer module, and two end ports of the second inductor L2 are respectively P3 and P4 ports of the transformer module;
the middle section of the first inductor L1 is provided with a first tap A, and the middle section of the second inductor L2 is provided with a second tap B; the first tap A is connected with a power supply, and the second tap B is grounded; the active device module comprises a first NMOS tube, a second NMOS tube, a differential tuning capacitor Cd, a first common mode tuning capacitor Cs1 and a second common mode tuning capacitor Cs2;
the P1 port of the transformer module is connected to the source electrode of the second NMOS tube, the P2 port of the transformer module is connected to the source electrode of the first NMOS tube, the P3 port of the transformer module is respectively connected to the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube, and the P4 port of the transformer module is respectively connected to the grid electrode of the second NMOS tube and the drain electrode of the first NMOS tube;
the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are connected to the Nd end of the differential tuning capacitor Cd, and the Pd end of the differential tuning capacitor Cd is connected to the gate electrode of the first NMOS tube and the drain electrode of the second NMOS tube respectively; the source electrode of the first NMOS tube is connected to the Ps end of the first common mode tuning capacitor Cs1, the source electrode of the second NMOS tube is connected to the Ps end of the second common mode tuning capacitor Cs2, and the Ns ends of the first common mode tuning capacitor Cs1 and the second common mode tuning capacitor Cs2 are grounded.
2. The low-phase noise differential mode common mode resonant and separated voltage controlled oscillator according to claim 1, wherein the first inductor L1 surrounds the second inductor L2, the first inductor L1 is a loop of inductor, the second inductor L2 is a two-loop inductor, the second inductor L2 includes a first branch and a second branch which are intersected with each other, one end of the first branch is a P3 port of the transformer module, the other end of the first branch is grounded through a second tap B, one end of the second branch is a P4 port of the transformer module, and the other end of the second branch is grounded through a second tap B; wherein the middle section of the first branch and the middle section of the second branch are intersected with each other.
3. The low-phase noise differential mode common mode resonant isolated voltage controlled oscillator of claim 1, wherein the first NMOS and the second NMOS are oscillating core NMOS.
4. The low phase noise differential mode common mode resonant split voltage controlled oscillator of claim 1, wherein the differential tuning capacitor Cd comprises an array of nd+1 differential tuning capacitors Cd connected in parallel.
5. The vco of claim 4 wherein any of the arrays of differential tuning capacitors Cd comprises: the first inverter, the second inverter, the third NMOS tube, the first resistor, the second resistor, the first capacitor and the second capacitor; the structure of the differential tuning capacitor Cd array is specifically as follows: the external signal is input to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and is respectively connected to the source electrode of the third NMOS tube and the negative electrode of the first capacitor through the first resistor, and is respectively connected to the drain electrode of the third NMOS tube and the negative electrode of the second capacitor through the second resistor; the output end of the second inverter is connected to the grid electrode of the third NMOS tube; the positive electrode of the first capacitor is connected to the drain electrode of the first NMOS tube through the Pd end of the differential tuning capacitor Cd, and the positive electrode of the second capacitor is connected to the drain electrode of the second NMOS tube through the Nd end of the differential tuning capacitor Cd.
6. The low-phase noise differential mode common mode resonant-separated voltage controlled oscillator according to claim 5, wherein the third NMOS transistor is a differential mode switch NMOS transistor, the size of the third NMOS transistor is (n+1) (W/L), the capacitance is (n+1) Cd, and the resistance is (n+1) R in the differential tuning capacitor Cd array of the nth control word; wherein W represents the width and length of the differential mode switch NMOS tube, and L represents the channel length of the differential mode switch NMOS tube.
7. The low phase noise differential mode common mode resonant split vco of claim 1 wherein the first and second common mode tuning capacitors Cs1 and Cs2 each comprise ns+1 parallel common mode tuning capacitors Cs, cm array.
8. The vco of claim 7, wherein any of the common-mode tuning capacitors Cs, cm array comprises: a third capacitor and a fourth NMOS tube; the positive electrode of the third capacitor is connected to the common mode tuning capacitor Cs, the cm end Ps, the negative electrode of the third capacitor is connected to the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected to the common mode tuning capacitor Cs, the cm end Ns and the ground, and an external signal is input to the grid electrode of the fourth NMOS tube.
9. The low-phase noise differential mode common mode resonant isolated voltage controlled oscillator of claim 8, wherein the fourth NMOS transistor is a common mode switching NMOS transistor.
10. The vco of claim 9, wherein the common-mode tuning capacitor Cs of the mth control word is (m+1) (W/L) and the fourth NMOS transistor has a size of (m+1) Cs in the cm array; wherein W represents the width and length of the common mode switch NMOS tube, and L represents the channel length of the common mode switch NMOS tube.
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