CN116820787B - Load balancing method, load balancing device, electronic equipment and computer readable storage medium - Google Patents
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Abstract
The embodiment of the application discloses a load balancing method, a load balancing device, electronic equipment and a computer readable storage medium. The method comprises the following steps: obtaining an access address sent by a multi-core processor in the chip; performing bitwise exclusive OR operation on the access address to obtain an index value of the access address; and determining the working nodes for mapping the access address in the coherent mesh network according to the index value of the access address, so that the access address can be randomly and evenly distributed to each working node, the technical problem of unbalanced load of the working nodes in the coherent mesh network can be solved, and the mapping efficiency of the access address can be improved.
Description
Technical Field
The present application relates to the field of multi-core load balancing technologies, and in particular, to a load balancing method, a device, an electronic device, and a computer readable storage medium.
Background
A coherent mesh network (CMN, coherence Mesh Network) designed for a wide range of intelligent connectivity systems including network infrastructure, storage, servers, HPCs, automotive and industrial solutions. The coherent mesh network adopts a mesh structure, forms a mesh network through fixed cross points, supports consistency, can be customized, and is suitable for a multi-core processor.
In the prior art, mapping is generally performed according to a region address space, for example, a chip memory is divided into two regions, namely, region0 and region1, wherein the address range of region0 is 0x10000000~0x1fffffff,region 1, and the address range of region0 is 0x20000000 to 0x2fffffff. Currently, when accessing region0, the access address is usually mapped into HN-F0 (Fully coherent Home Node, full-consistency master node) in the coherent mesh network; while when accessing region1, the access address is typically mapped into HN-F1 in the coherent mesh network. If the multicore processor accesses region0 more frequently, it may overload HN-F0, while accessing region1 less frequently, which necessarily results in unbalanced load of working nodes in the coherent mesh network.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides a load balancing method, a load balancing device, electronic equipment and a computer readable storage medium, and aims to solve the technical problem of unbalanced load of working nodes in a coherent mesh network in the prior art.
To solve the above problems, in a first aspect, the present application provides a load balancing method applied to a coherent mesh network inside a chip, the method comprising:
obtaining an access address sent by a multi-core processor in the chip;
performing bitwise exclusive OR operation on the access address to obtain an index value of the access address;
and determining the working node for mapping the access address in the coherent mesh network according to the index value of the access address.
Further, in the load balancing method, the performing bitwise exclusive-or operation on the access address to obtain an index value of the access address includes:
determining byte alignment rules of the area where the access address is located and the number of operable nodes in the coherent mesh network;
and performing bitwise exclusive OR operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes.
Further, in the load balancing method, the performing a bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes includes:
determining the least significant address bit of the access address for bitwise exclusive OR operation according to the byte alignment rule;
and performing bitwise exclusive OR operation on the access address from the least effective address bit to obtain an index value matched with the number of the workable nodes.
Further, in the load balancing method, before performing a bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value that matches the number of the workable nodes, the load balancing method further includes:
and determining the bit number of the index value according to the number of the workable nodes.
Further, in the load balancing method, the determining, according to the index value, a working node of the coherent mesh network to map the access address includes:
acquiring a mapping relation table between the operable node in the coherent mesh network and the index value of the access address;
and determining the working node for mapping the access address in the coherent mesh network according to the mapping relation table and the index value.
Further, in the load balancing method, before the obtaining the mapping relation table between the index value of the access address and the working node in the coherent mesh network, the method further includes:
acquiring workable nodes in the coherent mesh network;
and determining an index value corresponding to each operable node in the coherent mesh network to form the mapping relation table.
Further, in the load balancing method, before the working node that determines that the access address maps in the coherent mesh network according to the mapping relation table and the index value, the method further includes:
and carrying out binary conversion on the index value generated after the bitwise exclusive OR operation to obtain a value which is the same as the index value in the mapping relation table.
In a second aspect, the present application also provides a load balancing apparatus for use in a coherent mesh network within a chip, the apparatus comprising:
the acquisition unit is used for acquiring an access address sent by the multi-core processor in the chip;
the operation unit is used for carrying out bitwise exclusive OR operation on the access address to obtain an index value of the access address;
and the determining unit is used for determining the working node for mapping the access address in the coherent mesh network according to the index value of the access address.
In a third aspect, an embodiment of the present application further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and capable of running on the processor, where the processor implements the load balancing method according to the first aspect when executing the computer program.
In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, where the computer readable storage medium stores a computer program, where the computer program when executed by a processor causes the processor to perform the load balancing method described in the first aspect.
The load balancing method, the device, the electronic equipment and the computer readable storage medium provided by the embodiment of the application are used for obtaining the access address sent by the multi-core processor in the chip, performing bitwise exclusive OR operation on the access address to obtain the index value of the access address, and finally determining the working node for mapping the access address in the coherent mesh network through the index value of the access address, so that the access address can be randomly and evenly distributed to each working node, the technical problem of unbalanced load of the working node in the coherent mesh network can be solved, and the mapping efficiency of the access address can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a load balancing method according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a load balancing method according to an embodiment of the present application;
fig. 3 is another flow chart of a load balancing method according to an embodiment of the present application;
fig. 4 is another flow chart of a load balancing method according to an embodiment of the present application;
fig. 5 is another flow chart of a load balancing method according to an embodiment of the present application;
fig. 6 is a schematic block diagram of a load balancing apparatus according to an embodiment of the present application;
fig. 7 is a schematic block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
The load balancing method of the embodiment of the application is applied to the electronic equipment, and the method is executed through a response program installed in the electronic equipment so as to randomly and evenly distribute the access address to each working node. The electronic device may be an electronic device such as a desktop computer, a notebook computer, a tablet computer, or a mobile phone.
It should be noted that, the application scenario of the foregoing embodiment is merely an example, and the services and scenarios described in the embodiments of the present application are for more clearly describing the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application, and those skilled in the art can know that, with the evolution of the system and the appearance of the new service scenario, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems. The following will describe in detail.
The following description of the embodiments is not intended to limit the preferred embodiments. The load balancing method is described in detail below.
Referring to fig. 1, fig. 1 is a flowchart of a load balancing method according to an embodiment of the application.
As shown in FIG. 1, the method includes the following steps S110 to S130.
S110, obtaining an access address sent by the multi-core processor in the chip.
Specifically, the access address is the address of the access instruction sent by the multi-core processor, after the access address sent by the multi-core processor is obtained, the access address can be subjected to bitwise exclusive OR operation to obtain the index value of the access address, and the working nodes for mapping the access address in the coherent mesh network are determined through the index value, so that random and balanced allocation of the access address to each working node is realized, the load of each working node is reduced, and the mapping efficiency is improved.
S120, performing bitwise exclusive OR operation on the access address to obtain an index value of the access address.
In this embodiment, after performing bitwise exclusive or operation on the access address, hash processing on the access address can be implemented, that is, the present application adopts a special hash algorithm to perform hash processing on the access address, so as to obtain a hash value of the access address, that is, an index value.
The bitwise exclusive OR operation is to calculate the corresponding bits of two operation objects according to the following rules: 0^0 =0, 0 ζ1=1, 1 ζ0=1, 1 ζ1=0, i.e. if the values of the corresponding bits are the same, the result of the operation is 0, if the values of the corresponding bits are different, the result is 1.
For example, the result of operation 4 of 2≡6, where 2 is represented as binary 0010,6 and 0110, and two numbers are different from each other only in the third bit, the result is 0100, i.e. 4.
In other inventive embodiments, as shown in fig. 2, step S120 includes steps S121 and S122.
S121, determining byte alignment rules of the area where the access address is located and the number of operable nodes in the coherent mesh network;
s122, performing bitwise exclusive OR operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes.
Specifically, the bytes are aligned, that is, the bytes are arranged in space according to a certain rule, so that the fast operation of the CPU on the memory can be realized, the operable node is an idle operable node of the coherent mesh network, the operable node can be an HN-F node, the index value of the access address is matched with the number of the operable nodes, that is, the numerical value of the index value is not greater than the numerical value of the number of the operable nodes.
In this embodiment, by determining the byte alignment rule of the area where the access address is located and the number of the operable nodes in the coherent mesh network in advance, the index value generated after the bitwise exclusive or operation of the access address can be randomly and evenly distributed to each operable node, so that the efficiency of address mapping is improved.
In other inventive embodiments, as shown in fig. 3, step S122 includes steps S1221 and S1222.
S1221, determining the least significant address bit of the access address for bitwise exclusive OR operation according to the byte alignment rule;
s1222, performing bit exclusive OR operation on the access address from the least significant address bit to obtain an index value matched with the number of the workable nodes.
In this embodiment, after determining the byte alignment rule, the least significant address bit participating in the bitwise exclusive-or operation in the access address may be determined, so that the bitwise exclusive-or operation may be performed on the access address to obtain an index value that matches the number of workable nodes.
The byte alignment includes 1 byte alignment, 2 byte alignment, 4 byte alignment, 8 byte alignment, 16 byte alignment, 32 byte alignment, 64 byte alignment, 128 byte alignment, 256 byte alignment, etc. If 1 byte is aligned, the least significant bit is from bit [0], i.e. the least significant bit is 0; if the bits are aligned in 2 bytes, the least significant bits are from bit [1], i.e. the least significant bits are 1; if the bits are aligned with 4 bytes, the bits from bit [2] are the least significant bits, namely the least significant bits are 2; if the 8 bytes are aligned, the least significant bit is from bit [3], i.e. the least significant bit is 3; if the bits are aligned with 16 bytes, the bits from bit [4] are the least significant bits, namely the least significant bits are 4; if 32 bytes are aligned, the least significant bit is from bit [5], i.e., the least significant bit is 5; if 64 bytes are aligned, the least significant bit is from bit [6], i.e., the least significant bit is 6; if 128 bytes are aligned, the least significant bit is from bit [7], i.e., the least significant bit is 7; if 256 bytes are aligned, the least significant bits are from bit [8], i.e., the least significant bits are 8.
In other embodiments of the application, before step S1222, the method further includes the steps of: and determining the bit number of the index value according to the number of the workable nodes.
In this embodiment, the index value obtained after the bitwise exclusive or operation of the access address is a binary value, and since one index value needs to correspond to one workable node, and the number of workable nodes is generally represented by a decimal value, the decimal value needs to be converted into a binary value, and the number of bits of the index value obtained after the bitwise exclusive or operation of the access address is determined according to the number of bits of the binary value after the conversion.
S130, determining the working node of the access address mapped in the coherent mesh network according to the index value of the access address.
In this embodiment, after the access address is bitwise xored to obtain the index value of the access address, the working node corresponding to the index value can be determined by looking up a table, and the working node is a workable node in the coherent mesh network, so that random and balanced mapping of the access address to the working node in the coherent mesh network can be realized, thereby improving mapping efficiency.
For example, if the data is aligned in 64 bytes, the data may be the least significant bits from bit [6], the access address is 0x8000—0000, and the number of the operable nodes is 8, and the operable nodes may be as shown in the following table 1:
TABLE 1
From this, it can be seen that the binary bit number of the index value obtained by performing the bitwise exclusive or operation with the access address of 0x8000—0000 is 3, and further can be represented by the following table 2:
TABLE 2
From the above, after the access address is bitwise xored, the index value finally obtained can represent bit 3' b010, and further the operable node with ID 76 can be determined from table 1, so that the access address can be mapped into the operable node with ID 76.
For another example, if 128 bytes are aligned, the least significant bit may be from bit [7], the binary bit number obtained by performing the bitwise exclusive or operation with the access address of 0x8000—0000 may be 3, and further may be represented by the following table 3:
TABLE 3 Table 3
From the above, after the access address is bitwise xored, the index value finally obtained can represent bit 3' b001, and further the operable node with ID 63 can be determined from table 1, so that the access address can be mapped into the operable node with ID 63.
In other inventive embodiments, as shown in fig. 4, step S130 includes steps S131 and S132.
S131, obtaining a mapping relation table between the operable node in the coherent mesh network and the index value of the access address;
and S132, determining the working node of the access address mapped in the coherent mesh network according to the mapping relation table and the index value.
In this embodiment, the mapping relationship table is a relationship table between the operable node and the index value of the access address in the coherent mesh network, which may be constructed by using the table shown in table 1, and after the mapping relationship table between the operable node and the index value of the access address in the coherent mesh network is obtained, the working node where the access address is mapped in the coherent mesh network may be determined by a table look-up manner, so that random and balanced mapping of the access address to the working node in the coherent mesh network may be implemented, thereby improving the mapping efficiency.
In other embodiments of the application, as shown in fig. 5, steps S210 and S220 are further included before step S130.
S210, acquiring a workable node in the coherent mesh network;
s220, determining an index value corresponding to each operable node in the coherent mesh network to form the mapping relation table.
In this embodiment, the operable nodes may be obtained from the coherent mesh network before mapping the access address, and after each operable node in the coherent mesh network is obtained, each operable node is numbered, and the number may be directly used as a decimal value of an index value of the access address, so as to form a mapping relationship table between the operable node and the index value of the access address.
In other embodiments of the application, before step S130, the method further includes the steps of: and carrying out binary conversion on the index value generated after the bitwise exclusive OR operation to obtain a value which is the same as the index value in the mapping relation table.
Specifically, since the index value obtained after the bitwise exclusive or operation of the access address is a binary value, the index value in the mapping relation table can be other binary values, so that the index value obtained after the bitwise exclusive or operation of the access address also needs to be subjected to binary conversion to obtain the value with the same binary value as the index value in the mapping relation table, further, the working node for mapping the access address in the coherent mesh network can be determined, and further, random and balanced mapping of the access address to the working node in the coherent mesh network can be realized, and the mapping efficiency is improved.
In the load balancing method provided by the embodiment of the application, the access address sent by the multi-core processor in the chip is obtained; performing bitwise exclusive OR operation on the access address to obtain an index value of the access address; the working nodes for mapping the access address in the coherent mesh network are determined according to the index value of the access address, so that the access address can be randomly and evenly distributed to each working node, the technical problem of unbalanced load of the working nodes in the coherent mesh network can be solved, the mapping efficiency of the access address can be improved, and meanwhile, a cheap, effective and transparent method is provided to expand the bandwidth of network equipment and servers, increase the throughput, strengthen the network data processing capacity and improve the flexibility and usability of the network.
The embodiment of the application also provides a load balancing device 100, which is used for executing any embodiment of the load balancing method.
In particular, referring to fig. 6, fig. 6 is a schematic block diagram of a load balancing apparatus 100 according to an embodiment of the present application.
As shown in fig. 6, the load balancing apparatus 100 includes: an acquisition unit 110, an operation unit 120, a determination unit 130.
And the obtaining unit 110 is configured to obtain an access address sent by the multicore processor in the chip.
The operation unit 120 is configured to perform a bitwise exclusive-or operation on the access address to obtain an index value of the access address.
In one embodiment, the operation unit 120, when configured to perform a bitwise exclusive-or operation on the access address to obtain the index value of the access address, specifically includes: determining byte alignment rules of the area where the access address is located and the number of operable nodes in the coherent mesh network; and performing bitwise exclusive OR operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes.
In one embodiment, when performing a bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value that matches the number of the workable nodes, the method specifically includes: determining the least significant address bit of the access address for bitwise exclusive OR operation according to the byte alignment rule; and performing bitwise exclusive OR operation on the access address from the least effective address bit to obtain an index value matched with the number of the workable nodes.
In an embodiment, before performing a bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value that matches the number of the workable nodes, the method specifically further includes: and determining the bit number of the index value according to the number of the workable nodes.
A determining unit 130, configured to determine, according to the index value of the access address, a working node where the access address maps in the coherent mesh network.
In an embodiment, the determining unit 130, when configured to determine, according to the index value, a working node of the coherent mesh network that maps the access address, specifically includes: acquiring a mapping relation table between the operable node in the coherent mesh network and the index value of the access address; and determining the working node for mapping the access address in the coherent mesh network according to the mapping relation table and the index value.
In an embodiment, before obtaining the mapping relation table between the index value of the access address and the working node in the coherent mesh network, the method specifically further includes: acquiring workable nodes in the coherent mesh network; and determining an index value corresponding to each operable node in the coherent mesh network to form the mapping relation table.
In an embodiment, before determining the working node where the access address maps in the coherent mesh network according to the mapping relation table and the index value, the method specifically further includes: and carrying out binary conversion on the index value generated after the bitwise exclusive OR operation to obtain a value which is the same as the index value in the mapping relation table.
The load balancing device 100 provided by the embodiment of the present application is configured to perform the above-mentioned obtaining of the access address sent by the multicore processor in the chip; performing bitwise exclusive OR operation on the access address to obtain an index value of the access address; and determining the working node for mapping the access address in the coherent mesh network according to the index value of the access address.
It should be noted that, as will be clearly understood by those skilled in the art, the specific implementation process of the load balancing apparatus 100 and each unit may refer to the corresponding description in the foregoing method embodiments, and for convenience and brevity of description, the description is omitted here.
The load balancing apparatus described above may be implemented in the form of a computer program that is executable on an electronic device as shown in fig. 7.
Referring to fig. 7, fig. 7 is a schematic block diagram of an electronic device according to an embodiment of the present application.
Referring to fig. 7, the device 500 includes a processor 502, a memory, and a network interface 505, which are connected by a system bus 501, wherein the memory may include a storage medium 503 and an internal memory 504.
The storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032, when executed, may cause the processor 502 to perform a load balancing method.
The processor 502 is used to provide computing and control capabilities to support the operation of the overall device 500.
The internal memory 504 provides an environment for the execution of a computer program 5032 in the non-volatile storage medium 503, which computer program 5032, when executed by the processor 502, causes the processor 502 to perform a load balancing method.
The network interface 505 is used for network communication, such as providing for transmission of data information, etc. It will be appreciated by those skilled in the art that the structure shown in fig. 7 is merely a block diagram of a portion of the structure associated with the present inventive arrangements and is not limiting of the apparatus 500 to which the present inventive arrangements are applied, and that a particular apparatus 500 may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
Wherein the processor 502 is configured to execute a computer program 5032 stored in a memory to perform the following functions: obtaining an access address sent by a multi-core processor in the chip; performing bitwise exclusive OR operation on the access address to obtain an index value of the access address; and determining the working node for mapping the access address in the coherent mesh network according to the index value of the access address.
In one embodiment, when implementing the bitwise exclusive-or operation on the access address to obtain the index value of the access address, the processor 502 specifically implements the following steps: determining byte alignment rules of the area where the access address is located and the number of operable nodes in the coherent mesh network; and performing bitwise exclusive OR operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes.
In an embodiment, when implementing the bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value matching the number of the workable nodes, the processor 502 specifically implements the following steps: determining the least significant address bit of the access address for bitwise exclusive OR operation according to the byte alignment rule; and performing bitwise exclusive OR operation on the access address from the least effective address bit to obtain an index value matched with the number of the workable nodes.
In one embodiment, before implementing the bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value matching the number of the workable nodes, the processor 502 specifically implements the following steps: and determining the bit number of the index value according to the number of the workable nodes.
In one embodiment, when implementing the working node that determines that the coherent mesh network maps the access address according to the index value, the processor 502 specifically implements the following steps: acquiring a mapping relation table between the operable node in the coherent mesh network and the index value of the access address; and determining the working node for mapping the access address in the coherent mesh network according to the mapping relation table and the index value.
In one embodiment, before implementing the mapping table between the index value of the access address and the working node in the coherent mesh network, the processor 502 specifically implements the following steps: acquiring workable nodes in the coherent mesh network; and determining an index value corresponding to each operable node in the coherent mesh network to form the mapping relation table.
In one embodiment, before implementing the working node that determines that the access address maps in the coherent mesh network according to the mapping relationship table and the index value, the processor 502 specifically implements the following steps: and carrying out binary conversion on the index value generated after the bitwise exclusive OR operation to obtain a value which is the same as the index value in the mapping relation table.
Those skilled in the art will appreciate that the embodiment of the apparatus 500 shown in fig. 7 is not limiting of the specific construction of the apparatus 500, and in other embodiments, the apparatus 500 may include more or less components than illustrated, or certain components may be combined, or a different arrangement of components. For example, in some embodiments, the device 500 may include only the memory and the processor 502, and in such embodiments, the structure and the function of the memory and the processor 502 are consistent with the embodiment shown in fig. 7, and will not be described herein.
It should be appreciated that in an embodiment of the application, the processor 502 may be a central processing unit (Central Processing Unit, CPU), the processor 502 may also be other general purpose processors 502, digital signal processors 502 (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor 502 may be the microprocessor 502 or the processor 502 may be any conventional processor 502 or the like.
In another embodiment of the application, a computer storage medium is provided. The storage medium may be a nonvolatile computer-readable storage medium or a volatile storage medium. The storage medium stores a computer program 5032, wherein the computer program 5032 when executed by the processor 502 performs the steps of: obtaining an access address sent by a multi-core processor in the chip; performing bitwise exclusive OR operation on the access address to obtain an index value of the access address; and determining the working node for mapping the access address in the coherent mesh network according to the index value of the access address.
In one embodiment, when the processor executes the program instruction to implement the bitwise exclusive-or operation on the access address to obtain the index value of the access address, the following steps are specifically implemented: determining byte alignment rules of the area where the access address is located and the number of operable nodes in the coherent mesh network; and performing bitwise exclusive OR operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes.
In an embodiment, when the processor executes the program instruction to implement the bitwise exclusive-or operation on the access address according to the byte alignment rule, the method specifically includes the following steps: determining the least significant address bit of the access address for bitwise exclusive OR operation according to the byte alignment rule; and performing bitwise exclusive OR operation on the access address from the least effective address bit to obtain an index value matched with the number of the workable nodes.
In one embodiment, before executing the program instruction to implement the bitwise exclusive-or operation on the access address according to the byte alignment rule, the processor specifically implements the following steps to obtain an index value that matches the number of the workable nodes: and determining the bit number of the index value according to the number of the workable nodes.
In one embodiment, when the processor executes the program instructions to implement the working node that determines that the coherent mesh network maps the access address according to the index value, the processor specifically implements the following steps: acquiring a mapping relation table between the operable node in the coherent mesh network and the index value of the access address; and determining the working node for mapping the access address in the coherent mesh network according to the mapping relation table and the index value.
In one embodiment, the processor, before executing the program instructions to implement the obtaining the mapping table between the index value of the access address and the working node in the coherent mesh network, specifically implements the following steps: acquiring workable nodes in the coherent mesh network; and determining an index value corresponding to each operable node in the coherent mesh network to form the mapping relation table.
In one embodiment, before executing the program instructions to implement the working node that determines that the access address maps in the coherent mesh network according to the mapping table and the index value, the processor specifically implements the following steps: and carrying out binary conversion on the index value generated after the bitwise exclusive OR operation to obtain a value which is the same as the index value in the mapping relation table.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus, device and unit described above may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein. Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus, device and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units is merely a logical function division, there may be another division manner in actual implementation, or units having the same function may be integrated into one unit, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present application.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units may be stored in a storage medium if implemented in the form of software functional units and sold or used as stand-alone products. Based on such understanding, the technical solution of the present application may be essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing an apparatus 500 (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
While the application has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (8)
1. A method of load balancing, for use in a coherent mesh network within a chip, the method comprising:
obtaining an access address sent by a multi-core processor in the chip;
performing bitwise exclusive OR operation on the access address to obtain an index value of the access address;
determining a working node for mapping the access address in the coherent mesh network according to the index value of the access address;
the performing a bitwise exclusive-or operation on the access address to obtain an index value of the access address includes:
determining byte alignment rules of the area where the access address is located and the number of operable nodes in the coherent mesh network;
performing bitwise exclusive OR operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes;
the performing bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value matched with the number of the workable nodes, including:
determining the least significant address bit of the access address for bitwise exclusive OR operation according to the byte alignment rule;
and performing bitwise exclusive OR operation on the access address from the least effective address bit to obtain an index value matched with the number of the workable nodes.
2. The load balancing method according to claim 1, further comprising, before performing a bitwise exclusive-or operation on the access address according to the byte alignment rule to obtain an index value that matches the number of the workable nodes:
and determining the bit number of the index value according to the number of the workable nodes.
3. The load balancing method according to claim 1, wherein the determining the working node in which the access address maps in the coherent mesh network according to the index value of the access address comprises:
acquiring a mapping relation table between the operable node in the coherent mesh network and the index value of the access address;
and determining the working node for mapping the access address in the coherent mesh network according to the mapping relation table and the index value.
4. The method of claim 3, further comprising, prior to said obtaining a mapping table between the index value of the access address and the working nodes in the coherent mesh network:
acquiring workable nodes in the coherent mesh network;
and determining an index value corresponding to each operable node in the coherent mesh network to form the mapping relation table.
5. The load balancing method according to claim 3, further comprising, before said determining, from the mapping relation table, the working node in which the access address is mapped in the coherent mesh network, the index value:
and carrying out binary conversion on the index value generated after the bitwise exclusive OR operation to obtain a value which is the same as the index value in the mapping relation table.
6. A load balancing apparatus for use in a coherent mesh network within a chip, the apparatus comprising:
the acquisition unit is used for acquiring an access address sent by the multi-core processor in the chip;
the operation unit is used for carrying out bitwise exclusive OR operation on the access address to obtain an index value of the access address; specifically, determining byte alignment rules of the area where the access address is located and the number of operable nodes in the coherent mesh network; determining the least significant address bit of the access address for bitwise exclusive OR operation according to the byte alignment rule; performing bitwise exclusive OR operation on the access address from the least significant address bit to obtain an index value matched with the number of the workable nodes;
and the determining unit is used for determining the working node for mapping the access address in the coherent mesh network according to the index value of the access address.
7. An electronic device comprising a memory and a processor; the memory stores an application program, and the processor is configured to run the application program in the memory to perform the operations in the load balancing method according to any one of claims 1 to 5.
8. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program, which is executed by a processor to implement the load balancing method of any of claims 1 to 5.
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