CN116782711A

CN116782711A - Display panel and display device

Info

Publication number: CN116782711A
Application number: CN202310793432.1A
Authority: CN
Inventors: 代好
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-06-29
Filing date: 2023-06-29
Publication date: 2023-09-19

Abstract

The embodiment of the invention provides a display panel and a display device. The data line, the first power line and the shielding signal line in the display panel extend along a first direction, and the shielding signal line is connected with a constant voltage; the input end of the demultiplexer is coupled with the data terminal, and the output end of the demultiplexer is coupled with at least two data lines; the display panel comprises a substrate, and a first metal layer, a second metal layer and a third metal layer which are sequentially arranged far away from the substrate; the first power line is positioned on the first metal layer, the shielding signal line is positioned on the second metal layer, and the data line is positioned on the third metal layer; the data line comprises a first data line, the first power line comprises a first sub power line, and the first data line is adjacent to the first sub power line; the shielding signal line at least partially overlaps the first data line and/or at least partially overlaps the first sub-power line in a direction perpendicular to a plane in which the substrate is located. The invention can improve the line crosstalk and improve the display effect.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

An Organic Light-Emitting Diode (OLED) has a self-luminous characteristic, and is applied to the display field to make a display panel Light and thin, high in brightness, low in power consumption, fast in response, high in definition, good in flexibility and high in luminous efficiency, so that new requirements of consumers on display technologies can be met. At present, a line crosstalk problem exists in a display panel, and the display effect is affected.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which are used for solving the problem that the line crosstalk influences the display effect in the prior art.

In a first aspect, an embodiment of the present invention provides a display panel, including a demultiplexer, a data terminal, a data line, a first power line, and a shielding signal line; the data line, the first power line and the shielding signal line extend along a first direction, and the shielding signal line is connected with a constant voltage; the input end of the demultiplexer is coupled with the data terminal, the output end of the demultiplexer is coupled with n data lines, and n is an integer and is more than or equal to 2;

the display panel comprises a substrate, and a first metal layer, a second metal layer and a third metal layer which are sequentially arranged far away from the substrate; the first power line is positioned on the first metal layer, the shielding signal line is positioned on the second metal layer, and the data line is positioned on the third metal layer;

the data line comprises a first data line, the first power line comprises a first sub power line, and the first data line is adjacent to the first sub power line; the shielding signal line at least partially overlaps the first data line and/or at least partially overlaps the first sub-power line in a direction perpendicular to a plane in which the substrate is located.

In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display apparatus, including a display panel provided by any embodiment of the present invention.

The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: the display panel is provided with a shielding signal wire, and a metal layer where the shielding signal wire is located between the metal layer where the data wire is located and the metal layer where the first power wire is located. The shielding signal line at least partially overlaps the first data line, and/or the shielding signal line at least partially overlaps the first sub power line. The shielding signal line and the first data line are at least partially overlapped, so that the shielding signal line can shield voltage jump on the first data line, the coupling effect of the voltage jump on the first data line on the first sub power line is prevented, the voltage on the first sub power line can be prevented from being influenced by the first data line to generate fluctuation, and further the voltage fluctuation on the first sub power line is prevented from adversely affecting the voltage on the first data line. The shielding signal line and the first sub power line are at least partially overlapped, so that the shielding signal line can shield the first sub power line from being influenced by voltage jump on the first data line, the voltage on the first sub power line is prevented from being influenced by the first data line to generate fluctuation, and further the voltage fluctuation on the first sub power line is prevented from adversely influencing the voltage on the first data line. The shielding signal line provided by the embodiment of the invention can play a shielding role between the first data line and the first sub-power line, improve the line crosstalk between the first data line and the first sub-power line, and improve the display effect.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view taken at position A-A' of FIG. 3;

FIG. 5 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a portion of another display panel according to an embodiment of the invention;

FIG. 7 is a top view of a portion of the membrane layer of FIG. 6;

FIG. 8 is a schematic cross-sectional view of the position B-B' of FIG. 7;

FIG. 9 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a portion of the display panel provided in the embodiment of FIG. 9;

FIG. 11 is a top view of a portion of the film layer of FIG. 10;

FIG. 12 is a schematic cross-sectional view taken at the line C-C' of FIG. 11;

FIG. 13 is a simplified schematic diagram of a portion of another display panel according to an embodiment of the invention;

FIG. 14 is a simplified schematic diagram of a portion of another display panel according to an embodiment of the invention;

FIG. 15 is a simplified schematic diagram of a portion of another display panel according to an embodiment of the present invention;

FIG. 16 is a simplified schematic diagram of a portion of another display panel according to an embodiment of the invention;

FIG. 17 is a schematic view of a portion of another display panel according to an embodiment of the present invention;

FIG. 18 is a schematic view of a portion of another display panel according to an embodiment of the present invention;

FIG. 19 is a schematic view of a portion of another display panel according to an embodiment of the invention;

FIG. 20 is a schematic view of a portion of another display panel according to an embodiment of the invention;

FIG. 21 is a simplified schematic diagram of a portion of another display panel according to an embodiment of the invention;

FIG. 22 is a schematic diagram of a portion of another display panel according to an embodiment of the invention;

FIG. 23 is a schematic view of a portion of another display panel according to an embodiment of the present invention;

FIG. 24 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 25 is a schematic view of another display panel according to an embodiment of the present invention;

Fig. 26 is a schematic diagram of a display device according to an embodiment of the invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the prior art, the data lines are connected to the data terminals through a demultiplexer, one demultiplexer connecting at least two data lines. After a switch connected with a data line in the demultiplexer is turned on, the data terminal is conducted with the data line, and after the switch is conducted, a data signal is written into the data line by the data terminal. When the switch is closed, the data line is in a floating state, and when the data line is in a floating state, the voltage signal is easy to be influenced by coupling to generate fluctuation. If the display area is also provided with a power line, the extending directions of the power line and the data line are the same, and a larger coupling effect exists between the power line and the data line. When the sub-pixel driven by the data line is black-cut (i.e., switched to 0 gray scale), the voltage jump on the data line will cause the voltage jump on the power line, and the voltage jump on the power supply will affect the voltage on the data line in turn. When the data line is in a floating state after the switch is turned off, the voltage on the data line is easy to be coupled to generate fluctuation similar to the voltage on the power line, and the coupling effect between the data line and the power line is called line crosstalk, and the line crosstalk influences the data voltage and further influences the display effect.

In order to solve the problems in the prior art, the embodiment of the invention provides a display panel, wherein a shielding signal wire is arranged between a film layer where a data wire is positioned and a film layer where a power wire is positioned, a constant voltage is connected to the shielding signal wire, and the shielding signal wire is utilized to play a role in signal shielding between the data wire and the power wire, so that the wire crosstalk between the data wire and the power wire is improved.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 1, the display panel includes a demultiplexer 10, an input end of the demultiplexer 10 is coupled to a data terminal 20, an output end of the demultiplexer 10 is coupled to n data lines 30, n is an integer, and n is greater than or equal to 2. One data line 30 is coupled to a plurality of pixel circuits 40. The pixel circuit 40 is illustrated in fig. 1 only in a block diagram. The demultiplexer 10 includes n switches, one of which is connected to each of the data lines 30. The display panel is also provided with a control line, the control end of the switch is coupled with the control line, and the control line controls the switch to work. Fig. 1 illustrates that n=2, the display panel includes two control lines, namely a first control line 51 and a second control line 52, respectively, a control end of the first switch 11 in the demultiplexer 10 is connected to the first control line 51, and a control end of the second switch 12 is connected to the second control line 52. The first switch 11 and the second switch 12 are illustrated in fig. 1 as p-type transistors, which may also be n-type transistors in some embodiments.

The operation of the demultiplexer 10 is as follows: the first control line 51 provides an enable signal to control the first switch 11 to be turned on, and the data line 30 connected to the first switch 11 is turned on to the data terminal 20, and the data terminal 20 writes the data voltage to the data line 30. The first control line 51 then provides a disable signal to control the first switch 11 to be turned off, and the data line 30 connected to the first switch 11 is in a floating state. After the first switch 11 is turned off, the second control line 52 provides an enable signal to control the second switch 12 to be turned on, and then the data line 30 connected to the second switch 12 is turned on with the data terminal 20, and the data terminal 20 writes the data voltage to the corresponding data line 30. The first switch 11 and the second switch 12 are turned on respectively in different periods to write the data signal to the corresponding data line 30.

In the embodiment of the invention, the pixel circuit can be of an aTbC structure, a and b are positive integers, a is more than or equal to 2, b is more than or equal to 1, T represents a transistor, and C represents a capacitor. Fig. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present invention, and fig. 2 is a schematic diagram of a pixel circuit with a structure of 7T1C, that is, the pixel circuit includes 7 transistors and 1 capacitor. As shown in fig. 2, the pixel circuit includes a driving transistor Tm, a gate reset transistor T1, an electrode reset transistor T2, a data writing transistor T3, a threshold compensation transistor T4, a first light emission control transistor T5, and a second light emission control transistor T6. The driving transistor Tm is connected in series between the first light emission control transistor T5 and the second light emission control transistor T6, and a control terminal of the driving transistor Tm is connected to the first node N1. The control terminal of the first light emitting control transistor T5 and the control terminal of the second light emitting control transistor T6 receive the light control signal E, and the first light emitting control transistor T5 receives the first power signal P1. The second light emission control transistor T6 is also connected to the fourth node N4, the first electrode of the light emitting device PD is connected to the fourth node N4, and the second electrode of the light emitting device PD receives the second power signal P2. One of the first power signal P1 and the second power signal P2 is a positive power signal, and the other is a negative power signal. The data writing transistor T3 is connected to the second node N2, the data writing transistor T3 receives the data signal Vdata, the threshold compensating transistor T4 is connected in series between the first node N1 and the third node N3, the control terminal of the data writing transistor T3 receives the first scan signal S1, and the control terminal of the threshold compensating transistor T4 receives the second scan signal S2. One end of the electrode reset transistor T2 receives the reset signal Ref, the other end is connected to the fourth node N4, one end of the gate reset transistor T1 receives the reset signal Ref, the other end is connected to the first node N1, the control end of the electrode reset transistor T2 receives the third scan signal S3, and the control end of the gate reset transistor T1 receives the fourth scan signal S4. The pixel circuit further comprises a storage capacitor Cst, wherein one polar plate of the storage capacitor Cst is connected with the first node N1, and the other polar plate of the storage capacitor Cst receives the first power supply signal P1. The embodiment of the invention does not limit the types of transistors in the pixel circuit, and fig. 2 illustrates p-type transistors.

In some embodiments, the first scan signal S1 and the second scan signal S2 are the same signal, the third scan signal S3 and the fourth scan signal S4 are the same signal, and the first scan signal S1 and the third scan signal S3 are respectively provided by two cascaded bit registers in the display panel.

In some embodiments, the threshold compensation transistor T4 and the gate reset transistor T1 are n-type transistors, and the remaining transistors are p-type transistors. The active layers of the threshold compensation transistor T4 and the gate reset transistor T1, for example, contain metal oxides, and the active layers of the remaining transistors contain silicon. In this embodiment, the first scan signal S1 and the second scan signal S2 are respectively provided by two cascaded bit registers in the driving circuit, and the third scan signal S3 and the fourth scan signal S4 are respectively provided by two cascaded bit registers in the other driving circuit.

In some embodiments, the electrode reset transistor T2 and the gate reset transistor T1 receive the same reset signal. In other embodiments, the voltage values of the reset signals received by the electrode reset transistor T2 and the gate reset transistor T1 are different.

Fig. 3 is a schematic partial view of a display panel according to an embodiment of the invention, and fig. 4 is a schematic cross-sectional view at a position A-A' in fig. 3. Fig. 3 schematically shows the positions of two pixel circuits in the ith row in the display panel, where i is a positive integer. The pixel circuit 40 of fig. 3 can be understood in conjunction with fig. 2. Fig. 3 is a partial schematic view of the display panel provided in the embodiment of fig. 1. As shown in fig. 3, the data line 30, the first power line 60, and the shielding signal line 70 extend in the first direction y, the shielding signal line 70 is turned on at a constant voltage, and the data line 30 transmits a data signal. Optionally, the first power line 60 transmits a positive power signal. Also shown in fig. 3 is a via V0, through which the pixel circuit 40 is connected to the first electrode of the light emitting device PD.

Fig. 3 schematically illustrates a first Scan line scan1_i, a second Scan line scan2_i, a light emission control line emit_i, and a reset signal line Vref for driving the pixel circuits of the i-th row. Fig. 3 illustrates that the first Scan line scan1_i, the second Scan line scan2_i, the emission control line emit_i, and the reset signal line Vref extend in a second direction x, and the second direction x intersects the first direction y. The first Scan line scan1_i and the second Scan line scan2_i are respectively connected to two shift registers cascaded in one driving circuit, the first Scan line scan1_i supplies a Scan signal to control the gate reset transistor T1 in the pixel circuit of the i-th row, and the first Scan line scan1_i supplies a Scan signal to control the electrode reset transistor T2 in the pixel circuit of the i-1-th row. The first Scan line scan1_i+1 illustrated in fig. 3 transmits the same signal as the second Scan line scan2_i, and the electrode reset transistor T2 in the pixel circuit of the i-th row is controlled by the Scan signal supplied from the first Scan line scan1_i+1. In addition, the gate reset transistor T1 and the electrode reset transistor T2 are schematically illustrated in fig. 3 as being connected to the same reset signal line Vref.

As seen in connection with fig. 4, the display panel includes a substrate 00, and a first metal layer M1, a second metal layer M2, and a third metal layer M3 sequentially disposed away from the substrate 00; the first power line 60 is located at the first metal layer M1, the shielding signal line 70 is located at the second metal layer M2, and the data line 30 is located at the third metal layer M3. The display panel further includes a semiconductor layer 01 on the substrate 00 side, a gate metal layer 02, and an electrode metal layer 03, and an active layer of a transistor in a pixel circuit is located in the semiconductor layer 01, and a driving transistor Tm is illustrated in fig. 4. The gate (i.e., control terminal) of the driving transistor Tm is located in the gate metal layer 02. The first electrode plate of the storage capacitor Cst is positioned on the gate metal layer 02, and the second electrode plate is positioned on the electrode metal layer 03. The second electrode plate is connected to the first power line 60 through the first via hole V1, and optionally, the first power line 60 provides a positive power voltage.

The data line 30 includes a first data line 31, and the first power line 60 includes a first sub power line 61, and the first data line 31 is adjacent to the first sub power line 61. The first data line 31 and the first sub power line 61 extend in the same direction and are located in different metal layers, and adjacent to each other means that the driving transistor Tm in the pixel circuit 40 is not spaced therebetween in the plan view schematically shown in fig. 3. The adjacent first data line 31 and first sub power line 61 do not overlap in a direction perpendicular to the plane in which the substrate 00 is located, or the adjacent first data line 31 and first sub power line 61 have a partial overlap in a direction perpendicular to the plane in which the substrate 00 is located. The adjacent first data lines 31 and first sub power lines 61 are illustrated in fig. 3 not to overlap.

In the embodiment of the present invention, the shielding signal line 70 at least partially overlaps the first data line 31 and/or at least partially overlaps the first sub-power line 61 in the direction e perpendicular to the plane in which the substrate 00 is located. The fig. 3 and 4 embodiments are illustrated with only the shielded signal line 70 at least partially overlapping the first sub-power line 61. In other embodiments, the shielding signal line 70 at least partially overlaps the first data line 31. In other embodiments, the shielding signal line 70 at least partially overlaps both the first data line 31 and the first sub power line 61.

Although the adjacent first sub power line 61 and the first data line 31 are located at different film layers in the display panel, there is coupling between the two due to the adjacent and close distance therebetween. The coupling effect between two signal lines transmitting different signals is not only present at the overlapping position of the two signal lines, but also present at the sides of the signal lines because of the electric field, and even if the two signal lines do not overlap, the coupling effect exists as long as the distance between the two signal lines is closer. When the data voltage is written to the first data line 31 via the demultiplexer 10, a voltage jump on the first data line 31 causes a voltage jump on the first sub-power line 61. After the writing of the data voltage is completed, the switch connected to the first data line 31 in the demultiplexer 10 is turned off, so that the first data line 31 is in a floating state, the voltage on the first data line 31 is easily affected by the voltage jump on the first sub-power line 61 to generate a fluctuation similar to the voltage on the first sub-power line 61, and the line crosstalk affects the voltage on the first data line 31, thereby affecting the display effect.

The display panel provided in the embodiment of the invention is provided with the shielding signal line 70, and the metal layer where the shielding signal line 70 is located between the metal layer where the data line 30 is located and the metal layer where the first power line 60 is located. The shielding signal line 70 at least partially overlaps the first data line 31, and/or the shielding signal line 70 at least partially overlaps the first sub power line 61. The shielding signal line 70 at least partially overlaps the first data line 31, so that the shielding signal line 70 can shield the voltage jump on the first data line 31, and prevent the voltage jump on the first data line 31 from coupling to the first sub power line 61, thereby preventing the voltage on the first sub power line 61 from being influenced by the first data line 31 to generate fluctuation, and further preventing the voltage fluctuation on the first sub power line 61 from adversely affecting the voltage on the first data line 31. The shielding signal line 70 at least partially overlaps the first sub power line 61, so that the shielding signal line 70 can shield the first sub power line 61 from the voltage jump on the first data line 31, prevent the voltage on the first sub power line 61 from being influenced by the first data line 31 to generate fluctuation, and further prevent the voltage fluctuation on the first sub power line 61 from adversely affecting the voltage on the first data line 31. The shielding signal line 70 provided by the embodiment of the invention can play a shielding role between the first data line 31 and the first sub-power line 61, improve the line crosstalk between the first data line 31 and the first sub-power line 61, and improve the display effect.

In addition, in the embodiment of the present invention, the metal layer where the shielding signal line 70 is located between the metal layer where the data line 30 is located and the metal layer where the first power line 60 is located. Of the three shielded signal lines 70, the data lines 30 and the first power lines 60, the first metal layer M1 where the first power lines 60 are located is closest to the substrate 00, and the third metal layer M3 where the data lines 30 are located is farthest from the substrate 00. The first power line 60 needs to be connected to the second polar plate of the storage capacitor Cst through the via hole V1 penetrating through the insulating layer, the first metal layer M1 where the first power line 60 is arranged is closer to the substrate 00, the thickness of the insulating layer penetrated through by the via hole V1 can be reduced, and the electrical connection performance of via hole connection is ensured. In addition, there is a coupling effect between the data line 30 and the Scan lines (such as the first Scan line scan1_i and the second Scan line scan2_i in fig. 3), and the Scan line 30 is disposed in a metal layer far from the substrate 00, which is beneficial to reducing the coupling between the data line 30 and the Scan line, further improving the line crosstalk and enhancing the signal stability on the data line 30.

In some embodiments, fig. 5 is a schematic diagram of another display panel according to an embodiment of the present invention, as shown in fig. 5, a plurality of pixel circuits 40 are arranged in a pixel circuit column 40L along a first direction y; the data line 30 includes a first sub-data line 30-1 and a second sub-data line 30-2, the first sub-data line 30-1 is coupled to the odd-numbered pixel circuits 40 in the pixel circuit column 40L, and the second sub-data line 30-2 is coupled to the even-numbered pixel circuits 40 in the pixel circuit column 40L. That is, one pixel circuit column 40L is provided with two data lines 30 correspondingly. Fig. 5 illustrates an example in which one demultiplexer 10 connects two first sub data lines 30-1 and two second sub data lines 30-2, i.e., n=4. In other embodiments, n is 6, 8, or other numerical value.

As shown in fig. 5, the demultiplexer 10 includes a first switch 11, a second switch 12, a third switch 13, and a fourth switch 14, where the first switch 11 and the second switch 12 are respectively connected to a first sub-data line 30-1, and the third switch 13 and the fourth switch 14 are respectively connected to a second sub-data line 30-2. The control terminal of the first switch 11 is connected to a first control line 51, the control terminal of the second switch 12 is connected to a second control line 52, the control terminal of the third switch 13 is connected to a third control line 53, and the control terminal of the fourth switch 14 is connected to a fourth control line 54.

An example of the odd-numbered pixel circuit rows in the display panel is the first pixel circuit row from top to bottom in fig. 5, wherein the plurality of pixel circuits 40 are arranged in the pixel circuit row along the second direction x. When writing the corresponding data voltage into the first pixel circuit row, the first control line 51 provides an enable signal to control the first switch 11 to be turned on, the first sub data line 30-1 connected with the first switch 11 is conducted with the data terminal 20, and the data terminal 20 writes the data voltage into the first sub data line 30-1; the second control line 52 then provides an enable signal to control the second switch 12 to turn on, and the first sub data line 30-1 connected to the second switch 12 is connected to the data terminal 20 to conduct the write data voltage. The first switch 11 and the second switch 12 in the demultiplexer 10 are turned on once in different periods respectively, and the process of writing the data voltage to the first pixel circuit row is realized in cooperation with writing the data voltage to the first sub data line 30-1.

The second pixel circuit row from top to bottom in fig. 5 shows the even number of pixel circuit rows in the panel. When writing data voltage to the second pixel circuit row, the third control line 53 provides an enable signal to control the third switch 13 to be turned on, and the second sub data line 30-2 connected with the third switch 13 is connected with the data terminal 20 to conduct writing data voltage; the fourth control line 54 then provides an enable signal to control the fourth switch 14 to turn on, and the second sub data line 30-2 connected to the fourth switch 14 is connected to the data terminal 20 to conduct the write data voltage. The third switch 13 and the fourth switch 14 in the demultiplexer 10 are turned on once in different periods respectively, and write the data voltages to the second pixel circuit row in cooperation with writing the data voltages to the second sub data line 30-2.

In this embodiment, the odd-numbered pixel circuits 40 in the pixel circuit column 40L are connected to the first sub data line 30-1, the even-numbered pixel circuits 40 are connected to the second sub data line 30-2, the first sub data line 30-1 and the second sub data line 30-2 corresponding to one pixel circuit column 40L are connected to the same demultiplexer 10, and the first sub data line 30-1 and the second sub data line 30-2 are correspondingly connected to different switches. When the data voltages are written row by row to the display panel, the switch in the demultiplexer 10 is controlled to be turned on in a time-sharing manner to control the alternating writing of the data voltages to the first sub data line 30-1 and the second sub data line 30-2, so that the charging time on the first sub data line 30-1 and the charging time on the second sub data line 30-2 can be ensured to be sufficient, and the image distortion caused by the insufficient charging of the data lines can be avoided.

In the embodiment of fig. 5, two data lines 30 are correspondingly disposed in one pixel circuit column 40L, the number of data lines 30 on the display panel is larger, the coupling effect between the data lines 30 and the first power line 60 is stronger, and the line crosstalk problem is more serious. In some embodiments of the present invention, on the basis of the corresponding connection manner of the data line 30 and the pixel circuit column 40 in the embodiment of fig. 5, a shielding signal line is added to the display panel, so as to play a shielding role between the data line 30 and the first power line 60, and improve the line crosstalk problem.

Fig. 6 is a schematic partial view of another display panel according to an embodiment of the present invention, and fig. 6 illustrates a position of four pixel circuits 40 in the i-th row and the i+1-th row in the display panel, where i is a positive integer. The connection of the transistors in the pixel circuit 40 of fig. 6 can be understood in conjunction with fig. 2. Fig. 7 is a top view of a portion of the film layer of fig. 6, and fig. 7 illustrates only the data line 30, the first power line 60, and the shielding signal line 70. FIG. 8 is a schematic cross-sectional view of the position B-B' of FIG. 7.

The first Scan line scan1_i, the second Scan line scan2_i, the first Scan line scan1_i+1, and the first Scan line scan2_i+1 in fig. 6 can be understood in conjunction with the description of the embodiment of fig. 3, and are not repeated herein. A first reset signal line Vref1 and a second reset signal line Vref2 are schematically shown in fig. 6, wherein the gate reset transistor T1 is connected to the first reset signal line Vref1 and the electrode reset transistor T2 is connected to the second reset signal line Vref2. The first reset signal line Vref1 and the second reset signal line Vref2 transmit signals having different voltage values.

The connection manner of the data line 30 and the pixel circuit in fig. 6 can be understood with reference to fig. 5, and fig. 6 is a partial schematic diagram of the display panel provided in the embodiment of fig. 5. In fig. 6, the locations where the first sub data line 30-1 is electrically connected to the pixel circuits and the locations where the second sub data line 30-2 is electrically connected to the pixel circuits are schematically indicated by arrows, and it can be seen that the first sub data line 30-1 is electrically connected to the odd-numbered pixel circuits in the pixel circuit column and the second sub data line 30-2 is electrically connected to the even-numbered pixel circuits in the pixel circuit column.

The data line 30 illustrated in fig. 6 includes a first data line 31, and the first power line 60 includes a first sub power line 61, and the first data line 31 is adjacent to the first sub power line 61. The first data line 31 in the embodiment of fig. 6 includes a first sub data line 30-1, that is, the first sub data line 30-1 is adjacent to the first sub power line 61, and a shielding signal line 70 is disposed corresponding to the adjacent first sub data line 30-1 and first sub power line 61.

As can be seen in fig. 6 to 8, the first power line 60 is located at the first metal layer M1, the shielding signal line 70 is located at the second metal layer M2, and the data line 30 is located at the third metal layer M3. The shielding signal line 70 at least partially overlaps the first data line 31 in a direction e perpendicular to the plane of the substrate 00, and the shielding signal line 70 at least partially overlaps the first sub-power line 61.

In the embodiment of the invention, two data lines 30 are correspondingly arranged in one pixel circuit column 40L, when the data voltages are written row by row to the display panel, the switch in the demultiplexer 10 is controlled to be opened in a time-sharing manner to control the data voltages to be alternately written to the first sub-data line 30-1 and the second sub-data line 30-2, so that the charging time on the first sub-data line 30-1 and the charging time on the second sub-data line 30-2 are relatively sufficient, and the image distortion caused by the insufficient charging of the data lines is avoided. The shielding signal line 70 is manufactured between the film layer where the data line 30 is located and the film layer where the first power line 60 is located, and the shielding signal line 70 is arranged to at least partially overlap the first data line 31 and/or the shielding signal line 70 at least partially overlaps the first sub-power line 61, so that the shielding effect between the adjacent first data line 31 and first sub-power line 61 can be achieved by using the shielding signal line 70, and the problem of line crosstalk caused by coupling between the first data line 31 and the first sub-power line 61 can be improved.

In addition, fig. 8 only illustrates the substrate 00 in the display panel, and the first, second, and third metal layers M1, M2, and M3 in which the first power supply line 60, the shield signal line 70, and the data line 30 are located, respectively. The display panel further includes at least a semiconductor layer 00, a gate metal layer 02, and an electrode metal layer 03 as shown in fig. 4.

In other embodiments, fig. 9 is a schematic diagram of another display panel provided by the embodiment of the present invention, and fig. 10 is a partial schematic diagram of the display panel provided by the embodiment of fig. 9.

As shown in fig. 9, the display panel includes a display area AA and a non-display area NA, the data line 30 is located in the display area AA, and the demultiplexer 10 and the data terminal 20 are located in the non-display area NA. The first power line 60 and the shielding signal line 70 in the display panel are also located in the display area AA. The display area AA further includes a connection line 80, and the data line 30 includes a second data line 32, and one end of the connection line 80 is connected to the second data line 32, and the other end is connected to the output terminal of the demultiplexer 10. The connection line 80 comprises a first line segment 81 extending in a first direction y and a second line segment 82 extending in a second direction x, which intersects the first direction y. The second line segment 82 is coupled to the first line segment 81. In this embodiment, the second data line 32 is connected to the demultiplexer 10 of the non-display area NA through the connection line 80 located in the display area AA, so that the space of the non-display area NA can be saved, which is advantageous for narrowing the frame. The shape of the display area AA in fig. 9 is only schematically shown, and the embodiment of the present invention is applicable to a display panel having curved corners of the display area AA.

In fig. 9, a part of the data line 30 is shown connected to the demultiplexer 10 through a fanout line located in the non-display area NA, and the part of the data line 30 is located in the middle of the display area AA. The second data line 32 is located at edge positions of both sides of the display area AA in the second direction x.

Fig. 10 schematically illustrates the positions of part of the pixel circuits of the i-th row and the i+1-th row in the display panel. The pixel circuits and the signal lines in fig. 10 can be understood in conjunction with the description in fig. 6, and are not described herein. Fig. 11 is a top view of a portion of the film layer in fig. 10, and fig. 11 illustrates only the data line 30, the first power line 60, the shielding signal line 70, and the connection line 80. FIG. 12 is a schematic cross-sectional view taken at the line C-C' of FIG. 11. As seen in fig. 10 to 12, the first line segment 81 of the connection line 80 is located in the third metal layer M3, and the second line segment 82 of the connection line 80 is located in the second metal layer M2. That is, the first line segment 81 is located at the same layer as the data line 30, and the second line segment 82 is located at the same layer as the shielding signal line 70. It can be seen in connection with fig. 11 and 12 that the first line segment 81 and the second line segment 82 are electrically connected by a via penetrating the insulating layer.

In the embodiment of the invention, the first power lines 60 and the data lines 30 with the same extending direction are positioned on different layers, the shielding signal lines 70 are arranged between the film layer on which the first power lines 60 are positioned and the film layer on which the data lines 30 are positioned, and the shielding signal lines 70 can play a shielding role between the adjacent first sub power lines 61 and the first data lines 31, thereby improving the line crosstalk problem caused by the coupling effect between the first sub power lines 61 and the first data lines 31. The connection line 80 is further disposed in the display area AA, and the connection line 80 is connected between the second data line 32 and the demultiplexer 10, so that the space of the non-display area NA can be saved by disposing the connection line 80 in the display area AA, which is beneficial to narrowing the frame. The embodiment of the invention combines the schemes for improving the line crosstalk and the frame narrowing, and on the basis of the combination of the two schemes, the first line segment 81 in the connecting line 80 and the data line 30 with the same extending direction are arranged on the same layer, and the second line segment 82 in the connecting line 80 and the shielding signal line 70 are arranged on the same layer. Although the second line segment 82 and the shielding signal line 70 extend in different directions, they are still disposed on the same metal layer, and considering that the connection line 80 is substantially disposed in the display area AA near the lower border, the space occupied by the connection line 80 in the display area AA is relatively small. Therefore, the second line segment 82 and the shielding signal line 70 are arranged in the same layer, so that the wiring influence on the shielding signal line 70 is small, and the second line segment 82 and the shielding signal line 70 are arranged in the same layer, so that the process can be saved, and the thickness of the display panel can be reduced.

In some embodiments, as indicated by the dashed line in fig. 10 and 11, the shielded signal line 70 is broken at the location where it intersects the second line segment 82. This arrangement ensures that the second line segment 82 and the shielding signal line 70 are insulated from each other, and the transmission signals of the second line segment 82 and the shielding signal line 70 do not interfere with each other.

In some embodiments, fig. 13 is a partially simplified schematic illustration of another display panel according to an embodiment of the invention. Fig. 13 is a plan view illustrating only the adjacent first sub power lines 61 and first data lines 31, and the shield signal lines 70. As shown in fig. 13, the shielding signal line 70 includes a third line segment 70-3, the third line segment 70-3 at least partially overlaps the first data line 31 in a direction perpendicular to the plane of the substrate, and the third line segment 70-3 is adjacent to the first sub-power line 61.

In other embodiments, fig. 14 is a partially simplified schematic illustration of another display panel according to an embodiment of the invention. As shown in fig. 14, the shielding signal line 70 includes a fourth line segment 70-4, and the fourth line segment 70-4 at least partially overlaps the first sub-power line 61 in a direction perpendicular to a plane in which the substrate is located.

In other embodiments, fig. 15 is a partially simplified schematic illustration of another display panel according to an embodiment of the invention. As shown in fig. 15, the shielding signal line 70 includes a fifth line segment 70-5, the fifth line segment 70-5 at least partially overlaps the first data line 31 in a direction perpendicular to a plane of the substrate, and the fifth line segment 70-5 at least partially overlaps the first sub-power line 61.

In other embodiments, fig. 16 is a partially simplified schematic illustration of another display panel according to an embodiment of the invention. As shown in fig. 16, the shielding signal line 70 includes a sixth line segment 70-6, and the sixth line segment 70-6 does not overlap with the first data line 31 and the first sub-power line 61 in a direction perpendicular to the plane of the substrate; the first data line 31, the sixth line segment 70-6, and the first sub-power line 61 are sequentially arranged along a third direction c, which is parallel to the plane of the substrate. I.e. the sixth line segment 70-6 is seen in top view between the first data line 31 and the first sub-power line 61.

Fig. 13 to 16 illustrate several alternative cases of overlapping relationship between the line segment in the shield signal line 70 and the first data line 31 and the first sub power line 61. In the embodiment of the present invention, one shielding signal line 70 includes at least one of a third line segment 70-3, a fourth line segment 70-4, a fifth line segment 70-5, and a sixth line segment 70-6.

In some embodiments, as shown in FIG. 7, the shielded signal line 70 is a substantially straight line extending in the first direction y, and the shielded signal line 70 includes a third line segment 70-3 and a fifth line segment 70-5. The third line segment 70-3 at least partially overlaps the first data line 31 in a direction perpendicular to the plane of the substrate, and the fifth line segment 70-5 partially overlaps both the first sub-power line 61 and the first data line 31. In this embodiment, the first sub power line 61 is seen as a whole in the first direction y, and the first sub power line 61 includes a broken line segment at a partial position, and it can be considered that the first sub power line 61 extends in the first direction y. The shielding signal line 70 is arranged to have a line shape substantially the same as that of the first data line 31, and the shielding signal line 70 is used to play a shielding role between the first data line 31 and the first sub-power line 61, thereby improving the line crosstalk between the first data line 31 and the first sub-power line 61 and enhancing the display effect.

In other embodiments, fig. 17 is a schematic partial view of another display panel according to an embodiment of the present invention, and both the pixel circuit and the signal line in fig. 17 can be understood by referring to the above embodiment of fig. 6. As shown in fig. 17, the shielded signal line 70 includes a fifth line segment 70-5 and a sixth line segment 70-6. The fifth line segment 70-5 partially overlaps both the first sub-power line 61 and the first data line 31 in a direction perpendicular to the plane of the substrate. The sixth line segment 70-6 is located between the first sub power line 61 and the first data line 31 in a top view. In this embodiment, the first sub power line 61 includes a broken line segment at a local position, and the shielding signal line 70 includes a fifth segment 70-5 and a sixth segment 70-6 according to the line shape of the first sub power line 61 and the positional relationship between the first sub power line and the first data line 31, so that it can be ensured that each segment of the shielding signal line 70 plays a role in better signal shielding at the position where it is located.

In other embodiments, fig. 18 is a schematic partial view of another display panel provided by the embodiment of the present invention, and as can be understood from comparison with the embodiment of fig. 17, as shown in fig. 18, the shape of the shielding signal line 70 is the same as that of the first sub-power line 61, the shielding signal line 70 substantially covers the first sub-power line 61 along the direction perpendicular to the plane of the substrate, and a part of the line segment of the shielding signal line 70 overlaps the first data line 31. The shielding signal line 70 not only can play a shielding role between the first data line 31 and the first sub power line 61, but also can improve the line crosstalk between the first data line 31 and the first sub power line 61, thereby improving the display effect. Further, the mask for manufacturing the first sub power supply line 61 can be used to manufacture the shield signal line 70, which can reduce the cost.

In other embodiments, fig. 19 is a schematic diagram of a portion of another display panel according to an embodiment of the invention, as shown in fig. 19, the data line 30 includes a first data line 31 and a third data line 33, the first power line 60 includes a first sub-power line 61, the third data line 33 is adjacent to the first data line 31, and the first data line 31 and the third data line are adjacent to the first sub-power line 61. The third data line 33 is adjacent to the first data line 31 without spacing the driving transistors of the pixel circuits therebetween, and the third data line is adjacent to the first sub power line 61 without spacing the driving transistors of the pixel circuits therebetween.

The pixel circuits and signal lines in fig. 19 can be understood by referring to the above description of fig. 6. The data line 30 includes a first sub data line 30-1 and a second sub data line 30-2, the first data line 31 illustrated in fig. 19 is a second sub data line 30-2, and the third data line 33 is a second sub data line 30-2. It will be understood that the first data line 31 and the third data line 33 are named according to the adjacent relationship between the data line 30 and the first sub-power line 61, and the first sub-data line 30-1 and the second sub-data line 30-2 are named according to the connection relationship between the data line and the pixel circuits in the pixel circuit column.

Fig. 17 and 19 each illustrate the location of four pixel circuits, and fig. 19 differs from fig. 17 only in the location of the shielding signal line 70. The shape of the shielded signal wire 70 in fig. 19 can be understood in conjunction with fig. 17. Fig. 19 is a schematic plan view of the display panel, and it can be understood that the plan view is parallel to the plane direction perpendicular to the substrate. As can be seen in fig. 19, the shielded signal line 70 includes a seventh line segment 70-7. The seventh line segment 70-7 at least partially overlaps the first data line 31, the seventh line segment 70-7 at least partially overlaps the third data line 33, and the seventh line segment 70-7 at least partially overlaps the first sub-power line 61 in a direction perpendicular to a plane in which the substrate lies.

In this embodiment, the first sub power line 61 is adjacent to both the first data line 31 and the third data line 33, and both the first data line 31 and the third data line 33 are susceptible to the coupling of the first sub power line 61. A shielding signal line 70 is disposed at the positions of the first data line 31, the third data line 33 and the first sub-power line 61 adjacent thereto, and the seventh line segment 70-7 of the shielding signal line 70 partially overlaps with all of the three, thereby improving the line crosstalk problem by using one shielding signal line 70 to play a shielding role between the first data line 31 and the first sub-power line 61 and between the third data line 33 and the first sub-power line 61. In some embodiments, the shield signal line 70 turns on the reset signal. Fig. 20 is a schematic view of a portion of another display panel according to an embodiment of the invention. As shown in fig. 20, the display panel further includes a reset signal line Vref extending along a second direction x intersecting the first direction y. The display panel further comprises a fourth metal layer, wherein the fourth metal layer is positioned on one side of the first metal layer M1, which is close to the substrate 00, and the reset signal line Vref is positioned on the fourth metal layer; the shielding signal line 70 and the reset signal line Vref are electrically connected through the via hole V2 of the insulating layer. The position of the via V2 in fig. 20 is only schematically represented. The fourth metal layer may be the electrode metal layer 03 illustrated in fig. 4, as seen in connection with the film structure diagram illustrated in fig. 4. In this embodiment, the shielding signal line 70 is electrically connected to the reset signal line Vref, so that the shielding signal line 70 is turned on to perform a signal shielding function between the adjacent first data line 31 and first sub-power line 61 by using the shielding signal line 70, thereby improving line crosstalk between the adjacent first data line 31 and first sub-power line 61. And the shielding signal lines 70 and the reset signal lines Vref which are mutually crossed in the extending direction can be electrically connected to form a grid-shaped wiring, so that the voltage drop for transmitting the reset signal is reduced, and the in-plane uniformity of the reset signal is improved.

Fig. 20 illustrates that only one pixel circuit column is correspondingly provided with one data line, and the scheme provided by the embodiment of fig. 5 that one pixel circuit column is correspondingly provided with two data lines is also applicable to the technical scheme that the shielding signal line 70 is electrically connected with the reset signal line through the via hole of the insulating layer, which is not illustrated in the drawings.

In some embodiments, fig. 21 is a partially simplified schematic diagram of another display panel according to an embodiment of the invention. Fig. 21 simply illustrates the pixel circuit 40, the reset signal line, and the shielding signal line 70, and does not illustrate the data line 30 and the first power line 60. As shown in fig. 21, the reset signal lines in the display panel include a first reset signal line Vref1 and a second reset signal line Vref2, the first reset signal line Vref1 providing a first reset signal and the second reset signal line Vref2 providing a second reset signal, the voltage values of the first reset signal and the second reset signal being different; the first reset signal line Vref1 is electrically connected to the gate reset transistor T1, and the second reset signal line Vref2 is electrically connected to the electrode reset transistor T2. The shielding signal line 70 includes a first shielding signal line 71 and a second shielding signal line 72, the first shielding signal line 71 and the first reset signal line Vref1 are electrically connected through a first via V3, and the second shielding signal line 72 and the second reset signal line Vref2 are electrically connected through a second via V4. In order to distinguish the signal lines, fig. 21 shows only the first reset signal line Vref1 as a thick solid line and the second reset signal line Vref2 as a thin solid line, and the first shield signal line 71 as a thick solid line and the second shield signal line 72 as a thin solid line, and the thickness of the lines is not representative of the thickness of the lines in an actual product.

In this embodiment, two reset signal lines are provided, where the first reset signal line Vref1 provides a higher reset voltage to the control terminal of the driving transistor Tm, so that the faster the threshold of the control terminal of the driving transistor Tm is grasped, the shorter the time of grasping the threshold of the control terminal of the driving transistor Tm is applied to high-frequency display or low-brightness (or gray-scale) display, and the faster the threshold of the control terminal of the driving transistor Tm is grasped, the more accurate the threshold grasping is, so that display unevenness can be reduced; meanwhile, a lower reset voltage is provided to the electrode of the light emitting device PD through the second reset signal line Vref2, so that the lighting of the light emitting device PD can be reduced, and the low gray scale display effect can be improved. The first shielding signal line 71 is electrically connected with the first reset signal line Vref1, so that the first shielding signal line 71 and the first reset signal line are crossed to form a grid-shaped wiring, thereby reducing the voltage drop of the transmission first reset signal and improving the in-plane uniformity of the first reset signal. Providing the second shielding signal line 72 and the second reset signal line Vref2 electrically connected can cause the two to cross to form a grid-like trace, thereby reducing the voltage drop for transmitting the second reset signal and improving the in-plane uniformity of the second reset signal.

In some embodiments, as shown in fig. 21, the first shield signal lines 71 and the second shield signal lines 72 are alternately arranged in the second direction x.

In some embodiments, fig. 22 is a schematic partial view of another display panel according to an embodiment of the invention. As shown in fig. 22, the display panel includes a connection line 80, and the connection line 80 is located in the display area AA and connected to the second data line 32, and the connection line 80 is understood in conjunction with the embodiment of fig. 9. The connecting line 80 includes a second line segment 82 extending in the second direction x, and the shield signal line 70 is broken at a position intersecting the second line segment 82 (a position circled by a broken line in fig. 22). The line segment of the shielded signal line 70 between the adjacent two second line segments 82 is a shielded line segment 70x. The display panel further includes a first branch line z1 and a reset signal line, wherein one end of the first branch line z1 is coupled to the shielding line segment 70x, and the other end is coupled to the reset signal line, so that the shielding line segment 70x is connected to a constant voltage to ensure the shielding capability of the shielding line segment 70x. In fig. 22, the first branch line z1 is shown at the same level as the shield signal line 70, and the first branch line z1 is connected to the second reset signal line Vref2 through a via hole in the insulating layer. In other embodiments, the shielding signal line 70 is connected to the first reset signal line Vref1 through the first branch line z1, which is not illustrated herein.

In addition, in some embodiments, the shielding signal line 70 forms a break at a position crossing the second line segments 82, the shielding line segment 70x located between two adjacent second line segments 82 overlaps the reset signal line, and the shielding line segment 70x and the reset signal line overlapped therewith may be provided to be electrically connected through a via hole, such that the shielding line segment 70x is turned on a constant voltage to ensure shielding capability of the shielding line segment 70 x.

In other embodiments, fig. 23 is a schematic diagram illustrating a portion of another display panel according to an embodiment of the invention. As shown in fig. 23, the connection line 80 includes a first line segment 81 and a second line segment 82, the display panel further includes a second branch line z2, the second branch line z2 has the same extending direction as the first line segment 81, and the second branch line z2 is coupled to the reset signal line such that the second branch line z2 turns on the constant voltage; the second leg z2 at least partially overlaps the first leg 81 in a direction perpendicular to the plane of the substrate. In this embodiment, the connection line 80 transmits a data signal, and the second branch line z2 can shield the first line segment 81, so that interference of other signal lines on the data signal transmitted by the first line segment 81 can be reduced.

Fig. 23 illustrates that the second leg z2 is coupled to the first reset signal line Vref1 by a via, and in other embodiments, the second leg z2 is coupled to the second reset signal line Vref2, which is not illustrated herein.

In other embodiments, the display panel includes a second power line, and the shielding signal line is electrically connected to the second power line. Fig. 24 is a schematic diagram of another display panel according to an embodiment of the present invention, where, as shown in fig. 24, the display panel includes a display area AA and a non-display area NA, the data line 30, the first power line 60 and the shielding signal line 70 are located in the display area AA, and the demultiplexer 10 and the data terminal 20 are located in the non-display area NA; the display panel further includes a second power line 90 located in the non-display area NA, and the shielding signal line 70 is coupled to the second power line 90. By the arrangement, the voltage drop of the transmission power supply signal can be reduced, the in-plane uniformity of the power supply signal is improved, and the display effect is improved.

Alternatively, as shown in fig. 24, the shielding signal line 70 extends from the display area AA to the non-display area NA to be electrically connected to the second power line 90.

Only the shielding signal line 70 located in the display area AA, and the second power line 90 and the data terminal 20 located in the non-display area NA are illustrated in fig. 24. Optionally, the second power line 90 provides a negative power signal and the first power line 60 provides a positive power signal.

In other ways, fig. 25 is a schematic diagram of another display panel according to an embodiment of the present invention, and fig. 25 illustrates connection lines 80 and shielding signal lines 70 in a display area AA, and data terminals 20 and a demultiplexer 10 in a non-display area NA. As shown in fig. 25, the display panel further includes an auxiliary signal line 92 located in the display area NA, the auxiliary signal line 92 extending along a second direction x intersecting the first direction y; the auxiliary signal line 92 is electrically connected to the shielding signal line 70 in a crossing manner, and the auxiliary signal line 92 is located in the second metal layer M2, i.e., the auxiliary signal line 92 is located in the same layer as the shielding signal line 70. The auxiliary signal line 92 crosses and is electrically connected to the shielding signal line 70, and can further reduce the voltage drop of the transmission power signal.

In fig. 25, only the shielding signal line 70 extends from the display area AA to the non-display area NA and is electrically connected to the second power line 90, and in other embodiments, at least a portion of the auxiliary signal line 92 extends from the display area AA to the non-display area NA and is electrically connected to the second power line 90.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 26 is a schematic diagram of the display device provided by the embodiment of the present invention, and as shown in fig. 26, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 is already described in the above embodiments, and will not be described here again. The display device provided by the embodiment of the invention can be electronic equipment such as a mobile phone, a computer, a tablet, a television, a vehicle-mounted display, an intelligent wearing product and the like.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A display panel, wherein the display panel comprises a demultiplexer, a data terminal, a data line, a first power line and a shielding signal line; the data line, the first power line and the shielding signal line extend along a first direction, and the shielding signal line is connected with a constant voltage; the input end of the demultiplexer is coupled with the data terminal, the output end of the demultiplexer is coupled with n data lines, n is an integer, and n is more than or equal to 2;

2. The display panel of claim 1, wherein the display panel comprises,

The display panel comprises a display area and a non-display area, the data line, the first power line and the shielding signal line are positioned in the display area, and the demultiplexer and the data terminal are positioned in the non-display area;

the display area further comprises a connecting line, the data line comprises a second data line, one end of the connecting line is connected with the second data line, and the other end of the connecting line is connected with the output end of the demultiplexer;

the connecting line comprises a first line segment extending along the first direction and a second line segment extending along a second direction, and the second direction is intersected with the first direction;

the second line segment is coupled with the first line segment, the first line segment is located on the third metal layer, and the second line segment is located on the second metal layer.

3. The display panel of claim 2, wherein the display panel comprises,

the shielding signal line forms a fracture at a position crossing the second line segment.

4. The display panel according to claim 3, wherein,

the shielding signal line comprises shielding line segments, and the shielding line segments are positioned between two adjacent second line segments;

the display panel further comprises a first branch line and a reset signal line, wherein one end of the first branch line is coupled with the shielding line segment, and the other end of the first branch line is coupled with the reset signal line.

5. The display panel of claim 2, wherein the display panel comprises,

the display panel further comprises a second branch line and a reset signal line, wherein the second branch line and the first line segment extend in the same direction, and the second branch line is coupled with the reset signal line; the second branch line at least partially overlaps the first line segment in a direction perpendicular to a plane in which the substrate lies.

6. The display panel of claim 1, wherein the display panel comprises,

the shielding signal line comprises a third line segment which at least partially overlaps the first data line along the direction perpendicular to the plane of the substrate;

and/or the shielding signal line comprises a fourth line segment, and the fourth line segment at least partially overlaps with the first sub-power line along the direction perpendicular to the plane of the substrate;

and/or, the shielding signal line comprises a fifth line segment, and the fifth line segment at least partially overlaps the first data line and the fifth line segment at least partially overlaps the first sub-power line along the direction perpendicular to the plane of the substrate;

and/or, the shielding signal line comprises a sixth line segment, and the sixth line segment is not overlapped with the first data line and the first sub-power line along the direction perpendicular to the plane of the substrate; and the first data line, the sixth line segment and the first sub-power line are sequentially arranged along a third direction, and the third direction is parallel to the plane where the substrate is located.

7. The display panel of claim 1, wherein the display panel comprises,

the display panel further includes a pixel circuit, a plurality of the pixel circuits being arranged in a pixel circuit column along the first direction;

the data lines comprise first sub data lines and second sub data lines, wherein for the pixel circuit columns in the same column, the first sub data lines are coupled with the odd-numbered pixel circuits in the pixel circuit columns, and the second sub data lines are coupled with the even-numbered pixel circuits in the pixel circuit columns.

8. The display panel of claim 7, wherein the display panel comprises,

the data line further includes a third data line adjacent to the first data line, and the third data line adjacent to the first sub power line;

the shielding signal line comprises a seventh line segment, the seventh line segment at least partially overlaps the first data line, the seventh line segment at least partially overlaps the third data line, and the seventh line segment at least partially overlaps the first sub-power line along a direction perpendicular to a plane where the substrate is located.

9. The display panel of claim 1, wherein the display panel comprises,

The display panel further comprises a reset signal line positioned at one side of the substrate, wherein the reset signal line extends along a second direction, and the second direction is intersected with the first direction;

the display panel further comprises a fourth metal layer, wherein the fourth metal layer is positioned on one side, close to the substrate, of the first metal layer, and the reset signal line is positioned on the fourth metal layer;

the shielding signal line is electrically connected with the reset signal line through a via hole of the insulating layer.

10. The display panel of claim 9, wherein the display panel comprises,

the reset signal line comprises a first reset signal line and a second reset signal line, and signal voltage values provided by the first reset signal line and the second reset signal line are different;

the shielding signal wire comprises a first shielding signal wire and a second shielding signal wire, the first shielding signal wire is electrically connected with the first reset signal wire through a first through hole, and the second shielding signal wire is electrically connected with the second reset signal wire through a second through hole.

11. The display panel of claim 1, wherein the display panel comprises,

The display panel further comprises a second power line positioned in the non-display area, and the shielding signal line is coupled with the second power line.

12. The display panel of claim 11, wherein the display panel comprises,

the display panel further comprises an auxiliary signal line positioned in the display area, wherein the auxiliary signal line extends along a second direction, and the second direction is intersected with the first direction;

the auxiliary signal line is electrically connected with the shielding signal line in a crossing way, and the auxiliary signal line is positioned on the second metal layer.

13. A display device comprising the display panel according to any one of claims 1 to 12.