CN116741630B - Dry etching method and semiconductor process equipment - Google Patents
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Abstract
The embodiment of the invention discloses a dry etching method and semiconductor process equipment, wherein the dry etching method is used for selectively etching a laminated structure comprising Si layers and SiGe layers which are alternately stacked, and comprises the following steps: when selectively etching the SiGe layer from the laminated structure, performing plasma etching on the laminated structure by using a first etching gas, wherein the first etching gas comprises fluorine-containing gas and first auxiliary etching gas; when selectively etching the Si layer from the laminated structure, performing plasma etching on the laminated structure by using a second etching gas, wherein the second etching gas comprises the fluorine-containing gas and a second auxiliary etching gas; wherein the first auxiliary etching gas and the second auxiliary etching gas are used for adjusting the etching selection ratio between SiGe and Si.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a dry etching method and semiconductor process equipment.
Background
With the continued advancement of moore's law, gate All Around (GAA) transistors are considered as effective substitutes for fin field effect transistors (finfets) after the semiconductor process has evolved to the 3nm node. In GAA fabrication process engineering, high selectivity is critical to etching horizontally stacked nanoplatelets of the sacrificial layer. The industry typically produces vertically stacked Si or SiGe nanowires by selectively removing SiGe or Si in Si and SiGe multilayer stacks. Typically, nfets are formed by selectively removing SiGe in a Si and SiGe multilayer stack to produce vertically stacked Si nanoplatelets, and selectively removing Si material to produce vertically stacked SiGe nanoplatelets to form pfets. In order to reduce the subsequent negative impact on the device, it is desirable that the SiGe and Si materials have a very high selectivity during etching relative to the other to avoid or reduce damage to the channel.
At present, wet etching technology is generally adopted in the industry to realize high selectivity etching of SiGe and Si materials, however, wet etching is easy to distort etching patterns, and accurate etching effect is difficult to obtain. The dry etching process faces the dilemma of low etching selectivity.
Disclosure of Invention
The embodiment of the invention discloses a dry etching method and semiconductor process equipment, which are used for solving the problems of low etching selectivity and low productivity when a Si layer or a SiGe layer is selectively etched from a laminated structure of the Si layer and the SiGe layer in the related technology.
To solve the above technical problem, according to a first aspect, an embodiment of the present invention discloses a dry etching method for selectively etching a stacked structure including Si layers and SiGe layers alternately stacked, the method including: when selectively etching the SiGe layer from the laminated structure, performing plasma etching on the laminated structure by using a first etching gas, wherein the first etching gas comprises fluorine-containing gas and first auxiliary etching gas; when selectively etching the Si layer from the laminated structure, performing plasma etching on the laminated structure by using a second etching gas, wherein the second etching gas comprises the fluorine-containing gas and a second auxiliary etching gas; wherein the first auxiliary etching gas and the second auxiliary etching gas are used for adjusting the etching selection ratio between SiGe and Si, and the first auxiliary etching gas is different from the second auxiliary etching gas.
As some alternative embodiments, the first auxiliary etching gas includes at least one of He, ar; or the second auxiliary etching gas comprises oxygen element and nitrogen element.
As some alternative embodiments, the fluorine-containing gas comprises a fluorocarbon-based gas.
As some alternative embodiments, the fluorocarbon-based gas includes CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 At least one of F.
As some alternative embodiments, the second auxiliary etching gas includes N 2 、O 2 、NO、NO 2 At least one of (a) and (b).
As some alternative embodiments, in the first etching gas, a ratio of the fluorine-containing gas and the first auxiliary etching gas ranges from 0.1 to 10.
As some alternative embodiments, in the second etching gas, the ratio of fluorine element to oxygen element is in the range of 0.1 to 10; or the ratio of fluorine element to nitrogen element is in the range of 0.1 to 10.
As some alternative embodiments, in the step of plasma etching the stacked structure with the first etching gas, the process chamber pressure is 100 to 5000mTorr; or in the step of performing plasma etching on the laminated structure by using the second etching gas, the pressure of the process chamber is 100 to 5000mTorr.
As some alternative embodiments, in the step of performing plasma etching on the laminated structure by using a first etching gas, a flow rate of the first etching gas ranges from 10 sccm to 4000sccm; or in the step of performing plasma etching on the laminated structure by using a second etching gas, the flow rate of the second etching gas is in the range of 10 to 4000sccm.
As some alternative embodiments, in the step of performing plasma etching on the laminated structure by using the first etching gas, the plasma etching is isotropic etching; or in the step of performing plasma etching on the laminated structure by using the second etching gas, the plasma etching is isotropic etching.
As some alternative embodiments, before the step of plasma etching the stacked structure with the first etching gas or before the step of plasma etching the stacked structure with the second etching gas, the method further comprises: and removing the natural oxide layer on the surface of the Si layer or the SiGe layer.
As some alternative embodiments, the natural oxide layer of the stacked structure is subjected to anisotropic plasma etching by using the fluorine-containing gas.
According to a second aspect, an embodiment of the present invention provides a semiconductor processing apparatus, including: the wafer carrying device is arranged in the second area, and is used for carrying out the process on the wafer carrying device; control means comprising at least one memory and at least one processor, said memory having stored therein a computer program, said processor executing said computer program to implement the dry etching method according to any of the above-mentioned first aspects.
As some optional embodiments, the semiconductor process apparatus further comprises: and the remote plasma device is used for exciting the introduced process gas into plasma and is communicated with the first area.
As some alternative embodiments, the remote plasma device is a microwave source.
As some alternative embodiments, the perforated barrier comprises multiple layers, and at least some of the through holes of the perforated barrier of adjacent layers are not aligned with each other.
As some alternative embodiments, the perforated separator is grounded or a predetermined voltage is applied.
In the dry etching method and the semiconductor process equipment provided by the embodiment of the invention, the SiGe layer is selectively etched from the laminated structure of the Si layer and the SiGe layer which are alternately stacked by utilizing the first etching gas, the Si layer is selectively etched from the laminated structure by utilizing the second etching gas, the main etching gas adopted for selectively etching the SiGe layer is the same as the main etching gas adopted for selectively etching the Si layer, only the auxiliary etching gas is different, the selective etching of the SiGe layer and the Si layer can be respectively completed in the same process chamber, the wafer is not required to be transmitted back and forth between different process chambers, the productivity is improved, and the good etching selection ratio is realized.
Drawings
Fig. 1A is a schematic diagram showing a stacked structure to which a dry etching method according to an embodiment of the present invention is applied;
FIG. 1B shows a schematic diagram of selectively etching a SiGe layer from the stacked structure shown in FIG. 1A;
FIG. 1C shows a schematic diagram of selectively etching a Si layer from the stacked structure shown in FIG. 1A;
FIG. 2 shows an electron microscope image obtained after selectively etching a SiGe layer from a stacked structure using a dry etching method according to an embodiment of the present invention;
FIG. 3 shows an electron microscope image obtained after selectively etching a Si layer from a stacked structure using a dry etching method according to an embodiment of the present invention;
FIG. 4 shows a schematic diagram of a semiconductor processing apparatus according to an embodiment of the invention;
fig. 5 shows a schematic top view of a perforated baffle according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is to be understood by one skilled in the art that the present embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. Furthermore, each of the examples given in connection with the various embodiments is intended to be illustrative, and not limiting. Moreover, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details of the embodiments of the present invention are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present methods and structures. It should also be noted that like and corresponding elements are denoted by like reference numerals.
In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the invention. However, it will be understood by those skilled in the art that the various embodiments of the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present invention.
For purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof shall relate to the structure and method as disclosed in the drawing figures of the specification. It will be understood that when an element as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, it can be directly under the other element or intervening elements may be present. On the contrary. When an element is referred to as being directly under another element, there are no intervening elements present therebetween.
The technical scheme disclosed by the embodiment of the invention is described in detail below with reference to the accompanying drawings.
Fig. 1A shows a stacked structure applied by a dry etching method according to an embodiment of the present invention, where the stacked structure may include alternately stacked Si layers 101 and SiGe layers 102, a hard mask layer 103 may be disposed above the alternately stacked Si layers 101 and SiGe layers 102, the hard mask layer 103 may be a silicon oxide layer or a silicon nitride layer or a stack of a silicon oxide layer and a silicon nitride layer, and the Si layers 101 and SiGe layers 102 are etched with the hard mask layer 103 as an etching mask, so as to form a fin-shaped stacked structure as shown in fig. 1A, and in a subsequent semiconductor process, the Si layers 101 are selectively removed from the stacked structure to leave the Si layers 101 as channels of GAA-FETs to be formed, or the Si layers 101 are selectively removed from the stacked structure to leave the SiGe layers 102 as channels of GAA-FETs to be formed, so as to fabricate pfets. In the stacked structure illustrated in fig. 1A, the Si layer 101 and the SiGe layer 102 may be formed on the surface of a substrate by epitaxial growth, and in the example of fig. 1A, the substrate is Si, and it should be understood by those skilled in the art that the material of the substrate is not limited thereto, but may be other simple substance or compound semiconductor materials, such as Ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb or InP, etc.
To achieve nFET fabrication, siGe layer 102 needs to be selectively etched from the stack structure, as shown in fig. 1B; in order to achieve pFET fabrication, si layer 101 needs to be selectively etched from the stack structure, as shown in fig. 1C. The conventional method in the industry is to selectively remove the SiGe layer 102 by wet etching and selectively remove the Si layer 101 by dry etching, which requires that the wafer be transferred back and forth between different process chambers, severely affecting the throughput, and is limited by the wet etching process, which cannot be adopted in the process of the prior art node.
The inventors of the present invention have realized that these dry etching schemes for selectively removing SiGe layers are very different from the dry etching schemes for selectively removing Si layers, and thus, the wafer needs to be transferred back and forth between different process chambers, which seriously affects the throughput, and reports that a high etching selectivity ratio can not be achieved.
In order to solve the above technical problems, a main concept provided by the embodiments of the present invention is to use the same etching gas as possible to selectively etch the SiGe layer and the Si layer of the stacked structure, so that the selective etching of the SiGe layer and the Si layer can be completed in the same process chamber, the wafer does not need to be transferred back and forth between different process chambers, the productivity is improved, and the etching with high selectivity can be realized at the same time.
First, a technical scheme of selectively etching a SiGe layer from a stacked structure according to an embodiment of the present invention will be described in detail. In this embodiment, the stacked structure is plasma etched using a first etching gas including a fluorine-containing gas and a first auxiliary etching gas. The fluorine-containing gas is used as a main etching gas, and after being excited, fluorine ions and fluorine-containing free radicals are generated to react with the film layer to be etched to realize etching, and the first auxiliary gas is used for adjusting the etching selection ratio between SiGe and Si, so that the selective etching of the SiGe layer is realized.
In some alternative implementations of the present embodiments, the fluorine-containing gas may include a fluorocarbon-based gas, and more particularly may include CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 F, the first auxiliary etching gas comprises at least one of He and Ar.
Fig. 2 shows an electron microscope image obtained after selectively etching a SiGe layer from a stacked structure by using the dry etching method according to the embodiment of the present invention, and in contrast, the inventor of the present invention made an experiment for etching the stacked structure using only fluorine-containing gas, and as a result, the present invention showed that SiGe has a relatively low etching selectivity with respect to Si, and the Si layer was damaged relatively much while the SiGe layer was removed, and since the remaining Si layer was required to be a channel of a GAA-FET, the Si layer damaged relatively much would seriously affect the performance of the GAA-FET. As is clear from fig. 2, by adopting the dry etching method according to the embodiment of the present invention, since the first auxiliary etching gas is further added, the etching selectivity of SiGe to Si can be well improved, and the loss of Si layer is ensured to be smaller while removing the SiGe layer. Meanwhile, the side wall of the SiGe layer with the concave etching is smooth, so that the dry etching method is very suitable for removing the SiGe layer with the preset thickness. In a subsequent GAA-FET fabrication process, the space after the SiGe layer of predetermined thickness is removed may be filled with an insulating layer of silicon oxide or silicon nitride or the like, which may be used to avoid the gate structure of the subsequently formed GAA-FET from conducting with the source or drain region.
The inventor of the present invention found that when the flow ratio of the fluorine-containing gas to the first auxiliary etching gas in the first etching gas is changed, the topography of the etched laminated structure is affected. In some optional implementations of the embodiments of the present invention, when the flow ratio of the fluorine-containing gas to the first auxiliary etching gas ranges from 0.1 to 10, the topography of the stack structure after etching can be further improved.
The inventor of the invention also finds that the pressure of the process chamber can also affect the etching rate and the etched morphology of the laminated structure, and the increase of the pressure of the process chamber can improve the etching rate, but the excessive pressure of the process chamber can cause the etched morphology of the laminated structure to be poor. In some alternative implementations of the embodiments of the invention, the process chamber pressure ranges from 100 to 5000mTorr and the flow of the first etching gas ranges from 10 to 4000sccm.
In some alternative implementations of the embodiments of the invention, the power of the excited plasma ranges from 100 to 3000W and the lower electrode bias power ranges from 0 to 100W, such that the plasma etch is an isotropic etch or a substantially isotropic etch. Wherein the upper electrode rf coil may be used to energize the plasma, or a remote plasma may be used, embodiments of the present invention preferably employ a remote plasma, and more preferably employ a microwave source to energize the plasma.
In some alternative implementations of embodiments of the invention, the temperature of the wafer carrier, such as an electrostatic chuck, is 0 to 100 ℃.
Hereinafter, a technical scheme of selectively etching a Si layer from a stacked structure according to an embodiment of the present invention will be described in detail. In this embodiment, the stacked structure is subjected to plasma etching by using a second etching gas, where the second etching gas includes a fluorine-containing gas and a second auxiliary etching gas, where the fluorine-containing gas used in the technical scheme for selectively etching the Si layer is the same as the fluorine-containing gas used in the technical scheme for selectively etching the SiGe layer. The fluorine-containing gas is used as a main etching gas, fluorine ions and fluorine-containing free radicals are generated after the fluorine-containing gas is excited to react with the film to be etched to realize etching, and the second auxiliary gas is used for adjusting the etching selection ratio between SiGe and Si, so that the selective etching of the Si layer is realized. In this embodiment, since the main etching gas used for selectively etching the SiGe layer and the main etching gas used for selectively etching the Si layer are the same, only the auxiliary etching gas used is different, and thus, the selective etching of the SiGe layer and the Si layer can be completed in the same process chamber, the wafer does not need to be transferred back and forth between different process chambers, and the productivity is improved.
In some alternative implementations of the present embodiments, the fluorine-containing gas may also include fluorocarbon-based gases, and more particularly may include CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 F, the second auxiliary etching gas comprises oxygen element and nitrogen element, more specifically, the second auxiliary etching gas can comprise N 2 、O 2 、NO、NO 2 At least one of (a) and (b).
Fig. 3 shows an electron microscope image obtained after selectively etching a Si layer from a stacked structure by using the dry etching method according to the embodiment of the present invention, and it can be clearly seen from fig. 3 that, by using the dry etching method according to the embodiment of the present invention, since a second auxiliary etching gas is further added, the etching selectivity of Si relative to SiGe can be well improved, and the loss of the SiGe layer can be ensured to be smaller while removing the Si layer. As described above, the residual SiGe layer needs to be used as the channel of the GAA-FET, and the dry etching method according to the embodiment of the present invention can effectively improve the performance of the GAA-FET fabricated later.
The inventors of the present invention found that the oxygen element and the nitrogen element in the second etching gas can well adjust the etching rate and the etching selection ratio of the stacked structure. When the oxygen content in the second etching gas is increased, the etching rates of the SiGe layer and the Si layer are both increased, but the etching selection ratio between Si and SiGe is not changed greatly; and when the nitrogen content in the second etching gas is increased, the etching rate of Si is increased and the etching selectivity of Si relative to SiGe is increased, and when the nitrogen content in the second etching gas is reduced, the etching of Si and SiGe is inhibited and the etching selectivity of Si relative to SiGe is reduced. In some optional implementations of the embodiments of the present invention, the ratio of fluorine element to oxygen element in the second etching gas ranges from 0.1 to 10, and in this range, a faster etching rate and a better etching selectivity can be obtained; the ratio of fluorine element to nitrogen element in the second etching gas ranges from 0.1 to 10, and in the range, the etching selectivity of Si relative to SiGe can be well improved, and the loss of the SiGe layer is ensured to be smaller while the Si layer is removed.
The inventor of the invention also finds that in the technical scheme of selectively etching the Si layer, the pressure of the process chamber also has an influence on the etching rate and the etched morphology of the laminated structure, the etching rate can be improved by increasing the pressure of the process chamber, but the etched morphology of the laminated structure is deteriorated by excessively increasing the pressure of the process chamber. In some alternative implementations of the embodiments of the invention, the process chamber pressure ranges from 100 to 5000mTorr and the flow rate of the second etching gas ranges from 10 to 4000sccm.
In some alternative implementations of the embodiments of the invention, the power of the excited plasma ranges from 100 to 3000W and the lower electrode bias power ranges from 0 to 100W, such that the plasma etch is an isotropic etch or a substantially isotropic etch. Likewise, the upper electrode rf coil may be used to energize the plasma, or a remote plasma may be used, and embodiments of the present invention preferably employ a remote plasma, more preferably a microwave source.
In some alternative implementations of embodiments of the invention, the temperature of the wafer carrier, such as an electrostatic chuck, is 0 to 100 ℃.
Further, before the selective plasma etching is performed on the stacked structure, the dry etching method according to the embodiment of the present invention may further include: and removing the natural oxide layer on the surface of the Si layer or the SiGe layer.
In this embodiment, the natural oxide layer on the surface of the stacked structure may be removed by using a fluorine-containing gas, which may be the same as the fluorine-containing gas used for selectively etching the SiGe layer and selectively etching the Si layer, so that the steps of removing the natural oxide layer, selectively etching the SiGe layer, and selectively etching the Si layer may be completed in the same process chamber, without transferring the wafer back and forth between different process chambers, and improving the throughput.
In some alternative implementations of the present embodiments, the fluorine-containing gas may include a fluorocarbon-based gas, more particularly a CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 At least one of F. Unlike the steps of selectively etching the SiGe layer and selectively etching the Si layer, in the step of removing the natural oxide layer, a lower electrode bias power is applied so that the plasma etching is anisotropic etching.
In some alternative implementations of embodiments of the invention, in the step of removing the native oxide layer, the process chamber pressure is 0 to 2000mTorr, the upper electrode rf power applied is 10 to 2000W, the lower electrode rf bias power is 20 to 2000W, the upper and lower electrode rf frequencies may be, for example, 2MHz, 400KHz, 13.56MHz, 27MHz, etc., the total flow of process gases is 10 to 1000sccm, and the temperature of the wafer carrier, such as an electrostatic chuck, is 0 to 100 ℃.
Correspondingly, the embodiment of the invention also provides a semiconductor process device, and the dry etching method of the embodiment of the invention can be realized by adopting the semiconductor process device shown in fig. 4. As shown in fig. 4, the semiconductor processing apparatus may include a process chamber 210, the process chamber 210 may include a wafer carrier 211 and a perforated partition 212, and the wafer carrier 211 may include, for example, an electrostatic chuck, a vacuum chuck, a mechanical chuck, or the like, for carrying a wafer to be processed. The semiconductor processing equipment may employ an upper electrode rf coil to energize the plasma or a remote plasma. In some alternative implementations of embodiments of the invention, the semiconductor processing apparatus may further comprise a Remote Plasma (RPS) device 220, wherein the remote plasma device 220 is configured to energize the incoming process gas into a plasma. Optionally, the semiconductor processing apparatus may further comprise an rf power source coupled to the wafer carrier 211 for providing an rf bias.
The perforated separator 212 is generally plate-shaped, and two layers of perforated separator are shown in the example of fig. 4, however, the present invention is not limited thereto, and one or more layers of perforated separator may be provided, and as shown in fig. 5, a plurality of through holes are provided in the perforated separator 212, where the number, shape and size of the through holes are not limited, and preferably the through holes are uniformly distributed in the perforated separator 212. The perforated baffle 212 is disposed parallel to the load-bearing surface of the wafer load-bearing device 211 to divide the chamber body of the process chamber into a first region 213 located on the upper side of the process chamber and a second region 214 located on the lower side of the process chamber, the wafer load-bearing device 211 being located within the second region 214, the remote plasma device 220 being in communication with the first region 213. The remote plasma device 220 may be, for example, a microwave source that can excite more radicals to facilitate selective etching.
The plasma generated by the remote plasma device 220 is delivered to the first region 213, where the plasma includes energetic electrons, ions, and radicals. The perforated separator 212 is grounded or a predetermined voltage is applied such that electrons and charged ions are filtered out while passing through the perforated separator 212, and free radicals can pass through the perforated separator 212 to the second region 214 due to no charge, so that the reactive species in the second region 214 are mostly free radicals. Thus, in the dry etching method of the embodiment of the present invention, selective etching of the SiGe layer or selective etching of the Si layer from the stacked structure of alternately stacked Si layers and SiGe layers is mainly achieved using radicals.
In some implementations of the present embodiments, the perforated barrier 212 is multi-layered and at least some of the through holes of the perforated barrier 212 of adjacent layers are not aligned with each other, preferably all of the through holes of the perforated barrier 212 of adjacent layers are not aligned with each other, as shown in fig. 4, such that the process gas cannot pass through the multi-layered perforated barrier 212 in a straight line, lengthening the travel path of the process gas such that more electrons and charged ions are filtered or attenuated to further increase the proportion of radicals in the second region 214. Further, the through holes may be specifically designed, e.g., curved, to extend the travel path of the process gas so that more electrons and charged ions are filtered or attenuated to further increase the proportion of radicals in the second region 214, thereby enabling better selective etching.
The semiconductor process apparatus according to the embodiment of the present invention may further include a control device (not shown), which may be, for example, a lower computer or an upper computer of the semiconductor process apparatus, and the control device may include at least one memory and at least one processor, where the memory stores a computer program, and the processor executes the computer program to implement the dry etching method described above.
In the control device, the processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or a combination thereof.
The memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some alternative embodiments, the memory may also include memory located remotely from the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The memory, as a non-transitory computer readable storage medium, may be used to store a non-transitory software program, a non-transitory computer executable program, and a module, such as program instructions corresponding to a dry etching method in an embodiment of the present invention, for example, control to open a corresponding valve to enable etching gas of a corresponding kind and flow to enter the remote plasma device 220, control the remote plasma device 220 to excite plasma with a predetermined power, control the heater of the wafer carrier 211 to heat to a predetermined temperature, control the pumping device of the process chamber to enable the process chamber to reach a predetermined pressure, and so on. The processor executes the non-transitory program instructions stored in the memory to perform various functional applications of the processor and data processing, i.e., to implement the dry etching method in the method embodiment described above.
The details of the above semiconductor processing apparatus may be correspondingly understood by referring to the corresponding related descriptions and effects in the above-described dry etching method embodiment, which are not repeated herein.
The foregoing embodiments of the present invention mainly describe differences between the embodiments, and as long as there is no contradiction between different optimization features of the embodiments, the embodiments may be combined to form a better embodiment, and in view of brevity of line text, no further description is provided herein.
The foregoing is merely exemplary of the present invention and is not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are to be included in the scope of the claims of the present invention.
Claims (16)
1. A dry etching method for selectively etching a stacked structure including Si layers and SiGe layers alternately stacked, the method comprising:
when selectively etching the SiGe layer from the laminated structure, performing plasma etching on the laminated structure by using a first etching gas, wherein the first etching gas comprises fluorine-containing gas and first auxiliary etching gas;
when selectively etching the Si layer from the laminated structure, performing plasma etching on the laminated structure by using a second etching gas, wherein the second etching gas comprises the fluorine-containing gas and a second auxiliary etching gas; in the step of carrying out plasma etching on the laminated structure by utilizing first etching gas, the pressure of a process chamber is 100-5000 mTorr, the flow range of the first etching gas is 10-4000 sccm, the power range of exciting plasma is 100-3000W, and the temperature of a wafer bearing device is 0-100 ℃;
wherein the first auxiliary etching gas and the second auxiliary etching gas are used for adjusting the etching selection ratio between SiGe and Si, and the first auxiliary etching gas is different from the second auxiliary etching gas;
the first auxiliary etching gas comprises at least one of He and Ar, and the flow ratio of the fluorine-containing gas to the first auxiliary etching gas in the first etching gas is in the range of 0.1 to 10.
2. The dry etching method according to claim 1, wherein the second auxiliary etching gas includes an oxygen element and a nitrogen element.
3. The dry etching method according to claim 2, wherein the fluorine-containing gas comprises a fluorocarbon-based gas.
4. The dry etching method according to claim 3, wherein the fluorocarbon-based gas comprises CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 At least one of F.
5. The dry etching method according to claim 2, wherein the second auxiliary etching gas includes N 2 、O 2 、NO、NO 2 At least one of (a) and (b).
6. The dry etching method according to claim 2, wherein a content ratio of fluorine element to oxygen element in the second etching gas is in a range of 0.1 to 10; or alternatively
The content ratio of fluorine element to nitrogen element is in the range of 0.1 to 10.
7. The dry etching method according to claim 1, wherein in the step of plasma etching the laminated structure with the second etching gas, a process chamber pressure is 100 to 5000mTorr.
8. The dry etching method according to claim 1, wherein in the step of plasma etching the laminated structure with the second etching gas, a flow rate of the second etching gas is in a range of 10 to 4000sccm.
9. The dry etching method according to claim 1, wherein in the step of performing plasma etching on the laminated structure with the first etching gas, the plasma etching is isotropic etching; or alternatively
In the step of performing plasma etching on the laminated structure by using the second etching gas, the plasma etching is isotropic etching.
10. The dry etching method according to any one of claims 1 to 9, characterized in that before the step of plasma etching the laminated structure with the first etching gas or before the step of plasma etching the laminated structure with the second etching gas, the method further comprises:
and removing the natural oxide layer on the surface of the Si layer or the SiGe layer.
11. The dry etching method according to claim 10, wherein the natural oxide layer of the stacked structure is anisotropically plasma etched using the fluorine-containing gas.
12. A semiconductor processing apparatus, comprising:
the wafer carrying device is arranged in the second area, and is used for carrying out the process on the wafer carrying device;
control device comprising at least one memory and at least one processor, said memory having stored therein a computer program, said processor executing said computer program to implement the dry etching method according to any of claims 1 to 11.
13. The semiconductor processing apparatus of claim 12, further comprising:
and the remote plasma device is used for exciting the introduced process gas into plasma and is communicated with the first area.
14. The semiconductor processing apparatus of claim 13, wherein the remote plasma device is a microwave source.
15. The semiconductor processing apparatus of claim 12, wherein the perforated barrier comprises multiple layers and at least some of the perforations of the perforated barrier of adjacent layers are not aligned with each other.
16. The semiconductor processing apparatus of claim 12, wherein the perforated separator is grounded or a predetermined voltage is applied.
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