CN116662063A

CN116662063A - Error correction configuration method, error correction method, system, equipment and medium for flash memory

Info

Publication number: CN116662063A
Application number: CN202310526426.XA
Authority: CN
Inventors: 毛榆钧; 刘弋波; 赖鼐; 龚晖
Original assignee: Zhuhai Miaocun Technology Co ltd
Current assignee: Zhuhai Miaocun Technology Co ltd
Priority date: 2023-05-10
Filing date: 2023-05-10
Publication date: 2023-08-29
Anticipated expiration: 2043-05-10
Also published as: CN116662063B

Abstract

The application provides an error correction configuration method, an error correction system, error correction equipment and a medium of a flash memory, and belongs to the technical field of storage equipment. The method comprises the following steps: acquiring a target storage capacity of a memory in the LDPC module; acquiring the data capacity of initial data which need to be subjected to error correction in a flash memory page corresponding to the LDPC module; dividing the target storage capacity into a plurality of storage units according to the data capacity, wherein the capacity of each storage unit is the same as the data capacity; in the hard solution process, at least two of the storage units are determined to be first storage units for storing data to be corrected after the reading operation, and the rest storage units are determined to be second storage units for storing data to be exported after the hard solution operation is completed. The application saves the reading time of data, and can also carry out the hard solution operation of the next data to be corrected when the hard solution of one data to be corrected is completed, and the hard solution operation can not be executed because the data to be exported is not exported yet, thereby improving the speed of LDPC error correction.

Description

Error correction configuration method, error correction method, system, equipment and medium for flash memory

Technical Field

The present application relates to the field of storage devices, and in particular, to a method, a system, a device, and a medium for error correction configuration of a flash memory.

Background

NAND flash memory is a nonvolatile memory, which is generally used as a main storage medium for mobile devices, digital cameras, solid-state disks, and the like, and is composed of a plurality of physical pages (physical pages), each of which is composed of a plurality of logical pages (logical pages). When using NAND flash memory, hardware failures such as bit errors (bit errors) due to chip degradation and write errors (write disturbs) due to external disturbances (e.g., temperature, voltage variations) often occur, which errors result in data loss or corruption, and thus an error correction mechanism is needed to repair these errors.

In the related art, error correction is often performed by a low density parity check code (Low Density Parity Check Code, LDPC) module, and the error correction includes two aspects, hard decoding (hard decoding) and soft decoding (soft decoding). However, when the page is corrected, the data in the page can be corrected one by one, the next data in the page can be read only after the previous data is subjected to the error correction operation, and the data in the page is read for a long time, so that the speed of LDPC error correction is reduced.

Disclosure of Invention

The embodiment of the application mainly aims to provide an error correction configuration method, an error correction system, error correction equipment and an error correction medium for a flash memory, which can improve the speed of LDPC error correction.

To achieve the above object, a first aspect of an embodiment of the present application provides an error correction configuration method for a flash memory, where the method includes: acquiring a target storage capacity of a memory in the LDPC module; acquiring the data capacity of initial data which need to be subjected to error correction in a flash memory page corresponding to the LDPC module; dividing the target storage capacity into a plurality of storage units according to the data capacity, wherein the capacity of each storage unit is the same as the data capacity; in the hard solution process, determining at least two of the storage units as first storage units for storing data to be corrected after reading operation, and determining the rest of the storage units as second storage units for storing data to be exported after finishing the hard solution operation; the LDPC module converts the read initial data into the data to be corrected in the hard-solution error correction process and stores the data to be corrected in the first storage unit, and the LDPC module stores the data to be exported generated after hard-solution in the second storage unit after hard-solution operation is performed on the data to be corrected.

In some embodiments, the obtaining the target storage capacity of the memory in the LDPC module includes: acquiring the minimum storage capacity required by the LDPC module in the process of executing hard solution operation or soft solution operation; and taking the minimum storage space as a target storage capacity of a memory in the LDPC module.

In some embodiments, the target storage capacity is the minimum storage capacity required by the LDPC module in performing a soft-solution operation, the minimum storage capacity being obtained by: reading initial data of the flash memory page in the soft-decoding operation process to obtain hard data; re-reading the initial data based on the hard data to obtain a plurality of soft data; determining a first data capacity of data to be exported, which is obtained after soft solution operation of the hard data and a plurality of soft data; and determining a second data capacity of the hard data and the soft data in total, and calculating the minimum storage capacity according to the first data capacity and the second data capacity.

In some embodiments, when the target storage capacity is the minimum storage capacity, the method further comprises: in the hard solution process, two of the storage units are determined to be the first storage unit for storing data to be corrected after the reading operation; and determining the rest multiple storage units as the second storage units for storing data to be exported after the hard solution operation is completed.

In some embodiments, if the LDPC module is further used to perform a soft-solution operation, the method further comprises: in the soft solution process, determining one of the storage units as the second storage unit for storing data to be exported after the soft solution operation is completed; determining the rest memory cells as the first memory cells for storing data to be corrected after the reading operation, wherein the data to be corrected in the soft solution process is the hard data and the soft data; the LDPC module converts the read initial data into the data to be corrected in a soft-solution error correction process and stores the data to be corrected in the first storage unit, and the LDPC module sequentially stores the data to be exported generated after soft-solution in the second storage unit after performing soft-solution operation on the data to be corrected.

In order to achieve the above object, a second aspect of the embodiments of the present application provides an error correction method for a flash memory, which is applied to the flash memory, where the flash memory is provided with a flash page and a corresponding LDPC module, and at least two first storage units and a plurality of second storage units are provided in the LDPC module; the method comprises the following steps: reading initial data in the flash memory page to obtain first hard data, and storing the first hard data in one of the first storage units; continuously reading the rest initial data in the flash memory page, obtaining second hard data, and storing the second hard data in another first storage unit; and taking the first hard data and the second hard data as data to be corrected, sequentially performing hard-decoding operation on the data to be corrected, and sequentially storing data to be exported generated after hard-decoding in the second storage unit.

In some embodiments, if the LDPC module is further used for performing a soft-decoding operation, a plurality of the first storage units and one of the second storage units are disposed in the LDPC module, the method includes: reading initial data in the flash memory page and obtaining third hard data; re-reading the initial data based on the third hard data to obtain a plurality of soft data; storing the third hard data and the plurality of soft data in a plurality of corresponding first storage units; and taking the third hard data and the plurality of soft data as data to be corrected, sequentially performing soft decoding operation on the data to be corrected, and storing data to be exported generated after soft decoding in the second storage unit.

To achieve the above object, a third aspect of the embodiments of the present application provides an error correction configuration system for a flash memory, the system including: the target capacity acquisition module is used for acquiring the target storage capacity of the memory in the LDPC module; the data capacity acquisition module of the flash memory page is used for acquiring the data capacity of initial data which needs to be subjected to error correction in the flash memory page corresponding to the LDPC module; a storage capacity dividing module configured to divide the target storage capacity into a plurality of storage units on average according to the data capacity, wherein a capacity of each storage unit is the same as the data capacity; the storage configuration module is used for determining that at least two of the storage units are first storage units for storing data to be corrected after the reading operation in the hard solution process, and determining that the rest of the storage units are second storage units for storing data to be exported after the hard solution operation is completed; the LDPC module takes the read initial data as the data to be corrected in the hard-solution error correction process and stores the data to be exported in the first storage unit, and the LDPC module stores the data to be exported generated after hard-solution operation is performed on the data to be corrected in the second storage unit.

To achieve the above object, a fourth aspect of the embodiments of the present application provides an electronic device, where the electronic device includes a memory and a processor, and the memory stores a computer program, and the processor executes the computer program to implement the method for configuring error correction of a flash memory according to the first aspect of the embodiments of the present application, or the method for correcting error correction of a flash memory according to the second aspect of the embodiments of the present application.

To achieve the above object, a fifth aspect of the embodiments of the present application proposes a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the error correction configuration method of the flash memory according to the first aspect of the embodiments, or the error correction method of the flash memory according to the second aspect of the embodiments.

The error correction configuration method, the error correction method, the system, the equipment and the medium of the flash memory provided by the embodiment of the application can be applied to the error correction configuration system of the flash memory. The method comprises the steps of obtaining target storage capacity of a memory in the LDPC module by executing an error correction configuration method of a flash memory, wherein the target storage capacity is the capacity of a storage device for storing data to be corrected and data to be exported in an error correction process, determining the data capacity of initial data to be corrected, dividing the target storage capacity into a plurality of storage units according to the data capacity, storing one data in each storage unit, configuring each storage unit with the same capacity as the data capacity, determining at least two storage units in the storage units as a first storage unit for storing the data to be corrected in a hard solution process, determining the rest of the storage units as second storage units for storing the data to be exported, and simultaneously reading the two data to be corrected in the error correction process of hard solution, thereby saving the time for reading the data, storing the exported data in a plurality of second storage units once hard solution of a certain item of data to be corrected is completed, and further performing hard solution operation of the next item of data to be corrected, and thus improving the LDPC error correction speed.

Drawings

FIG. 1 is a flow chart of a method for error correction configuration of a flash memory according to an embodiment of the present application;

fig. 2 is a schematic flow chart of step S101 in fig. 1;

FIG. 3 is a flow chart of a minimum storage capacity obtaining process according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating a method for error correction configuration of a flash memory according to another embodiment of the present application;

FIG. 5 is a schematic diagram of a hard solution process provided by an embodiment of the present application;

FIG. 6 is a schematic flow chart of a memory space in a soft solution configuration operation according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a soft solution process provided by an embodiment of the present application;

FIG. 8 is a flowchart illustrating a method for error correction of a flash memory according to an embodiment of the present application;

FIG. 9 is a flowchart illustrating a method for error correction of a flash memory according to another embodiment of the present application;

FIG. 10 is a schematic diagram of a functional module of an error correction configuration system for a flash memory according to an embodiment of the present application;

fig. 11 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.

First, several nouns involved in the present application are parsed:

flash memory products can be classified into four major categories according to the connection modes of the basic storage units of the flash memory. The method comprises the following steps of: NAND flash, NOR flash, DINOR (video Bit-Line NOR) flash, AND flash. The NAND Flash memory is one of Flash memories, and belongs to a nonvolatile semiconductor memory.

NAND flash memory operates with pages (pages) as minimal storage, each page typically containing multiple blocks of data (blocks) and metadata, such as hard data (hard data), for the purpose of ensuring the reliability and integrity of the data. These data are often referred to as "hard" (hard) or "soft" (soft). In low-density parity-check (LDPC) coding, hard decoding (hard decoding) and soft decoding (soft decoding) are two different methods.

The LDPC module is a module that performs error correction, and data stored in an internal memory unit is changed when hard and soft solutions are performed. Specifically, a large amount of matrix operation is needed for both operations, and a large amount of memory space is needed for matrix operation, so that during operation, a part of data needs to be fetched from a storage unit and calculated, and finally the result is written back to the storage unit.

In hard-decoding operations, data is typically accelerated using techniques such as caching to achieve faster decoding speeds. This process may involve reading the data in the flash memory without any modification of the data, and therefore, if the memory cell already contains the data to be read, no change is required. If there is no data to be read in the memory cell, the data needs to be read from the flash memory and written to the memory cell.

In the soft solution operation, since the soft solution needs to be subjected to iterative computation and each iteration needs to read and update the data in the storage unit, the data in the storage unit changes with the progress of the iteration in the process. Specifically, each iteration modifies the data at certain locations in the memory cells to optimize the decoding effect. Thus, during soft solution, the data in the memory cells is constantly changing as the iteration proceeds.

LDPC modules are typically composed of several parts or structures:

and an encoder, the LDPC encoder converting the input data into an LDPC codeword including redundancy check bits. The main function of the Encoder is to space-time shuffle and encode the messages, extracting and reconstructing the original data from the LDPC code in correspondence with the decoder.

Decoder, LDPC decoder is a key part of the module, which can recover the original data from noisy LDPC codeword. The design of the decoder is typically based on an iterative message passing algorithm, such as Beliefpropagation (BP) or its variant sum-product algorithm (SPA).

The controller is mainly responsible for controlling synchronization and timing, directing the operation of the processor at the different stages of decoding and ensuring proper Sequence of processing.

And the storage unit is used for storing a plurality of data such as check matrixes, variable values, marks and the like by the LDPC module by using a large amount of memory. The memory cells should be well organized to efficiently support the decoding operation.

Matrix generator/legacy (Regular/Irregular forms) LDPC codes use numerous, small-connection-point, large-size matrices to guarantee and verify. The ith row and the jth column are formed by connecting one of the b blocks. LDPC decoders also contain up to hundreds or thousands of nodes from which the input data is reconstructed.

In the related art, when hard-decoding and error correction are performed on a page, only data in the page can be subjected to error correction one by one, the next data in the page can be read only after the previous data finishes the error correction operation, and the time for reading the data in the page is longer, so that the speed of LDPC error correction is reduced.

Based on this, the embodiment of the application provides an error correction configuration method, an error correction method, a system, equipment and a medium for a flash memory, which can improve the speed of LDPC error correction.

The embodiment of the application can be applied to NAND flash memories, and can also be applied to other flash memories on the premise of meeting the requirements of the embodiment of the application, and the embodiment is not particularly limited.

The error correction configuration method, the error correction method, the system, the device and the medium of the flash memory provided by the embodiment of the application are specifically described by the following embodiments, and the error correction configuration method of the flash memory in the embodiment of the application is described first.

Fig. 1 is an optional flowchart of a method for error correction configuration of a flash memory according to an embodiment of the present application, where the method in fig. 1 may include, but is not limited to, steps S101 to S104.

Step S101, obtaining a target storage capacity of a memory in an LDPC module;

The error correction configuration method (may be simply referred to as a method) of the flash memory may be applied to the flash memory, or may be applied to a terminal or a server where the flash memory is located, where the terminal or the server may be an error correction configuration system of the flash memory. The terminal can be a smart phone, a tablet computer, a notebook computer, a desktop computer and the like; the server side can be configured as an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, and a cloud server for providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, basic cloud computing services such as big data and artificial intelligent platforms and the like.

The flash memory is provided with an LDPC module, which can correct data, and the structure of the LDPC module is described in the above embodiments, which is not particularly limited herein.

The LDPC module is provided with a memory, where the memory may store data in an error correction process, including read data to be corrected and data to be derived after error correction, and in the embodiment of the present application, the target storage capacity refers to a capacity of the memory for storing the data to be corrected and the data to be derived, and it is understood that other capacity spaces may be further provided in the memory to store data required in the error correction process, where these capacities do not belong to the target storage capacity. For example, the target storage capacity may be 12kb, 24kb, or other size.

Step S102, obtaining the data capacity of initial data which needs to be subjected to error correction in a flash memory page corresponding to the LDPC module;

illustratively, LDPC is used to error-correct any one of the flash memory pages, and when error correction is required, data in the corresponding flash memory page needs to be determined, and "corresponding" refers to that flash memory page needs to be error corrected by using LDPC.

In flash memory pages operating as the minimum storage specification in flash memory, each page typically contains a number of data blocks and metadata as initial data, which may include, for example, hard data (hard data) for the purpose of ensuring the reliability and integrity of the data. These data are often referred to as "hard" (hard) or "soft" (soft), and the initial data in embodiments of the present application are hard data.

After the initial data is acquired, the embodiment of the present application needs to determine the data capacity of the initial data, where the data capacity is the data size of the initial data, for example, the data capacity of one initial data may be 2kb, 4kb, or other sizes.

Step S103, dividing the target storage capacity into a plurality of storage units according to the data capacity, wherein the capacity of each storage unit is the same as the data capacity;

for example, in order to better store data in the error correction process and improve the error correction speed, in the embodiment of the application, the target storage capacity is divided into a plurality of storage units, each storage unit is a specific unit for storing data, the capacity of each storage unit is the same as the data capacity, and further, the capacity of each storage unit is the same as the data size of hard data.

After obtaining a data capacity of one data, in the embodiment of the present application, the target storage capacity is divided into a plurality of storage units according to the data capacity, specifically, the integer part of the obtained value is the number of storage units by dividing the target storage capacity by the data capacity.

For example, if one data size is 4kb and the target storage size is 24kb, then the size of one storage unit obtained after calculation is 4kb, and 6 storage units can be obtained by dividing.

Step S104, in the hard solution process, determining at least two of the storage units as first storage units for storing data to be corrected after the reading operation, and determining the rest storage units as second storage units for storing data to be exported after the hard solution operation is completed;

the LDPC module converts the read initial data into data to be corrected in a hard-solution error correction process, the data to be corrected are stored in the first storage unit, and after hard-solution operation is carried out on the data to be corrected, the LDPC module stores data to be exported, which is generated after hard-solution, in the second storage unit.

For example, after a plurality of memory cells are obtained by partitioning, in the embodiment of the present application, the memory cells may be partitioned during the LDPC hard solution process. In the related art, the LDPC can only read one initial data, hard-decode the initial data, and store the data generated after error correction as data to be derived, so that the data can only be corrected one by one, and after the data to be derived is not derived, the error correction channel is occupied, and the time is spent for reading the data, so that the error correction speed is slow.

Therefore, in the embodiment of the present application, two of the divided storage units are selected as the first storage unit storing the data to be corrected after the reading operation, and the remaining plurality of storage units are used as the second storage unit storing the data to be exported after the hard-reading operation is completed. It should be noted that, there are a plurality of, even more than four, storage units generally calculated, so that in the LDPC module after storage division, there are at least two storage units as the first storage unit, where the read data to be corrected can be stored, and the remaining plurality of storage units as the second storage unit, where the data to be derived is stored.

After error correction configuration is carried out, the LDPC can read two data to be corrected simultaneously in the hard solution process, so that the time for reading the data is saved, the data derived after the error correction is finished can be stored in a plurality of second storage units, and once the hard solution of one data to be corrected is finished, the hard solution operation of the next data to be corrected can be carried out, and the hard solution operation cannot be carried out because the data to be derived is not derived yet, thereby improving the speed of LDPC error correction.

Referring to fig. 2, in some embodiments, step S101 may include steps S201 to S202:

step S201, obtaining the minimum storage capacity required by the LDPC module in the process of executing hard solution operation or soft solution operation;

step S202, the minimum storage space is used as the target storage capacity of the memory in the LDPC module.

By way of example, LDPC modules are provided in many flash memories, so how to better set an error correction mode of LDPC and accomplish fast error correction at lower cost becomes a difficult problem in the industry.

The embodiment of the application can carry out error correction configuration according to the minimum storage capacity required in the hard solution operation or soft solution operation process. Specifically, in the embodiment of the application, the minimum storage capacity required by the LDPC module in the process of executing the hard solution operation or the soft solution operation can be obtained, and the minimum storage space is used as the target storage capacity of the memory in the LDPC module.

For example, if the LDPC only requires a hard solution operation, the selection of the minimum storage capacity according to the hard solution operation may be performed based on the above method. For example, in order to achieve faster reading and error correction speeds, the LDPC memory cells may be configured with two first memory cells and two second memory cells, such that there is at least one data to be error corrected that is read out and in a state waiting for error correction, at least one data to be derived may be placed in the second memory cells first, and there is also one empty data to be error corrected that is stored. However, in this way, two data to be exported must be exported in real time to further increase the error correction speed.

Alternatively, if the LDPC further requires a soft-solution operation, the target storage capacity is set according to the minimum storage capacity required in the soft-solution process.

For example, in general, the LDPC module needs to perform hard-solution and soft-solution operations, and when the hard-solution operation fails to correct, the soft-solution operation is often required to be performed by the LDPC module.

Further, in an embodiment of the present application, the target storage capacity is the minimum storage capacity required by the LDPC module in the process of performing soft-decoding operation, referring to fig. 3, in some embodiments, the minimum storage capacity is obtained by the following steps, which may include steps S301 to S304:

step S301, reading initial data of a flash memory page in a soft-decoding operation process to obtain hard data;

step S302, re-reading initial data based on hard data to obtain a plurality of soft data;

step S303, determining a first data capacity of data to be exported, which is obtained after soft solution operation of hard data and a plurality of soft data;

step S304, determining a second data capacity of the hard data and the soft data, and calculating the minimum storage capacity according to the first data capacity and the second data capacity.

Illustratively, to determine the minimum storage capacity required for the soft solution process, the size of the data that needs to be stored during the soft solution process is determined. Specifically, the application needs to read the initial data of the flash memory page in the soft-decoding operation process to obtain the hard data.

In NAND flash memory, hard decision (hard decision) refers to whether or not a detected voltage is greater than a certain threshold value when one cell is analog-read. Soft decision (soft decision) quantifies this voltage to a value between 0 and 1 to indicate the reliability of the information captured by this read. Therefore, when the LDPC module soft-decodes one page in the NAND flash memory, one hard decision needs to be processed into multiple soft, which may be different according to a specific bayesian soft decision algorithm and actual situations. It can be understood that in the embodiment of the present application, taking an example that one hard decision needs to be processed into four soft decisions, that is, four soft data (soft data) is obtained based on the hard data re-reading the initial data.

In the embodiment of the present application, the first data capacity of the data to be exported, which is obtained after the soft solution operation of the hard data and the plurality of soft data, is determined, and it can be understood that in the soft solution process, the LDPC performs soft solution error correction on the hard data and the plurality of soft data, and obtains a piece of data to be exported, where the data size of the data to be exported is the first data capacity.

In the embodiment of the application, hard data and a plurality of soft data stored in the LDPC module are used as data to be corrected, the data size of the data to be corrected is calculated to be second data capacity, and finally the minimum storage capacity is calculated according to the first data capacity and the second data capacity.

There are various ways to calculate the minimum storage capacity. For example, the minimum storage capacity can be obtained by directly adding the first data capacity and the second data capacity, and only the data stored by soft solution or some necessary data need to be stored in the LDPC; in addition, some of the data for the error correction program that is necessary to be stored may also be counted in the minimum storage capacity, without being particularly limited herein.

For example, if one hard data size is 4kb, 4 parts of soft data, i.e., 16kb, can be obtained, and the first data size is 4kb and the second data size is 20kb, so that the minimum data size is 24kb. Alternatively, if the size of one hard data is 2kb, 4 parts of soft data, i.e., 8kb, can be obtained, and the first data size is 2kb and the second data size is 10kb, so that the minimum data size is calculated to be 12kb.

When the target storage capacity is the minimum storage capacity, referring to fig. 4, in some embodiments, the error correction configuration method of the flash memory may further include steps S401 to S402:

step S401, in the hard solution process, two of the storage units are determined to be the first storage unit for storing the data to be corrected after the reading operation;

In step S402, the remaining plurality of storage units are determined as second storage units storing data to be exported after the hard solution operation is completed.

For example, when the target storage capacity is the minimum storage capacity, a storage space configuration method at the lowest cost and the fastest speed is required. Specifically, if the target storage capacity is the minimum storage capacity, the first storage unit is not set too much in the hard solution process, so that two of the storage units are required to be determined to be the first storage unit for storing the data to be corrected after the reading operation, and the rest of the storage units are required to be the second storage unit for storing the data to be exported after the hard solution operation is completed, thus, the condition that one data to be corrected is in a state waiting for correction during reading is ensured, more data to be exported can be saved, and no memory space is reserved for the data to be exported after the error correction is avoided.

For example, if one hard data size is 4kb, and the minimum storage capacity is 24kb, as shown in fig. 5, 6 storage units will be obtained, where two storage units are the first storage unit 11, the remaining four storage units are the second storage unit 12, and the correlation unit 13 for error correction is disposed in the ldpc module, and when one flash page can store 16kb of data, there are four initial data 10 in the flash page, and the total size is 16kb. In the hard solution, after two initial data 10 are read, the obtained hard data are stored in the first storage unit 11 as data to be corrected, and the data to be derived after the error correction is completed can be stored in any one of the four second storage units 12, and since the initial data 10 at this time also has only 16kb, that is, four data, the initial data 10 can be continuously read through one LDPC error correction module, and four data to be derived after the error correction can be derived at one time. The embodiment of the present application is illustrated with hard data having a size of 4kb, and is not meant to limit the embodiment of the present application.

If one hard data has a size of 2kb, and the minimum storage capacity is 12kb, 6 memory cells will be obtained, two of the memory cells will be the first memory cell, the remaining four will be the second memory cell, and one flash page can store 16kb data, and eight initial data will be stored in the flash page, and the total size will be 16kb. In the hard solution, after two initial data are read, the obtained hard data are stored in the first storage unit as data to be corrected, at this time, the data to be derived after the completion of error correction can be stored in any one of the four second storage units, and since the initial data at this time have 16kb, namely eight data, and only four data to be derived are stored in the second storage units, the data can be derived twice when the initial data are continuously read through one LDPC error correction module, and the error correction of all the data can be completed.

If the LDPC module is further used for performing soft-decoding operation, referring to fig. 6, in some embodiments, the error correction configuration method of the flash memory may further include steps S501 to 502:

step S501, in the soft solution process, determining one of the storage units as a second storage unit for storing data to be exported after the soft solution operation is completed;

Step S502, determining the rest memory cells as the first memory cell for storing the data to be corrected after the reading operation, wherein the data to be corrected in the soft decoding process is hard data and a plurality of soft data;

the LDPC module converts the read initial data into data to be corrected in a soft-solution error correction process, and stores the data in a first storage unit, and after soft-solution operation is performed on the data to be corrected, the LDPC module sequentially stores data to be exported, which is generated after soft-solution, in a second storage unit.

In an exemplary embodiment of the present application, the storage space configuration in the hard solution error correction process is performed according to the minimum storage capacity required in the soft solution process, and if the LDPC module is further used to perform the soft solution operation, the storage space of the LDPC in the soft solution process may be further configured according to the minimum storage capacity.

Specifically, in the LDPC module in the embodiment of the present application, only one part of data needs to be exported in the soft solution process, so that it is determined that one of the storage units is a second storage unit storing data to be exported after completing the soft solution operation, and the remaining plurality of storage units is a first storage unit storing data to be corrected after reading operation, and it is pointed out that the data to be corrected in the soft solution process is hard data and a plurality of soft data.

For example, if one hard data has a size of 4kb, the minimum storage capacity is 24kb, as shown in fig. 7, so that 6 storage units are obtained, one storage unit may be used as the second storage unit 12 in the soft solution process at this time, the second storage unit 12 is 4kb, and the remaining five storage units are used as the first storage units 11 for storing hard data and a plurality of soft data, and total 20kb is obtained, and since the hard data and the plurality of soft data have exactly 20kb, the storage requirement in the soft solution process is satisfied exactly under the minimum storage capacity.

If the size of one hard data is 2kb, the minimum storage capacity is 12kb, so that 6 storage units are obtained, at this time, one storage unit can be used as a second storage unit in the soft solution process, the second storage unit is 2kb, the remaining five storage units are used as first storage units for storing the hard data and a plurality of soft data, and the total is 10kb, and because the hard data and the plurality of soft data are exactly 10kb, the storage requirement in the soft solution process is satisfied under the minimum storage capacity.

According to the error correction configuration method of the flash memory, the storage space of the LDPC module in the hard solution process can be allocated under the condition of meeting the minimum storage capacity required by the soft solution process, so that the error correction speed is higher under the condition of meeting the minimum cost for error correction, and the storage cost of each LDPC can be saved in such a way, so that the cost of the flash memory is reduced.

The embodiment of the application also provides an error correction method of the flash memory, which is applied to the flash memory, wherein the flash memory is provided with a flash memory page and a corresponding LDPC module, and the LDPC module is provided with at least two first storage units and a plurality of second storage units, and fig. 8 is an optional flowchart of the error correction method of the flash memory provided by the embodiment of the application, and the method in fig. 8 can include, but is not limited to, steps S601 to S603.

Step S601, reading initial data in a flash memory page to obtain first hard data, and storing the first hard data in one of the first storage units;

step S602, continuing to read the rest initial data in the flash memory page, obtaining second hard data, and storing the second hard data in another first storage unit;

and step S603, performing hard-decoding operation on the data to be corrected sequentially by taking the first hard data and the second hard data as the data to be corrected, and sequentially storing the data to be exported generated after hard-decoding in the second storage unit.

The error correction method of the flash memory in the embodiment of the present application is applied to the flash memory, and the flash memory can complete the configuration of the storage space through the error correction configuration method of the flash memory in the above embodiment, which is not described herein.

In the process of hard error correction, the embodiment of the application can read the initial data in the flash memory page to obtain the first hard data, store the first hard data in one of the first storage units, take at least two first storage units as an example, and can continuously read the remaining initial data in the flash memory page to obtain the second hard data, and store the second hard data in the other first storage unit. In the embodiment of the application, the first hard data and the second hard data are both hard data, and the first hard data and the second hard data are only hard data obtained by reading two initial data in sequence and represent two hard data stored in two first storage units.

And then, in the process of hard-decoding operation, the embodiment of the application takes the first hard data and the second hard data as data to be corrected, sequentially performs hard-decoding operation on the data to be corrected, and sequentially stores the data to be exported generated after hard-decoding in the second storage unit. The second storage units are multiple at this time, and can store multiple data to be exported.

For example, if one hard data has a size of 4kb in the scheme shown in fig. 5, and the minimum storage capacity is 24kb, as shown in fig. 5, 6 storage units will be obtained, where two are the first storage unit 11, and the remaining four are the second storage unit 12, and one flash page can store 16kb of data, there are four initial data 10 in the flash page, and the total size is 16kb. In the hard solution, after two initial data 10 are read, the obtained hard data are stored in the first storage unit 11 as data to be corrected, and the data to be derived after the error correction is completed can be stored in any one of the four second storage units 12, and since the initial data 10 at this time also has only 16kb, that is, four data, the initial data 10 can be continuously read through one LDPC error correction module, and four data to be derived after the error correction can be derived at one time. The embodiment of the present application is illustrated with hard data having a size of 4kb, and is not meant to limit the embodiment of the present application.

Therefore, when the flash memory obtained after error correction configuration in the above embodiment is subjected to the LDPC hard-decoding process, two data to be error-corrected can be read at the same time, so that the time for reading the data is saved, and the data derived after the error correction is completed can be stored in a plurality of second storage units, so that once the hard-decoding of a certain data to be error-corrected is completed, the hard-decoding operation of the next data to be error-corrected can be performed, and the hard-decoding operation cannot be performed because the data to be derived is not derived yet, thereby improving the speed of LDPC error correction.

If the LDPC module is further used for performing soft-decoding operations, a plurality of first storage units and one second storage unit are disposed in the LDPC module, referring to fig. 9, in some embodiments, the error correction method of the flash memory may further include steps S701 to S704:

step S701, reading initial data in a flash memory page and obtaining third hard data;

step S702, re-reading the initial data based on the third hard data to obtain a plurality of soft data;

step S703, storing the third hard data and the plurality of soft data in a plurality of corresponding first storage units;

in step S704, the third hard data and the plurality of soft data are used as data to be error-corrected, soft-decoding operation is sequentially performed on the data to be error-corrected, and the data to be exported generated after soft-decoding is stored in the second storage unit.

For example, if the LDPC module is further configured to perform a soft-decoding operation, in the embodiment of the present application, initial data in a flash page may be read, and third hard data may be obtained. The third hard data in the embodiment of the application is the same as the first hard data and the second hard data, and the third hard data in the soft solution process is distinguished from the hard data only for expressing the sequence of the hard data, and represents the hard data stored in the first storage unit in the soft solution process.

In the embodiment of the present application, the third hard data re-reads the initial data to obtain a plurality of soft data, so as to realize the conversion of soft decision, and the specific reference may be made to the above embodiment, which is not described herein. After a plurality of soft data are obtained, in the embodiment of the application, the third hard data and the plurality of soft data are stored in a plurality of corresponding first storage units, then the third hard data and the plurality of soft data are used as data to be corrected, soft decoding operation is sequentially carried out on the data to be corrected, and the data to be exported generated after soft decoding is stored in a second storage unit.

Examples of soft solution processes are described in the above embodiments, and are not described here again.

Referring to fig. 10, the embodiment of the present application further provides an error correction configuration system of a flash memory, which can implement the error correction configuration method of a flash memory, where the error correction configuration system of a flash memory includes:

A target capacity acquisition module 1001, configured to acquire a target storage capacity of a memory in the LDPC module;

a flash memory page data capacity obtaining module 1002, configured to obtain a data capacity of initial data that needs to be corrected in a flash memory page corresponding to the LDPC module;

a storage capacity division module 1003 for equally dividing a target storage capacity into a plurality of storage units according to a data capacity, wherein a capacity of each storage unit is the same as the data capacity;

the storage configuration module 1004 is configured to determine that at least two of the storage units are first storage units storing data to be corrected after a read operation, and determine that the remaining plurality of storage units are second storage units storing data to be exported after the hard solution operation is completed;

the LDPC module takes the read initial data as data to be corrected in the hard-solution error correction process and stores the data in a first storage unit, and after hard-solution operation is carried out on the data to be corrected, the LDPC module stores data to be exported, which is generated after hard-solution, in a second storage unit.

For example, the error correction configuration system (may be simply referred to as a system) of the flash memory may be applied to the flash memory, and the error correction configuration method of the flash memory according to any one of the above embodiments may be performed. The system can be a terminal or a server where the flash memory is located, and the terminal or the server can configure the system for error correction of the flash memory. The terminal can be a smart phone, a tablet computer, a notebook computer, a desktop computer and the like; the server side can be configured as an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, and a cloud server for providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, basic cloud computing services such as big data and artificial intelligent platforms and the like.

In flash memory pages operating as the minimum storage specification in flash memory, each page typically contains a number of data blocks and metadata as initial data, which may include, for example, hard data (hec) for the purpose of ensuring the reliability and integrity of the data. These data are often referred to as "hard" (hard) or "soft" (soft), and the initial data in embodiments of the present application are hard data.

The specific implementation of the error correction configuration system of the flash memory is basically the same as the specific embodiment of the error correction configuration method of the flash memory, and will not be described herein. On the premise of meeting the requirements of the embodiment of the application, the error correction configuration system of the flash memory can also be provided with other functional modules so as to realize the error correction configuration method of the flash memory in the embodiment.

The embodiment of the application also provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the error correction configuration method of the flash memory or the error correction method of the flash memory when executing the computer program. The electronic equipment can be any intelligent terminal including a tablet personal computer, a vehicle-mounted computer and the like.

Referring to fig. 11, fig. 11 illustrates a hardware structure of an electronic device according to another embodiment, the electronic device includes:

the processor 1101 may be implemented by a general purpose CPU (central processing unit), a microprocessor, an application specific integrated circuit (ApplicationSpecificIntegratedCircuit, ASIC), or one or more integrated circuits, etc. for executing related programs to implement the technical solution provided by the embodiments of the present application;

The memory 1102 may be implemented in the form of read-only memory (ReadOnlyMemory, ROM), static storage, dynamic storage, or random access memory (RandomAccessMemory, RAM). The memory 1102 may store an operating system and other application programs, and when the technical solution provided in the embodiments of the present disclosure is implemented by software or firmware, relevant program codes are stored in the memory 1102, and the processor 1101 invokes an error correction configuration method for executing the flash memory or an error correction method for the flash memory according to the embodiments of the present disclosure;

an input/output interface 1103 for implementing information input and output;

the communication interface 1104 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (e.g. USB, network cable, etc.), or may implement communication in a wireless manner (e.g. mobile network, WIFI, bluetooth, etc.);

bus 1105 transmits information between the various components of the device (e.g., processor 1101, memory 1102, input/output interface 1103, and communication interface 1104);

wherein the processor 1101, memory 1102, input/output interface 1103 and communication interface 1104 enable communication connection therebetween within the device via bus 1105.

The embodiment of the application also provides a computer readable storage medium, which stores a computer program, and the computer program realizes the error correction configuration method of the flash memory or the error correction method of the flash memory when being executed by a processor.

The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The embodiments described in the embodiments of the present application are for more clearly describing the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application, and those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

It will be appreciated by persons skilled in the art that the embodiments of the application are not limited by the illustrations, and that more or fewer steps than those shown may be included, or certain steps may be combined, or different steps may be included.

The above described apparatus embodiments are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Those of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.

The terms "first," "second," "third," "fourth," and the like in the description of the application and in the above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

In the several embodiments provided by the present application, it should be understood that the disclosed systems and methods may be implemented in other ways. For example, the system embodiments described above are merely illustrative, e.g., the division of the above elements is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including multiple instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing a program.

The preferred embodiments of the present application have been described above with reference to the accompanying drawings, and are not thereby limiting the scope of the claims of the embodiments of the present application. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and spirit of the embodiments of the present application shall fall within the scope of the claims of the embodiments of the present application.

Claims

1. An error correction configuration method for a flash memory, the method comprising:

acquiring a target storage capacity of a memory in the LDPC module;

acquiring the data capacity of initial data which need to be subjected to error correction in a flash memory page corresponding to the LDPC module;

dividing the target storage capacity into a plurality of storage units according to the data capacity, wherein the capacity of each storage unit is the same as the data capacity;

in the hard solution process, determining at least two of the storage units as first storage units for storing data to be corrected after reading operation, and determining the rest of the storage units as second storage units for storing data to be exported after finishing the hard solution operation;

the LDPC module converts the read initial data into the data to be corrected in the hard-solution error correction process and stores the data to be corrected in the first storage unit, and the LDPC module stores the data to be exported generated after hard-solution in the second storage unit after hard-solution operation is performed on the data to be corrected.

2. The method for error correction configuration of flash memory according to claim 1, wherein the obtaining the target storage capacity of the memory in the LDPC module comprises:

acquiring the minimum storage capacity required by the LDPC module in the process of executing hard solution operation or soft solution operation;

and taking the minimum storage space as a target storage capacity of a memory in the LDPC module.

3. The error correction configuration method of a flash memory according to claim 2, wherein the target storage capacity is the minimum storage capacity required by the LDPC module in performing a soft-decoding operation, the minimum storage capacity being obtained by:

reading initial data of the flash memory page in the soft-decoding operation process to obtain hard data;

re-reading the initial data based on the hard data to obtain a plurality of soft data;

determining a first data capacity of data to be exported, which is obtained after soft solution operation of the hard data and a plurality of soft data;

and determining a second data capacity of the hard data and the soft data in total, and calculating the minimum storage capacity according to the first data capacity and the second data capacity.

4. A method of error correction configuration of a flash memory according to claim 2 or 3, wherein when the target storage capacity is the minimum storage capacity, the method further comprises:

In the hard solution process, two of the storage units are determined to be the first storage unit for storing data to be corrected after the reading operation;

and determining the rest multiple storage units as the second storage units for storing data to be exported after the hard solution operation is completed.

5. The error correction configuration method of a flash memory according to claim 3, wherein if the LDPC module is further used for performing a soft-decoding operation, the method further comprises:

in the soft solution process, determining one of the storage units as the second storage unit for storing data to be exported after the soft solution operation is completed;

determining the rest memory cells as the first memory cells for storing data to be corrected after the reading operation, wherein the data to be corrected in the soft solution process is the hard data and the soft data;

the LDPC module converts the read initial data into the data to be corrected in a soft-solution error correction process and stores the data to be corrected in the first storage unit, and the LDPC module sequentially stores the data to be exported generated after soft-solution in the second storage unit after performing soft-solution operation on the data to be corrected.

6. The error correction method of the flash memory is characterized by being applied to the flash memory, wherein the flash memory is provided with a flash memory page and a corresponding LDPC module, and at least two first storage units and a plurality of second storage units are arranged in the LDPC module;

the method comprises the following steps:

reading initial data in the flash memory page to obtain first hard data, and storing the first hard data in one of the first storage units;

continuously reading the rest initial data in the flash memory page, obtaining second hard data, and storing the second hard data in another first storage unit;

and taking the first hard data and the second hard data as data to be corrected, sequentially performing hard-decoding operation on the data to be corrected, and sequentially storing data to be exported generated after hard-decoding in the second storage unit.

7. The error correction method of a flash memory according to claim 6, wherein if the LDPC module is further used for performing a soft-decoding operation, a plurality of the first storage units and one of the second storage units are provided in the LDPC module, the method comprising:

reading initial data in the flash memory page and obtaining third hard data;

Re-reading the initial data based on the third hard data to obtain a plurality of soft data;

storing the third hard data and the plurality of soft data in a plurality of corresponding first storage units;

and taking the third hard data and the plurality of soft data as data to be corrected, sequentially performing soft decoding operation on the data to be corrected, and storing data to be exported generated after soft decoding in the second storage unit.

8. An error correction configuration system for a flash memory, the system comprising:

the target capacity acquisition module is used for acquiring the target storage capacity of the memory in the LDPC module;

the data capacity acquisition module of the flash memory page is used for acquiring the data capacity of initial data which needs to be subjected to error correction in the flash memory page corresponding to the LDPC module;

a storage capacity dividing module configured to divide the target storage capacity into a plurality of storage units on average according to the data capacity, wherein a capacity of each storage unit is the same as the data capacity;

the storage configuration module is used for determining that at least two of the storage units are first storage units for storing data to be corrected after the reading operation in the hard solution process, and determining that the rest of the storage units are second storage units for storing data to be exported after the hard solution operation is completed;

The LDPC module takes the read initial data as the data to be corrected in the hard-solution error correction process and stores the data to be exported in the first storage unit, and the LDPC module stores the data to be exported generated after hard-solution operation is performed on the data to be corrected in the second storage unit.

9. An electronic device comprising a memory storing a computer program and a processor implementing the error correction configuration method of a flash memory according to any one of claims 1 to 5 or the error correction method of a flash memory according to any one of claims 6 to 7 when the computer program is executed.

10. A computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the error correction configuration method of a flash memory according to any one of claims 1 to 5 or the error correction method of a flash memory according to any one of claims 6 to 7.