CN116666345A - Semiconductor package structure and method for forming the same - Google Patents

Abstract

An embodiment of the present invention provides a semiconductor package structure, including: a first substrate, including an upper surface and a lower surface opposite to the upper surface, the upper surface has a plurality of solder pads; The edge of the substrate extends to the upper surface and covers part of the plurality of pads; a plurality of openings pass through the molding layer to respectively expose part of the pads. On the other hand, the embodiments of the present invention also provide a method for forming a semiconductor package structure.

Description

Semiconductor package structure and method for forming the same

technical field

The present invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure and a forming method thereof.

Background technique

FIG. 1 is a schematic diagram of a semiconductor package structure of a current System In a Package (SIP). Referring to FIG. 1, in the system-in-package process, the mounting process of the substrate 10 on the substrate 20 is usually completed first, and then the surface mount technology (surface mount technology, SMT) process is performed to mount the chip, so as to It solves the problem that the substrate 10 and 20 cannot be installed due to the excessive tolerance of the overall packaging structure brought about by the surface SMT process first. Wherein, before the mounting process of the substrate 10 and the substrate 20 , a molding process is performed to form a molding layer 30 encapsulating components between the substrate 10 and the substrate 20 .

However, since the substrate 10 is subjected to a cutting process (such as laser cutting, laser) before the molding process, in order to ensure the cutting process, it is necessary to avoid the copper layer in the central area of the substrate 10, and the cutting substrate 10 is far away from the surface 18 of the substrate 20 The peripheral area of the substrate 10 will cause the depression 15 to be formed in the peripheral area of the surface 18 of the substrate 10 . Due to the existence of the recess 15 , during the molding process of the molding layer 30 , there may be a problem of bleeding of the molding layer 30 extending toward the recess 15 . And further, the molding layer 30 that overflows onto the surface 18 of the substrate 10 will cover the pads (pad) 12 on the surface 18 (as shown in the partially enlarged view in FIG. 12 bonding solder balls (solder ball) or SMT process.

The molding film 40 used during the molding process will not be effective for protecting the pads 12, resulting in a yield loss of about 30%-70% in the final package structure. If the recess 15 is filled by means of glue material filling, etc., there is a problem that it is difficult to control the thickness of the glue material.

At present, for example, laser can be used to remove all the overflow molding layer 30 on the surface 18 of the substrate 10, but this method will damage the surface 18 of the substrate 10, such as destroying the solder mask (solder mask) as the outermost layer of the substrate 10. . Moreover, peeling of the solder resist layer will be caused in the subsequent water washing process.

Contents of the invention

In view of the problems existing in the related art, the object of the present invention is to provide a semiconductor packaging structure and its forming method, which can improve the yield loss and avoid damage to the solder resist layer of the substrate.

To achieve the above object, the present invention provides a semiconductor package structure, comprising: a first substrate including an upper surface and a lower surface opposite to the upper surface, the upper surface has a plurality of solder pads; a molding layer located on On the lower surface, extending through the edge of the first substrate to the upper surface, and covering part of the pads in the plurality of pads; a plurality of openings, passing through the molding layer to respectively expose the part pad.

In some embodiments, the width of the opening is smaller than the width of the corresponding pad.

In some embodiments, the upper surface of the first substrate has a solder resist layer, and the opening is located in the solder resist layer.

In some embodiments, the plurality of openings have different depths.

In some embodiments, a first opening of the plurality of openings is closer to the edge of the first substrate than a second opening of the plurality of openings, wherein the first opening is deeper than the second opening. The depth of the second opening is deeper.

In some embodiments, it further includes: a second substrate located below the first substrate and opposite to the first substrate, and the edge of the first substrate is retracted relative to the edge of the second substrate.

In some embodiments, the molding layer on the upper surface of the first substrate has an uneven surface, wherein, in the direction from the edge of the first substrate to away from the edge, the molding layer The thickness of the seal layer gradually decreases.

The present invention also provides a method for forming a semiconductor package structure, comprising: providing a second substrate and mounting a first substrate on the second substrate, wherein the edge of the first substrate is relatively opposite to the edge of the second substrate. The edge is retracted; a molding layer is formed between the first substrate and the second substrate, wherein the upper surface of the first substrate includes a plurality of solder pads, and the molding layer passes through the first substrate The edge of the plurality of pads extends to cover some of the pads; using a laser drilling process to form holes in the molding layer on the upper surface of the first substrate that respectively expose the part of the pads Multiple openings.

In some embodiments, the method further includes: forming a plurality of solder balls respectively connected to the pads through the openings.

In some embodiments, the method further includes: bonding a chip on the lower surface of the second substrate.

In the above technical solution, by providing openings in the molding layer on the upper surface of the first substrate to expose the pads covered by the molding layer, the connection between each pad on the upper surface and subsequent solder balls or chips can be ensured. Electrical connection, so the semiconductor package structure can have lower yield loss. Furthermore, by providing openings in the molding layer, it is not necessary to remove all of the molding layer on the upper surface, thereby avoiding the removal of the entire molding layer which would result in damage to the upper surface of the first substrate.

Description of drawings

Aspects of the present invention are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a schematic diagram of a semiconductor package structure of an existing system-in-package.

FIG. 2 is a schematic diagram of a semiconductor package structure provided according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of the structure of region A in FIG. 2 according to an embodiment of the semiconductor package structure of the present invention.

FIG. 4 is a schematic structural diagram of region A in FIG. 2 according to another embodiment of the semiconductor package structure of the present invention.

5a to 5e show various steps in the method of forming the semiconductor package structure.

Detailed ways

In order to better understand the spirit of the embodiments of the present application, it will be further described below in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification of the present application, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative, diagrammatic and are used to provide a basic understanding of the application. The examples of the present application should not be construed as limiting the present application. For ease of description, "first", "second", etc. may be used herein to distinguish different components in a figure or series of figures. "First", "second", etc. are not intended to describe corresponding components.

FIG. 2 is a schematic diagram of a semiconductor package structure 1000 provided according to an embodiment of the present invention. As shown in FIG. 2 , the semiconductor package structure 1000 includes a first substrate 100 , and the first substrate 100 includes an upper surface 110 and a lower surface 120 opposite to the upper surface 110 . A molding layer 300 is disposed on the lower surface 120 of the first substrate 100 , and the molding layer 300 can be used to encapsulate the electronic components 255 bonded on the lower surface 120 . The electronic component 255 can be a passive component, such as a capacitor, a resistor, etc., and the electronic component 255 can also be various suitable types of electronic components such as an active component.

The molding layer 300 can extend to the upper surface 110 of the first substrate 100 through the edge (ie, the sidewall) of the first substrate 100 . As shown in FIG. 2 , the molding layer 300 extends to the peripheral area of the upper surface 110 but not to the central area of the upper surface 110 . The upper surface 110 of the first substrate 100 has a plurality of pads 112a, 112b. Wherein, the molding layer 300 extending to the upper surface 110 may cover part of the pads 112a located in the peripheral area of the upper surface 110, while part of the pads 112b located in the central area of the upper surface 110 are not covered.

A plurality of openings 400 corresponding to the plurality of pads 112 a may be disposed in the molding layer 300 on the upper surface 110 , so as to expose the pads 112 a covered by the molding layer 300 through openings 400 .

In the above-mentioned semiconductor package structure 1000, by setting the opening 400 in the molding layer 300 on the upper surface 110 of the first substrate 100 to expose the pads 112a covered by the molding layer 300, it can be ensured that each on the upper surface 110 The pads 112a, 112b are electrically connected to subsequent components (such as solder balls and chips), so the semiconductor package structure 1000 can have lower yield loss, for example, the yield loss can be improved from 40% to 0%. In addition, by providing the opening 400 in the molding layer 300, it is not necessary to remove all the molding layer 300 on the upper surface 110, thereby avoiding damage to the first substrate 100 caused by removing the entire molding layer 300. upper surface 110 .

In addition, since the molding layer 300 has a structure extending from the lower surface 120 of the substrate 100 along the edge of the substrate 100 to the upper surface 110, the molding layer 300 of this structure can play a locking role on the first substrate 100. , so as to reduce delamination of the semiconductor package structure 1000 .

Continuing to refer to FIG. 2 , the semiconductor package structure 1000 further includes a second substrate 200 . The second substrate 200 is located below the first substrate 100 and is opposite to the first substrate 100 . The first substrate 100 and the second substrate 200 are bonded to each other with solder balls 500 disposed therebetween. The edge of the first substrate 100 is retracted relative to the edge of the second substrate 200 . That is, the width of the first substrate 100 is smaller than that of the second substrate 200 , and the edge of the second substrate 200 exceeds the edge of the first substrate 100 . The molding layer 300 is filled between the first substrate 100 and the second substrate 200 . And the edge of the molding layer 300 may be vertically aligned with the edge of the second substrate 200 .

It should be understood that FIG. 2 schematically shows that the top surface of the molding layer 300 on the upper surface 110 is flat, but since the molding layer 300 at the upper surface 110 overflows from the edge of the first substrate 100 to the center region , the top surface of the molding layer 300 on the upper surface 110 may be uneven. The top surface of the molding layer 300 may gradually decrease from the peripheral area to the central area. In some embodiments, in the peripheral region adjacent to the edge of the first substrate 100 (such as between each edge of the first substrate 100 and the corresponding pad 112a adjacent to the edge), the upper surface 110 may have a recess, and the mold The sealing layer 300 may extend to cover the pad 112a through the recess.

FIG. 3 is a schematic structural diagram of region A in FIG. 2 according to an embodiment of the semiconductor package structure of the present invention. Referring to FIG. 3 , there is shown a solder resist layer 150 as the uppermost layer of the first substrate 100 (shown in FIG. 2 ), and the upper surface of the solder resist layer 150 serves as the upper surface 110 of the first substrate 100 . The pad 112 a is embedded in the solder resist layer 150 . The upper surface of the pad 112 a is lower than the upper surface 110 . In addition, solder balls 600 bonded to pads 112a are shown in FIG. 3 . Solder balls 600 are bonded to pads 112 a through openings 400 in molding layer 300 . The lower portion of the solder ball 600 is located in the opening 400 of the molding layer 300 . The upper portion of the solder ball 600 is located outside the opening 400 and may have a curved surface. Since the molding layer 300 has good heat dissipation performance, the molding layer 300 located on the upper surface 110 can help the solder balls 600 to dissipate heat.

Part of the upper surface of the pad 112 a is exposed by the solder resist layer 150 . The width of the pad 112a is W1, the width of the part of the pad 112a exposed by the solder resist layer 150 is W2, and the width of the opening 400 is W3. In the embodiment shown in FIG. 3, width W2 is smaller than width W1. The width W3 of the opening 400 is smaller than the width W1 of the pad 112 a , and the width W3 of the opening 400 is smaller than the width W2 of the pad 112 a exposed by the solder resist layer 150 .

In some embodiments, the width W3 of the opening 400 is smaller than the width W2, so the portion of the upper surface of the pad 112a adjacent to the solder resist layer 150 is reserved, so that the solder ball 600 and the solder resist layer 150 are separated by the molding layer 300 open. The solder ball 600 is not in contact with the solder resist layer 150 .

Since in the aspect shown in FIG. 3 , the molding layer 300 on the upper surface 110 has an uneven surface, the thickness of the molding layer 300 at different positions on the upper surface 110 is different. Specifically, in the direction from the peripheral region to the central region of the upper surface 110 , the thickness of the molding layer 300 gradually decreases. In some embodiments, the maximum thickness of the molding layer 300 on the upper surface 110 (the maximum distance from the surface of the molding layer 300 to the upper surface 110 ) may be about 30 μm. In some embodiments, the height of solder ball 600 may be approximately 400 μm. Since the height of the solder ball 600 is much greater than the maximum thickness of the molding layer 300 , the remaining molding layer 300 will not affect the bonding of the solder ball 600 to the pad 112 a.

FIG. 4 is a schematic structural diagram of region A in FIG. 2 according to another embodiment of the semiconductor package structure of the present invention. In the embodiment shown in FIG. 4 , the width W3 of the opening 400 is greater than the width W2 of the pad 112 a exposed by the solder resist layer 150 , and the width W3 of the opening 400 is greater than the width W1 of the corresponding pad 112 a. The opening 400 extends into the solder resist layer 150 . Part of the surface of the pad 112 a exposed by the solder resist layer 150 is in contact with the solder ball 600 . And the opening 400 exposes part of the upper surface 110 , so the part of the upper surface 110 adjacent to the solder ball 600 exposed by the opening 400 is also in contact with the solder ball 600 .

In some embodiments, the opening 400 may be formed by a laser drilling process. Because the laser has the characteristic of shift (shift)<25μm, it is easier to control when opening the opening, and the size and position of the opening are more accurate. Moreover, in such an embodiment, the opening 400 is formed by a laser drilling process, which can avoid unnecessary damage to the solder resist layer 150 due to excessive displacement when forming the opening 400 .

Although shown in FIGS. 2 , 3 and 4 in the direction from the edge to the central area of the first substrate 100 , the molding layer 300 on the upper surface 110 covers only one pad 112a at each opposite edge. But in other embodiments, the molding layer 300 on the upper surface 110 may cover a plurality of pads 112a at each edge. And in the embodiment covering a plurality of solder pads 112a at each edge, since the thickness of the molding layer 300 on the upper surface 110 gradually decreases from the edge to the central area of the first substrate 100, each The plurality of openings 400 covered at each edge have different depths H. If a first opening of the plurality of openings 400 is closer to the corresponding edge of the first substrate 100 than a second opening of the plurality of openings 400, the depth of the first opening is greater than the depth of the second opening. Deeper. In the embodiment shown in FIGS. 3 and 4 , the depth H of the opening 400 is the distance from the top of the thicker molding layer 300 around the opening 400 to the surface of the pad 112 a.

The invention also provides a method for forming a semiconductor packaging structure. 5a to 5e show schematic diagrams at various steps in the method for forming a semiconductor package structure according to an embodiment of the present invention.

Referring to FIG. 5a, a first substrate 100 and a second substrate 200 are provided. The first substrate 100 is disposed over the upper surface 210 of the second substrate 200 . The first substrate 100 has an upper surface 110 and a lower surface 120 facing each other. The lower surface 120 of the first substrate 100 is opposite to the upper surface 210 of the second substrate 200 . Solder balls 500 and a plurality of electronic components 255 are disposed on the lower surface 120 of the first substrate 100 . A plurality of pads 112 are disposed on the upper surface 110 of the first substrate 100 . A plurality of welding pads 223 are disposed on the upper surface 210 of the second substrate 200 , and a plurality of welding pads 224 are disposed on the lower surface 220 of the second substrate 200 .

The edge of the first substrate 100 is retracted relative to the edge of the second substrate 200 . Solder 250 is disposed on the pad 223 of the upper surface 210 of the second substrate 200 , and the solder ball 500 of the first substrate 100 can be connected to the pad 223 of the second substrate 200 through the solder 250 of the second substrate 200 .

Referring to FIG. 5 b , after the first substrate 100 and the second substrate 200 are bonded by solder balls 500 , a molding layer 300 is formed between the first substrate 100 and the second substrate 200 using, for example, a molding process. The molding layer 300 encapsulates the electronic components 255 and the solder balls 500 between the first substrate 100 and the second substrate 200 .

In some embodiments, the molding layer 300 extends upward along the edge of the first substrate 100 onto the upper surface 110 of the first substrate 100 , and covers a portion of the plurality of pads 112 adjacent to the edge of the first substrate 100 . Disc 112a. Another part of the pads 112 b among the plurality of pads 112 is exposed by the molding layer 300 . In some embodiments, since the molding layer 300 on the upper surface 110 overflows from the edge of the first substrate 100 to the central area, the molding layer 300 on the upper surface 110 has an uneven surface. Moreover, the molding layer 300 has a thicker thickness near the edge of the first substrate 100 and a thinner thickness away from the edge.

In some embodiments, before the molding layer 300 is formed, a cutting process may be performed on the upper surface 110 of the first substrate 100 . In such an embodiment, the dicing process forms a recess in the upper surface 110 adjacent the edge of the first substrate 100 (eg, between each edge of the first substrate 100 and a corresponding pad 112a adjacent the edge), and The molding layer 300 may extend to cover the pad 112a through the recess.

Referring to FIG. 5 c , a plurality of openings 400 are formed in the molding layer 300 on the upper surface 110 of the first substrate 100 by using, for example, a laser drilling process. The plurality of openings 400 respectively expose the pads 112 a covered by the molding layer 300 . In some embodiments, the width of the opening 400 may be smaller than the width of the pad 112a. Because the laser has a shift (shift) that can reach less than 25 μm, it is easier to control when opening the opening, and the size and position of the opening are more accurate, and it can avoid excessive displacement when opening the opening 400, which will affect the upper surface of the first substrate 100. 110 causing unnecessary damage. In some embodiments, the width of the opening 400 is also greater than the width of the pad 112a. In some embodiments, the uppermost layer of the first substrate 100 is a solder resist layer, and the upper surface of the solder resist layer can serve as the upper surface 110 of the first substrate 100 . The pads 112 b not covered by the molding layer 300 are exposed by the upper surface 110 .

It should be understood that although the example shown in FIG. 5 c shows that the molding layer 300 only covers one pad 112 a at each edge of the first substrate 100 . But in other embodiments, the molding layer 300 may cover multiple pads 112a at each edge. And in the embodiment covering multiple solder pads 112a at each edge, in the direction extending from the edge of the first substrate 100 to the central area, the thickness of the molding layer 300 on the upper surface 110 gradually decreases, and every The plurality of openings 400 covered at each edge have different depths. If the first opening of the plurality of openings 400 is closer to the corresponding edge of the first substrate 100 than the second opening of the plurality of openings, the depth of the first opening is deeper than the depth of the second opening. .

Referring to FIG. 5d, corresponding solder balls 600 are respectively formed on each solder pad 112a, 112b. Wherein, the solder ball 600 corresponding to the pad 112a is connected to the pad 112a through the opening 400 (see FIG. 5c ) of the molding layer 300 .

Referring to FIG. 5e, the structure obtained in FIG. 5d is reversed to obtain the structure shown in FIG. 5e. In FIG. 5e, the lower surface 220 of the second substrate 200 faces upward. Then, the chip 700 is bonded on the pad 224 on the lower surface 220 of the second substrate 200 to obtain the final semiconductor package structure. The number of chips 700 in this embodiment is two. In other embodiments, the number of chips 700 may be other numbers.

In the above-mentioned method for forming a semiconductor package structure, an opening 400 is formed in the molding layer 300 at the upper surface 110 of the first substrate 100 by using a laser drilling process, and the opening 400 is formed by using a laser drilling process, thereby exposing the 300 covers the soldering pad 112a, so it does not affect the subsequent setting of the solder ball 600, and also avoids damage to the solder resist layer 150, thereby avoiding the problem of the solder resist layer 150 falling off.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A semiconductor package structure, comprising:

a first substrate including an upper surface and a lower surface opposite the upper surface, the upper surface having a plurality of pads;

a mold seal layer located on the lower surface, extending onto the upper surface through an edge of the first substrate, and covering a portion of the plurality of pads;

and a plurality of openings passing through the mold seal layer to expose the partial pads, respectively.

2. The semiconductor package according to claim 1, wherein,

the width of the opening is smaller than the width of the corresponding bonding pad.

3. The semiconductor package according to claim 1, wherein,

the upper surface of the first substrate is provided with a solder mask layer, and the opening is positioned in the solder mask layer.

4. The semiconductor package according to claim 1, wherein,

the plurality of openings have different depths.

5. The semiconductor package according to claim 4, wherein,

a first opening of the plurality of openings is closer to an edge of the first substrate than a second opening of the plurality of openings, wherein a depth of the first opening is deeper than a depth of the second opening.

6. The semiconductor package according to claim 1, further comprising:

a second substrate positioned below the first substrate and opposite to the first substrate,

the edge of the first substrate is retracted relative to the edge of the second substrate.

7. The semiconductor package according to claim 11, wherein,

the mold seal layer on the upper surface of the first substrate has an uneven surface, wherein the thickness of the mold seal layer gradually decreases in a direction from an edge of the first substrate to a distance from the edge.

8. A method of forming a semiconductor package, comprising:

providing a second substrate and mounting a first substrate on the second substrate, wherein the edge of the first substrate is retracted relative to the edge of the second substrate;

forming a mold seal layer between the first substrate and the second substrate, wherein an upper surface of the first substrate includes a plurality of pads, the mold seal layer extending past an edge of the first substrate to cover a portion of the plurality of pads;

a plurality of openings respectively exposing the partial pads are formed in the mold seal layer on the upper surface of the first substrate using a laser opening process.

9. The method of forming a semiconductor package according to claim 8, further comprising:

a plurality of solder balls connected to the pads through the openings, respectively, are formed.

10. The method of forming a semiconductor package according to claim 8, further comprising:

and bonding a chip on the lower surface of the second substrate.