CN116505886A

CN116505886A - Voltage ripple reduction in power management circuits

Info

Publication number: CN116505886A
Application number: CN202310044807.4A
Authority: CN
Inventors: M·R·卡伊; N·卡拉特
Original assignee: Qorvo US Inc
Current assignee: Qorvo US Inc
Priority date: 2022-01-27
Filing date: 2023-01-30
Publication date: 2023-07-28

Abstract

Voltage ripple reduction in power management circuits is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a Radio Frequency (RF) signal based on a modulation voltage and an Envelope Tracking Integrated Circuit (ETIC) configured to provide the modulation voltage to the power amplifier circuit via a conductive path. Notably, the output impedance presented at the input of the power amplifier circuit may interact with the modulated load current in the power amplifier circuit to produce voltage fluctuations in the modulated voltage, potentially causing undesirable errors in the RF signal. Here, the ETIC is configured to modify the modulation voltage based on feedback of the voltage fluctuations in the modulation voltage. Thus, it is possible to reduce the output impedance at the input of the power amplifier circuit, thereby reducing the voltage ripple in the modulated voltage.

Description

Voltage ripple reduction in power management circuits

RELATED APPLICATIONS

The present application claims the benefit of U.S. provisional patent application Ser. No. 63/303,532 filed on 1 month 27 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The technology of the present disclosure relates generally to reducing voltage fluctuations of a modulation voltage in a power management circuit.

Background

The fifth generation (5G) New Radio (NR) (5G-NR) is widely recognized as the next generation wireless communication technology beyond the current third generation (3G) and fourth generation (4G) technologies. In this regard, wireless communication devices capable of supporting 5G-NR wireless communication techniques are expected to achieve higher data rates, improved coverage, enhanced signaling efficiency, and reduced latency.

Downlink and uplink transmissions in 5G-NR systems are widely based on Orthogonal Frequency Division Multiplexing (OFDM) techniques. In an OFDM-based system, the physical radio resources are divided into a plurality of subcarriers in the frequency domain and a plurality of OFDM symbols in the time domain. The subcarriers are separated orthogonally from each other by a subcarrier spacing (SCS). The OFDM symbols are separated by a Cyclic Prefix (CP), which acts as a guard band to help overcome inter-symbol interference (ISI) between OFDM symbols.

Radio Frequency (RF) signals transmitted in OFDM-based systems are typically modulated into a plurality of subcarriers in the frequency domain and a plurality of OFDM symbols in the time domain. The plurality of subcarriers occupied by the RF signal collectively define a modulation bandwidth of the RF signal. In another aspect, the plurality of OFDM symbols define a plurality of time intervals during which the RF signal is transmitted. In 5G-NR systems, the RF signal is typically modulated with a high modulation bandwidth exceeding 200MHz (e.g., 1 GHz).

The duration of the OFDM symbol depends on the SCS and the modulation bandwidth. The following table (table 1) provides some OFDM symbol durations defined by the 3G partnership project (3 GPP) standards for various SCS and modulation bandwidths. Notably, the higher the modulation bandwidth, the shorter the OFDM symbol duration will be. For example, when SCS is 120KHz and the modulation bandwidth is 400MHz, the OFDM symbol duration is 8.93 μs.

TABLE 1

Notably, wireless communication devices rely on battery cells (e.g., li-ion batteries) to power their operation and services. Despite recent advances in battery technology, wireless communication devices may be in a low-battery state from time to time. In this regard, it is desirable to extend battery life while enabling rapid voltage changes between OFDM symbols.

Disclosure of Invention

Embodiments of the present disclosure relate to voltage ripple reduction in power management circuits. The power management circuit includes a power amplifier circuit configured to amplify a Radio Frequency (RF) signal based on a modulation voltage and an Envelope Tracking Integrated Circuit (ETIC) configured to provide the modulation voltage to the power amplifier circuit via a conductive path. Notably, the output impedance presented at the input of the power amplifier circuit (e.g., inductive impedance associated with the ETIC and conductive paths) may interact with the modulated load current in the power amplifier circuit to produce voltage fluctuations in the modulated voltage, potentially causing undesirable errors in the RF signal. In embodiments disclosed herein, the ETIC is configured to modify the modulation voltage based on feedback indicative of voltage fluctuations in the modulation voltage received at the power amplifier input. By modifying the modulation voltage based on knowledge of the voltage fluctuations, it is possible to reduce the output impedance at the input of the power amplifier circuit, thereby reducing the voltage fluctuations in the modulation voltage.

In one aspect, a power management circuit is provided. The power management circuit includes a power amplifier circuit. The power amplifier circuit is configured to amplify an RF signal based on a modulated voltage received at a power amplifier input. The modulated voltage received at the power amplifier input includes voltage fluctuations caused by an output impedance presented at the power amplifier input. The power management circuit also includes an ETIC. The ETIC includes a voltage output coupled to the power amplifier input via a conductive path. The ETIC also includes a voltage modulation circuit. The voltage modulation circuit is configured to generate the modulation voltage at the voltage output based on a modulation target voltage. The voltage modulation circuit is further configured to receive a power amplifier voltage feedback indicative of the voltage fluctuations in the modulated voltage received at the power amplifier input. The voltage modulation circuit is further configured to modify the modulation voltage based on the power amplifier voltage feedback to cause a decrease in the output impedance to reduce the voltage ripple in the modulation voltage received at the power amplifier input.

Those skilled in the art will recognize the scope of the present disclosure and appreciate additional aspects thereof upon reading the following detailed description of the preferred embodiments and the associated drawings.

Drawings

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1A is a schematic diagram of an exemplary prior art transmit circuit based on a conventional approach, wherein a power management circuit is configured to reduce voltage fluctuations in a modulated voltage;

FIG. 1B is a schematic diagram of an exemplary electrical model of the power management circuit of FIG. 1A;

FIG. 1C is a graph providing an exemplary illustration of magnitude impedance as a function of modulation frequency;

FIG. 2 is a schematic diagram of an exemplary power management circuit configured to reduce voltage fluctuations in a modulated voltage by reducing an output impedance presented at a power amplifier input of the power amplifier circuit, in accordance with an embodiment of the present disclosure; and is also provided with

Fig. 3 is a schematic diagram providing an exemplary illustration of the internal structure of the voltage amplifier in the power management circuit of fig. 2.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "over" or "extending over" another element, it can extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Before discussing specific voltage fluctuation reducing embodiments of the present disclosure, beginning with fig. 2, a brief overview of an existing transmit circuit is first discussed with reference to fig. 1A-1C to help understand some of the problems associated with conventional approaches based on reducing voltage fluctuation.

Fig. 1A is a schematic diagram of an exemplary prior art transmit circuit 10 based on a conventional approach, wherein a power management circuit 12 is configured to reduce a modulation voltage V _CC Voltage fluctuation V in (a) _CC-RP . The power management circuit 12 includes an ETIC 14 and a power amplifier circuit 16. The ETIC 14 is configured to be based on the modulation target voltage V _TGT Generating a modulation voltage V _CC And the modulation voltage V is coupled via a conductive path 18 (e.g., a conductive trace) between a voltage output 20 of the ETIC 14 and a power amplifier input 22 of the power amplifier circuit 16 _CC To the power amplifier circuit 16. The power amplifier circuit 16 is configured to be based on the modulation voltage V _CC The RF signal 24 is amplified.

Notably, there may be an internal routing distance from the power amplifier input 22 to the actual voltage input 26 (e.g., collector node) of the power amplifier circuit. Since the internal routing distance is much shorter than the conductive path 18, the internal routing distance is omitted hereinafter. Thus, the power amplifier input 22 as shown herein may be equivalent to the actual voltage input 26 of the power amplifier circuit 16.

Power management circuit 12 may be coupled to transceiver circuit 28. Herein, the transceiver circuit 28 is configured to generate the RF signal 24 and the modulation target voltage V _TGT 。

Voltage fluctuation V _CC-RP The quantitative analysis may be based on an equivalent electrical model of the power management circuit 12. In this regard, FIG. 1B is the illustration of FIG. 1ASchematic diagram of an exemplary equivalent electrical model 30 of power management circuit 12. Common elements between fig. 1A and 1B are shown with common element numbers and will not be described again herein.

The ETIC 14 inherently has a inductance L that can be passed through the ETIC _ETIC Modeled inductance impedance Z _ETIC . Conductive path 18 may also be coupled to a trace inductance L _TRACE Modeled inductance trace impedance Z _TRACE And (5) associating. Thus, from the power amplifier input 22 toward the ETIC 14, the power amplifier circuit 16 will see a circuit that includes an inductive impedance Z _ETIC And inductance trace impedance Z _TRACE The output impedance Z of both _OUT 。

The power amplifier circuit 16 may be modeled as a current source. In this regard, the power amplifier circuit 16 will be based on the modulation voltage V _CC For load current I _LOAD Modulation is performed. Load current I _LOAD Can be connected with output impedance Z _OUT Interact to modulate a voltage V received at a power amplifier input 22 _CC Is generated with voltage fluctuation V _CC-RP . In this respect, the voltage fluctuates V _CC-RP Is to modulate the load current I _LOAD And output impedance Z _OUT As shown in the following equation (equation 1).

V _CC-RP ＝I _LOAD *Z _OUT (equation 1)

Notably, according to equation (equation 1), the output impedance Z seen at the power amplifier input 22 can be reduced by _OUT To reduce voltage fluctuation V _CC-RP . In this regard, a method for reducing voltage ripple V in power management circuit 12 of FIG. 1A _CC-RP Is to add a decoupling capacitor C inside the power amplifier circuit 16 _PA And as close as possible to the power amplifier input 22. By adding decoupling capacitor C _PA Output impedance Z _OUT Can be expressed simply as equation (equation 2).

Z _OUT ＝Z _CPA ||(Z _ETIC +Z _TRACE ) (equation 2)

In equation (equation 2), Z _CPA Representing decoupling capacitor C _PA Is a capacitive resistor of (2)And (3) resistance. Capacitance impedance Z _CPA And inductance impedance Z _ETIC Z is as follows _TRACE Each may be determined according to the following equations (equations 3.1-3.3).

|Z _CPA |＝1/2πf*C _PA (equation 3.1)

|Z _ETIC |＝2πf*L _ETIC (equation 3.2)

|Z _TRACE |＝2πf*L _TRACE (equation 3.3)

In the equations (equations 3.1-3.3), f represents the load current I _LOAD Is used for modulating the frequency of the modulation. In this respect, the capacitive impedance Z _CPA Inductance impedance Z _ETIC And inductance trace impedance Z _TRACE Each as a function of the modulation frequency f. Fig. 1C is a graph providing an exemplary illustration of magnitude impedance versus modulation frequency f.

When the modulation frequency f is lower than 10MHz, the output impedance Z _OUT From inductance impedance Z _ETIC Real and inductive trace impedance Z _TRACE Is governed by the real part of (2). Between 10MHz and 100MHz, the output impedance Z _OUT From inductance impedance Z _ETIC And inductance trace impedance Z _TRACE Dominating. At above 1000MHz, the output impedance Z _OUT Will be composed of capacitance impedance Z _CPA Dominating.

In this context, the modulation bandwidth BW of the RF signal 24 _MOD May fall between 100MHz and 1000MHz (e.g., 100-500 MHz). In this frequency range, the output impedance Z _OUT Will pass through the output impedance Z _OUT The determination is as expressed by equation (equation 2).

Notably, according to equations (equations 2 and 3.1), the capacitive impedance Z _CPA And thus the output impedance Z _OUT Will follow the capacitance C _PA And decreases with increasing numbers. In this respect, for reducing the ripple voltage V _CC-RP The conventional approach of (a) relies mainly on adding decoupling capacitors C with larger capacitance (e.g. 1F to 2F) _PA . However, doing so may cause some significant problems.

It will be appreciated that the modulation voltage V _CC Rate of change (DeltaV) _CC Or dV/dt) may be subjected to decoupling capacitor C _PA Is of the capacitance of (a)The opposite effect is shown in the following equation (equation 4).

ΔV _CC ＝I _CC /C _PA (equation 4)

In equation (equation 4), I _CC Indicating when decoupling capacitor C _PA A low frequency current (also called a starting current) supplied through the ETIC 14 at the time of charge or discharge. In this respect, decoupling capacitor C _PA The larger the capacitance is, the larger the amount of low frequency current I is required _CC To a desired rate of change (DeltaV _CC ) Changing the modulation voltage V _CC . Thus, the existing transmit circuit 10 may negatively impact battery life.

If low frequency current I _CC Maintaining a low level to extend battery life may be difficult for the existing transmit circuit 10 to meet the desired rate of change (av) _CC ) Particularly when the RF signal 24 is modulated based on Orthogonal Frequency Division Multiplexing (OFDM) to be transmitted in the millimeter wave (mmWave) spectrum. Thus, the existing transmit circuit 10 may not be able to change the modulation voltage V between OFDM symbols _CC 。

On the other hand, if the decoupling capacitor C is reduced _PA Is helpful for improving the modulation voltage V _CC Rate of change (DeltaV) _CC ) And reduce the starting current I _CC Doing so may result in an output impedance Z _OUT Insufficient reduction of (c) and thus cause voltage fluctuation V _CC-RP . Therefore, it is desirable to increase the modulation voltage V _CC Rate of change (DeltaV) _CC ) And reduce the starting current I _CC At the same time as the modulation bandwidth BW is sufficiently reduced _MOD Fluctuating voltage V in _CC-RP 。

Fig. 2 is a diagram configured to reduce the output impedance Z presented at the power amplifier input 34 of the power amplifier circuit 36 in accordance with an embodiment of the present disclosure _OUT To reduce the modulation voltage V _CC Voltage fluctuation V in (a) _CC-RP Schematic diagram of an exemplary power management circuit 32. Here, the power amplifier circuit 36 is configured to receive the modulation voltage V via a conductive path 38 (e.g., a conductive trace) _CC And based on the modulation voltage V _CC The RF signal 40 is amplified. The power amplifier circuit 36 includes decouplingCapacitor C _PA . Similar to decoupling capacitor C in power amplifier circuit 16 in fig. 1A _PA A decoupling capacitor C is also provided as close as possible to the power amplifier input 34 _PA 。

The power management circuit 32 includes an ETIC 42. The ETIC 42 includes a voltage modulation circuit 44. The voltage modulation circuit 44 is configured to modulate the target voltage V _TGT Generating a modulated voltage V at a voltage output 46 _CC . Here, the voltage output 46 is coupled to the power amplifier input 34 via the conductive path 38.

Similar to the power management circuit 12 in fig. 1A, the decoupling capacitor C _PA With capacitive impedance Z _CPA The ETIC 42 inherently has an inductive impedance Z _ETIC And the conductive path 38 is inherently connected to the inductive trace impedance Z _TRACE In association, this can be expressed as in equations (equations 3.1-3.3). Thus, the power amplifier circuit 36 will see an output impedance Z as determined in equation (equation 2) within the modulation bandwidth (e.g., 100-500 MHz) of the RF signal 40 _OUT . Here, the power amplifier circuit 36 also operates as a current source, which may be based on the modulation voltage V _CC To inductively modulate the load current I _LOAD . Similar to the power management circuit 12 in fig. 1A, the load current I is modulated _LOAD Can be connected with output impedance Z _OUT Interact to produce a modulated voltage V received at the power amplifier input 34 _CC Voltage fluctuation V in (a) _CC-RP 。

In the embodiments disclosed herein, a decoupling capacitor C in the power amplifier circuit 16 of fig. 1A _PA In contrast, decoupling capacitor C _PA With a smaller capacitance (e.g., 100 pF). By using smaller decoupling capacitors C _PA It is possible to increase the modulation voltage V _CC Rate of change (DeltaV) _CC ) To meet streaming voltage switching time requirements (e.g., according to OFDM symbols or sub-symbols) in advanced wireless systems such as fifth generation (5G) and 5G new radios (5G-NR) while reducing start-up current I _CC To extend battery life.

Further, the power management circuit 32 is configured to control the power amplifier input 34 by reducing the output presented at the power amplifier inputOutput impedance P _OUT And/or generating a notch filter at the power amplifier input 34 to reduce the modulation voltage V _CC Voltage fluctuation V in (a) _CC-RP . As a result, power management circuit 32 may achieve a defined performance threshold, such as RMS EVM and/or peak EVM, within the modulation bandwidth of RF signal 40.

In an embodiment, the voltage modulation circuit 44 includes a voltage amplifier 48 (denoted "VA"), which may be an operational amplifier (OpAmp), as an example. The voltage amplifier 48 is configured to modulate the target voltage V _TGT And supply voltage V _SUP Generating an initial modulation voltage V at the voltage amplifier output 50 _AMP . The voltage modulation circuit 44 also includes an offset capacitor C coupled between the voltage amplifier output 50 and the voltage output 46 _OFF . Offset capacitor C _OFF Is configured to modulate an initial modulation voltage V _AMP Increasing the offset voltage V _OFF To produce a modulated voltage V at a voltage output 46 _CC (V _CC ＝V _AMP +V _OFF )。

The voltage amplifier 48 is also configured to receive a modulated voltage feedback V _CC-FB The feedback indicates the modulation voltage V at the voltage output 46 _CC Thereby making the voltage modulation circuit 44 a closed loop circuit. Thus, the voltage amplifier 48 may be based on the modulation feedback V _CC-FB Regulating the initial modulation voltage V _AMP And thus adjusts the modulation voltage V _CC To better track the modulation target voltage V _TGT 。

The voltage amplifier 48 includes an input/bias stage 52 and an output stage 54. The output stage 54 is coupled in series to the voltage amplifier output 50. According to an embodiment of the present disclosure, the output stage 54 is configured to receive a power amplifier voltage feedback V _CC-PA-FB The feedback indicates the modulation voltage V as received at the power amplifier input 34 _CC . Output stage 54 may receive power amplifier voltage feedback V via feedback path 56 _CC-PA-FB . Feedback path 56 is similar to conductive path 38 with inductive feedback trace impedance Z _TRACE-FB In association, the inductive feedback trace impedance may be determined by the feedback inductance L _TRACE-FB Modeling.

It will be appreciated that due to the power amplifier voltage feedback V _CC-PA-FB Is provided from the power amplifier input 34, and thus the power amplifier voltage feedback V _CC-PA-FB Will contain the modulated voltage V as received at the power amplifier input 34 _CC Voltage fluctuation V in (a) _CC-RP . Thus, the voltage amplifier 48 may be based on the power amplifier voltage feedback V _CC-PA-FB Modifying the initial modulation voltage V _AMP So that the output impedance Z _OUT Reduced at the power amplifier input 34, thus helping to reduce the modulation voltage V received at the power amplifier input 34 _CC Voltage fluctuation V in (a) _CC-RP 。

As an example, the ETIC 42 may contain a control circuit 58, which may be a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). In an embodiment, the control circuit 58 may control the voltage amplifier 48 to feedback V based on the power amplifier voltage, for example, via the control signal 60 _CC-PA-FB Modifying the initial modulation voltage V _AMP Thereby reducing the output impedance Z at the power amplifier input 34 _OUT 。

Fig. 3 is a schematic diagram providing an exemplary illustration of the internal structure of the voltage amplifier 48 in fig. 2. Common elements between fig. 2 and 3 are shown here with common element numbers and will not be repeated here.

In an embodiment, the input/bias stage 52 is configured to receive a modulation voltage V _TGT And modulating voltage feedback V _CC-FB . Thus, the input/bias stage 52 generates a pair of bias signals 62P (also referred to as first bias signals), 62N (also referred to as second bias signals) to control the output stage 54.

In an embodiment, the output stage 54 is configured to generate the initial modulation voltage V at the voltage amplifier output 50 based on a selected one of the bias signals 62P, 62N _AMP . The output stage 54 is also configured to receive a power amplifier voltage feedback V _CC-FB . Thus, the output stage 54 may be based on the power amplifier voltage feedback V _CC-FB Modifying the initial modulation voltage V _AMP To reduce the output impedance Z _OUT And thereby reduce the power amplifierVoltage ripple V at input 34 _CC-RP 。

In an embodiment, the output stage 54 includes a first transistor 64P and a second transistor 64N. In a non-limiting example, the first transistor 64P is a P-type field effect transistor (pFET) and the second transistor 64N is an N-type field effect transistor (nFET). In this example, the first transistor 64P includes a first source electrode C ₁ First drain electrode D ₁ And a first gate electrode G ₁ And the second transistor 64N includes a second source electrode C ₂ Second drain electrode D ₂ And a second gate electrode G ₂ . Specifically, the first drain electrode D ₁ Is configured to receive a supply voltage V _SUP The second drain electrode D2 is coupled to Ground (GND), and the first source electrode C ₁ And a second source electrode C ₂ Are coupled to the voltage amplifier output 50.

First gate electrode G ₁ Coupled to the input/bias stage 52 to receive the bias signal 62P, and a second gate electrode G ₂ Coupled to the input/bias stage 52 to receive the bias signal 62N. Here, the input/bias stage 52 is configured to be responsive to a modulation voltage V _CC Generates a bias signal 62P or is responsive to a modulation voltage V _CC Generates the bias signal 62N. Specifically, the first transistor 64P will be turned on in response to receiving the bias signal 62P to output the initial modulation voltage V _AMP And provides a voltage from the power supply voltage V _SUP High-frequency current I of (2) _AMP (e.g., alternating current) and the second transistor 64N will be turned on to output a voltage from the supply voltage V in response to receiving the bias signal 62N _SUP Is set to the initial modulation voltage V of _AMP And will high frequency current I _AMP Sink to GND.

In this embodiment, the output stage 54 also includes a first Miller capacitor (Miller capacitor) C _Miller1 And a second miller capacitor C _Miller2 . Specifically, a first Miller capacitor C _Miller1 Coupled between the voltage amplifier output 50 and the first gate electrode G ₁ And a second Miller capacitor C _Miller2 Coupled between the voltage amplifier output 50 and the second gate electrode G ₂ Between them. In this regard, the output stage 54 may be considered as typicalClass AB rail-to-rail (OpAmp) output stage. First Miller capacitor C _Miller1 And a second miller capacitor C _Miller2 Not only can the control of the first transistor 64P and the second transistor 64N be stabilized (e.g., so-called Miller effect is mitigated), but the closed loop output impedance of the voltage amplifier 48 can also be reduced.

Notably, due to the first miller capacitor C _Miller1 And a second miller capacitor C _Miller2 Each coupled to a voltage amplifier output 50, a first miller capacitor C _Miller1 And a second miller capacitor C _Miller2 Can only be reduced as seen at the power amplifier input 34 as output impedance Z _OUT Inductance impedance Z of a portion of (a) _ETIC . Thus, to further reduce the output impedance Z _OUT It is also necessary to reduce the inductance trace impedance Z _TRACE 。

In this regard, the output stage 54 further includes a first resistor-capacitor (RC) circuit 66P and a second RC circuit 66N. The first RC circuit 66P and the second RC circuit 66N are each coupled to the power amplifier input 34 via the feedback path 56 to receive the power amplifier voltage feedback V _CC-FB . Specifically, a first RC circuit 66P is coupled between the power amplifier input 34 and the first gate electrode G ₁ And a second RC circuit 66N coupled between the power amplifier input 34 and the second gate electrode G ₂ Between them. Thus, the first RC circuit 66P may enable the power amplifier voltage feedback V _CC-FB Combined with the bias signal 62P to modify the bias signal 62P. Similarly, the second RC circuit 66N may enable the power amplifier voltage feedback V _CC-FB Combined with the bias signal 62N to modify the bias signal 62N.

In an embodiment, the first RC circuit 66P includes a first adjustable resistor R _FB1 And a first adjustable capacitor C _FB1 And the second RC circuit 66N includes a second adjustable resistor R _FB2 And a second adjustable capacitor C _FB2 . Feedback path 56 and inductive feedback trace impedance Z _TRACE-FB The associated call may be made by feedback inductance L _TRACE-FB Modeling is performed. Thus, the first adjustable resistor R _FB1 First canRegulating capacitor C _FB1 And feedback inductance L _TRACE-FB May be equivalent to a first resistor-inductor-capacitor (RLC) circuit having a first resonant frequency f as expressed in equation (equation 5) below ₁ 。

Likewise, a second adjustable resistor R _FB2 Second adjustable capacitor C _FB2 And feedback inductance L _TRACE-FB May be equivalent to a second RLC circuit having a second resonant frequency f as expressed in the following equation (equation 6) ₂ 。

According to equations (equations 5 and 6), the first adjustable capacitors C can be individually adjusted _FB1 And a second adjustable capacitor C _FB2 To be connected with feedback inductance L _TRACE-FB Resonance at a first resonance frequency f ₁ And a second resonance frequency f ₂ Creating a low impedance feedback path. First adjustable resistor R _FB1 Will be at modulation bandwidth BW _MOD Upper to first resonant frequency f ₁ Q-removing to prevent the first adjustable capacitor C _FB1 And feedback inductance L _TRACE-FB At a first resonant frequency f ₁ Into oscillation. Likewise, a second adjustable resistor R _FB2 Will be at modulation bandwidth BW _MOD Upper to second resonance frequency f ₂ Q-removing to prevent the second adjustable capacitor C _FB2 And feedback inductance L _TRACE-FB At a second resonance frequency f ₂ Into oscillation.

The voltage ripple V seen at the power amplifier input 34 _CC-RP Is fed back to the first gate electrode G ₁ Or a second gate electrode G ₂ When the first transistor 64P and the second transistor 64N may function like a common source amplifier that amplifies and inverts at a voltageInitial modulation voltage V at amplifier output 50 _AMP And thus amplifies and inverts the voltage output 46 of the ETIC 42. Inverting the initial modulation voltage V _AMP Will cause the load current I to _LOAD Through a conductive path 38 (also known as a trace inductor L _TRACE ) Flows to GND, rather than through the power amplifier circuit 36, thus reducing the inductive trace impedance Z _TRACE And thus reduce the output impedance Z at the power amplifier input 34 _OUT 。

Thus, by adjusting the first adjustable capacitor C _FB1 A first adjustable resistor R _FB1 Second adjustable capacitor C _FB2 And/or a second adjustable resistor R _FB2 It is possible to output the impedance Z _OUT Reduced to the whole modulation bandwidth BW _MOD . In an embodiment, a first adjustable capacitor C _FB1 A first adjustable resistor R _FB1 Second adjustable capacitor C _FB2 And/or a second adjustable resistor R _FB2 May be regulated by the control circuit 58 via a control signal 60.

By using a first Miller capacitor C _Miller1 And a second miller capacitor C _Miller2 To help reduce the inductance impedance Z _ETIC And further employs first and second RC circuits 66P and 66N to help reduce the inductive trace impedance Z _TRACE It is possible to reduce the output impedance Z _OUT Thereby reducing the modulation voltage V _CC Voltage fluctuation V in (a) _CC-RP . The simulation shows that the power management circuit 32 can fluctuate the voltage V at a 200MHz load current modulation frequency _CC-RP The RMS value of (c) is reduced from 231mV to 134mV, which is equivalent to a 42% improvement, as shown in the power management circuit 12 in fig. 1A.

Referring to fig. 2, etic 42 further includes a switching circuit 68. In an embodiment, the switching circuit 68 includes a power inductor L _P A multi-level charge pump (MCP) 70 coupled to the voltage output 46. As an example, the MCP 70 may be a buck-boost voltage converter configured to be based on the battery voltage V _BAT Generating a low frequency voltage V _DC . Specifically, the MCP 70 may operate in a buck mode to produceAt 0 XV _BAT Or 1 XV _BAT Low frequency voltage V of (2) _DC Or in boost mode to produce a voltage at 2 XV _BAT Low frequency voltage V of (2) _DC . Thus, by configuring the MCP 70 to be at 0V based on the appropriate duty cycle _BAT 、1×V _BAT And/or 2 XV _BAT Switching between, the MCP 70 may generate a low frequency voltage V at a plurality of voltage levels _DC 。

Power inductor L _P Is configured to be based on the low frequency voltage V _DC Inducing a low frequency current I _CC (also known as starting current). As previously described in fig. 1A, low frequency current I _CC Is provided to the power amplifier input 34 for decoupling the capacitor C _PA And (5) charging.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A power management circuit, the power management circuit comprising:

a power amplifier circuit configured to amplify a Radio Frequency (RF) signal based on a modulated voltage received at a power amplifier input, wherein the modulated voltage received at the power amplifier input comprises voltage fluctuations caused by an output impedance presented at the power amplifier input; and

an envelope tracking integrated circuit ETIC, the ETIC comprising:

a voltage output coupled to the power amplifier input via a conductive path; and

a voltage modulation circuit configured to:

generating a modulation voltage at the voltage output based on a modulation target voltage;

receiving a power amplifier voltage feedback indicative of the voltage fluctuations in the modulated voltage received at the power amplifier input; and is also provided with

The modulation voltage is modified based on the power amplifier voltage feedback to cause the output impedance to decrease, thereby reducing the voltage ripple in the modulation voltage received at the power amplifier input.

2. The power management circuit of claim 1, wherein the output impedance presented at the power amplifier input comprises an inductive impedance of the ETIC and an inductive trace impedance associated with the conductive path.

3. The power management circuit of claim 2, wherein the voltage modulation circuit comprises:

a voltage amplifier configured to generate an initial modulated voltage at a voltage amplifier output based on the modulated target voltage; and

an offset capacitor configured to step up the initial modulation voltage by an offset voltage to produce the modulation voltage at the voltage output.

4. The power management circuit of claim 3, wherein the voltage amplifier comprises an output stage configured to:

generating the initial modulation voltage at the voltage amplifier output;

receiving the power amplifier voltage feedback, the power amplifier voltage feedback being indicative of the voltage fluctuations in the modulated voltage received at the power amplifier input; and is also provided with

The initial modulation voltage is modified based on the power amplifier voltage feedback to cause the output impedance to decrease, thereby reducing the voltage ripple in the modulation voltage received at the power amplifier input.

5. The power management circuit of claim 4, wherein the voltage amplifier further comprises an input/bias stage configured to:

receiving the modulation target voltage and a modulation voltage feedback indicative of the modulation voltage at the voltage output; and is also provided with

A pair of bias signals is generated based on the modulation target voltage and the modulation voltage feedback, thereby causing the output stage to generate the initial modulation voltage.

6. The power management circuit of claim 5, wherein the output stage comprises:

a first transistor, the first transistor comprising:

a first drain electrode configured to receive a supply voltage;

a first gate electrode configured to receive a first bias signal of the pair of bias signals; and

a first source electrode coupled to the voltage amplifier output; and

a second transistor, the second transistor comprising:

a second source electrode coupled to the voltage amplifier output;

a second gate electrode configured to receive a second bias signal of the pair of bias signals; and

a second drain electrode coupled to ground;

wherein a selected one of the first transistor and the second transistor is biased by a selected one of the first bias signal and the second bias signal to output the initial modulation voltage at the voltage amplifier output.

7. The power management circuit of claim 6, wherein the output stage further comprises:

a first miller capacitor coupled between the first gate electrode and the first source electrode and configured to reduce an impedance at the voltage output, thereby reducing the inductive impedance of the ETIC when the first transistor is biased by the first bias signal; and

a second miller capacitor coupled between the second gate electrode and the second source electrode and configured to reduce the impedance at the voltage output, thereby reducing the inductive impedance of the ETIC when the second transistor is biased by the second bias signal.

8. The power management circuit of claim 6, wherein the output stage further comprises:

a first resistor-capacitor (RC) circuit coupled between the power amplifier input and the first gate electrode and configured to combine the power amplifier voltage feedback with the first bias signal, thereby reducing the inductive trace impedance at the power amplifier input; and

a second RC circuit coupled between the power amplifier input and the second gate electrode and configured to combine the power amplifier voltage feedback with the second bias signal, thereby reducing the inductive trace impedance at the power amplifier input.

9. The power management circuit of claim 8, wherein the first RC circuit and the second RC circuit each comprise a respective adjustable resistor and a respective adjustable capacitor coupled in series between the power amplifier input and a respective one of the first gate electrode and the second gate electrode.

10. The power management circuit of claim 9, wherein the ETIC further comprises a control circuit configured to adjust at least one of the respective adjustable resistor and the respective capacitor in a respective one of the first RC circuit and the second RC circuit to cause the output impedance within a modulation bandwidth of the power amplifier circuit to decrease.

11. An envelope tracking integrated circuit ETIC, the ETIC comprising:

a voltage output coupled to a power amplifier circuit via a conductive path, the power amplifier circuit configured to amplify a Radio Frequency (RF) signal based on a modulated voltage received at a power amplifier input, wherein the modulated voltage received at the power amplifier input comprises a voltage ripple caused by an output impedance presented at the power amplifier input; and

a voltage modulation circuit configured to:

The modulation voltage is modified based on the power amplifier voltage feedback to cause a decrease in the output impedance to reduce the voltage ripple in the modulation voltage received at the power amplifier input.

12. The ETIC of claim 11, wherein the output impedance presented at the power amplifier input includes an inductive impedance of the ETIC and an inductive trace impedance associated with the conductive path.

13. The ETIC of claim 12, wherein the voltage modulation circuit includes:

14. The ETIC of claim 13, wherein the voltage amplifier includes an output stage configured to:

generating the initial modulation voltage at the voltage amplifier output;

15. The ETIC of claim 14, wherein the voltage amplifier further comprises an input/bias stage configured to:

16. The ETIC of claim 15, wherein the output stage includes:

a first transistor, the first transistor comprising:

a first drain electrode configured to receive a supply voltage;

a first source electrode coupled to the voltage amplifier output; and

a second transistor, the second transistor comprising:

a second source electrode coupled to the voltage amplifier output;

a second drain electrode coupled to ground;

17. The ETIC of claim 16, wherein the output stage further comprises:

18. The ETIC of claim 16, wherein the output stage further comprises:

19. The ETIC of claim 18, wherein the first RC circuit and the second RC circuit each include a respective adjustable resistor and a respective adjustable capacitor coupled in series between the power amplifier input and a respective one of the first gate electrode and the second gate electrode.

20. The ETIC of claim 19, wherein the ETIC further includes a control circuit configured to adjust at least one of the respective adjustable resistor and the respective capacitor in a respective one of the first RC circuit and the second RC circuit to cause the output impedance within a modulation bandwidth of the power amplifier circuit to decrease.