CN116505886A - Voltage ripple reduction in power management circuits - Google Patents

Abstract

Voltage fluctuation reduction in power management circuits is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulation voltage, and an envelope tracking integrated circuit (ETIC), the ETIC configured to transmit the modulated signal via a conductive path. voltage is supplied to the power amplifier circuit. It is worth noting that the output impedance presented at the input of the power amplifier circuit can interact with the modulating load current in the power amplifier circuit to produce voltage fluctuations in the modulation voltage, potentially causing the Undesired errors in RF signals. Here, the ETIC is configured to modify the modulation voltage based on feedback of the voltage fluctuations in the modulation voltage. Therefore, it is possible to reduce the output impedance at the input of the power amplifier circuit, thereby reducing the voltage fluctuation in the modulation voltage.

Description

Reduced voltage fluctuations in power management circuits

related application

This application claims the benefit of US Provisional Patent Application Serial No. 63/303,532, filed January 27, 2022, the disclosure of which is incorporated herein by reference in its entirety.

technical field

The techniques of this disclosure generally relate to reducing voltage fluctuations of modulation voltages in power management circuits.

Background technique

Fifth-generation (5G) New Radio (NR) (5G-NR) is widely regarded as the next generation of wireless communication technology beyond the current third-generation (3G) and fourth-generation (4G) technologies. In this regard, wireless communication devices capable of supporting 5G-NR wireless communication technology are expected to achieve higher data rates, improved coverage, enhanced signal conduction efficiency, and reduced delay.

The downlink and uplink transmissions in 5G-NR systems are widely based on Orthogonal Frequency Division Multiplexing (OFDM) technology. In OFDM based systems, physical radio resources are divided into subcarriers in the frequency domain and OFDM symbols in the time domain. The subcarriers are orthogonally separated from each other by subcarrier spacing (SCS). OFDM symbols are separated by a cyclic prefix (CP), which acts as a guard band to help overcome inter-symbol interference (ISI) between OFDM symbols.

A radio frequency (RF) signal transmitted in an OFDM based system is typically modulated into multiple subcarriers in the frequency domain and multiple OFDM symbols in the time domain. The multiple subcarriers occupied by the RF signal collectively define the modulation bandwidth of the RF signal. On the other hand, a plurality of OFDM symbols define a plurality of time intervals during which RF signals are transmitted. In 5G-NR systems, RF signals are typically modulated with a high modulation bandwidth exceeding 200 MHz (eg, 1 GHz).

The duration of an OFDM symbol depends on the SCS and modulation bandwidth. The following table (Table 1) provides some OFDM symbol durations defined by the 3G Partnership Project (3GPP) standards for various SCS and modulation bandwidths. It is worth noting that the higher the modulation bandwidth, the shorter the OFDM symbol duration will be. For example, when the SCS is 120KHz and the modulation bandwidth is 400MHz, the OFDM symbol duration is 8.93μs.

Table 1

Notably, wireless communication devices rely on battery cells (eg, Li-ion batteries) to power their operations and services. Despite recent advances in battery technology, wireless communication devices may be in a low battery state from time to time. In this regard, it is desirable to extend battery life while enabling fast voltage changes between OFDM symbols.

Contents of the invention

Embodiments of the present disclosure relate to voltage fluctuation reduction in power management circuits. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulation voltage, and an envelope tracking integrated circuit (ETIC), the ETIC configured to transmit the modulated signal via a conductive path. voltage is supplied to the power amplifier circuit. Notably, the output impedance presented at the input of the power amplifier circuit (e.g., the inductive impedance associated with the ETIC and conductive path) can interact with the modulating load current in the power amplifier circuit to produce the voltage fluctuations in the modulation voltage, potentially causing undesired errors in the RF signal. In embodiments disclosed herein, the ETIC is configured to modify the modulation voltage based on feedback indicative of voltage fluctuations in the modulation voltage received at the input of the power amplifier. By modifying the modulation voltage based on knowledge of the voltage fluctuations, it is possible to reduce the output impedance at the input of the power amplifier circuit, thereby reducing the voltage fluctuations in the modulation voltage.

In one aspect, a power management circuit is provided. The power management circuitry includes power amplifier circuitry. The power amplifier circuit is configured to amplify an RF signal based on a modulation voltage received at a power amplifier input. The modulation voltage received at the power amplifier input includes voltage fluctuations caused by an output impedance presented at the power amplifier input. The power management circuit also includes an ETIC. The ETIC includes a voltage output coupled to the power amplifier input via a conductive path. The ETIC also includes a voltage modulation circuit. The voltage modulation circuit is configured to generate the modulation voltage at the voltage output based on a modulation target voltage. The voltage modulation circuit is further configured to receive power amplifier voltage feedback indicative of the voltage fluctuation in the modulation voltage received at the power amplifier input. The voltage modulation circuit is further configured to modify the modulation voltage based on the power amplifier voltage feedback to cause a decrease in the output impedance, thereby reducing the modulation voltage received at the power amplifier input. of the voltage fluctuations.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects after reading the following detailed description of the preferred embodiment and the associated drawings.

Description of drawings

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

FIG. 1A is a schematic diagram of an exemplary prior art transmit circuit based on a conventional approach, wherein a power management circuit is configured to reduce voltage fluctuations in a modulation voltage;

FIG. 1B is a schematic diagram of an exemplary electrical model of the power management circuit in FIG. 1A;

FIG. 1C is a graph providing an exemplary illustration of magnitude impedance as a function of modulation frequency;

2 is a schematic diagram of an exemplary power management circuit configured to reduce voltage fluctuations in a modulation voltage by reducing an output impedance presented at a power amplifier input of a power amplifier circuit in accordance with an embodiment of the present disclosure; and

FIG. 3 is a schematic diagram providing an exemplary illustration of the internal structure of a voltage amplifier in the power management circuit of FIG. 2 .

Detailed ways

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It is to be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending onto" another element, it can be directly on or directly extending onto the other element. , or intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "extending over" another element, it can be directly on or directly on the other element. extends above, or intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the difference between an element, layer or region and another element as shown in the figures. , layer or region relationship. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is also to be understood that when used herein, the term "comprises/comprising" and/or includes/including specifies the presence of said features, integers, steps, operations, elements and/or parts, but does not exclude One or more other features, integers, steps, operations, elements, components and/or groups thereof are present or added.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that, unless expressly defined herein, terms used herein should be interpreted to have meanings consistent with their meanings in the context of this specification and related art, and will not be interpreted in an idealized or overly formal sense explain.

Embodiments of the present disclosure relate to voltage fluctuation reduction in power management circuits. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulation voltage, and an envelope tracking integrated circuit (ETIC), the ETIC configured to transmit the modulated signal via a conductive path. voltage is supplied to the power amplifier circuit. Notably, the output impedance presented at the input of the power amplifier circuit (e.g., the inductive impedance associated with the ETIC and conductive path) can interact with the modulating load current in the power amplifier circuit to produce the voltage fluctuations in the modulation voltage, potentially causing undesired errors in the RF signal. In embodiments disclosed herein, the ETIC is configured to modify the modulation voltage based on feedback indicative of voltage fluctuations in the modulation voltage received at the input of the power amplifier. By modifying the modulation voltage based on knowledge of the voltage fluctuations, it is possible to reduce the output impedance at the input of the power amplifier circuit, thereby reducing the voltage fluctuations in the modulation voltage.

Before discussing specific voltage fluctuation reduction embodiments of the present disclosure, starting from FIG. 2, a brief overview of existing transmitting circuits is first discussed with reference to FIGS. .

FIG. 1A is a schematic diagram of an exemplary conventional transmit circuit 10 based on a conventional approach, in which a power management circuit 12 is configured to reduce voltage fluctuation V _CC-RP in a modulation voltage V _CC . Power management circuitry 12 includes ETIC 14 and power amplifier circuitry 16 . ETIC 14 is configured to generate modulation voltage V _CC based on modulation target voltage V _TGT , and via conductive path 18 (e.g., a conductive trace) coupled between voltage output 20 of ETIC 14 and power amplifier input 22 of power amplifier circuit 16 The modulation voltage V _CC is provided to a power amplifier circuit 16 . Power amplifier circuit 16 is configured to amplify RF signal 24 based on modulation voltage V _CC .

It is worth noting that there may be an internal routing distance from the power amplifier input 22 to the actual voltage input 26 (eg collector node) of the power amplifier circuit. Since the internal routing distance is much shorter than the conductive path 18, the internal routing distance is ignored below. Therefore, the power amplifier input 22 as shown herein may be equated to the actual voltage input 26 of the power amplifier circuit 16 .

Power management circuitry 12 may be coupled to transceiver circuitry 28 . Herein, the transceiver circuit 28 is configured to generate the RF signal 24 and modulate the target voltage V _TGT .

The voltage fluctuation V _CC-RP can be quantitatively analyzed based on the equivalent electrical model of the power management circuit 12 . In this regard, FIG. 1B is a schematic diagram of an exemplary equivalent electrical model 30 of the power management circuit 12 in FIG. 1A . Common elements between FIGS. 1A and 1B are shown with common element numbers and will not be re-described herein.

ETIC 14 inherently has an inductive impedance Z _ETIC that can be modeled by ETIC inductance L _ETIC . Conductive path 18 may also be associated with an inductive trace impedance Z _TRACE which may be modeled by trace inductance L _TRACE . Thus, looking from the power amplifier input 22 towards the ETIC 14, the power amplifier circuit 16 will see an output impedance _ZOUT comprising both the inductive impedance _ZETIC and the inductive trace impedance _ZTRACE .

The power amplifier circuit 16 can be modeled as a current source. In this regard, the power amplifier circuit 16 will modulate the load current I _LOAD based on the modulation voltage V _CC . The load current I _LOAD may interact with the output impedance Z _OUT to produce a voltage fluctuation V _CC-RP in the modulation voltage V _CC received at the power amplifier input 22 . In this regard, the voltage fluctuation V _CC-RP is a function of the modulating load current I _LOAD and the output impedance Z _OUT as shown in the following equation (Equation 1).

V _CC-RP = I _LOAD * Z _OUT (equation 1)

It is worth noting that, according to equation (Equation 1), the voltage fluctuation V _CC-RP can be reduced by reducing the output impedance Z _OUT seen at the power amplifier input 22 . In this regard, a conventional approach for reducing voltage fluctuation V _CC-RP in the power management circuit 12 of FIG. 1A is to add a decoupling capacitor C _PA inside the power amplifier circuit 16 and as close as possible to the power amplifier input 22 . By adding a decoupling capacitor C _PA , the output impedance Z _OUT can be simply expressed as an equation (Equation 2).

Z _OUT =Z _CPA ||(Z _ETIC +Z _TRACE ) (Equation 2)

In the equation (Equation 2), Z _CPA represents the capacitive impedance of the decoupling capacitor C _PA . The capacitive impedance Z _CPA and the inductive impedance Z _ETIC and Z _TRACE can each be determined according to the following equations (Equations 3.1-3.3).

|Z _CPA |=1/2πf*C _PA (equation 3.1)

|Z _ETIC |=2πf*L _ETIC (equation 3.2)

|Z _TRACE |=2πf*L _TRACE (equation 3.3)

In the equations (Equations 3.1-3.3), f represents the modulation frequency of the load current I _LOAD . In this regard, the capacitive impedance Z _CPA , the inductive impedance Z _ETIC and the inductive trace impedance Z _TRACE are each a function of the modulation frequency f. FIG. 1C is a graph providing an exemplary illustration of magnitude impedance versus modulation frequency f.

When the modulation frequency f is lower than 10MHz, the output impedance Z _OUT is dominated by the real part of the inductive impedance Z _ETIC and the real part of the inductive trace impedance Z _TRACE . Between 10MHz and 100MHz, the output impedance Z _OUT is dominated by the inductor impedance Z _ETIC and the inductor trace impedance Z _TRACE . Above 1000MHz, the output impedance Z _OUT will be dominated by the capacitive impedance Z _CPA .

Herein, the modulation bandwidth BW _MOD of the RF signal 24 may fall between 100 MHz and 1000 MHz (eg, 100-500 MHz). In this frequency range, the output impedance Z _OUT will be determined by the output impedance Z _OUT as expressed by the equation (Equation 2).

It is worth noting that according to the equations (Equations 2 and 3.1), the capacitive impedance Z _CPA and thus the output impedance Z _OUT will decrease as the capacitance C _PA increases. In this regard, conventional methods for reducing the fluctuating voltage V _CC-RP mainly rely on adding a decoupling capacitor C _PA with a larger capacitance (eg, 1F to 2F). However, doing so can cause some obvious problems.

It should be appreciated that the rate of change (ΔV _CC or dV/dt) of the modulation voltage V _CC may be oppositely affected by the capacitance of the decoupling capacitor C _PA as shown in the following equation (Equation 4).

ΔV _CC =I _CC /C _PA (Equation 4)

In the equation (Equation 4), I _CC represents the low frequency current (also known as cranking current) supplied through the ETIC 14 when the decoupling capacitor C _PA is charged or discharged. In this regard, the greater the capacitance that the decoupling capacitor C _PA has, the greater the amount of low frequency current I _CC required to vary the modulation voltage V _CC at the desired rate of change (ΔV _CC ). Therefore, existing transmit circuits 10 may negatively impact battery life.

If the low frequency current I _CC is kept at a low level to prolong battery life, the existing transmit circuit 10 may struggle to meet the required rate of change (ΔV _CC ), especially when RF is based on Orthogonal Frequency Division Multiplexing (OFDM) Signal 24 is modulated for transmission in the millimeter wave (mmWave) spectrum. Therefore, the existing transmit circuit 10 may not be able to vary the modulation voltage V _CC between OFDM symbols.

On the other hand, if reducing the capacitance of the decoupling capacitor C _PA helps improve the rate of change (ΔV _CC ) of the modulation voltage V _CC and reduces the starting current I _CC , doing so may result in an insufficient reduction of the output impedance Z _OUT , and thus cause voltage fluctuation V _CC-RP . Therefore, it is desirable to sufficiently reduce the fluctuation voltage V _{CC -RP} within the modulation bandwidth BW _MOD while increasing the rate of change (ΔV _CC ) of the modulation voltage V CC and reducing the starting current I _CC .

2 is an exemplary power configuration configured to reduce the voltage fluctuation V _CC-RP in the modulation voltage V _CC by reducing the output impedance Z _OUT presented at the power amplifier input 34 of the power amplifier circuit 36 according to an embodiment of the present disclosure. Schematic diagram of the management circuit 32. Here, power amplifier circuit 36 is configured to receive modulation voltage V _CC via conductive path 38 (eg, a conductive trace) and to amplify RF signal 40 based on modulation voltage V _CC . The power amplifier circuit 36 includes a decoupling capacitor C _PA . Similar to the decoupling capacitor C _PA in the power amplifier circuit 16 in FIG. 1A , a decoupling capacitor C _PA is also provided as close as possible to the power amplifier input 34 .

Power management circuitry 32 includes ETIC 42 . ETIC 42 includes voltage modulation circuitry 44 . The voltage modulation circuit 44 is configured to generate a modulation voltage V _CC at a voltage output 46 based on a modulation target voltage V _TGT . Here, voltage output 46 is coupled to power amplifier input 34 via conductive path 38 .

Similar to power management circuit 12 in FIG. 1A , decoupling capacitor C _PA has capacitive impedance Z _CPA , ETIC 42 inherently has inductive impedance Z _ETIC , and conductive path 38 is inherently associated with inductive trace impedance Z _TRACE , which can As represented in the equations (Equations 3.1-3.3). Accordingly, the power amplifier circuit 36 will see an output impedance Z _OUT as determined in equation (Equation 2) within the modulation bandwidth of the RF signal 40 (eg, 100-500 MHz). Here, the power amplifier circuit 36 also operates as a current source that can sense a modulated load current I _LOAD based on the modulated voltage V _CC . Similar to power management circuit 12 in FIG. 1A , modulated load current I _LOAD may interact with output impedance Z _OUT to produce a voltage ripple V _CC-RP in modulated voltage V _CC received at power amplifier input 34 .

In embodiments disclosed herein, decoupling capacitor C _PA has a smaller capacitance (eg, 100 pF) than decoupling capacitor C _PA in power amplifier circuit 16 in FIG. 1A . By adopting a smaller decoupling capacitor C _PA , it is possible to increase the rate of change (ΔV _CC ) of the modulation voltage V _CC to meet the serial requirements in advanced wireless systems such as fifth generation (5G) and 5G new radio (5G-NR). Current voltage switching time requirements (for example, according to OFDM symbol or sub-symbol), while reducing the starting current I _CC to prolong battery life.

Furthermore, the power management circuit 32 is configured to reduce the voltage fluctuation V in the modulation voltage V _CC by reducing the output impedance P _OUT presented at the power amplifier input 34 and/or creating a notch filter at the power amplifier input 34 _CC-RP . As a result, power management circuitry 32 may achieve defined performance thresholds, such as RMS EVM and/or peak EVM, within the modulation bandwidth of RF signal 40 .

In an embodiment, the voltage modulation circuit 44 includes a voltage amplifier 48 (denoted "VA"), which may be an operational amplifier (OpAmp), as an example. Voltage amplifier 48 is configured to generate an initial modulation voltage V _AMP at voltage amplifier output 50 based on modulation target voltage V _TGT and supply voltage V _SUP . Voltage modulation circuit 44 also includes an offset capacitor C _OFF coupled between voltage amplifier output 50 and voltage output 46 . Offset capacitor C _OFF is configured to boost initial modulation voltage V _AMP by offset voltage V _OFF to produce modulation voltage V _CC at voltage output 46 (V _CC =V _AMP +V _OFF ).

Voltage amplifier 48 is also configured to receive modulation voltage feedback V _CC-FB indicative of modulation voltage V _CC at voltage output 46 , thereby making voltage modulation circuit 44 a closed loop circuit. Accordingly, the voltage amplifier 48 can adjust the initial modulation voltage V _AMP , and thus the modulation voltage V _CC , based on the modulation feedback V _CC-FB to better track the modulation target voltage V _TGT .

Voltage amplifier 48 includes an input/bias stage 52 and an output stage 54 . Output stage 54 is coupled in series to voltage amplifier output 50 . According to an embodiment of the present disclosure, output stage 54 is configured to receive power amplifier voltage feedback V _CC-PA-FB indicative of modulation voltage V _CC as received at power amplifier input 34 . Output stage 54 may receive power amplifier voltage feedback V _CC-PA-FB via feedback path 56 . Like conductive path 38 , feedback path 56 is associated with an inductive feedback trace impedance Z _TRACE-FB that can be modeled by feedback inductance L _TRACE-FB .

It will be appreciated that since the power amplifier voltage feedback V _CC-PA-FB is provided from the power amplifier input 34, the power amplifier voltage feedback V _CC-PA-FB will contain the modulation voltage V as received at the power amplifier input 34 The voltage in _CC fluctuates V _CC-RP . Therefore, the voltage amplifier 48 can modify the initial modulation voltage V _AMP based on the power amplifier voltage feedback V _CC-PA-FB such that the output impedance Z _OUT is reduced at the power amplifier input 34 , thus helping to reduce the output impedance Z OUT at the power amplifier input 34 . The voltage fluctuation V _CC-RP in the modulation voltage V _CC received at .

As an example, ETIC 42 may contain control circuitry 58, which may be a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). In an embodiment, control circuit 58 may control voltage amplifier 48, eg, via control signal 60, to modify initial modulation voltage V _AMP based on power amplifier voltage feedback V _CC-PA-FB , thereby reducing output impedance Z _OUT at power amplifier input 34 .

FIG. 3 is a schematic diagram providing an exemplary illustration of the internal structure of voltage amplifier 48 in FIG. 2 . Common elements between Figures 2 and 3 are shown here with common element numbers and will not be described repeatedly herein.

In an embodiment, input/bias stage 52 is configured to receive modulation voltage V _TGT and modulation voltage feedback V _CC-FB . Accordingly, the input/bias stage 52 generates a pair of bias signals 62P (also referred to as a first bias signal), 62N (also referred to as a second bias signal) to control the output stage 54 .

In an embodiment, the output stage 54 is configured to generate an initial modulation voltage V _AMP at the voltage amplifier output 50 based on a selected one of the bias signals 62P, 62N. Output stage 54 is also configured to receive power amplifier voltage feedback V _CC-FB . Accordingly, output stage 54 may modify initial modulation voltage V _AMP based on power amplifier voltage feedback V _CC-FB to reduce output impedance Z _OUT and thereby reduce voltage fluctuation V _CC-RP at power amplifier input 34 .

In an embodiment, the output stage 54 includes a first transistor 64P and a second transistor 64N. In a non-limiting example, first transistor 64P is a p-type field effect transistor (pFET), and second transistor 64N is an n-type field effect transistor (nFET). In this example, the first transistor 64P includes a first source electrode C ₁ , a first drain electrode D ₁ , and a first gate electrode G ₁ , and the second transistor 64N includes a second source electrode C ₂ , a second drain electrode D ₂ and the second gate electrode G ₂ . Specifically, the first drain electrode _D1 is configured to receive the supply voltage V _SUP , the second drain electrode D2 is coupled to ground (GND), and both the first source electrode _C1 and the second source electrode _C2 are coupled to the voltage amplifier output 50.

The first gate electrode _G1 is coupled to the input/bias stage 52 to receive a bias signal 62P, and the second gate electrode _G2 is coupled to the input/bias stage 52 to receive a bias signal 62N. Here, input/bias stage 52 is configured to generate bias signal 62P in response to an increase in modulation voltage V _CC or to generate bias signal 62N in response to a decrease in modulation voltage V _CC . Specifically, the first transistor 64P will be turned on in response to receiving the bias signal 62P to output the initial modulation voltage V _AMP and provide a high frequency current I _AMP (for example, alternating current) from the supply voltage V _SUP , and the second transistor 64N will be turned on in response to receiving the bias signal 62N to output the initial modulation voltage V _AMP from the supply voltage V _SUP and sink the high frequency current I _AMP to GND.

In this embodiment, the output stage 54 further includes a first Miller capacitor C _Miller1 and a second Miller capacitor C _Miller2 . Specifically, a first Miller capacitor C _Miller1 is coupled between the voltage amplifier output 50 and the first gate electrode _G1 , and a second Miller capacitor C _Miller2 is coupled between the voltage amplifier output 50 and the second gate electrode _G2 . In this regard, output stage 54 may be considered a typical Class AB rail-to-rail OpAmp output stage. The first Miller capacitor C _Miller1 and the second Miller capacitor C _Miller2 can not only stabilize the control of the first transistor 64P and the second transistor 64N (eg, alleviate the so-called Miller effect), but also reduce the voltage amplifier 48 closed-loop output impedance.

It is worth noting that since the first Miller capacitor C _Miller1 and the second Miller capacitor C _Miller2 are each coupled to the voltage amplifier output 50, the first Miller capacitor C _Miller1 and the second Miller capacitor C _Miller2 can only be reduced as in The inductive impedance Z _ETIC is a fraction of the output impedance Z _OUT seen at the power amplifier input 34 . Therefore, in order to further reduce the output impedance Z _OUT , it is also necessary to reduce the inductive trace impedance Z _TRACE .

In this regard, the output stage 54 further includes a first resistor-capacitor (RC) circuit 66P and a second RC circuit 66N. First RC circuit 66P and second RC circuit 66N are each coupled to power amplifier input 34 via feedback path 56 to receive power amplifier voltage feedback V _CC-FB . Specifically, a first RC circuit 66P is coupled between the power amplifier input 34 and the first gate electrode _G1 , and a second RC circuit 66N is coupled between the power amplifier input 34 and the second gate electrode _G2 . Accordingly, the first RC circuit 66P may combine the power amplifier voltage feedback V _CC-FB with the bias signal 62P, thereby modifying the bias signal 62P. Similarly, the second RC circuit 66N may combine the power amplifier voltage feedback V _CC-FB with the bias signal 62N, thereby modifying the bias signal 62N.

In an embodiment, the first RC circuit 66P includes a first adjustable resistor R _FB1 and a first adjustable capacitor C _FB1 , and the second RC circuit 66N includes a second adjustable resistor R _FB2 and a second adjustable capacitor C _FB2 . The invocation of the feedback path 56 associated with the inductive feedback trace impedance Z _TRACE-FB may be modeled by the feedback inductance L _TRACE-FB . Thus, the first adjustable resistor R _FB1 , the first adjustable capacitor C _FB1 and the feedback inductance L _TRACE-FB can be identified with a first resistor-inductor-capacitor (RLC) circuit having The first resonant frequency f ₁ expressed in the text equation (Equation 5).

Likewise, the second adjustable resistor R _FB2 , the second adjustable capacitor C _FB2 and the feedback inductance L _TRACE-FB can be identified with a second RLC circuit having the following equation (Equation 6) The second resonant frequency f ₂ represented in .

According to the equations (Equations 5 and 6), the first adjustable capacitor C _FB1 and the second adjustable capacitor C _FB2 can be individually adjusted to resonate with the feedback inductance L _TRACE-FB so that at the first resonant frequency f ₁ and the second A corresponding one of the two resonant frequencies _f2 creates a low impedance feedback path. The first adjustable resistor R _FB1 will de-Q the first resonant frequency _f1 over the modulation bandwidth BW _MOD to prevent the first adjustable capacitor C _FB1 and the feedback inductance L _TRACE-FB from entering at the first resonant frequency _f1 oscillation. Likewise, the second adjustable resistor R _FB2 will de-Q the second resonant frequency _f2 over the modulation bandwidth BW _MOD to prevent the second adjustable capacitor C _FB2 and the feedback inductance L _TRACE-FB at the second resonant frequency f ₂ goes into oscillation.

When the voltage fluctuation _VCC-RP seen at the power amplifier input 34 is fed back to the first gate electrode _G1 or the second gate electrode _G2 , the first transistor 64P and the second transistor 64N can act like a common source amplifier Functioning, it amplifies and inverts the initial modulation voltage V _AMP at the voltage amplifier output 50 , and thus amplifies and inverts the voltage output 46 of the ETIC 42 . Reversing the initial modulation voltage V _AMP will cause more of the load current I _LOAD to flow through the conduction path 38 (aka trace inductor L _TRACE ) to GND rather than through the power amplifier circuit 36, thus reducing the inductance of the trace impedance Z _TRACE , and thus reduces the output impedance Z _OUT at the input 34 of the power amplifier.

Therefore, by adjusting the first adjustable capacitor C _FB1 , the first adjustable resistor R _FB1 , the second adjustable capacitor C _FB2 and/or the second adjustable resistor R _FB2 , it is possible to reduce the output impedance Z _OUT to The entire modulation bandwidth BW _MOD . In an embodiment, the first adjustable capacitor C _FB1 , the first adjustable resistor R _FB1 , the second adjustable capacitor C _FB2 , and/or the second adjustable resistor R _FB2 are adjustable by the control circuit 58 via the control signal 60 .

Help reduce the inductive trace impedance Z _ETIC by employing a first Miller capacitor C _Miller1 and a second Miller capacitor C _Miller2 , and further employ a first RC circuit 66P and a second RC circuit 66N to help reduce the inductive trace impedance Z _TRACE , it is possible to reduce the output impedance Z _OUT , thereby reducing the voltage fluctuation V _CC-RP in the modulation voltage V _CC . The simulation shows that under the 200MHz load current modulation frequency, the power management circuit 32 can reduce the RMS value of the voltage fluctuation VCC _-RP from 231mV to 134mV, as shown in the power management circuit 12 in FIG. 1A, which is equivalent to improving 42%.

Referring to FIG. 2 , the ETIC 42 further includes a switching circuit 68 . In an embodiment, switching circuit 68 includes a multilevel charge pump (MCP) 70 coupled to voltage output 46 via power inductor L _P . As an example, MCP 70 may be a buck-boost voltage converter configured to generate a low frequency voltage V _DC based on a battery voltage V _BAT . Specifically, the MCP 70 can operate in a buck mode to generate a low frequency voltage V _DC at 0×V _BAT or 1×V _BAT , or in a boost mode to generate a low frequency voltage V _DC at 2×V _BAT . Thus, by configuring MCP 70 to switch between 0×V _BAT , 1×V _BAT and/or 2×V _BAT based on an appropriate duty cycle, MCP 70 can generate a low frequency voltage V _DC at multiple voltage levels .

The power inductor L _P is configured to induce a low frequency current I _CC (also referred to as cranking current) based on the low frequency voltage V _DC . As previously described in FIG. 1A , the low frequency current I _CC is provided to the power amplifier input 34 to charge the decoupling capacitor C _PA .

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (20)

1. A power management circuit, the power management circuit comprising:

a power amplifier circuit configured to amplify a Radio Frequency (RF) signal based on a modulated voltage received at a power amplifier input, wherein the modulated voltage received at the power amplifier input comprises voltage fluctuations caused by an output impedance presented at the power amplifier input; and

an envelope tracking integrated circuit ETIC, the ETIC comprising:

a voltage output coupled to the power amplifier input via a conductive path; and

a voltage modulation circuit configured to:

generating a modulation voltage at the voltage output based on a modulation target voltage;

receiving a power amplifier voltage feedback indicative of the voltage fluctuations in the modulated voltage received at the power amplifier input; and is also provided with

The modulation voltage is modified based on the power amplifier voltage feedback to cause the output impedance to decrease, thereby reducing the voltage ripple in the modulation voltage received at the power amplifier input.

2. The power management circuit of claim 1, wherein the output impedance presented at the power amplifier input comprises an inductive impedance of the ETIC and an inductive trace impedance associated with the conductive path.

3. The power management circuit of claim 2, wherein the voltage modulation circuit comprises:

a voltage amplifier configured to generate an initial modulated voltage at a voltage amplifier output based on the modulated target voltage; and

an offset capacitor configured to step up the initial modulation voltage by an offset voltage to produce the modulation voltage at the voltage output.

4. The power management circuit of claim 3, wherein the voltage amplifier comprises an output stage configured to:

generating the initial modulation voltage at the voltage amplifier output;

receiving the power amplifier voltage feedback, the power amplifier voltage feedback being indicative of the voltage fluctuations in the modulated voltage received at the power amplifier input; and is also provided with

The initial modulation voltage is modified based on the power amplifier voltage feedback to cause the output impedance to decrease, thereby reducing the voltage ripple in the modulation voltage received at the power amplifier input.

5. The power management circuit of claim 4, wherein the voltage amplifier further comprises an input/bias stage configured to:

receiving the modulation target voltage and a modulation voltage feedback indicative of the modulation voltage at the voltage output; and is also provided with

A pair of bias signals is generated based on the modulation target voltage and the modulation voltage feedback, thereby causing the output stage to generate the initial modulation voltage.

6. The power management circuit of claim 5, wherein the output stage comprises:

a first transistor, the first transistor comprising:

a first drain electrode configured to receive a supply voltage;

a first gate electrode configured to receive a first bias signal of the pair of bias signals; and

a first source electrode coupled to the voltage amplifier output; and

a second transistor, the second transistor comprising:

a second source electrode coupled to the voltage amplifier output;

a second gate electrode configured to receive a second bias signal of the pair of bias signals; and

a second drain electrode coupled to ground;

wherein a selected one of the first transistor and the second transistor is biased by a selected one of the first bias signal and the second bias signal to output the initial modulation voltage at the voltage amplifier output.

7. The power management circuit of claim 6, wherein the output stage further comprises:

a first miller capacitor coupled between the first gate electrode and the first source electrode and configured to reduce an impedance at the voltage output, thereby reducing the inductive impedance of the ETIC when the first transistor is biased by the first bias signal; and

a second miller capacitor coupled between the second gate electrode and the second source electrode and configured to reduce the impedance at the voltage output, thereby reducing the inductive impedance of the ETIC when the second transistor is biased by the second bias signal.

8. The power management circuit of claim 6, wherein the output stage further comprises:

a first resistor-capacitor (RC) circuit coupled between the power amplifier input and the first gate electrode and configured to combine the power amplifier voltage feedback with the first bias signal, thereby reducing the inductive trace impedance at the power amplifier input; and

a second RC circuit coupled between the power amplifier input and the second gate electrode and configured to combine the power amplifier voltage feedback with the second bias signal, thereby reducing the inductive trace impedance at the power amplifier input.

9. The power management circuit of claim 8, wherein the first RC circuit and the second RC circuit each comprise a respective adjustable resistor and a respective adjustable capacitor coupled in series between the power amplifier input and a respective one of the first gate electrode and the second gate electrode.

10. The power management circuit of claim 9, wherein the ETIC further comprises a control circuit configured to adjust at least one of the respective adjustable resistor and the respective capacitor in a respective one of the first RC circuit and the second RC circuit to cause the output impedance within a modulation bandwidth of the power amplifier circuit to decrease.

11. An envelope tracking integrated circuit ETIC, the ETIC comprising:

a voltage output coupled to a power amplifier circuit via a conductive path, the power amplifier circuit configured to amplify a Radio Frequency (RF) signal based on a modulated voltage received at a power amplifier input, wherein the modulated voltage received at the power amplifier input comprises a voltage ripple caused by an output impedance presented at the power amplifier input; and

a voltage modulation circuit configured to:

generating a modulation voltage at the voltage output based on a modulation target voltage;

receiving a power amplifier voltage feedback indicative of the voltage fluctuations in the modulated voltage received at the power amplifier input; and is also provided with

The modulation voltage is modified based on the power amplifier voltage feedback to cause a decrease in the output impedance to reduce the voltage ripple in the modulation voltage received at the power amplifier input.

12. The ETIC of claim 11, wherein the output impedance presented at the power amplifier input includes an inductive impedance of the ETIC and an inductive trace impedance associated with the conductive path.

13. The ETIC of claim 12, wherein the voltage modulation circuit includes:

a voltage amplifier configured to generate an initial modulated voltage at a voltage amplifier output based on the modulated target voltage; and

an offset capacitor configured to step up the initial modulation voltage by an offset voltage to produce the modulation voltage at the voltage output.

14. The ETIC of claim 13, wherein the voltage amplifier includes an output stage configured to:

generating the initial modulation voltage at the voltage amplifier output;

receiving the power amplifier voltage feedback, the power amplifier voltage feedback being indicative of the voltage fluctuations in the modulated voltage received at the power amplifier input; and is also provided with

The initial modulation voltage is modified based on the power amplifier voltage feedback to cause the output impedance to decrease, thereby reducing the voltage ripple in the modulation voltage received at the power amplifier input.

15. The ETIC of claim 14, wherein the voltage amplifier further comprises an input/bias stage configured to:

receiving the modulation target voltage and a modulation voltage feedback indicative of the modulation voltage at the voltage output; and is also provided with

A pair of bias signals is generated based on the modulation target voltage and the modulation voltage feedback, thereby causing the output stage to generate the initial modulation voltage.

16. The ETIC of claim 15, wherein the output stage includes:

a first transistor, the first transistor comprising:

a first drain electrode configured to receive a supply voltage;

a first gate electrode configured to receive a first bias signal of the pair of bias signals; and

a first source electrode coupled to the voltage amplifier output; and

a second transistor, the second transistor comprising:

a second source electrode coupled to the voltage amplifier output;

a second gate electrode configured to receive a second bias signal of the pair of bias signals; and

a second drain electrode coupled to ground;

wherein a selected one of the first transistor and the second transistor is biased by a selected one of the first bias signal and the second bias signal to output the initial modulation voltage at the voltage amplifier output.

17. The ETIC of claim 16, wherein the output stage further comprises:

a first miller capacitor coupled between the first gate electrode and the first source electrode and configured to reduce an impedance at the voltage output, thereby reducing the inductive impedance of the ETIC when the first transistor is biased by the first bias signal; and

a second miller capacitor coupled between the second gate electrode and the second source electrode and configured to reduce the impedance at the voltage output, thereby reducing the inductive impedance of the ETIC when the second transistor is biased by the second bias signal.

18. The ETIC of claim 16, wherein the output stage further comprises:

a first resistor-capacitor (RC) circuit coupled between the power amplifier input and the first gate electrode and configured to combine the power amplifier voltage feedback with the first bias signal, thereby reducing the inductive trace impedance at the power amplifier input; and

a second RC circuit coupled between the power amplifier input and the second gate electrode and configured to combine the power amplifier voltage feedback with the second bias signal, thereby reducing the inductive trace impedance at the power amplifier input.

19. The ETIC of claim 18, wherein the first RC circuit and the second RC circuit each include a respective adjustable resistor and a respective adjustable capacitor coupled in series between the power amplifier input and a respective one of the first gate electrode and the second gate electrode.

20. The ETIC of claim 19, wherein the ETIC further includes a control circuit configured to adjust at least one of the respective adjustable resistor and the respective capacitor in a respective one of the first RC circuit and the second RC circuit to cause the output impedance within a modulation bandwidth of the power amplifier circuit to decrease.