CN116482960A - Resource-saving short-chain structure time-to-digital converter and conversion method thereof - Google Patents
Resource-saving short-chain structure time-to-digital converter and conversion method thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of time measurement, and discloses a resource-saving short-chain structure time digital converter and a conversion method thereof, wherein a local oscillator is built by using a delay unit and a conversion circuit, and an input signal is overturned to an output state at fixed time intervals within continuous high-level time; the time of the level generation turning of the local oscillator is known, the time of the last turning is obtained by using the TDL TDC, and the time of the starting moment and the time of the last turning are obtained by recording the turning times of the local oscillator. The time-to-digital conversion method of the resource-saving short-chain structure provided by the invention has good linearity, and completely avoids the problem of nonlinearity caused by inconsistent line length introduced by crossing a plurality of resource blocks; the resource-saving short-chain structure time-to-digital converter has the advantages of simple and flexible structure, low resource consumption and high utilization rate; the robustness is good, the method can be directly transplanted between different channels and even devices, and drift caused by temperature can be corrected on line.
Description
Technical Field
The invention belongs to the technical field of time measurement, and particularly relates to a resource-saving short-chain structure time-to-digital converter and a conversion method thereof.
Background
Currently, a time-to-digital converter (Time to Digital Converter, TDC) is widely used in various fields including biomedicine, communication engineering, etc., as a time measuring tool having picosecond accuracy. Simple TDCs can be implemented by counting directly the number of variations of the high frequency clock, which is then limited to the clock frequency, typically in the nanosecond range.
Existing TDCs can be categorized into analog scheme-based TDCs and digital scheme-based TDCs depending on the implementation. The analog scheme-based TDC includes time-to-amplitude conversion or time stretching. On one hand, the method introduces analog quantity in realization, and the analog quantity is easy to be interfered by noise, so that a test result is easy to be interfered by the noise; on the other hand, the single measurement time of these methods is often longer than the time interval to be measured, i.e. longer conversion time, which results in too long dead time and thus failure to perform high frequency measurement. Thus, while analogue scheme based TDCs can achieve better nonlinear performance, even sub-picosecond time resolution, they are not common. In contrast, digital scheme based TDCs are more popular because they can be deployed and iterated (on FPGA) faster, have a more compact hardware architecture, are flexible, and are more tolerant of noise interference.
The first digital solution is an interpolation scheme, the Nutt method, the basic idea of which is to interpolate the system clock with a number of delay units (usually carry modules in FPGAs). In the Nutt method, the time to be measured is divided into two parts of a coarse time and a fine time, wherein the coarse time is directly obtained by using a high-frequency system clock, namely, the variation number of the system clock in the time interval to be measured is counted; the "fine" time is obtained by concatenating a series of delay elements together to form a long chain (also called a tapped delay line, tapped Delay Line, TDL), interpolating between the system clocks, and counting the number of delay elements in the chain that are triggered. The measurement of the "fine" time can be achieved by the code density test to obtain the delay time that each delay element in the TDL chain can cause, and the number of triggers of these elements can be obtained directly by measurement, so that the value of the "fine" time can be obtained. The final time interval can be calculated directly by combining the "coarse" time and the "fine" time.
The premise of this approach is that each delay element on the TDL chain is required to have the same delay time, which also determines the time resolution of the measurement. However, the characteristics of these delay cells are susceptible to device inherent defects, voltage and temperature dynamics, and the like, resulting in serious non-linearity problems. Furthermore, the inherent delay of each delay cell is determined by its manufacturing process and cannot be modified, so once the hardware platform is determined, the time resolution of the TDC is determined. To solve these problems, numerous methods have been proposed, which can be largely classified into a multi-chain averaging topology, a vernier method, a bin-to-bin calibration, and a WaveUnion architecture.
While the above approaches can improve performance in some aspects of TDC, they often require some sacrifice, which in turn leads to other problems. For example, a multi-chain average topology may occupy more resources. The vernier method can greatly alleviate nonlinear defects existing in the equipment, improve time resolution and even exceed inherent time delay of a delay unit, but needs more logic resources and longer conversion rate, and leads to longer dead time. The bin-to-bin calibration method can only alleviate the nonlinear problem of the delay unit, has poor expansibility, needs to be reprocessed when changing the channel position or replacing the hardware platform, and reduces the robustness. The WaveUnion approach, while saving resources, requires a complex ring oscillator design whose performance depends on non-uniformity among delay cells. However, as semiconductor manufacturing processes are advanced, such non-uniformities have not been serious.
TDC designs using Application-specific integrated circuits (ASIC) can significantly solve the above problems, achieving better TDC performance, but they require longer design cycles and higher manufacturing costs on the one hand, resulting in slow technical iterations, thus greatly limiting development speed; on the other hand, they cannot be reused, resulting in poor flexibility. Thus, only experienced and resource-rich communities have a strong choice of ASIC-based solutions. This phenomenon may inhibit innovation to some extent, so many TDC designs often use FPGAs for verification and ASICs for batch streaming.
Conventional TDCs typically string delay cells together in a straight line. For example, the TDC based on the FPGA is formed by taking a carry unit of the FPGA as a delay unit in a string. To ensure that the resources on the TDC chain are able to fully "interpolate" the system clock, the requirement that the overall delay chain produce an inherent delay greater than the clock period of the counter is often referred to as a clock condition. The delay generated by the whole delay chain is determined by the inherent delay of each delay unit and the total number of delay units, so when the inherent delay of the delay units is small under the condition of fixed counter clock, a large number of delay units are needed, and the traditional single-chain TDC is long in series on the FPGA, which also causes the following technical problems:
(1) The linearity is poor. An ideal TDC requires the same transfer delay between each delay unit in order to ensure high linearity. However, only delay units in the same resource block can guarantee good consistency in practice; delay cells among different resource blocks have serious nonlinear problems due to large differences in wiring resources, which result in large differences in inherent delays.
(2) The error is large. When the TDC chain length is too long, the problem of "bubbles" is aggravated, i.e. when a signal passes through one chain, all delay cells it has experienced are theoretically triggered, i.e. the output should be all "1" (or conversely "0"), whereas when the chain length is long, there may be many "0" s in the trigger segment of all "1". This will severely interfere with the measurement of TDC.
(3) The robustness is poor. The inherent delay time of the delay unit is greatly influenced by temperature, and when the temperature change is large, the linearity of the delay unit in the chain is influenced, the integral inherent delay is offset, and errors are caused to measurement.
Through the above analysis, the problems and defects existing in the prior art are as follows:
(1) The existing TDC based on the simulation scheme introduces an analog quantity in the implementation, and the analog quantity is easily interfered by noise, so that a test result is easily interfered by the noise; the single measurement time is often higher than the time interval to be measured, and longer conversion time leads to overlong dead time, so that high-frequency measurement cannot be performed.
(2) The characteristics of the delay unit of the existing Nutt method are easily influenced by inherent defects of devices, dynamic changes of voltage and temperature and the like, so that serious nonlinear problems are caused; the inherent delay of each delay cell cannot be modified as determined by the manufacturing process, and the time resolution of the TDC after the hardware platform is determined.
(3) The existing vernier method itself requires more logic resources and longer conversion rate, resulting in longer dead time; the bin-to-bin calibration method has poor expansibility, and needs to be reprocessed when the channel position is changed or a hardware platform is replaced, so that the robustness is reduced; the WaveUnion approach requires a complex ring oscillator design.
(4) The existing TDC design method using an application-specific integrated circuit requires a longer design period and higher manufacturing cost, so that the technology is slow in iteration and development speed is limited; and cannot be reused, resulting in poor flexibility; however, the conventional TDC has problems of poor linearity, large error and poor robustness.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a resource-saving short-chain structure time-to-digital converter and a conversion method thereof.
The invention is realized in such a way that a resource-saving short-chain structure time digital conversion method comprises the following steps: a local oscillator is built by using a delay unit and a conversion circuit, and an input signal is turned over to an output state at fixed time intervals within a continuous high-level time; and obtaining the time between the starting moment and the last time of turning by recording the turning times of the local oscillator.
Further, the time at which the local oscillator causes the level to flip is known. The local oscillator means that it is seen on the delay chain that the signal level is regularly flipped during the measurement. The time at which each level flip occurs is determined by the time difference of the delay cells (on the non-delay chain). When the start of the signal arrives at the delay chain, the delay unit and the conversion circuit (on the non-delay chain) will flip the level signal on the delay chain at regular intervals (specifically, the delay time difference of the delay unit), so that the delay unit and the conversion circuit act as a local oscillator. Wherein the oscillation time or period of the local oscillator can be freely configured, and is not necessarily required to be periodic.
Further, the time of the last flip is obtained by using the TDL TDC. The end time of the signal and the time of the last turn of the oscillator are observed on the delay chain. The time from the start of the signal observed on the delay chain to the last flip of the signal is determined by the configuration process, which time is known. The time from the last turning to the end of the signal is uncertain and can be measured by the trigger state on the delay chain, i.e. how many delay cells are triggered. Thus, by means of two-stage measurement, a total fine time component can be obtained.
Further, in an actual implementation, the local oscillator generates at most two inversions, and the number of specific inversions is determined according to the clock condition and the delay chain measurement range.
Further, the resource-saving short-chain structure time-to-digital conversion method further comprises the following steps:
the method comprises the steps that a local oscillator is formed by a first delay unit, a second delay unit and a conversion circuit, and time interval measurement is carried out on a signal to be detected by combining the local oscillator with a TDL TDC; the delay unit in the local oscillator is freely configured through software, and is preferably IDELAY resources in the Xilinx FPGA; the delay cells in the delay chain have a fixed delay, preferably carrier 4/8 resources in the Xilinx FPGA.
Further, the resource-saving short-chain structure time-to-digital conversion method further comprises the following steps:
the input of the TDL TDC delay chain is the output waveform of the conversion circuit, and the measurement range Mtau meets the condition Mtau>ΔT 2 -ΔT 1 Clock condition Mτ>T clk +ΔT 1 -ΔT 2 The method comprises the steps of carrying out a first treatment on the surface of the Where M is the number of delay cells in the delay chain, τ is the inherent delay of the delay cells, T clk Is the "coarse" clock period of the system.
When a signal with a time interval of Deltat is input, a start time T s ＝ΔT i +M s *τ+N s *T clk End time T e ＝ΔT j +M e *τ+N e *T clk The method comprises the steps of carrying out a first treatment on the surface of the Where i, j denote the number of times the local oscillator output signal toggles between rising and falling edges of the input signal, M s And M e Indicating the number of triggered units on the delay chain, N s And N e Representing the integer value of the coefficient clock, Δt=t e -T s ＝(N e -N s )*T clk +(ΔT j -ΔT i )+(M e -M s )*τ。
Another object of the present invention is to provide a resource-saving short-chain structure time-to-time converter applying the method, wherein the resource-saving short-chain structure time-to-time converter includes a first delay unit, a second delay unit, and a conversion circuit; wherein the delay time of the first delay unit and the second delay unit is respectively delta T 1 、ΔT 2 And DeltaT 2 >ΔT 1 The method comprises the steps of carrying out a first treatment on the surface of the The signals are converted into two paths of delay signals after passing through the first delay unit and the second delay unit, and are directly input into the conversion circuit to be converted into one path of signals.
It is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of the resource-efficient short-chain structure time-to-digital conversion method.
It is a further object of the present invention to provide a computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of the resource-efficient short-chain structure time-to-digital conversion method.
Another object of the present invention is to provide an information data processing terminal, where the information data processing terminal is configured to implement the resource-saving short-chain structure time-to-digital converter.
In combination with the technical scheme and the technical problems to be solved, the technical scheme to be protected has the following advantages and positive effects:
first, aiming at the technical problems in the prior art and the difficulty of solving the problems, the technical problems solved by the technical proposal of the invention are analyzed in detail and deeply by tightly combining the technical proposal to be protected, the results and data in the research and development process, and the like, and some technical effects brought after the problems are solved have creative technical effects. The specific description is as follows:
1. the linearity is good. The time-to-digital conversion method provided by the invention utilizes the delay unit and the conversion circuit to build the local oscillator, and further subdivides the system clock period, so that the measurement range of the delay chain in the TDL TDC is reduced, the number of delay units required by the delay chain in the TDL TDC is reduced under the condition that the inherent delay of the delay unit is unchanged, and thus, all the delay units are placed in one logic block, and the problem of nonlinearity caused by inconsistent line lengths which are led across a plurality of resource blocks is completely avoided.
2. Simple and flexible structure, low resource consumption and high utilization rate. The resource-saving short-chain structure time digital conversion method provided by the invention has a simple and flexible structure, the system clock period can be subdivided only by setting up the local oscillator by combining a fixed delay unit with a small amount of basic logic gate resources, and then the system clock period can be further measured by utilizing a short delay chain set up by a small amount of delay units, so that the resource consumption is reduced. Meanwhile, due to the adoption of the short delay chain, the layout can be more compact, so that the resource waste caused by the layout is reduced, and the resource utilization rate is improved. In contrast, when long-chain resources are laid out in a limited space, the unused portion may not be able to re-distribute the next chain, resulting in resource waste. This is similar to memory allocation in a computer system, long chains are equivalent to empty regions with contiguous large block addresses, while short chains are equivalent to small segments of memory in different spaces. Memory with continuous large block addresses is a well-known scarce resource and is very limited; and the free area of the small block has more memory, so that the resource utilization rate can be improved by successfully utilizing the memory.
3. The robustness is good, the method can be directly transplanted between different channels and even devices, and drift caused by temperature can be corrected on line. The device has better similarity, namely better consistency, of the adjacent resources when in production and manufacture, and the property cannot be changed along with channel change or device change. Therefore, the TDC built based on adjacent position resources is better in time delay consistency of each delay unit, and when the TDC is transplanted to other channels and even other devices, the consistency is still reserved, so that the TDC is better in robustness. In addition, the invention adopts logic resources capable of freely configuring delay time, such as IDELAY units in Xilinx FPGA, which are not sensitive to temperature, and the local oscillator built by the resources can generate level signals with the constant turnover time interval along with the temperature, and the change of the number of triggered units on the delay chain under different temperatures can be measured in the turnover time interval by matching with the delay chain, so that the inherent delay time of a single delay unit under different temperature conditions can be obtained, and the drift caused by the temperature change is further compensated.
Secondly, the technical scheme is regarded as a whole or from the perspective of products, and the technical scheme to be protected has the following technical effects and advantages:
(1) The technical effects are as follows: one of the criteria for measuring the performance of a TDC is DNL and INL, and the smaller the value is, the better the linearity is, the better the performance is, and the DNL and INL of the TDC which are usually qualified are smaller than 1LSB. The code density test result of the TDC shows that the INL and DNL of the TDC are lower than 0.6LSB without any calibration method, and the TDC has excellent performance.
(2) The advantages are that: the TDC needs to be capable of accurately measuring time in application, and the accuracy mainly depends on the minimum resolution and linearity of the TDC.
Thirdly, as inventive supplementary evidence of the claims of the present invention, the following important aspects are also presented:
(1) The technical scheme of the invention fills the technical blank in the domestic and foreign industries: traditional TDC has poor linearity, poor robustness, complex structure and low resource utilization rate. In order to solve the problem of linearity and time resolution, more resources are needed to be introduced, so that the resource consumption is higher and the structure is more complex; or require a lot of effort to calibrate, making robustness very poor. Although the performance is improved, the method has great cost, is difficult to be widely applied, and is difficult to popularize especially in a multi-channel scene, and the resource-saving short-chain structure time-to-digital converter provided by the invention fills the blank of the technology.
(2) The technical scheme of the invention solves the technical problems that people are always desirous of solving but are not successful all the time: while current digital circuit-based TDCs have serious nonlinearity problems, typical solutions require excessive resource or time costs, the TDC architecture of the present invention uses very few resources and can perfectly solve the nonlinearity problems without calibration (i.e., without additional time and computation costs).
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for converting a time to a digital value of a resource-saving short-chain structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a resource-saving short-chain structure time-to-digital conversion method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a "fine" time measurement section provided by an embodiment of the present invention;
fig. 4A is a graph of experimental effects of a TDC according to an embodiment of the present invention in a code density test;
fig. 4B is an experimental effect diagram of the TDC in DNL provided by the embodiment of the present invention;
fig. 4C is a graph showing experimental effects of TDC in INL according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In view of the problems existing in the prior art, the present invention provides a resource-saving short-chain structure time-to-digital converter and a conversion method thereof, and the present invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the resource-saving short-chain structure time-to-digital conversion method provided by the embodiment of the invention includes the following steps:
s101, a local oscillator is built by using a delay unit and a conversion circuit, and an input signal is turned over to an output state at fixed time intervals within a continuous high-level time;
s102, acquiring the time of last overturn by using a TDL TDC;
s103, knowing the time when the local oscillator causes the level to turn over, and obtaining the time of the initial moment and the last turn over by recording the turn over times of the local oscillator.
The core idea of the resource-saving short-chain structure time digital conversion method is that a delay unit and a conversion circuit are utilized to build a local oscillator, an input signal is overturned to the output state of the local oscillator at fixed time intervals within the continuous high-level time, the time for the level to be overturned is known because of the local oscillator, and the time between the initial time and the last time of the overturned can be obtained by recording the times of the overturned of the local oscillator. And the time of the last flip is obtained using TDL TDC. The level inversion generated by the local oscillator divides the coarse clock of the system, so that the measurement range of the fine time required by the TDL TDC is reduced, namely the measurement range required by the TDC delay chain is smaller, the number of the delay units required is smaller under the condition that the delay sizes of the delay units of the delay chain are unchanged, and the consumed resources are lower. Taking the example that the local oscillator generates at most two inversions here, in a practical implementation process, the local oscillator may be required to generate at most more than two inversions, and the specific number of inversions is determined according to the clock condition and the delay chain measurement range.
Fig. 2 is a basic schematic diagram of time interval measurement of a signal to be measured by using a local oscillator in combination with a TDL TDC according to an embodiment of the present invention. The first delay unit, the second delay unit and the conversion circuit form a local oscillator, wherein the delay time of the first delay unit and the delay time of the second delay unit are respectively delta T 1 、ΔT 2 Require DeltaT 2 >ΔT 1 . The signals are converted into two paths of delay signals after passing through the first delay unit and the second delay unit, then are directly input into the conversion circuit, are converted into one path of signals, and output waveforms are shown as green lines in the figure. Note that the delay cells in this case are two different logic resources than the delay cells in the TDC delay chain. The delay units herein are IDELAY resources that can be freely configured by software, such as in Xilinx FPGAs; delay cells in the delay chain have a fixed delay, such as carrier 4/8 resources in the Xilinx FPGA.
The input of TDL TDC delay chain is the output waveform of the conversion circuit, the measurement range Mτ of which should satisfy the condition Mτ>ΔT 2 -ΔT 1 Clock condition Mτ>T clk +ΔT 1 -ΔT 2 Where M is the number of delay cells in the delay chain, τ is the inherent delay of the delay cells, T clk Is the "coarse" clock period of the system.
When a signal with a time interval of Deltat is input, the start time T thereof s ＝ΔT i +M s *τ+N s *T clk End time T e ＝ΔT j +M e *τ+N e *T clk Where i, j represents the number of times the local oscillator output signal toggles between rising and falling edges of the input signal, M s And M e Indicating the number of triggered units on the delay chain, N s And N e Represents an integer value of the coefficient clock, so Δt=t e -T s ＝(N e -N s )*T clk +(ΔT j -ΔT i )+(M e -M s )*τ。
The resource-saving short-chain structure time-to-digital converter provided by the embodiment of the invention comprises a first delay unit, a second delay unit and a conversion circuit; wherein the delay time of the first delay unit and the second delay unit is respectively delta T 1 、ΔT 2 And DeltaT 2 >ΔT 1 The method comprises the steps of carrying out a first treatment on the surface of the The signals are converted into two paths of delay signals after passing through the first delay unit and the second delay unit, and are directly input into the conversion circuit to be converted into one path of signals.
The invention can be applied to various fields such as biomedicine, communication engineering, nuclear physics and the like. The positron emission tomography (Positron Emission Tomography, PET) is used as one of tip imaging technologies in the biomedical field, early diagnosis of cancers can be realized noninvasively, so that treatment can be performed on patients in time, survival probability of the patients is improved, accuracy of time-of-flight measurement and deposition energy calculation of the PET detector on high-energy particles is a key factor for determining PET spatial resolution, a main measurement means adopted at present is to utilize TDC, and the high linearity performance of the invention can effectively improve accuracy of measurement results; in addition, the current PET detector has tens of signal readout channels, which results in tens of TDCs being required for the back end, while for some special methods, even hundreds of TDCs are required, the low resource consumption performance and high robustness of the present invention can greatly reduce the complexity of multi-channel integration. In the communication engineering, products with higher time precision requirements such as a laser radar are mostly measured by adopting a TDC, and the high linearity of the invention can enable the measurement result to be more accurate. In nuclear physics, such as particle detection, high-precision TDC is required for measurement, and the accuracy of measurement can be greatly improved by adopting the invention.
The embodiment of the invention has a great advantage in the research and development or use process, and has the following description in combination with data, charts and the like of the test process.
The specific implementation of the present invention will be described by way of example Xilinx Ultrascale FPGA. The TDC provided by the invention has the same measuring principle as TDL TDC in essence, namely, the 'coarse' time is measured through a system clock, the 'fine' time is measured through a delay chain resource, and the innovation of the invention is that the measuring structure of the 'fine' time is creatively updated, so that only the 'fine' time measuring implementation process is described.
A schematic diagram of a system implementation is shown in fig. 3. The whole system comprises three parts of a signal delay unit, a conversion circuit and a delay chain, wherein the signal delay unit comprises 3 IDELAY units and 3D triggers; the conversion circuit comprises 6 basic logic gates; the delay chain is a short chain consisting of 30 CARRY 8. Where the IDELAY delay time and short chain measurement range are marked in the figure, the short chain measurement range of 30 CARRY8 is only 900ps, since each CARRY8 has a delay time of only about 30 ps. The above settings satisfy the clock condition: 900-0 is less than or equal to 900, 1800-900 is less than or equal to 900, 1800+30×30=2700ps>T clk =2.5 ns, i.e. 400MHz system clock. In operation, the time interval to be measured can be obtained by detecting the latching result of the D trigger and the triggering state on each chain. Let the delay units before each chain be: delta T 1 ，ΔT 2 ，ΔT 3 The delay cells on each short chain have an inherent delay of τ and a system clock period of T clk . The measurement procedure for the "fine" time is as follows:
(1) Detecting the result of the D trigger, and when the result is 001,011,111, the measurement result is a rising edge; when the result is 110,100,000, the measurement result is a falling edge.
(2) Based on the result of the D flip-flop, when the result of the D flip-flop is 001, 111, 100, the position of the "01" jump edge on the short chain is counted as P 01 The method comprises the steps of carrying out a first treatment on the surface of the When the D trigger results in 011, 110, 000, the position of the "10" jump edge on the short chain is counted as P 10 。
(3) Calculating rising edgesTime: t (T) s ＝ΔT i +P 01(10) Xτ, where i is the number of 1's in the D flip-flop result;
(4) Calculating the falling edge time: t (T) e ＝ΔT j +P 01(10) Xτ, where j is the number of 0's in the D flip-flop result;
(5) Determining T s And T is e The number of system clocks experienced between transition edges is N s And N e The interval Δt= (N) of the pulse e -N s )×T clk +T s -T e 。
The experimental effect of TDC in the code density test is shown in fig. 4A to 4C.
One of the criteria for measuring the performance of a TDC is DNL and INL, and the smaller the value is, the better the linearity is, the better the performance is, and the DNL and INL of the TDC which are usually qualified are smaller than 1LSB.
Fig. 4A to fig. 4C show code density test results of the TDC according to the embodiment of the present invention, where INL and DNL are both lower than 0.6LSB without any calibration method, and the performance is excellent.
It should be noted that the embodiments of the present invention can be realized in hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or special purpose design hardware. Those of ordinary skill in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such as provided on a carrier medium such as a magnetic disk, CD or DVD-ROM, a programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The device of the present invention and its modules may be implemented by hardware circuitry, such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., as well as software executed by various types of processors, or by a combination of the above hardware circuitry and software, such as firmware.
The foregoing is merely illustrative of specific embodiments of the present invention, and the scope of the invention is not limited thereto, but any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention will be apparent to those skilled in the art within the scope of the present invention.
Claims (10)
1. A resource-efficient short-chain structure time-to-digital conversion method, comprising: a local oscillator is built by using a delay unit and a conversion circuit, and an input signal is turned over to an output state at fixed time intervals within a continuous high-level time; and obtaining the time between the starting moment and the last time of turning by recording the turning times of the local oscillator.
2. The resource-efficient short-chain-structure time-to-digital conversion method of claim 1, wherein the time at which the local oscillator causes the level to flip is known.
3. The resource-efficient short-chain-structure time-to-digital conversion method of claim 1, wherein the time of the last flip is obtained using TDL TDC.
4. The resource-efficient short-chain-structure time-to-digital conversion method of claim 1, wherein in an actual implementation, the local oscillator generates at most two flips, and the number of times of the flips is determined according to a clock condition and a delay chain measurement range.
5. The resource-efficient short-chain-structure time-to-digital conversion method as recited in claim 1, wherein the resource-efficient short-chain-structure time-to-digital conversion method further comprises:
the method comprises the steps that a local oscillator is formed by a first delay unit, a second delay unit and a conversion circuit, and time interval measurement is carried out on a signal to be detected by combining the local oscillator with a TDL TDC; the delay unit in the local oscillator is freely configured through software, and is preferably IDELAY resources in the Xilinx FPGA; the delay cells in the delay chain have a fixed delay, preferably carrier 4/8 resources in the Xilinx FPGA.
6. The resource-efficient short-chain-structure time-to-digital conversion method as recited in claim 1, wherein the resource-efficient short-chain-structure time-to-digital conversion method further comprises:
the input of the TDL TDC delay chain is the output waveform of the conversion circuit, and the measurement range Mtau meets the condition Mtau>ΔT 2 -ΔT 1 Clock condition Mτ>T clk +ΔT 1 -ΔT 2 The method comprises the steps of carrying out a first treatment on the surface of the Where M is the number of delay cells in the delay chain, τ is the inherent delay of the delay cells, T clk Is the "coarse" clock period of the system;
when a signal with a time interval of Deltat is input, a start time T s ＝ΔT i +M s *τ+N s *T clk End time T e ＝ΔT j +M e *τ+N e *T clk The method comprises the steps of carrying out a first treatment on the surface of the Where i, j denote the number of times the local oscillator output signal toggles between rising and falling edges of the input signal, M s And M e Indicating the number of triggered units on the delay chain, N s And N e Representing the integer value of the coefficient clock, Δt=t e -T s ＝(N e -N s )*T clk +(ΔT j -ΔT i )+(M e -M s )*τ。
7. A resource-saving short-chain structure time digital converter applying the method according to any one of claims 1-6, characterized in that the resource-saving short-chain structure time digital converter comprises a first delay unit, a second delay unit and a conversion circuit, wherein the delay time of the first delay unit and the delay time of the second delay unit are respectively deltat 1 、ΔT 2 And DeltaT 2 >ΔT 1 The method comprises the steps of carrying out a first treatment on the surface of the The signal is back-turned through the first delay unit and the second delay unitTwo paths of delay signals are converted and directly input into a conversion circuit to be converted into one path of signals.
8. A computer device comprising a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the steps of the resource-efficient short-chain-structure time-to-digital conversion method of any one of claims 1 to 6.
9. A computer readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of the resource-efficient short-chain structure time-to-digital conversion method of any one of claims 1 to 6.
10. An information data processing terminal, characterized in that the information data processing terminal is arranged to implement the resource-efficient short-chain-structure time-to-digital converter as claimed in claim 7.
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