CN116455412A - Transmitter - Google Patents

Abstract

The invention provides a transmitter, which comprises a first variable resistor and first to fourth transistors. The first variable resistor is coupled between the supply voltage and the first node. The first electrode of the first transistor is coupled to the first node and the second electrode is coupled to the first output of the transmitter. The first electrode of the second transistor is coupled to the first output terminal of the transmitter, and the second electrode is coupled to the second node. The first electrode of the third transistor is coupled to the first node, and the second electrode is coupled to the second output terminal of the transmitter. The first electrode of the fourth transistor is coupled to the second output terminal of the transmitter, and the second electrode is coupled to the second node. The transmitter has first and second input signals to control the turning on and off of the first through fourth transistors to generate a first output signal at a first output terminal and a second output signal at a second output terminal.

Description

Transmitter

Technical Field

The present invention relates to a transmitter, and more particularly, to a transmitter having a wide bandwidth and low power.

Background

In conventional transmitters, a variable resistor is usually designed at the output of the transmitter for impedance matching, wherein the variable resistor is implemented by a resistor bank (resistor bank) consisting of a plurality of parallel switching resistors. However, the switch in the variable resistor has a high parasitic capacitance, and therefore the output of the transmitter also has a high parasitic capacitance, which reduces the bandwidth of the transmitter.

Disclosure of Invention

It is therefore an object of the present invention to provide a transmitter in which the parasitic capacitance of the output terminal does not affect the bandwidth thereof, so as to solve the above-mentioned problems.

According to one embodiment of the present invention, a transmitter is disclosed that includes a first variable resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first variable resistor is coupled between the supply voltage and the first node. A first electrode of the first transistor is coupled to the first node and a second electrode of the first transistor is coupled to the first output of the transmitter. A first electrode of the second transistor is coupled to the first output of the transmitter and a second electrode of the second transistor is coupled to the second node. The first electrode of the third transistor is coupled to the first node, and the second electrode of the third transistor is coupled to the second output terminal of the transmitter. The first electrode of the fourth transistor is coupled to the second output terminal of the transmitter, and the second electrode of the fourth transistor is coupled to the second node. The transmitter has a first input signal and a second input signal to control the turning on and off of the first transistor, the second transistor, the third transistor, and the fourth transistor to generate a first output signal at a first output terminal and a second output signal at a second output terminal.

By designing the variable resistor between the power supply voltage and the first node to realize impedance matching, the transmitter does not need to have the variable resistor at the output end, so that the signal at the output end is not affected by high parasitic capacitance, and the bandwidth of the transmitter is not deteriorated due to the design of the variable resistor.

These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures and the drawing figures.

Drawings

The invention may be more completely understood in consideration of the following detailed description and examples in connection with the accompanying drawings, in which:

fig. 1 is a schematic diagram illustrating a transmitter according to one embodiment of the present invention.

Fig. 2 is a schematic diagram illustrating a variable resistor according to an embodiment of the present invention.

Fig. 3 is a schematic diagram illustrating a transmitter according to an embodiment of the present invention.

Detailed Description

Certain terms are used throughout the description and claims to refer to particular components. Those of ordinary skill in the art will appreciate that manufacturers may refer to a component by different names. The description and claims do not take the form of an element with differences in names, but rather with differences in functions of the elements as references to differences. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" as used herein includes any direct or indirect electrical connection. Thus, if a first device is electrically connected to a second device, that connection may be made directly to the second device or indirectly to the second device through other devices or connection means.

Fig. 1 is a schematic diagram illustrating a transmitter 100 according to one embodiment of the present invention. Referring to fig. 1, a transmitter 100 includes transistors M1-M4, a variable resistor RB1, a variable resistor RB2, a capacitor c_vdd, a capacitor c_gnd, and two resistors R. In the present embodiment, the variable resistor RB1 is coupled between the power voltage VDD and the node N1, wherein the node N1 is coupled to the first electrode of the transistor M1 and the first electrode of the transistor M3. A second electrode of the transistor M1 is coupled to the first output terminal No1 of the transmitter 100, and a second electrode of the transistor M3 is coupled to the second output terminal No2 of the transmitter 100. A first electrode of the transistor M2 is coupled to the first output terminal No1 of the transmitter 100, and a first electrode of the transistor M4 is coupled to the second output terminal No2 of the transmitter 100. The variable resistor RB2 is coupled between the ground voltage and the node N2, wherein the node N2 is coupled to the second electrode of the transistor M2 and the second electrode of the transistor M4. In this embodiment, each of the transistors M1-M4 is an N-type metal oxide semiconductor (NMOS), and the transmitter 100 may be used in any suitable serializer/deserializer circuit.

Fig. 2 is a schematic diagram illustrating a variable resistor 200 according to an embodiment of the present invention, wherein the variable resistor 200 may be used to implement variable resistor RB1 and/or variable resistor RB2. As shown in fig. 2, the variable resistor 200 includes a plurality of switches SW1-SWn and a plurality of resistors R1-Rn, one of which may be regarded as one switching resistor (e.g., SW1 and R1), and a plurality of switching resistors may be connected in parallel. The variable resistor 200 may be controlled to have different resistance values by enabling or disabling at least a portion of the switches SW 1-SWn.

The transmitter 100 is configured to receive the first input signal Vip and the second input signal Vin to generate a first output signal Vop and a second output signal Von through the resistor R. Specifically, the first input signal Vip and the second input signal Vin are differential input signals, the first input signal Vip is input to the gates of the transistors M1 and M4, and the second input signal Vin is input to the gates of the transistors M2 and M3. When the first input signal Vip is at a high level (i.e., logic value "1") and the second input signal Vin is at a low level (i.e., logic value "0"), the transistors M1, M4 are turned on (enabled), and the transistors M2 and M3 are turned off (disabled), so that the first output signal Vop is at a high level and the second output signal Von is at a low level. Similarly, when the first input signal Vip is at a low level and the second input signal Vin is at a high level, the transistors M1 and M4 are turned off, and the transistors M2 and M3 are turned on, so that the first output signal Vop is at a low level and the second output signal Von has a high level.

In the operation of the transmitter 100, the differential input signal causes the transistors Ml and M3 to be alternately turned on, and thus the current flowing from the power supply voltage VDD and the variable resistor RB1 to the node Nl should always be the same (assuming that the current flowing through the transistor M1 is substantially the same as the current flowing through the transistor M3), the voltage level of the node N1 can be regarded as constant. Specifically, when the first input signal Vip is at a high voltage level and the second input signal Vin is at a low voltage level, the current path is from the power supply voltage VDD, the variable resistor RB1, the node N1, the transistor M1 to the first output terminal No1; when the first input signal Vip is at a low level and the second input signal Vin is at a high level, the current path is the power supply voltage VDD, the variable resistor RB1, the node N1, the transistor M3 to the second output terminal No2. Therefore, since the node N1 always has a constant voltage level, which means that the node N1 is not charged or discharged, the high parasitic capacitance of the variable resistor RB1 does not affect the waveform of either one of the first output signal Vop and the second output signal Von, i.e., the bandwidth of the transmitter 100 is not affected by the high parasitic capacitance of the variable resistor RB 1.

Similarly, the differential input signal causes the transistors M2 and M4 to be alternately turned on, so that the current flowing from the node N2 through the variable resistor RB2 to the ground voltage should always be the same (assuming that the current flowing through the transistor M2 is substantially the same as the current flowing through the transistor M4), the voltage level of the node N2 may be regarded as constant. Specifically, when the first input signal Vip is at a high voltage level and the second input signal Vin is at a low voltage level, the current path is from the second output terminal No2, the transistor M4, the node N2, the variable resistor RB2 to the ground voltage; when the first input signal Vip is at a low voltage level and the second input signal Vin is at a high voltage level, the current path is from the first output terminal No1, the transistor M2, the node N2, the variable resistor RB2 to the ground voltage. Therefore, since the node N2 always has a constant voltage level, which means that the node N2 is not charged or discharged, the high parasitic capacitance of the variable resistor RB2 does not affect the waveforms of any signals related to the first output signal Vop and the second output signal Von, i.e., the bandwidth of the transmitter 100 is not affected by the high parasitic capacitance of the variable resistor RB2.

In summary, by designing the variable resistor RB1 between the power supply voltage VDD and the node N1 and/or the variable resistor RB2 between the ground voltage and the node N2 to achieve impedance matching, the transmitter 100 does not need to have a variable resistor at the output terminals, i.e., the signals of the first output terminal No1 and the second output terminal No2 are not affected by high parasitic capacitance, and the bandwidth of the transmitter 100 is not deteriorated due to the design of the variable resistor.

In addition, the capacitor c_vdd and the capacitor c_gnd are used to provide low impedance at high frequency, and the capacitor c_vdd and the capacitor c_gnd may be removed from fig. 1 without affecting the normal operation of the transmitter 100.

Fig. 3 is a schematic diagram illustrating a transmitter 300 according to an embodiment of the present invention. As shown in fig. 3, transmitter 300 includes transistors M1-M4, variable resistor RB1, variable resistor RB2, capacitor c_vdd, capacitor c_gnd, and two resistors R. In the present embodiment, the variable resistor RB1 is coupled between the power voltage VDD and the node N1, wherein the node N1 is coupled between the first electrode of the transistor M1 and the first electrode of the transistor M3. A second electrode of the transistor M1 is coupled to the first output terminal No1 of the transmitter 300, and a second electrode of the transistor M3 is coupled to the second output terminal No2 of the transmitter 300. A first electrode of the transistor M2 is coupled to the first output terminal No1 of the transmitter 300, and a first electrode of the transistor M4 is coupled to the second output terminal No2 of the transmitter 300. The variable resistor RB2 is coupled between the ground voltage and the node N2, wherein the node N2 is coupled to the second electrode of the transistor M2 and the second electrode of the transistor M4. In this embodiment, transistors M1 and M3 are implemented by PMOS and transistors M2 and M4 are implemented by NMOS, and transmitter 300 may be used in any suitable serializer/deserializer circuit.

The variable resistor RB1 and/or the variable resistor RB2 as shown in fig. 3 may be implemented by the variable resistor 200.

The transmitter 300 is configured to receive a first input signal Vip and a second input signal Vin, and to generate a first output signal Vop and a second output signal Von via a resistor R. Specifically, the first input signal Vip and the second input signal Vin are differential input signals, the first input signal Vip is input to the gates of the transistors M1 and M2, and the second input signal Vin is input to the gates of the transistors M3 and M4. When the first input signal Vip is at a high level (i.e., logic value "1") and the second input signal Vin is at a low level (i.e., logic value "0"), the transistors M1, M4 are turned off, and the transistors M2 and M3 are turned on, such that the first output signal Vop is at a low level and the second output signal Von is at a high level. Similarly, when the first input signal Vip is at a low level and the second input signal Vin is at a high level, the transistors M1 and M4 are turned on, and the transistors M2 and M3 are turned off, so that the first output signal Vop is at a high level and the second output signal Von has a low level.

In operation of transmitter 300, the differential input signal causes transistors Ml and M3 to alternately turn on, so the current flowing from supply voltage VDD and variable resistor RB1 to node Nl should always be the same (assuming that the current flowing through transistor M1 is substantially the same as the current flowing through transistor M3), the voltage level at node N1 may be considered constant. Specifically, when the first input signal Vip is at a low voltage level and the second input signal Vin is at a high voltage level, the current path is from the power supply voltage VDD, the variable resistor RB1, the node N1, the transistor M1 to the first input-output terminal No1; when the first input signal Vip is at a high level and the second input signal Vin is at a low level, the current path is from the power supply voltage VDD, the variable resistor RB1, the node N1, the transistor M3 to the second output terminal No2. Therefore, since the node N1 always has a constant voltage level, which means that the node N1 is not charged or discharged, the high parasitic capacitance of the variable resistor RB1 does not affect the waveform of any one of the first output signal Vop and the second output signal Von, i.e., the bandwidth of the transmitter 300 is not affected by the high parasitic capacitance of the variable resistor RB 1.

Similarly, the differential input signal causes transistors M2 and M4 to alternately turn on, so the current from node N2 to ground voltage via variable resistor RB2 should always be the same (assuming that the current through transistor M2 is substantially the same as the current through transistor M4), the voltage level of node N2 may be considered constant. Specifically, when the first input signal Vip is at a low voltage level and the second input signal Vin is at a high voltage level, the current path is from the second output terminal No2, the transistor M4, the node N2, the variable resistor RB2 to the ground voltage; when the first input signal Vip is at a high level and the second input signal Vin is at a low level, the current path is from the first output terminal No1, the transistor M2, the node N2, the variable resistor RB2 to the ground voltage. Therefore, since the node N2 always has a constant voltage level, which means that the node N2 is not charged or discharged, the high parasitic capacitance of the variable resistor RB2 does not affect the waveform of either one of the first output signal Vop and the second output signal Von, i.e., the bandwidth of the transmitter 300 is not affected by the high parasitic capacitance of the variable resistor RB2.

In summary, by designing the variable resistor RB1 between the power supply voltage VDD and the node Nl and/or the variable resistor RB2 between the ground voltage and the node N2 to achieve impedance matching, the transmitter 300 does not need to have a variable resistor at the output, i.e., the signals of the first output No1 and the second output No2 are not affected by high parasitic capacitance, and the bandwidth of the transmitter 300 is not deteriorated due to the design of the variable resistor.

In addition, the capacitor c_vdd and the capacitor c_gnd are used to provide low impedance at high frequency, and the capacitor c_vdd and the capacitor c_gnd may be removed from fig. 3 without affecting the normal operation of the transmitter 300.

Those skilled in the art will readily recognize that many modifications and variations of the apparatus and methods are possible while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the appended claims.

Claims (12)

1. A transmitter, comprising:

a first variable resistor coupled between a power supply voltage and a first node;

a first transistor, wherein a first electrode of the first transistor is coupled to the first node and a second electrode of the first transistor is coupled to a first output of the transmitter;

a second transistor, wherein a first electrode of the second transistor is coupled to the first output terminal of the transmitter and a second electrode of the second transistor is coupled to a second node;

a third transistor, wherein a first electrode of the third transistor is coupled to the first node, and a second electrode of the third transistor is coupled to the second output terminal of the transmitter; and

a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the second output terminal of the transmitter, and a second electrode of the fourth transistor is coupled to the second node;

wherein the transmitter has a first input signal and a second input signal to control the turning on or off of the first transistor, the second transistor, the third transistor, and the fourth transistor to generate a first output signal at the first output terminal and a second output signal at the second output terminal.

2. The transmitter of claim 1, wherein the first and second input signals are differential input signals, the second and third transistors are controlled to be off when the first and fourth transistors are controlled to be on, and the second and third transistors are controlled to be on when the first and fourth transistors are controlled to be off.

3. The transmitter of claim 2, wherein the first transistor and the third transistor are alternately turned on such that a current flowing through the first node is substantially the same whether the first transistor is turned on or the third transistor is turned on.

4. The transmitter of claim 1, further comprising:

and a second variable resistor coupled between a ground voltage and the second node.

5. The transmitter of claim 4, wherein the first and second input signals are differential input signals, the second and third transistors are controlled to be off when the first and fourth transistors are controlled to be on, and the second and third transistors are controlled to be on when the first and fourth transistors are controlled to be off; the first transistor and the third transistor are alternately turned on such that a current flowing through the first node is substantially the same whether the first transistor is turned on or the third transistor is turned on; the second transistor and the fourth transistor are alternately turned on such that a current flowing through the second node is substantially the same regardless of whether the second transistor is turned on or the fourth transistor is turned on.

6. The transmitter of claim 4, wherein the first and second variable resistors are used for impedance matching of the transmitter, and no other variable resistor is directly connected to the first and second outputs of the transmitter.

7. The transmitter of claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each N-type transistors, the first input signal and the second input signal are differential input signals, the first input signal is input to gates of the first transistor and the fourth transistor, and the second input signal is input to gates of the second transistor and the third transistor.

8. The transmitter of claim 7, wherein the first transistor and the third transistor are alternately turned on such that a current flowing through the first node is substantially the same whether the first transistor is turned on or the third transistor is turned on.

9. The transmitter of claim 7, further comprising:

a second variable resistor coupled between a ground voltage and the second node;

wherein the first transistor and the third transistor are alternately turned on such that a current flowing through the first node is substantially the same whether the first transistor is turned on or the third transistor is turned on; the second transistor and the fourth transistor are alternately turned on such that a current flowing through the second node is substantially the same regardless of whether the second transistor is turned on or the fourth transistor is turned on.

10. The transmitter of claim 1, wherein the first transistor and the third transistor are each P-type transistors, the second transistor and the fourth transistor are each N-type transistors, the first input signal and the second input signal are differential input signals, the first input signal is input to gates of the first transistor and the second transistor, and the second input signal is input to gates of the third transistor and the fourth transistor.

11. The transmitter of claim 10, wherein the first transistor and the third transistor are alternately turned on such that a current flowing through the first node is substantially the same whether the first transistor is turned on or the third transistor is turned on.

12. The transmitter of claim 10, further comprising:

a second variable resistor coupled between a ground voltage and the second node;

wherein the first transistor and the third transistor are alternately turned on such that a current flowing through the first node is substantially the same whether the first transistor is turned on or the third transistor is turned on; the second transistor and the fourth transistor are alternately turned on such that a current flowing through the second node is substantially the same whether the second transistor is turned on or the fourth transistor is turned on.