CN116455367A - Edge detection and channel synthesizer based on high-frequency combinational logic and design method thereof - Google Patents
Edge detection and channel synthesizer based on high-frequency combinational logic and design method thereof Download PDFInfo
- Publication number
- CN116455367A CN116455367A CN202310378682.9A CN202310378682A CN116455367A CN 116455367 A CN116455367 A CN 116455367A CN 202310378682 A CN202310378682 A CN 202310378682A CN 116455367 A CN116455367 A CN 116455367A
- Authority
- CN
- China
- Prior art keywords
- edge detection
- frequency
- channel
- circuit
- channel synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003708 edge detection Methods 0.000 title claims abstract description 78
- 238000013461 design Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 32
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 32
- 230000002194 synthesizing effect Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 6
- 230000000694 effects Effects 0.000 claims description 5
- 230000002441 reversible effect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims description 2
- 230000035515 penetration Effects 0.000 claims 2
- 238000001514 detection method Methods 0.000 abstract description 8
- 238000011161 development Methods 0.000 abstract description 6
- 230000001360 synchronised effect Effects 0.000 abstract description 5
- 230000004044 response Effects 0.000 description 11
- 238000012360 testing method Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 239000002070 nanowire Substances 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- 241000282414 Homo sapiens Species 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/04—Position modulation, i.e. PPM
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
- G01J2001/4413—Type
- G01J2001/442—Single-photon detection or photon counting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
The invention discloses an edge detection and channel synthesizer based on high-frequency combinational logic and a design method thereof, comprising a sixteen-in-one edge detection and channel synthesizer, wherein the sixteen-in-one edge detection and channel synthesizer comprises four-in-one edge detection and channel synthesizers and three-channel synthesizers for synthesizing four paths of signals output by the four-in-one edge detection and channel synthesizers into one path; the four-in-one edge detection and channel synthesizer comprises a four-way edge detection circuit connected in parallel and a three-way signal synthesis circuit for synthesizing output signals of the four-way edge detection circuit into one way. The edge detection and channel synthesizer based on the high-frequency combinational logic and the design method thereof have the advantages of low development cost, accurate signal synchronization, large synchronous signal scale and the like, thereby having great application prospect in the field of detection and synthesis of high-frequency signals.
Description
Technical Field
The invention relates to the technical field of detection and synthesizer of high-frequency signals, in particular to an edge detection and channel synthesizer based on high-frequency combinational logic and a design method thereof.
Background
The deep space detection aiming at the moon orbit and the space outside the moon orbit has important significance for the development of human beings, and with the continuous increase of the deep space detection distance, the deep space laser communication technology becomes an important research direction for the deep space detection of the human beings.
Because the detection distance is long and the deep space environment is bad, the requirements for realizing high-speed stable communication are also higher and higher. At present, a high-sensitivity single photon detector adopting a PPM modulation mode is widely studied as a communication system for detecting very weak signals in deep space. Because of the high speed PPM communication required, single photon pulses have a longer tail. The single photon detector array is adopted, and the received extremely narrow single photon pulse signals are synthesized according to accurate time slots and synchronously processed, so that the method has a great challenge at present.
For the design field of edge detection and channel synthesizer, the scheme adopted at home and abroad is currently a sequential logic circuit proposed by Lincoln laboratories in America. However, the edge detection and channel synthesizer based on sequential logic design requires a high-frequency clock circuit to complete clock synchronization, and has high hardware cost. On the other hand, it is difficult to achieve accurate synchronization of the high-frequency clock signals of each channel (200 ps single photon pulse signals) due to the presence of clock jitter and phase noise. Meanwhile, in the processing of the device, there is a difference in transmission path delay due to errors.
Disclosure of Invention
In order to solve the problems, the invention provides an edge detection and channel synthesizer based on high-frequency combinational logic and a design method thereof, which have the advantages of low development cost, accurate signal synchronization, large synchronous signal scale and the like, thereby having great application prospect in the field of detection and synthesis of high-frequency signals and solving the problems that the high-frequency clock signals are difficult to accurately synchronize and the delay difference compensation of each transmission path is difficult
In order to achieve the above object, the present invention provides an edge detection and channel synthesizer based on high frequency combinational logic, comprising a sixteen-in-one edge detection and channel synthesizer, wherein the sixteen-in-one edge detection and channel synthesizer comprises four-block four-in-one edge detection and channel synthesizers and three-block channel synthesizers for synthesizing four paths of signals output by the four-block four-in-one edge detection and channel synthesizers into one path;
the four-in-one edge detection and channel synthesizer comprises a four-way edge detection circuit connected in parallel and a three-way signal synthesis circuit for synthesizing output signals of the four-way edge detection circuit into one way.
Preferably, the edge detection circuit comprises a high-speed comparator, a delayer and an AND gate, wherein the in-phase output end and the reverse output end of the high-speed comparator are respectively connected with the two delayers through microstrip lines with different lengths, and the two delayers are connected with the AND gate.
Preferably, the signal synthesis circuit comprises an or gate and two adjustable delayers, wherein the two adjustable delayers are respectively connected with two input ends of the or gate through two microstrip lines with equal lengths.
The design method of the edge detection and channel synthesizer based on the high-frequency combinational logic comprises the following steps:
s1, sequentially connecting a high-speed comparator, a delay device and an AND gate in series through a microstrip line to form an edge detection circuit;
s2, connecting an AND gate and a multi-stage OR gate of the edge detection circuit in a cascade mode, and adding an adjustable delayer at the input end of the OR gate to form a signal synthesis circuit so as to compensate delay errors of all signals;
s3, respectively integrating the edge detection circuit and the signal synthesis circuit on different high-frequency PCB boards to manufacture the high-frequency PCB boards;
s4, integrating a power supply rectifying circuit on each high-frequency PCB;
s5, packaging four high-frequency PCB integrated with an edge detection circuit and three high-frequency PCB integrated with a signal synthesis circuit in a rectangular shielding cavity to form a four-in-one edge detection and channel synthesizer, and simultaneously forming the high-frequency PCB integrated with the signal synthesis circuit into a channel synthesizer;
s6, sequentially cascading the four-in-one edge detection and channel synthesizer and the three-in-one channel synthesizer through high-frequency wires to form a sixteen-in-one edge detection and channel synthesizer.
Preferably, the step S1 specifically includes the following steps:
s11, adopting a high-frequency circuit design method, and respectively connecting an in-phase output end and a reverse output end of the high-speed comparator with two delays through two paths of microstrip lines with unequal lengths based on a principle of radio frequency impedance matching so as to ensure that the relative delay of two paths of signals with opposite phases is 200ps;
s12, respectively connecting the two output ends of the delayer with the two input ends of the AND gate through two microstrip lines with equal lengths.
Preferably, the high-frequency PCB in step S3 is a rogers high-frequency board.
Preferably, in step S3, vias are filled between the layers of the high frequency PCB board to compensate for the capacitive effect between the layers.
Preferably, the power rectifying circuit in step S4 uniformly provides an input voltage of 12V by the external power module.
Preferably, in step S5, a feedthrough capacitor is connected to a wall of the rectangular shielding cavity, and the external power module is connected to the power rectifier circuit through the feedthrough capacitor, so as to reduce electromagnetic interference.
The invention has the following beneficial effects:
1. the synchronous clock is not needed, a high-frequency 5GHz clock generation circuit is omitted, and the hardware development cost is saved; on the other hand, adverse effects caused by clock jitter and phase noise characteristics are avoided, and meanwhile, the difficulty that accurate synchronization of high-frequency clock signals of all channels is required to be realized is overcome.
2. And the delay of each path is regulated by adopting a high-precision delay device with a step level of a plurality of ps, so that the delay difference of transmission paths among paths caused by processing errors can be accurately compensated, and the accurate alignment of 16 paths of ppm signal time slots is realized.
3. The 16-path ppm signal synthesis design adopts a two-in-one cascade expansion network architecture, which is favorable for further expanding the channel number and realizing larger-scale high-speed single photon signal synthesis.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
FIG. 1 is a block diagram of a high frequency combinational logic based edge detection and channel synthesizer of the present invention;
FIG. 2 is a diagram of a 16-way analog single photon signal synthesis according to an embodiment of the present invention;
FIG. 3 is a graph of the result of synthesizing a 16-way analog single photon signal according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of a shaped PPM signal output by a single photon detector of a superconducting nanowire according to an embodiment of the present invention;
FIG. 5 is a graph of test results of joint debugging of a multichannel signal synthesizer and a single photon detector under the premise of error response in an embodiment of the invention;
fig. 6 is a diagram of test results of joint debugging of a multichannel signal synthesizer and a single photon detector under the premise of existence of leakage response according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings, and it should be noted that, while the present embodiment provides a detailed implementation and a specific operation process on the premise of the present technical solution, the protection scope of the present invention is not limited to the present embodiment.
The edge detection and channel synthesizer based on the high-frequency combinational logic comprises a sixteen-in-one edge detection and channel synthesizer, wherein the sixteen-in-one edge detection and channel synthesizer comprises four-in-one edge detection and channel synthesizers and three channel synthesizers used for synthesizing four paths of signals output by the four-in-one edge detection and channel synthesizers into one path; the four-in-one edge detection and channel synthesizer comprises a four-way edge detection circuit connected in parallel and a three-way signal synthesis circuit for synthesizing output signals of the four-way edge detection circuit into one way.
The edge detection circuit comprises a high-speed comparator, a delay device and an AND gate, wherein the in-phase output end and the reverse output end of the high-speed comparator are respectively connected with the two delay devices through microstrip lines with different lengths, and the two delay devices are connected with the AND gate.
Preferably, the signal synthesis circuit comprises an or gate and two adjustable delayers, wherein the two adjustable delayers are respectively connected with two input ends of the or gate through two microstrip lines with equal lengths.
The design method of the edge detection and channel synthesizer based on the high-frequency combinational logic comprises the following steps:
s1, sequentially connecting a high-speed comparator, a delay device and an AND gate in series through a microstrip line to form an edge detection circuit;
preferably, the step S1 specifically includes the following steps:
s11, adopting a high-frequency circuit design method, and based on the principle of radio frequency impedance matching (the design method of radio frequency impedance matching is strictly followed when wiring, each path of differential signal wires are strictly equal in length, and each layer of each high-frequency circuit board is paved with a large area of ground;
s12, respectively connecting the two output ends of the delayer with the two input ends of the AND gate through two microstrip lines with equal lengths.
S2, connecting an AND gate and a multi-stage OR gate of the edge detection circuit in a cascade mode, adding an adjustable delayer at the input end of the OR gate to form a signal synthesis circuit so as to compensate delay errors of all paths of signals, and compensating delay errors among all paths of signals due to non-ideal transmission paths by using the adjustable delayer;
s3, respectively integrating the edge detection circuit and the signal synthesis circuit on different high-frequency PCB boards to manufacture the high-frequency PCB boards;
preferably, the high-frequency PCB in step S3 is a rogers high-frequency board.
Preferably, in step S3, vias are filled between the layers of the high frequency PCB board to compensate for the capacitive effect between the layers.
S4, integrating a power supply rectifying circuit on each high-frequency PCB;
preferably, the power rectifying circuit in step S4 uniformly provides an input voltage of 12V by the external power module.
S5, packaging four high-frequency PCB integrated with an edge detection circuit and three high-frequency PCB integrated with a signal synthesis circuit in a rectangular shielding cavity to form a four-in-one edge detection and channel synthesizer, and simultaneously forming the high-frequency PCB integrated with the signal synthesis circuit into a channel synthesizer;
preferably, in step S5, a feedthrough capacitor is connected to a wall of the rectangular shielding cavity, and the external power module is connected to the power rectifier circuit through the feedthrough capacitor, so as to reduce electromagnetic interference.
S6, sequentially cascading the four-in-one edge detection and channel synthesizer and the three-in-one channel synthesizer through high-frequency wires to form a sixteen-in-one edge detection and channel synthesizer.
Examples
FIG. 2 is a diagram of a 16-way analog single photon signal synthesis according to an embodiment of the present invention; FIG. 3 is a graph of the result of synthesizing a 16-way analog single photon signal according to an embodiment of the present invention; FIG. 4 is a waveform diagram of a shaped PPM signal output by a single photon detector of a superconducting nanowire according to an embodiment of the present invention; FIG. 5 is a graph of test results of joint debugging of a multichannel signal synthesizer and a single photon detector under the premise of error response in an embodiment of the invention; FIG. 6 is a graph of test results of joint debugging of a multi-channel signal synthesizer and a single photon detector on the premise of leak response, and it is to be noted that the abscissa in FIGS. 2-6 is time, and the ordinate is amplitude, as shown in FIGS. 2-6, the 16-path ppm signal synthesis design adopts a two-in-one cascade expansion network architecture, and it is to be noted that the number of channels can be further expanded to realize larger-scale high-speed single photon signal synthesis; in the four-in-one edge detection and channel synthesizer, each signal respectively passes through a high-speed comparator, two signals with opposite phases are output at high speed, the difference of the line length between the signals in each channel is utilized, the relative delay of the signals with opposite phases in each channel is accurately adjusted to be 200ps (according to the dielectric constant and thickness of a pcb, the propagation speed of a microstrip line tem mode is calculated, the length difference of the microstrip line is calculated according to the required 200ps time difference, the time difference is accurately adjusted through the delay, the design error is greatly reduced), the delay difference of a transmission path caused by the processing error between the channels can be accurately compensated, the accurate alignment of each ppm signal time slot is realized, the edge extraction is completed through an AND gate, and then the two-stage signal synthesizer consisting of OR gates is finally formed; and four-in-one edge detection and four paths of signals output by the channel synthesizer can be synthesized into one path of signals by a two-stage signal synthesizer, so that 16 paths of pulse sequences are synthesized into one path of PPM signals to be output.
Compared with an edge detection and channel synthesizer based on a sequential logic circuit, the circuit designed by the embodiment does not need a synchronous clock, so that a 5GHz high-frequency clock generation circuit is omitted, and the hardware development cost is saved; on the other hand, adverse effects caused by clock jitter and phase noise characteristics are avoided, and the difficulty in realizing accurate synchronization of high-frequency clock signals of all channels is overcome.
Experimental example 1: 16-channel signal synthesis performance test experiment of edge detection and channel synthesizer
In order to verify the 16-channel signal synthesis performance of the sixteen-in-one edge detection and channel synthesizer, an FPGA board card is used for simulating 16-channel single photon signals in a North-care laboratory, and parameters such as pulse width (20 ns), peak value (about 500 mV), period (no period), rising edge time difference (not measured) and the like are similar to the output signals of the single photon detector. In the experiment, 3 direct current power supplies are adopted to supply power to four-in-one edge detection and channel synthesizers and signal synthesizers, and the total power consumption of all modules is about 100W.
From the test results, it can be clearly identified according to the pulse waveform period, and all 16 paths of signals are successfully synthesized into 1 path. The combined signal has no redundant pulse or missing pulse, and the relative time positions of all the pulses are found to correspond to the setting accurately by strict comparison. 1 pulse in the synthesized signal is arbitrarily selected for analysis, and the pulse width can be calculated to be approximately 200ps. Since the fundamental frequency of the pulse signal is too high, the pulse shape is not a very standard rectangular pulse shape, which is affected by the limitation of the adoption rate of the oscilloscope and the high-frequency loss of the cable, and the phenomenon is reasonable. Thus, it was demonstrated that the 16-channel signal synthesis performance of the edge detection and channel synthesizer has been successfully verified.
Example 2: multi-channel signal synthesizer and single photon detector joint debugging experiment
In the system demonstration verification test, a PPM laser signal transmitter is adopted as a signal generation source, a single photon detector array of Nanjing university is adopted as an uplink signal receiving device and a downlink signal receiving device, and the 16-channel edge detection and synthesizer is adopted. It is known that for uplink signals, the optical fiber coupling superconducting nanowire single photon detector is coupled with a 53cm telescope, and receives the uplink signals, so that a communication ranging function is realized. For the downlink signals, the space coupling superconducting nanowire array single photon detector is coupled with a 1.2m telescope, receives the downlink signals, and realizes the integrated functions of communication ranging and tracking angle measurement.
The process of photon absorption by superconducting nanowire array single photon detectors appears as a fast rise in the circuit followed by exponentially decaying electrical pulses. Experiments have found that the pulse exhibits a strong jitter, which is proportional to the laser pulse width. It was found through experimental adjustment that reducing the laser pulse width can reduce the pulse jitter to some extent.
Meanwhile, the test result of the joint debugging of the multichannel signal synthesizer and the single photon detector can be known. The response signal of the single photon detector is affected by factors such as dark count and noise, and a situation of time slot multi-response pulse (false response) or few pulses (missing response) occurs. The error response pulse and the leakage response pulse have great influence on subsequent signal synthesis, demodulation and ranging, so that the reliability of the system needs to be improved by measures such as increasing response intensity, correcting channel coding and decoding algorithm and the like. The multichannel signal synthesizer can accurately extract the single photon output PPM pulse position.
The above results all meet the design requirements and are very ideal, also illustrating the feasibility of the invention.
Therefore, the edge detection and channel synthesizer based on the high-frequency combinational logic and the design method thereof have the advantages of low development cost, accurate signal synchronization, large synchronous signal scale and the like, thereby having great application prospect in the field of detection and synthesis of high-frequency signals.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention and not for limiting it, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that: the technical scheme of the invention can be modified or replaced by the same, and the modified technical scheme cannot deviate from the spirit and scope of the technical scheme of the invention.
Claims (9)
1. The edge detection and channel synthesizer based on the high-frequency combinational logic is characterized in that: the device comprises a sixteen-in-one edge detection and channel synthesizer, wherein the sixteen-in-one edge detection and channel synthesizer comprises four-in-one edge detection and channel synthesizers and three channel synthesizers, wherein the three channel synthesizers are used for synthesizing four paths of signals output by the four-in-one edge detection and channel synthesizers into one path;
the four-in-one edge detection and channel synthesizer comprises a four-way edge detection circuit connected in parallel and a three-way signal synthesis circuit for synthesizing output signals of the four-way edge detection circuit into one way.
2. The high frequency combinational logic based edge detection and channel synthesizer of claim 1, wherein: the edge detection circuit comprises a high-speed comparator, a delayer and an AND gate, wherein the in-phase output end and the reverse output end of the high-speed comparator are respectively connected with the two delayers through microstrip lines with different lengths, and the two delayers are connected with the AND gate.
3. The high frequency combinational logic based edge detection and channel synthesizer of claim 1, wherein: the signal synthesis circuit comprises an OR gate and two adjustable delayers, wherein the two adjustable delayers are respectively connected to two input ends of the OR gate through two microstrip lines with equal lengths.
4. A method of designing a high frequency combinational logic based edge detection and channel synthesizer as claimed in any one of the preceding claims 1-3, characterized by: the method comprises the following steps:
s1, sequentially connecting a high-speed comparator, a delay device and an AND gate in series through a microstrip line to form an edge detection circuit;
s2, connecting an AND gate and a multi-stage OR gate of the edge detection circuit in a cascade mode, and adding an adjustable delayer at the input end of the OR gate to form a signal synthesis circuit so as to compensate delay errors of all signals;
s3, respectively integrating the edge detection circuit and the signal synthesis circuit on different high-frequency PCB boards to manufacture the high-frequency PCB boards;
s4, integrating a power supply rectifying circuit on each high-frequency PCB;
s5, packaging four high-frequency PCB integrated with an edge detection circuit and three high-frequency PCB integrated with a signal synthesis circuit in a rectangular shielding cavity to form a four-in-one edge detection and channel synthesizer, and simultaneously forming the high-frequency PCB integrated with the signal synthesis circuit into a channel synthesizer;
s6, sequentially cascading the four-in-one edge detection and channel synthesizer and the three-in-one channel synthesizer through high-frequency wires to form a sixteen-in-one edge detection and channel synthesizer.
5. The design method according to claim 4, wherein: the step S1 specifically comprises the following steps:
s11, adopting a high-frequency circuit design method, and respectively connecting an in-phase output end and a reverse output end of the high-speed comparator with two delays through two paths of microstrip lines with unequal lengths based on a principle of radio frequency impedance matching so as to ensure that the relative delay of two paths of signals with opposite phases is 200ps;
s12, respectively connecting the two output ends of the delayer with the two input ends of the AND gate through two microstrip lines with equal lengths.
6. The design method according to claim 4, wherein: and step S3, the high-frequency PCB is a rogers high-frequency board.
7. The design method according to claim 4, wherein: in step S3, vias are filled between the layers of the high frequency PCB to compensate for the capacitive effects between the layers.
8. The design method according to claim 4, wherein: the power rectifying circuit in step S4 uniformly provides an input voltage of 12V by an external power module.
9. The design method according to claim 4, wherein: and step S5, a penetration capacitor is connected to the cavity wall of the rectangular shielding cavity, and the external power supply module is connected with the power supply rectifying circuit through the penetration capacitor, so that electromagnetic interference is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310378682.9A CN116455367A (en) | 2023-04-11 | 2023-04-11 | Edge detection and channel synthesizer based on high-frequency combinational logic and design method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310378682.9A CN116455367A (en) | 2023-04-11 | 2023-04-11 | Edge detection and channel synthesizer based on high-frequency combinational logic and design method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116455367A true CN116455367A (en) | 2023-07-18 |
Family
ID=87133145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310378682.9A Pending CN116455367A (en) | 2023-04-11 | 2023-04-11 | Edge detection and channel synthesizer based on high-frequency combinational logic and design method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116455367A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0911970A2 (en) * | 1997-10-09 | 1999-04-28 | Lucent Technologies Inc. | Edge detection circuit |
| KR19990052189A (en) * | 1997-12-22 | 1999-07-05 | 이계철 | Phase Comparison Detector and Detection Method by Signal Transition Method |
| US5942937A (en) * | 1997-11-19 | 1999-08-24 | Advanced Micro Devices, Inc. | Signal detection circuit using a plurality of delay stages with edge detection logic |
| US6037812A (en) * | 1998-05-18 | 2000-03-14 | National Semiconductor Corporation | Delay locked loop (DLL) based clock synthesis |
| JP2004112252A (en) * | 2002-09-18 | 2004-04-08 | Hitachi Kokusai Electric Inc | Burst edge detection circuit and distortion compensation amplifier |
| US20040135712A1 (en) * | 2002-07-22 | 2004-07-15 | Iain Robertson | Data transmission |
| US20040141567A1 (en) * | 2003-01-22 | 2004-07-22 | Fuji Yang | Multi-level pulse amplitude modulation receiver |
| US20060044022A1 (en) * | 2004-08-25 | 2006-03-02 | Tayler Michael K | Edge detector and method |
| US20150212494A1 (en) * | 2012-09-05 | 2015-07-30 | IQ-Analog Corporation | Traveling Pulse Wave Quantizer |
| CN111781569A (en) * | 2020-06-23 | 2020-10-16 | 芜湖易来达雷达科技有限公司 | Civil continuous wave radar target simulation method |
-
2023
- 2023-04-11 CN CN202310378682.9A patent/CN116455367A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0911970A2 (en) * | 1997-10-09 | 1999-04-28 | Lucent Technologies Inc. | Edge detection circuit |
| US5942937A (en) * | 1997-11-19 | 1999-08-24 | Advanced Micro Devices, Inc. | Signal detection circuit using a plurality of delay stages with edge detection logic |
| KR19990052189A (en) * | 1997-12-22 | 1999-07-05 | 이계철 | Phase Comparison Detector and Detection Method by Signal Transition Method |
| US6037812A (en) * | 1998-05-18 | 2000-03-14 | National Semiconductor Corporation | Delay locked loop (DLL) based clock synthesis |
| US20040135712A1 (en) * | 2002-07-22 | 2004-07-15 | Iain Robertson | Data transmission |
| JP2004112252A (en) * | 2002-09-18 | 2004-04-08 | Hitachi Kokusai Electric Inc | Burst edge detection circuit and distortion compensation amplifier |
| US20040141567A1 (en) * | 2003-01-22 | 2004-07-22 | Fuji Yang | Multi-level pulse amplitude modulation receiver |
| US20060044022A1 (en) * | 2004-08-25 | 2006-03-02 | Tayler Michael K | Edge detector and method |
| US20150212494A1 (en) * | 2012-09-05 | 2015-07-30 | IQ-Analog Corporation | Traveling Pulse Wave Quantizer |
| CN111781569A (en) * | 2020-06-23 | 2020-10-16 | 芜湖易来达雷达科技有限公司 | Civil continuous wave radar target simulation method |
Non-Patent Citations (1)
| Title |
|---|
| 陈峰;王航;眭明;: "基于时钟相位补偿的同步触发信号产生技术", 计算机测量与控制, no. 05, 25 May 2020 (2020-05-25) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101803267B (en) | Method and system for multi-point signal generation with phase synchronized local carriers | |
| EP0547274B1 (en) | Calibration of plural - channel system | |
| US3519746A (en) | Means and method to obtain an impulse autocorrelation function | |
| Domnin et al. | Kharkiv incoherent scatter facility | |
| Jeong et al. | A self-compensating built-in self-test solution for RF phased array mismatch | |
| US11677538B2 (en) | Chip to chip time synchronization | |
| CN101398481A (en) | Digital high precision dynamic cymoscope | |
| CN109683658A (en) | A kind of clock signal phase control device and method | |
| US20170285143A1 (en) | Electronic circuit, radar apparatus, and method of correcting radar transmission channels | |
| CN201499145U (en) | Millimeter wave frequency source | |
| CN116455367A (en) | Edge detection and channel synthesizer based on high-frequency combinational logic and design method thereof | |
| CN104734792A (en) | Hybrid two-channel millimeter wave attenuation measuring method and system | |
| CN109617633B (en) | Millimeter wave attenuation measurement system and method | |
| CN110391799A (en) | A kind of picosecond pulse generating unit | |
| Sun et al. | Design and implementation of an FPGA‐based timing pulse programmer for pulsed‐electron paramagnetic resonance applications | |
| Lin et al. | Accurate synchronization method of 38-GHz 5G channel measurement system | |
| CN111751793B (en) | Biplane pulse Doppler radar seeker channel merging and time division processing circuit | |
| CN112019215B (en) | Pulse width modulation single-distribution type multichannel ADC synchronization method | |
| Groth et al. | Accurate PPCC-based DoA estimation using multiple calibration planes for WSN nodes equipped with ESPAR antennas | |
| Filipek et al. | Fast synchronous distribution network of data streams for RPC Muon Trigger in CMS experiment | |
| Gruchala et al. | Frequency detector with power combiner dividers | |
| WO2014210268A1 (en) | Devices, methods and computer readable storage media storing instructions for generating pulse signals | |
| Groth et al. | Efficient RSS-based DoA estimation for ESPAR antennas using multiplane SDR calibration approach | |
| Zhou et al. | Self-calibration Fan-out Method Research for Heavy-ion Accelerator Timing System | |
| Lyon et al. | Microwave pulse generation using the Bragg cutoff of a nonlinear transmission line |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |