CN116405031A - Analog-to-digital converter and chip - Google Patents
Analog-to-digital converter and chip Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuits, and discloses an analog-to-digital converter and a chip, wherein the analog-to-digital converter comprises: first and second passive switched capacitor integrators; two capacitive analog-to-digital conversion arrays; a control logic circuit for closing the first and second switch groups in the first passive switched capacitor integrator to output a first residual voltage and closing the third and fourth switch groups in the second passive switched capacitor integrator to output a second residual voltage when the capacitors in the array are reset; and a double differential input comparator for receiving the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receiving the second residual voltage as a second differential input signal, and outputting a comparison result, wherein the control logic circuit is further used for outputting a plurality of switch control signals to the capacitive analog-to-digital conversion array according to the comparison result so as to output digital data of the current preset period, thereby effectively suppressing quantization noise in a signal band.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an analog-to-digital converter and a chip.
Background
Successive approximation type analog-to-digital converters are widely used in various scenes due to their low power consumption and high energy efficiency characteristics, but various non-ideal factors and various noises inside the successive approximation type analog-to-digital converters limit the signal-to-noise ratio that can be achieved by the successive approximation type analog-to-digital converters, wherein quantization noise is the most prominent. The over-sampling and noise shaping technique can be used for noise shaping of quantization noise and comparator noise by constructing corresponding high-pass or band-pass noise transfer functions, so that the in-band signal-to-noise ratio of the analog-to-digital converter is effectively improved. However, in order to well inhibit noise in a signal band, an active circuit module with larger power consumption is often required to be used for constructing a circuit in a noise shaping loop, which is not beneficial to the realization of a low-power consumption system.
Disclosure of Invention
The invention aims to provide an analog-to-digital converter and a chip, which adopt a second-order passive hybrid noise shaping technology to sample and integrate residual voltage of the previous preset period through two groups of passive switched capacitor integrators respectively, and respectively convert input sampling signals fed into the current period through the output of the two integrators in an error feedback and forward addition mode, so that in-band quantization noise and comparator noise of the analog-to-digital converter are modulated to a high frequency band, and a second-order high-pass noise shaping effect is realized to inhibit related noise in a signal band.
To achieve the above object, a first aspect of the present invention provides an analog-to-digital converter including: a first passive switched capacitor integrator, comprising: 2Q first capacitances and a first switch group connecting Q capacitances of the 2Q first capacitances in series and a second switch group connecting another Q capacitances of the 2Q first capacitances in series; a second passive switched capacitor integrator comprising: 2Q second capacitances and a third switch group connecting Q of the 2Q second capacitances in series and a fourth switch group connecting another Q of the 2Q second capacitances in series; two capacitive analog-to-digital conversion arrays; the control logic circuit is used for closing the first switch group and the second switch group under the condition that the capacitors in the two capacitive analog-to-digital conversion arrays are reset to an initial state, so that the first passive switched capacitor integrator outputs a first residual voltage, and closing the third switch group and the fourth switch group, so that the second passive switched capacitor integrator outputs a second residual voltage, wherein the first residual voltage is the sum of first sub residual voltages of the 2Q first capacitors in a last preset period, and the second residual voltage is the sum of second sub residual voltages of the 2Q second capacitors in the last preset period; and a dual differential input comparator for receiving the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receiving the second residual voltage as a second differential input signal, and outputting a comparison result, wherein the control logic circuit is further configured to output a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays according to the comparison result so as to output digital data of the current preset period corresponding to the input voltage of the current preset period.
Preferably, the first passive switched capacitor integrator further comprises: and a fifth switch group connected in parallel with the 2Q first capacitors, and correspondingly, after outputting the digital data of the last preset period corresponding to the input voltage of the last preset period, the control logic circuit is further configured to distribute the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitors by closing the fifth switch group, so that the voltages of the first capacitors are the first sub residual voltages.
Preferably, the second passive switched capacitor integrator further comprises: and a sixth switch group connecting the 2Q second capacitances in parallel, and correspondingly, after performing the step of distributing the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitances by closing the fifth switch group, the control logic circuit is further configured to open the fifth switch group and distribute the updated residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q second capacitances by closing the sixth switch group so that the voltages of the second capacitances are the second sub residual voltages.
Preferably, the digital data is N-bit data, and the analog-to-digital converter further includes: the sampling switch circuit, before the capacitors in the two capacitive analog-to-digital conversion arrays are reset to the initial state, the control logic circuit is further configured to: according to the predicted value of the current preset period, connecting lower polar plates of the highest capacitors on the positive electrode side and the negative electrode side in the two capacitive analog-to-digital conversion arrays to different reference voltages; switching on the sampling switch circuit to sample the input voltage of the current preset period to the capacitive analog-to-digital conversion array; and disconnecting the sampling switch circuit, and resetting each capacitor in the capacitive analog-to-digital conversion array to an initial state so as to feed in a pre-offset compensation amount corresponding to the reference voltage and low-N-1 bit data in the N-bit data output in the last preset period.
Preferably, after the step of outputting the digital data of the current preset period corresponding to the input voltage of the current preset period is performed, the control logic circuit is further configured to: subtracting low-N-1 bit data in the N-bit data output in the previous preset period from the N-bit data output in the current preset period to obtain an N-bit difference value; and subtracting a value corresponding to the pre-offset compensation amount from the N-bit difference value to output compensated N-bit data of the current preset period corresponding to the input voltage of the current preset period.
Preferably, the control logic circuit is further configured to add the compensated N-bit data of the current preset period to the low N-1 bit data of the N-bit data output by the current preset period, so as to obtain a predicted value about a next preset period.
Preferably, the control logic circuit is configured to connect the lower plates of the highest capacitors on the positive and negative sides of the two capacitive analog-to-digital conversion arrays to different reference voltages, including: connecting the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the positive input end to a positive reference voltage and the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the negative input end to a negative reference voltage, with a predicted value of 1 for the current preset period; or in case that the predicted value for the current preset period is 0, connecting the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the positive end of the input to a negative reference voltage, and connecting the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the negative end of the input to the positive reference voltage.
Preferably, the control logic circuit is configured to reset each capacitor in the capacitive analog-to-digital conversion array to an initial state, including: the lower plate of the capacitor on the positive side in the capacitive analog-to-digital conversion array is connected to a positive reference voltage, and the lower plate of the capacitor on the negative side in the capacitive analog-to-digital conversion array is grounded.
Preferably, the first passive switched capacitor integrator comprises 4 first capacitors; and the second passive switched capacitor integrator comprises 4 second capacitors, wherein the capacitance values of the first and second capacitors are equal to 1/2 times the total capacitance value of the capacitive analog-to-digital conversion array.
Through the technical scheme, under the condition that the capacitors in the two capacitive analog-to-digital conversion arrays are reset to an initial state, the first switch group and the second switch group are closed through the control logic circuit so that the first passive switch capacitor integrator outputs a first residual voltage, and the third switch group and the fourth switch group are closed through the control logic circuit so that the second passive switch capacitor integrator outputs a second residual voltage; receiving the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal through a double differential input comparator, receiving the second residual voltage as a second differential input signal, and outputting a comparison result; and then, outputting a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays through the control logic circuit according to the comparison result so as to output digital data of the current preset period corresponding to the input voltage of the current preset period. The invention adopts the second-order passive mixed noise shaping technology to sample and integrate the residual voltage of the previous preset period through two groups of passive switched capacitor integrators, and respectively converts the input sampling signals fed into the current period by the output of the two integrators in an error feedback and forward addition mode, thereby modulating the in-band quantization noise and the comparator noise of the analog-to-digital converter to a high frequency band, realizing the second-order high-pass noise shaping effect and inhibiting the related noise in the signal band.
The second aspect of the invention provides a chip comprising the analog-to-digital converter
Specific details and benefits of the chip provided by the embodiments of the present invention can be found in the above description of the analog-to-digital converter, and are not repeated here.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a block diagram of a successive approximation analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a block diagram of a first passive switched capacitor integrator according to an embodiment of the present invention;
FIG. 3 is a block diagram of a second passive switched capacitor integrator provided in accordance with one embodiment of the present invention;
FIG. 4 is a schematic diagram of a first passive switched capacitor integrator and a second passive switched capacitor integrator according to an embodiment of the present invention at different times;
FIG. 5 is a timing diagram of the operation of a successive approximation analog-to-digital converter according to an embodiment of the present invention; and
Fig. 6 is a flow chart of an operation mechanism of the analog-to-digital converter according to an embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Fig. 1 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention, where the analog-to-digital converter may include: a first passive switched capacitor integrator 10; a second passive switched capacitor integrator 20; two capacitive analog to digital conversion arrays (i.e., CDACs) 30; control logic 40 and dual differential input comparator 50 as shown in fig. 1.
Wherein the first passive switched capacitor integrator 10 may comprise: 2Q first capacitances and a first switch group connecting Q of the 2Q first capacitances in series and a second switch group connecting another Q of the 2Q first capacitances in series.
Wherein Q is a positive integer. For example, the first passive switched capacitor integrator may include 4 first capacitors (i.e., C A1 -C A4 ) The method comprises the steps of carrying out a first treatment on the surface of the First switch group S A9 、S A10 The method comprises the steps of carrying out a first treatment on the surface of the A second switch group S A11 、S A12 As shown in fig. 2. Wherein the capacitance value of the first capacitor (e.g., 1/2C DAC ) Equal to the total capacitance value (e.g., C DAC ) 1/2 times that of (C).
Wherein the second passive switched capacitor integrator 20 may comprise: 2Q second capacitances and a third switch group connecting Q of the 2Q second capacitances in series and a fourth switch group connecting another Q of the 2Q second capacitances in series.
For example, the second passive switched capacitor integrator may include 4 second capacitors (i.e., C B1 –C B4 ) The method comprises the steps of carrying out a first treatment on the surface of the Third switch group S B9 、S B10 The method comprises the steps of carrying out a first treatment on the surface of the Fourth switch group S B11 、S B12 As shown in fig. 3. Wherein the capacitance of the second capacitor (e.g., 1/2C DAC ) Equal to the total capacitance value (e.g., C DAC ) 1/2 times that of (C).
The control logic circuit 40 is configured to close the first switch group and the second switch group to enable the first passive switched capacitor integrator to output a first residual voltage, and close the third switch group and the fourth switch group to enable the second passive switched capacitor integrator to output a second residual voltage when the capacitors in the capacitive analog-to-digital conversion array 30 are reset to an initial state.
Specifically, the first residual voltage is the sum of first sub-residual voltages of the 2Q first capacitors in a previous preset period, and the second residual voltage is the sum of second sub-residual voltages of the 2Q second capacitors in the previous preset period.
For example, after the start-up signal (Φrst signal) is restored to high (i.e., the capacitances in the capacitive analog-to-digital conversion array 30 are reset to an initial state) and the conversion control signal (Φcnv signal) is pulled high (as shown in fig. 5), the first and second switch groups (i.e., switches S) in the passive switched-capacitor integrator 10 are turned on A9 -S A12 ) And third switch group in passive switched capacitor integrator 20Four-switch group switch (i.e. switch S) B9 -S B12 ) The configuration of the passive switched-capacitor integrator 10 and the passive switched-capacitor integrator 20 is now closed as shown on the right side of fig. 4. The sub residual voltage V of the last preset period after passive integration in the passive switched capacitor integrator 10 is calculated EF After 2 times passive multiplication (i.e. a first residual voltage of 2V EF ) Connected in series with the input voltage and applied to a first differential input of the dual differential input comparator 50; at the same time, the sub residual voltage V of the last preset period of passive integration in the passive switched capacitor integrator 20 is calculated CIFF After 2 times passive multiplication (i.e. the second residual voltage is 2V CIFF ) Applied to the second differential input as shown in fig. 1.
The dual differential input comparator 50 is configured to receive a sum of the first residual voltage and an input voltage of a current preset period as a first differential input signal, receive the second residual voltage as a second differential input signal, and output a comparison result.
For example, the amplification factor of the first differential input terminal of the dual differential input comparator is 1; and the amplification factor of the second differential input end of the double differential input comparator is 5.
Specifically, the dual differential input comparator 50 outputs 2V from the passive switched capacitor integrator 10 when the comparator control signal Φclkc is high during the time that the signal Φcnv is high EF The sum of the first differential input signal and the input voltage is used as a first differential input signal; at the same time, 2V output by the passive switched capacitor integrator 10 CIFF As a second differential input signal, then, a corresponding comparison result is output according to the signal expressed by the above equation: when the sum of the signals received by the two positive differential ends of the comparator is larger than the sum of the signals received by the two negative differential ends of the comparator, the comparison result is positive, and otherwise, the comparison result is negative.
In the case that the dual differential input comparator outputs a comparison result, the control logic circuit 40 is further configured to output a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays according to the comparison result, so as to output digital data of a current preset period corresponding to the input voltage of the current preset period.
Specifically, the control logic circuit 40 may switch the capacitances on the corresponding bits in the two capacitive analog-to-digital conversion arrays 30 according to the switching scheme of the split switched capacitor array according to the comparison result output by the dual differential input comparator 50.
For example, when the comparison result is positive and the comparison (conversion) result of the kth bit is 1, the successive approximation control circuit 41 in the control logic circuit 40 controls the corresponding switch to drive the lower plate of the P-side capacitor corresponding to the kth bit in the capacitive analog-to-digital conversion array 30 at the input positive end from the positive reference voltage V REFP Change to negative reference voltage V REFN So that the voltage value V on the upper plate of the capacitor in the capacitive analog-to-digital conversion array 30 of the positive terminal is input DACP Lowering (1/4) k (V REFP -V REFN ) The method comprises the steps of carrying out a first treatment on the surface of the While the lower plate of the N-side capacitor in the capacitive analog-to-digital conversion array 30 at the negative input terminal is controlled by the successive approximation control circuit 41 to be controlled by the negative reference voltage V REFN Change to positive reference voltage V REFP So that the voltage value V on the upper plate of the capacitor in the capacitive analog-to-digital conversion array 30 of the negative terminal is input DACN Lifting (1/4) k (V REFP -V REFN ). Conversely, when the comparison result is negative, the comparison (conversion) result of the kth bit is 0, the lower plate of the N-side capacitor corresponding to the kth bit in the capacitive analog-to-digital conversion array 30 at the positive input end is driven by the negative reference voltage V REFN Change to positive reference voltage V REFP So that the voltage value V on the upper plate of the capacitor in the capacitive analog-to-digital conversion array 30 of the positive terminal is input DACP Lifting (1/4) k (V REFP -V REFN ) While the lower plate of the P-side capacitor in the capacitive analog-to-digital conversion array 30 at the negative input terminal is driven by the positive reference voltage V REFP Change to negative reference voltage V REFN So that the voltage value V on the upper plate of the capacitor in the capacitive analog-to-digital conversion array 30 of the negative terminal is input DACN Lowering (1/4) k (V REFP -V REFN ) To achieve a binary successive approximation with the common mode level unchanged.
The whole isThe successive approximation process is shown in the following formula, wherein N is the bit/bit number of the analog-to-digital converter, D k Representing the conversion result of the kth bit, V IP And V is equal to IN Representing the voltage value sampled by the capacitive analog-to-digital conversion array (i.e., CDAC) 30 at the positive input end and the voltage value of the capacitive analog-to-digital conversion array 30 at the negative input end, V REFP 、V REFN Respectively positive reference voltage/level, negative reference voltage/level, V DACP 、V DACN Representing the voltage value of the capacitive analog to digital conversion array (i.e., CDAC) 30 at the positive input and the voltage value of the capacitive analog to digital conversion array 30 at the negative input, respectively:
when the comparison is performed to the last bit, if the comparison result is positive, the lower plate of the lowest positive (P) side capacitor in the capacitive analog-to-digital conversion array (i.e. CDAC) 30 at the input positive end is changed from the positive reference voltage to the negative reference voltage to generate the correct residual voltage (V) RES ) Completing successive approximation conversion; otherwise, the bottom plate of the lowest positive (P) side capacitor of the capacitive analog-to-digital conversion array (i.e., CDAC) 30 at the negative input terminal is changed from the positive reference voltage to the negative reference voltage, and the successive approximation conversion is completed.
The first sub-residual voltage of the first capacitor in the previous preset period and the second sub-residual voltage of the second capacitor in the previous preset period in the above embodiments are described below.
The first passive switched-capacitor integrator 10 may further comprise: and a fifth switch group connected in parallel with the 2Q first capacitors, and correspondingly, after outputting the digital data of the last preset period corresponding to the input voltage of the last preset period, the control logic circuit is further configured to distribute the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitors by closing the fifth switch group, so that the voltages of the first capacitors are the first sub residual voltages.
For example, the first passive switched capacitor integrator 10 may further comprise: a fifth switch group (e.g., switch S shown in fig. 2) of 4 first capacitors connected in parallel A1 -S A8 )。
The second passive switched capacitor integrator 20 may further comprise: and a sixth switch group connecting the 2Q second capacitances in parallel, and correspondingly, after performing the step of distributing the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitances by closing the fifth switch group, the control logic circuit is further configured to open the fifth switch group and distribute the updated residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q second capacitances by closing the sixth switch group so that the voltages of the second capacitances are the second sub residual voltages.
For example, the second passive switched capacitor integrator 20 may further include: a sixth switch group of 4 second capacitances connected in parallel (e.g., switch S shown in FIG. 2 B1 -S B8 )。
Specifically, after the previous preset period is converted to the corresponding digital data, in the analog domain, the control logic 40 controls the control signal Φef to be pulled high to turn on the fifth switch group (i.e., switch S) in the passive switched capacitor integrator 10 A1 -S A8 The passive switched-capacitor integrator 10 is now configured as shown in the left-hand side of fig. 4) so that the residual voltage on the upper plates of all the capacitors of the capacitive analog-to-digital conversion array 30 can be sampled differentially to the integrating capacitor C by charge redistribution between the capacitors A1 -C A4 The upper part of the upper part is provided with a plurality of grooves,to achieve a first order passive integration. This process satisfies the formula V EF For the first capacitor, a first sub-residual voltage of the last preset period is:
after ΦEF returns to low (switch S open A1 -S A8 ) Thereafter, the control logic circuit 40 controls the signal Φciff to pull high to turn on the sixth switch set (i.e., switch S) in the passive switched capacitor integrator 20 B1 -S B8 The configuration of the passive switched-capacitor integrator 20 is shown on the left side of fig. 4) updates the residual voltages on the upper plates of all the capacitors of the capacitive analog-to-digital conversion array 30 (i.e., the residual voltages of the capacitive analog-to-digital conversion array 30 sampled by the passive switched-capacitor integrator 10, which have a value equal to the capacitor C A1 -C A4 Voltage V on each capacitor in (a) EF ) Sampling to integrating capacitor C using charge redistribution in differential mode B1 -C B4 And the second-order passive integration is realized. This process satisfies the formula V CIFF A second sub residual voltage of the last preset period is set for the second capacitor:
2V output by the passive switched capacitor integrator 10 EF The sum of the sum and the input voltage is used as a first differential input signal of the dual differential input comparator 50; at the same time, 2V output by the passive switched capacitor integrator 10 CIFF As the second differential input signal, the successive approximation control circuit 41 outputs a signal (a system signal transfer function of the discrete domain) represented by:
D OUT (z)＝V INPUT (z)+4V EF (z)+5×4V CIFF (z)＝V INPUT (z)+(1-0.8z -1 ) 2 Q(z)，
Where z is a variable in the discrete domain, V CIFF Corresponding 5 times of additional gain pass ratioThe size of the transistor of the second differential input of the comparator is implemented in a corresponding multiple of the size of the transistor of the first differential input.
The second-order passive hybrid noise shaping technology samples and integrates the converted residual voltage through two groups of passive switched capacitor integrators, and then feeds the output of the two integrators into the input sampling signal of the next period for conversion in a mode of error feedback and forward addition, so that in-band quantization noise and comparator noise of the analog-to-digital converter are modulated to a high frequency band, and a second-order high-pass noise shaping effect is realized. The scheme can effectively reduce quantization noise and comparator noise in the signal bandwidth, and can further improve the in-band signal-to-noise ratio of the analog-to-digital converter and simultaneously maintain a smaller chip area.
For a capacitive analog to digital conversion array (i.e., CDAC) 30, it includes: n pairs of capacitors and corresponding N pairs of switches. Each pair of capacitors corresponds to one data bit, specifically, the N pairs of capacitors include a pair of highest capacitors (including a highest capacitor on the positive side and a highest capacitor on the negative side) and N-1 pairs of other low capacitors (including N-2 middle low capacitors on the positive side, N-2 middle low capacitors on the negative side, and 1 lowest capacitor and 1 complementary capacitor on the positive side), which sequentially correspond to the highest data and the low N-1 data.
Although the over-sampling and noise shaping techniques can effectively improve the in-band signal-to-noise ratio of the analog-to-digital converter, the effects of harmonic distortion introduced by the capacitor array mismatch on the analog-to-digital converter cannot be reduced, and the latter often has a greater effect on the signal-to-noise ratio of the high-resolution analog-to-digital converter.
Aiming at the technical problems, in the embodiment, a low-order conversion result of a previous preset period is fed into a current conversion mechanism aiming at error feedback mismatch error shaping based on a predicted input signal pre-offset technology, and the section where a voltage value to be converted after the low-order result is fed into a next period is predicted according to the conversion result of the previous preset period by utilizing the characteristic of oversampling; the input pre-offset is realized by pre-switching the high-order capacitor of the capacitor array, so that the voltage to be converted does not exceed the full swing of the input signal range, and the input dynamic range is not influenced. It should be noted that, since the present approach employs a two-point prediction technique, it can effectively avoid introducing new harmonics.
In an embodiment, the digital data may be N-bit data, and the analog-to-digital converter may further include: sampling switch circuit 60 is shown in fig. 1.
The control logic 40 is further configured to, prior to resetting the capacitances in the two capacitive analog-to-digital conversion arrays to an initial state: according to the predicted value of the current preset period, connecting lower polar plates of the highest capacitors on the positive electrode side and the negative electrode side in the two capacitive analog-to-digital conversion arrays to different reference voltages; switching on the sampling switch circuit to sample the input voltage of the current preset period to the capacitive analog-to-digital conversion array; and disconnecting the sampling switch circuit, and resetting each capacitor in the capacitive analog-to-digital conversion array to an initial state so as to feed in a pre-offset compensation amount corresponding to the reference voltage and low-N-1 bit data in the N-bit data output in the last preset period.
Wherein the control logic 40 is configured to connect the bottom plates of the highest capacitors on the positive and negative sides of the two capacitive analog-to-digital conversion arrays to different reference voltages may include: connecting the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the positive input end to a positive reference voltage and the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the negative input end to a negative reference voltage, with a predicted value of 1 for the current preset period; or in case that the predicted value for the current preset period is 0, connecting the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the positive end of the input to a negative reference voltage, and connecting the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the negative end of the input to the positive reference voltage.
Wherein the control logic 40 is configured to reset each capacitor in the capacitive analog-to-digital conversion array to an initial state may include: the lower plate of the capacitor on the positive side in the capacitive analog-to-digital conversion array is connected to a positive reference voltage, and the lower plate of the capacitor on the negative side in the capacitive analog-to-digital conversion array is grounded.
Specifically, after obtaining the predicted value about the current preset period, the lower plates of the highest capacitors of the two capacitive analog-to-digital conversion arrays 30 are controlled according to the corresponding predicted result and changed to the positive reference voltage (the predicted result is positive) or the negative reference voltage (the predicted result is negative) to input the pre-offset, so as to prepare for the input pre-offset: as a result, the lower plates of the highest capacitors on the positive electrode (P) side are all changed to the positive reference voltage, and the lower plates of the highest capacitors on the negative electrode (N) side are all changed to the negative reference voltage; and the predicted result is negative, otherwise.
At the beginning of a preset period, the control logic circuit 40 pulls the sampling control signal Φclks high and holds for 4 clock cycles to turn on the sampling switch, so that the input signal can be differentially sampled onto the capacitive analog-to-digital conversion array 30 at the positive and negative ends; the switches connected with the lower polar plates of the rest low-order capacitors keep the connection of the last preset period unchanged, and the low-order conversion result of the last preset period is kept on the corresponding bit so as to realize the mismatch error shaping (of the low-order capacitors compared with the highest-order capacitors).
After the control signal Φclks goes low (i.e., turns off the sampling switch circuit 60), the start signal Φrst is pulled low for one clock cycle to reset all the capacitances in the capacitive analog-to-digital conversion array 30 to an initial state after a short delay: the lower plates of all capacitors on the P side are changed to the positive reference voltage and the lower plates of all capacitors on the N side are changed to ground. During resetting, the feeding of the low-order conversion result of the last preset period required by mismatch error shaping is completed simultaneously, and the input pre-offset compensation amount + -1/2 (V) required by mismatch error shaping influence is eliminated REFP -V REFN ) (in case the predicted value for the current preset period is 1, it will be at the positive inputThe lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array are connected to a positive reference voltage and the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the negative input terminal are connected to a negative reference voltage, in which case the compensation introduced in the reset phase is negative, i.e., -1/2 (V REFP -V REFN ) The method comprises the steps of carrying out a first treatment on the surface of the Conversely, the compensation introduced during the reset phase is positive, i.e. +1/2 (V REFP -V REFN ) Is added) to the process. The pre-offset operation can offset the overload of the input signal caused by feeding the last low-order conversion result, so that the fed signal to be converted is still in the normal input range of the analog-to-digital converter, thereby avoiding the input dynamic range loss caused by adopting mismatch error shaping. Because the scheme only needs to add an array adder, an additional dynamic element matching circuit is not needed, the influence of the original mismatch error shaping scheme on the input dynamic range is eliminated, and the implementation is simple and the robustness is good.
Since the low N-1 bit data DAC of the last preset period output is introduced before conversion (i.e. in the analog domain) LSB (n-1) and Pre-offset Compensation amount DAC PRE (N) as shown in fig. 6, the converted N-bit data of the current preset period can be correspondingly corrected.
After performing the step of outputting digital data of a current preset period corresponding to the input voltage of the current preset period, the control logic circuit 40 is further configured to perform the following operations: subtracting low-N-1 bit data in the N-bit data output in the previous preset period from the N-bit data output in the current preset period to obtain an N-bit difference value; and subtracting a value corresponding to the pre-offset compensation amount from the N-bit difference value to output compensated N-bit data of the current preset period corresponding to the input voltage of the current preset period.
Specifically, since the last low-order signal of the preset period is added to the input signal in the analog domain, the 10-bit data D outputted from the analog-to-digital converter in the digital domain after the conversion is completed<1:10>(the lower 9 bits of the current preset period nData D LSB (n) the most significant data D corresponding to the current preset period n MSB (n) sum) into subtractor using D <1:10>Subtracting the lower 9-bit conversion result of the last preset period n-1 stored in the corresponding register (i.e., D LSB (n-1)), as shown in FIG. 6, to construct a corresponding high-pass shaping transfer function (1-z) for the lower capacitance versus the most significant mismatch E (n) -1 ) And realizing first-order high-pass mismatch error shaping.
The reason is as follows: since the actual low-order capacitance has a mismatch compared to the highest-order capacitance, the low-order conversion result of the mode converter (DAC) will carry the corresponding mismatch error E (n) (where DAC LSB (n) represents the low-order conversion result left on the CDAC-corresponding lower plate, D LSB (n) represents the lower 9-bit result excluding the most significant bit in the output digital code),
DAC LSB (n)＝D LSB (n)+E(n)；
mismatch shaping (MES) techniques rely on returning the low order of the conversion result of the previous cycle carrying the mismatch error E (n) to the current cycle, constructing a high-pass shaping function for E (n). In the analog domain, only the last converted low bit (LSB) result is kept on the corresponding capacitor lower polar plate during sampling, and the input signal and DAC can be realized by resetting after the sampling is completed LSB Addition of (n):
V INPUT (n)+DAC LSB (n-1)-DAC MSB (n)-DAC LSB (n)＝0；
since the last period of low-order signal is added to the input signal in the analog domain, after the conversion is completed, the 10-bit output D of the analog-to-digital converter is in the digital domain <1:10>Enters a subtracter to subtract the last 9-bit conversion result stored in the corresponding register to subtract the last-period low-bit result fed in, and constructs a corresponding high-pass shaping transfer function (1-z -1 ) Realizing first-order high-pass mismatch error shaping:
D OUT (n)＝D MSB (n)+D LSB (n)-D LSB (n-1)。
substituting the first two formulas into a third formula, and finishing to obtain
D OUT (n)＝V INPUT (n)+E(n-1)-E(n)，
Namely:
D OUT (z)＝V INPUT (z)+(1-z -1 )E(z)，
which is equivalent to first order high pass shaping of mismatch errors carried in the output result.
The result of the above subtraction is then fed to an adder-subtractor to subtract the value corresponding to the pre-offset compensation amount (i.e., D shown in FIG. 6 PRE (n)) taking the output result as the output digital quantity S after compensation with the current preset period<1:10>. Specifically, according to the predicted value with respect to the current preset period, in the case where the predicted value with respect to the current preset period is 1, the compensation amount introduced in the reset phase is a negative value (i.e., -1/2 (V REFP -V REFN ) Then add 1/2 (V) to the subtraction result REFP -V REFN ) The method comprises the steps of carrying out a first treatment on the surface of the Conversely, in the case where the predicted value for the preset period is 0, the compensation amount introduced in the reset phase is a positive value (i.e., +1/2 (V REFP -V REFN ) Subtracting 1/2 (V) from the subtraction result REFP -V REFN )。
After acquiring the compensated N-bit data of the current preset period, the control logic circuit 40 is further configured to add the compensated N-bit data of the current preset period to the low N-1 bit data of the N-bit data output by the current preset period to acquire a predicted value related to the next preset period.
Specifically, the output processing and predicting circuit 42 in the control logic circuit 40 outputs the compensated N-bit data S of the current preset period<1:10>The lower N-1 bit data D in the N bit data output from the current preset period LSB (n) adding to obtain a predicted value for the next preset period.
The output processing and predicting circuit 42 further SETs the corresponding control bit to 0 (positive predicted value) or 1 (negative predicted value) according to the positive and negative of the predicted value of the next preset period, and then sends the value of the control bit to the control switch of the highest capacitor when the last clock rising edge of the current preset period and the ΦSET signal is high, and the lower plate of the highest capacitor is changed to realize the input signal pre-shift predicted based on the input signal range.
Since the analog-to-digital conversion process requires the corresponding result of the last preset period, the corresponding preset period is defined in the above embodiments, but it should be noted that each step in the analog-to-digital conversion process in each of the above embodiments is not limited to the corresponding preset period (e.g., the current preset period), and it can be similarly applied to each preset period (e.g., the last preset period or the next preset period).
The following describes the analog-to-digital conversion process in the current preset period, which mainly includes the following steps S1-S8.
S1: the ΦSET signal is high at the last clock rising edge of the last preset period, and the lower plates of the highest capacitors at the positive side and the negative side in the capacitive analog-to-digital conversion array 30 can be controlled to be changed to a positive reference voltage (the predicted result is positive) or a negative reference voltage (the predicted result is negative) together according to the corresponding predicted result of the last preset period to the current preset period so as to prepare for inputting the pre-offset.
S2: when the current preset period starts, the sampling control signal Φclks is pulled up and kept for 4 clock periods to turn on the sampling switch, so as to differentially sample the input signal onto the two capacitive analog-to-digital conversion arrays 30; the switches connected with the lower polar plates of the rest low-order capacitors maintain the connection of the last preset period unchanged so as to keep the low-order conversion result of the last preset period on the corresponding bit, thereby realizing the mismatch error shaping (of the low-order capacitors compared with the highest-order capacitors).
S3: after the control signal Φclks goes low, the start signal Φrst is pulled down by one clock cycle after a short delay, resetting all the capacitances in the two capacitive analog-to-digital conversion arrays 30 to an initial state.
S4: after the Φrst signal returns high, the Φcnv signal pulls high to pull switch S in passive switched-capacitor integrator 10 A9 -S A12 And in a passive switched-capacitor integrator 20Switch S B9 -S B12 Closing, namely passively integrating the sub residual voltage V of the last preset period in the passive switched capacitor integrator 10 EF After 2 times passive multiplication (i.e. a first residual voltage of 2V EF ) Connected in series with the input voltage and applied to a first differential input of the dual differential input comparator 50; at the same time, the sub residual voltage V of the last preset period of passive integration in the passive switched capacitor integrator 20 is calculated CIFF After 2 times passive multiplication (i.e. the second residual voltage is 2V CIFF ) Applied to the second differential input.
S5: during the time when the control signal Φcnv is high, the dual differential input comparator 50 outputs 2V from the passive switched capacitor integrator 10 when the comparator control signal Φclkc is high EF The sum of the first differential input signal and the input voltage is used as a first differential input signal; at the same time, 2V output by the passive switched capacitor integrator 10 CIFF As a second differential input signal, and outputs a comparison result. According to the output of the comparator, the capacitances on the corresponding bits in the two capacitive analog-to-digital conversion arrays 30 are switched according to a switching scheme that splits the switched capacitance arrays.
S6: after the conversion is completed, in the analog domain, the control signal ΦEF is pulled high to turn on the switch S in the passive switched-capacitor integrator 10 A1 -S A8 Sampling the residual voltage on the upper plate of the capacitive analog-to-digital conversion array 30 to the integrating capacitance C in a differential manner by charge redistribution between the capacitances A1 -C A4 To achieve a first order passive integration. After Φef returns low, the control signal Φciff pulls high to turn on switch S in passive switched capacitor integrator 20 B1 -S B8 Sampling the residual voltage on the upper plate of the capacitive analog-to-digital conversion array 30 to the integrating capacitance C using charge redistribution in a differential manner B1 -C B4 And the second-order passive integration is realized.
S7: since the last low-order signal with preset period is added into the input signal in the analog domain, after the conversion is completed, the 10-bit data D output by the analog-to-digital converter is output in the digital domain<1:10>Enter subtracter, use D<1:10>Subtracting D stored in the corresponding register LSB (n-1), as shown in fig. 6, first order high pass mismatch error shaping is implemented. Then, the subtraction result is sent to an adder-subtractor, and the value D corresponding to the pre-offset compensation amount is subtracted according to the predicted value of the current preset period PRE (n) taking the output result as the output digital quantity S after compensation with the current preset period <1:10>。
S8: the output processing and predicting circuit 42 outputs the compensated N-bit data S of the current preset period<1:10>The lower N-1 bit data D in the N bit data output from the current preset period LSB (n) adding to obtain a predicted value for the next preset period. The output processing and predicting circuit 42 further SETs the corresponding control bit to 0 (positive predicted value) or 1 (negative predicted value) according to the positive and negative of the predicted value of the next preset period, and then sends the value of the control bit to the control switch of the highest capacitor when the last clock rising edge of the current preset period and the ΦSET signal is high, and the lower plate of the highest capacitor is changed to realize the input signal pre-shift predicted based on the input signal range.
The above embodiments mainly adopt two technologies, namely a passive hybrid noise shaping technology and a pre-offset technology based on a predicted input signal, so as to further improve the signal-to-noise ratio in the signal band of the analog-to-digital converter, and realize a higher signal-to-noise ratio and a spurious-free dynamic range (SFDR) with lower system complexity, smaller chip area and lower power consumption. The scheme can be applied to a low-power consumption sensor system, can effectively reduce quantization noise in a signal bandwidth, improve the in-band signal-to-noise ratio of the analog-to-digital converter, and can eliminate the influence of a mismatch error shaping technology on the input dynamic range of the analog-to-digital converter while having a good mismatch error shaping (eliminating) effect, thereby effectively improving the resolution and linearity of the analog-to-digital converter in the system.
In summary, in the case that the capacitors in the two capacitive analog-to-digital conversion arrays are reset to the initial state, the first switch group and the second switch group are closed by the control logic circuit to enable the first passive switched capacitor integrator to output a first residual voltage, and the third switch group and the fourth switch group are closed by the control logic circuit to enable the second passive switched capacitor integrator to output a second residual voltage; receiving the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal through a double differential input comparator, receiving the second residual voltage as a second differential input signal, and outputting a comparison result; and then, outputting a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays through the control logic circuit according to the comparison result so as to output digital data of the current preset period corresponding to the input voltage of the current preset period. The invention adopts the second-order passive mixed noise shaping technology to sample and integrate the residual voltage of the previous preset period through two groups of passive switched capacitor integrators, and respectively converts the input sampling signals fed into the current period by the output of the two integrators in an error feedback and forward addition mode, thereby modulating the in-band quantization noise and the comparator noise of the analog-to-digital converter to a high frequency band, realizing the second-order high-pass noise shaping effect and inhibiting the related noise in the signal band.
The embodiment of the invention also provides a chip, which comprises the analog-to-digital converter.
Specific details and benefits of the chip provided by the embodiments of the present invention can be found in the above description of the analog-to-digital converter, and are not repeated here.
The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all the simple modifications belong to the protection scope of the present invention.
In addition, the specific features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various possible combinations are not described further.
Those skilled in the art will appreciate that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, including instructions for causing a single-chip microcomputer, chip or processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Moreover, any combination of the various embodiments of the invention can be made without departing from the spirit of the invention, which should also be considered as disclosed herein.
Claims (10)
1. An analog-to-digital converter, the analog-to-digital converter comprising:
a first passive switched capacitor integrator, comprising: 2Q first capacitances and a first switch group connecting Q capacitances of the 2Q first capacitances in series and a second switch group connecting another Q capacitances of the 2Q first capacitances in series;
a second passive switched capacitor integrator comprising: 2Q second capacitances and a third switch group connecting Q of the 2Q second capacitances in series and a fourth switch group connecting another Q of the 2Q second capacitances in series;
two capacitive analog-to-digital conversion arrays;
the control logic circuit is used for closing the first switch group and the second switch group under the condition that the capacitors in the two capacitive analog-to-digital conversion arrays are reset to an initial state, so that the first passive switched capacitor integrator outputs a first residual voltage, and closing the third switch group and the fourth switch group, so that the second passive switched capacitor integrator outputs a second residual voltage, wherein the first residual voltage is the sum of first sub residual voltages of the 2Q first capacitors in a last preset period, and the second residual voltage is the sum of second sub residual voltages of the 2Q second capacitors in the last preset period; and
A dual differential input comparator for receiving a sum of the first residual voltage and an input voltage of a current preset period as a first differential input signal, receiving the second residual voltage as a second differential input signal, and outputting a comparison result,
the control logic circuit is further configured to output a plurality of switch control signals to the two capacitive analog-to-digital conversion arrays according to the comparison result, so as to output digital data of a current preset period corresponding to the input voltage of the current preset period.
2. The analog-to-digital converter of claim 1, wherein the first passive switched-capacitor integrator further comprises: a fifth switch group connecting the 2Q first capacitors in parallel,
correspondingly, after outputting the digital data of the previous preset period corresponding to the input voltage of the previous preset period, the control logic circuit is further configured to distribute the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitors by closing the fifth switch group, so that the voltages of the first capacitors are the first sub residual voltages.
3. The analog-to-digital converter of claim 2, wherein the second passive switched-capacitor integrator further comprises: a sixth switch group connecting the 2Q second capacitors in parallel,
Accordingly, after performing the step of distributing the residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q first capacitances by closing the fifth switch group, the control logic is further configured to open the fifth switch group and distribute the updated residual voltages of the upper plates of the two capacitive analog-to-digital conversion arrays to the 2Q second capacitances by closing the sixth switch group such that the voltages of the second capacitances are the second sub-residual voltages.
4. The analog-to-digital converter of claim 1, wherein the digital data is N-bit data, and the analog-to-digital converter further comprises: the sampling switch circuit is used for sampling the data,
the control logic is further configured to, prior to resetting the capacitances in the two capacitive analog-to-digital conversion arrays to an initial state, perform the following operations:
according to the predicted value of the current preset period, connecting lower polar plates of the highest capacitors on the positive electrode side and the negative electrode side in the two capacitive analog-to-digital conversion arrays to different reference voltages;
switching on the sampling switch circuit to sample the input voltage of the current preset period to the capacitive analog-to-digital conversion array; and
And switching off the sampling switch circuit, and resetting each capacitor in the capacitive analog-to-digital conversion array to an initial state so as to feed in a pre-offset compensation amount corresponding to the reference voltage and low-N-1 bit data in the N-bit data output in the last preset period.
5. The analog-to-digital converter of claim 4, wherein after performing the step of outputting digital data of a current preset period corresponding to the input voltage of the current preset period, the control logic circuit is further configured to:
subtracting low-N-1 bit data in the N-bit data output in the previous preset period from the N-bit data output in the current preset period to obtain an N-bit difference value; and
subtracting a value corresponding to the pre-offset compensation amount from the N-bit difference value to output compensated N-bit data of the current preset period corresponding to the input voltage of the current preset period.
6. The analog-to-digital converter of claim 5, wherein said control logic is further configured to add the compensated N-bit data of the current preset period to the low N-1 bit data of the N-bit data output from the current preset period to obtain a predicted value for the next preset period.
7. The analog-to-digital converter of claim 4, wherein the control logic circuit for connecting the bottom plates of the highest bit capacitances of the positive and negative sides of the two capacitive analog-to-digital conversion arrays to different reference voltages comprises:
connecting the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the positive input end to a positive reference voltage and the lower plates of the highest capacitors of the positive and negative sides in the capacitive analog-to-digital conversion array at the negative input end to a negative reference voltage, with a predicted value of 1 for the current preset period; or alternatively
In case that the predicted value for the current preset period is 0, the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the positive input end are connected to a negative reference voltage, and the lower plates of the highest capacitors on the positive and negative sides in the capacitive analog-to-digital conversion array at the negative input end are connected to a positive reference voltage.
8. The analog-to-digital converter of claim 4, wherein the control logic circuit for resetting each capacitor in the capacitive analog-to-digital conversion array to an initial state comprises:
The lower plate of the capacitor on the positive side in the capacitive analog-to-digital conversion array is connected to a positive reference voltage, and the lower plate of the capacitor on the negative side in the capacitive analog-to-digital conversion array is grounded.
9. The analog-to-digital converter of claim 1, wherein said first passive switched capacitor integrator comprises 4 first capacitors; and the second passive switched capacitor integrator comprises 4 second capacitors,
wherein the capacitance value of the first capacitor and the second capacitor is equal to 1/2 times of the total capacitance value of the capacitive analog-to-digital conversion array.
10. Chip, characterized in that it comprises an analog-to-digital converter according to any of claims 1-9.
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