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CN116344620A - MOS structure with shielding grid and manufacturing method thereof - Google Patents

MOS structure with shielding grid and manufacturing method thereof Download PDF

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Publication number
CN116344620A
CN116344620A CN202310334838.3A CN202310334838A CN116344620A CN 116344620 A CN116344620 A CN 116344620A CN 202310334838 A CN202310334838 A CN 202310334838A CN 116344620 A CN116344620 A CN 116344620A
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China
Prior art keywords
layer
substrate
oxide layer
mos structure
forming
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Application number
CN202310334838.3A
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Chinese (zh)
Inventor
韩继武
周闻天
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202310334838.3A priority Critical patent/CN116344620A/en
Publication of CN116344620A publication Critical patent/CN116344620A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a MOS structure with a shielding gate, which comprises a substrate, wherein a groove is formed on the substrate; a first oxide layer is formed on the groove, and a first silicon nitride layer and a second oxide layer with heights lower than the depth of the groove are sequentially formed on the first oxide layer; a shielding gate polysilicon layer and a third oxide layer positioned on the shielding gate polysilicon layer are formed on the second oxide layer; the control gate polysilicon layer is formed on the rest part of the groove; the substrate is provided with a doped well, a source region, a drain region and a metal interconnection layer which is electrically contacted with the control gate polysilicon layer and the source region and the drain region. According to the MOS structure with the shielding gate, a gate dielectric layer does not need to be regrown in the manufacturing process, and the process is simplified.

Description

MOS structure with shielding grid and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a MOS structure with a shielding gate and a manufacturing method thereof.
Background
MOSFET Metal-Oxide-semiconductor field effect transistor (MOSFET) is abbreviated as Metal-Oxide-Semiconductor Field-Effect Transistor. Typically metal-oxide-semiconductor field effect transistors, or metal-insulator-semiconductors. G: gate; s: source; d: drain of drain. The source and drain of the MOS transistor are interchangeable, and they are both N-type regions formed in the P-type back gate. In most cases, the two regions are identical, and even the two ends are reversed, so that the performance of the device is not affected. Such devices are considered symmetrical. The field effect transistor is divided into a PMOS (P-channel type) transistor and an NMOS (N-channel type) transistor, and belongs to an insulated gate field effect transistor.
Referring to fig. 1, a prior art MOS structure with a shield gate includes:
a substrate 201, a trench being formed on the substrate 201;
a shielding gate dielectric layer 202 with a U-shaped section is formed on the groove, and a shielding gate polysilicon layer 203 is formed on the shielding gate dielectric layer 202;
a first control gate dielectric layer 204 is formed on the shielding gate dielectric layer 202 and the shielding gate polysilicon layer 203, a second control gate dielectric layer 206 is formed on at least the side wall of the groove of the first control gate dielectric layer 204, and a control gate polysilicon layer 205 is formed between the first control gate dielectric layer and the second control gate dielectric layer;
doped wells and source and drain regions, and a metal interconnect layer 207 in electrical contact with the control gate polysilicon layer 206, the source and drain regions are formed on the substrate 201.
The MOS structure generally uses only an oxide layer as the gate dielectric layer, which is generally removed after the back etching of the shielded gate polysilicon layer 203, and the control gate dielectric layer needs to be regrown.
In order to solve the above-mentioned problems, a novel MOS structure with a shielding gate and a method for manufacturing the same are needed.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present invention is directed to providing a MOS structure with a shielding gate and a method for manufacturing the same, which are used for solving the problem that in the prior art, a gate dielectric layer is generally removed after a shielding gate polysilicon layer is etched back, and a control gate dielectric layer needs to be regrown.
To achieve the above and other related objects, the present invention provides a MOS structure with a shield gate, comprising:
a substrate on which a trench is formed;
a first oxide layer is formed on the groove, and a first silicon nitride layer and a second oxide layer with the heights lower than the depth of the groove are sequentially formed on the first oxide layer;
a shielding gate polysilicon layer and a third oxide layer positioned on the shielding gate polysilicon layer are formed on the second oxide layer;
a control gate polysilicon layer is formed on the rest part of the groove;
and a doped well, a source region, a drain region and a metal interconnection layer which is electrically contacted with the control gate polysilicon layer and the source region and the drain region are formed on the substrate.
Preferably, the substrate comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
The invention provides a manufacturing method of a MOS structure with a shielding gate, which comprises the following steps:
step one, providing a substrate, and forming a groove on the substrate;
forming a first lamination layer covering the groove on the substrate, wherein the first lamination layer consists of a first oxide layer, a first nitride layer and a second oxide layer which are stacked in sequence from bottom to top;
step three, forming a shielding gate polysilicon layer on the second oxide layer by utilizing deposition and back etching;
forming a third oxide layer on the shielding gate polysilicon layer;
step five, etching to remove the first nitride layer and the second oxide layer on the third oxide layer;
forming a control gate polysilicon layer filling the rest grooves by deposition and back etching;
and step seven, grinding the first oxide layer to the substrate to form a doped well, a source region and a drain region, and then forming a metal interconnection layer which is electrically contacted with the control gate polysilicon layer and the source region and the drain region.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, before forming the trench in the first step, a second lamination layer is formed on the substrate, and the second lamination layer is composed of a fourth oxide layer, a second nitride layer and a fifth oxide layer which are stacked in sequence from bottom to top.
Preferably, the method of back etching in the third step is dry etching.
Preferably, the third oxide layer is formed by a thermal oxidation method in the fourth step.
Preferably, the etching method in the fifth step is wet etching.
Preferably, the method of etching back in the step six is dry etching.
Preferably, the polishing method in the seventh step is chemical mechanical planarization polishing.
As described above, the MOS structure with shielding gate and the method for manufacturing the same of the present invention have the following advantages:
according to the MOS structure with the shielding gate, a gate dielectric layer does not need to be regrown in the manufacturing process, and the process is simplified.
Drawings
Fig. 1 is a schematic diagram of a prior art MOS structure with a shield gate;
FIG. 2 is a schematic diagram of forming a trench in a substrate in accordance with the present invention;
FIG. 3 is a schematic view of a first laminate formed in accordance with the present invention;
FIG. 4 is a schematic diagram of a polysilicon layer for forming a shield gate according to the present invention;
FIG. 5 is a schematic diagram illustrating formation of a third oxide layer according to the present invention;
FIG. 6 is a schematic diagram of an etched first stack according to the present invention;
FIG. 7 is a schematic diagram of forming a control gate polysilicon layer according to the present invention;
FIG. 8 is a schematic diagram of a metal interconnect layer formed in accordance with the present invention;
fig. 9 shows a schematic process flow diagram of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 8, the present invention provides a MOS structure with a shielding gate, including:
a substrate 101, a trench being formed on the substrate 101;
a first oxide layer 1031 is formed on the trench, and a first silicon nitride layer and a second oxide layer 1033 with heights lower than the depth of the trench are sequentially formed on the first oxide layer 1031; the first silicon nitride layer and the second oxide layer 1033 are generally uniform in height on top, and the first and second oxide layers are made of silicon dioxide.
A shield gate polysilicon layer 104 and a third oxide layer 105 on the shield gate polysilicon layer 104 are formed on the second oxide layer 1033;
the remainder of the trench is formed with a control gate polysilicon layer 106;
doped wells and source and drain regions, and a metal interconnect layer 107 in electrical contact with the control gate polysilicon layer 106, the source and drain regions are formed on the substrate 101.
Preferably, the substrate 101 comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
Referring to fig. 9, the present invention further provides a method for manufacturing a MOS structure with a shield gate, including:
step one, providing a substrate 101, forming a groove on the substrate 101, and forming a structure shown in fig. 2;
preferably, the substrate 101 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
Preferably, before forming the trench in the first step, a second stack 102 is further formed on the substrate 101, where the second stack 102 is composed of a fourth oxide layer, a second nitride layer, and a fifth oxide layer stacked sequentially from bottom to top, and the second stack 102 is removed in a subsequent polishing step.
Step two, forming a first stack 103 covering the trench on the substrate 101, wherein the first stack 103 is composed of a first oxide layer 1031, a first nitride layer 1032 and a second oxide layer 1033 which are stacked in sequence from bottom to top, so as to form a structure as shown in fig. 3;
step three, forming a shielding gate polysilicon layer 104 on the second oxide layer 1033 by deposition and back etching to form a structure shown in fig. 4; i.e., a layer of polysilicon material is deposited in the trench, and then the selectivity of the etch back is controlled, the polysilicon material being etched back to form the shield gate polysilicon layer 104 of the desired thickness.
Preferably, the method of etching back in the third step is dry etching.
Step four, forming a third oxide layer 105 on the shielding gate polysilicon layer 104 to form a structure shown in fig. 5;
preferably, the third oxide layer 105 is formed using a thermal oxidation method in step four.
Step five, etching to remove the first nitride layer 1032 and the second oxide layer 1033 on the third oxide layer 105, so as to form a structure as shown in fig. 6;
preferably, the etching method in the fifth step is wet etching, and the first nitride layer 1032 and the second oxide layer 1033 are sequentially removed by controlling the selection ratio of the wet etching.
Step six, forming a control gate polysilicon layer 106 filling the residual grooves by deposition and back etching to form a structure shown in fig. 7; i.e., a layer of polysilicon material is deposited in the trench, and then the selectivity of the etch back is controlled, the polysilicon material being etched back to form the control gate polysilicon layer 106 of the desired thickness.
Preferably, the method of etching back in the step six is dry etching.
Step seven, grinding the first oxide layer 1031 to the substrate 101 to form a doped well and source and drain regions (not shown in the figure), and then forming a metal interconnection layer 107 electrically contacting the control gate polysilicon layer 106 and the source and drain regions, thereby forming the structure shown in fig. 8. The metal interconnect layer 107 is formed by a metal interconnect process, which is a process of depositing a metal thin film on an integrated circuit chip and forming wiring by photolithography, and interconnecting the isolated elements to a desired circuit according to certain requirements, and may be typically a copper interconnect process or an aluminum interconnect process, i.e., forming a multi-layered sequentially stacked interlayer dielectric layer (typically silicon dioxide), a metal layer structure (e.g., copper or aluminum), and electrically connecting the different metal layers through a contact hole structure (typically tungsten filled contact holes).
Preferably, the polishing method in the seventh step is chemical mechanical planarization polishing.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, according to the MOS structure with the shielding gate, the gate dielectric layer does not need to be regrown in the manufacturing process, so that the process is simplified. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The MOS structure with shielding gate of claim 1, comprising:
a substrate on which a trench is formed;
a first oxide layer is formed on the groove, and a first silicon nitride layer and a second oxide layer with the heights lower than the depth of the groove are sequentially formed on the first oxide layer;
a shielding gate polysilicon layer and a third oxide layer positioned on the shielding gate polysilicon layer are formed on the second oxide layer;
a control gate polysilicon layer is formed on the rest part of the groove;
and a doped well, a source region, a drain region and a metal interconnection layer which is electrically contacted with the control gate polysilicon layer and the source region and the drain region are formed on the substrate.
2. The MOS structure with shielding gate of claim 1, wherein: the substrate comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method for manufacturing a MOS structure with a shield gate according to any one of claims 1 to 2, characterized by comprising at least:
step one, providing a substrate, and forming a groove on the substrate;
forming a first lamination layer covering the groove on the substrate, wherein the first lamination layer consists of a first oxide layer, a first nitride layer and a second oxide layer which are stacked in sequence from bottom to top;
step three, forming a shielding gate polysilicon layer on the second oxide layer by utilizing deposition and back etching;
forming a third oxide layer on the shielding gate polysilicon layer;
step five, etching to remove the first nitride layer and the second oxide layer on the third oxide layer;
forming a control gate polysilicon layer filling the rest grooves by deposition and back etching;
and step seven, grinding the first oxide layer to the substrate to form a doped well, a source region and a drain region, and then forming a metal interconnection layer which is electrically contacted with the control gate polysilicon layer and the source region and the drain region.
4. The method for manufacturing a MOS structure with a shield gate according to claim 3, wherein: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
5. The method for manufacturing a MOS structure with a shield gate according to claim 3, wherein: and before forming the groove in the first step, forming a second lamination layer on the substrate, wherein the second lamination layer consists of a fourth oxide layer, a second nitride layer and a fifth oxide layer which are stacked from bottom to top in sequence.
6. The method for manufacturing a MOS structure with a shield gate according to claim 3, wherein: and step three, the back etching method is dry etching.
7. The method for manufacturing a MOS structure with a shield gate according to claim 3, wherein: and step four, forming the third oxide layer by using a thermal oxidation method.
8. The method for manufacturing a MOS structure with a shield gate according to claim 3, wherein: and step five, the etching method is wet etching.
9. The method for manufacturing a MOS structure with a shield gate according to claim 3, wherein: and step six, the etching back method is dry etching.
10. The method for manufacturing a MOS structure with a shield gate according to claim 3, wherein: the polishing method in the seventh step is chemical mechanical planarization polishing.
CN202310334838.3A 2023-03-30 2023-03-30 MOS structure with shielding grid and manufacturing method thereof Pending CN116344620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310334838.3A CN116344620A (en) 2023-03-30 2023-03-30 MOS structure with shielding grid and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310334838.3A CN116344620A (en) 2023-03-30 2023-03-30 MOS structure with shielding grid and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN116344620A true CN116344620A (en) 2023-06-27

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