CN116317557A - Dynamic current balancing circuit of parallel gallium nitride power device - Google Patents
Dynamic current balancing circuit of parallel gallium nitride power device Download PDFInfo
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- CN116317557A CN116317557A CN202310314446.0A CN202310314446A CN116317557A CN 116317557 A CN116317557 A CN 116317557A CN 202310314446 A CN202310314446 A CN 202310314446A CN 116317557 A CN116317557 A CN 116317557A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
- H02M1/15—Arrangements for reducing ripples from dc input or output using active elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a dynamic current balancing circuit of a parallel gallium nitride power device, which comprises: the power circuit consists of a direct current bus side circuit and a GaNHEMT parallel device circuit; the driving circuit is composed of a power supply side, a signal input side, a gate driver and an output side. The invention can make the switching speed of the parallel device faster, expand the current capacity, and reduce the unbalance of the drain current, so as to achieve the requirement of balancing the dynamic current of the gallium nitride device.
Description
Technical Field
The invention relates to the technical field of performance test of power semiconductor devices, in particular to a dynamic current balancing circuit of a parallel gallium nitride power device.
Background
With GaN as the excellent physical properties of third generation semiconductor materials that have been rising for the last 20 years, gaN HEMTs have been increasingly penetrated into industrial and telecommunication power application fields including data communication, base stations, UPS, and industrial lidar. Compared with the novel SiC MOSFET device which is one of the wide bandgap semiconductor representative devices, the GaN HEMT has the advantages of lower conduction loss, faster switching speed and the like. The GaN HEMT has higher frequency capability, is mainly applied to 100V to 900V, and has good development prospect in the aspects of DC-DC converters, vehicle-mounted chargers and the like. Similar to the traditional silicon device, the unit die area of the GaN HEMT is limited by the practical production process, and the current processing capability of a single device has an upper limit. However, parasitic inductance of the GaN HEMT gate loop is unavoidable, so that the gate loop can generate strong oscillation under the excitation of the driver driving pulse. Meanwhile, the parallel chip inside the gallium nitride power module bears larger voltage overshoot and unbalanced current in the high-speed switch switching process, so that the performance of the gallium nitride device is reduced.
Disclosure of Invention
The invention aims to solve the defects in the prior art, and provides a dynamic current balancing circuit of a parallel gallium nitride power device, so as to improve strong oscillation generated by a grid loop under the excitation of a driver driving pulse, reduce current imbalance phenomenon between parallel devices, and expand current capacity to meet the requirement of balancing the dynamic current of the gallium nitride device.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
the invention relates to a dynamic current balancing circuit of a parallel gallium nitride power device, which is characterized by comprising the following components: a power circuit, a driving circuit;
the power circuit consists of a direct current bus side circuit and a GaN HEMT parallel device circuit which are connected in parallel;
the direct-current bus-side circuit includes: the direct-current power supply interface, the supporting capacitor and the decoupling capacitor;
the supporting capacitor and the decoupling capacitor are connected in parallel between the positive electrode DC+ and the negative electrode DC-of the direct current power supply interface; the support capacitor is formed by connecting N1 capacitors in parallel, and the decoupling capacitor is formed by connecting N2 capacitors in parallel;
the GaN HEMT parallel device circuit is a half-bridge circuit formed by connecting two symmetrical branches A and B in series;
the branch A and the branch B are formed by connecting 4 gallium nitride high electron mobility transistors in parallel;
the drain electrode of the first gallium nitride high electron mobility transistor HEMT1, the drain electrode of the second gallium nitride high electron mobility transistor HEMT2, the drain electrode of the third gallium nitride high electron mobility transistor HEMT3 and the drain electrode of the fourth gallium nitride high electron mobility transistor HEMT4 in the branch a are connected in parallel and then connected with the positive electrode dc+;
the source of the first gallium nitride high electron mobility transistor HEMT5, the source of the second gallium nitride high electron mobility transistor HEMT6, the source of the third gallium nitride high electron mobility transistor HEMT7 and the source of the fourth gallium nitride high electron mobility transistor HEMT8 in the branch B are connected in parallel and then connected with the negative electrode DC-;
a node a formed by connecting a source of the first gallium nitride high electron mobility transistor HEMT1, a source of the second gallium nitride high electron mobility transistor HEMT2, a source of the third gallium nitride high electron mobility transistor HEMT3 and a source of the fourth gallium nitride high electron mobility transistor HEMT4 in parallel in the branch a is connected with a drain of the first gallium nitride high electron mobility transistor HEMT5, a drain of the second gallium nitride high electron mobility transistor HEMT6, a drain of the third gallium nitride high electron mobility transistor HEMT7 and a drain of the fourth gallium nitride high electron mobility transistor HEMT8 in parallel in the branch B, and a neutral point MID is led out from between the node a and the node B;
the gates of the first gallium nitride high electron mobility transistor HEMT1 to the fourth gallium nitride high electron mobility transistor HEMT4 of the branch A are connected with the high-side positive electrode of the driving circuit, and the sensing source is connected with the negative electrode of the driving circuit;
the gates of the first gallium nitride high electron mobility transistor HEMT5 to the fourth gallium nitride high electron mobility transistor HEMT8 of the branch B are connected with the low-side positive electrode of the driving circuit, and the sensing source is connected with the negative electrode of the driving circuit;
the gates of the first gallium nitride high electron mobility transistor HEMT1 to the fourth gallium nitride high electron mobility transistor HEMT4 of the branch A are respectively connected with a resistor and are sequentially marked as R1 to R4;
the gates of the first gallium nitride high electron mobility transistor HEMT5 to the fourth gallium nitride high electron mobility transistor HEMT8 of the branch B are respectively connected with a resistor and are sequentially marked as R5 to R8;
the sensing source electrode of the first gallium nitride high electron mobility transistor HEMT 5-fourth gallium nitride high electron mobility transistor HEMT8 of the branch B is led out of a compensation branch, resistors R9-R12 are connected to the compensation branch led out of the sensing source electrode, the upper end parts of the resistors R9-R12 are connected with the compensation branch, and the lower end parts of the resistors R9-R12 are connected with the lower side negative electrode of the driving circuit;
the high-side output of the driving circuit provides a driving signal for a branch A in the power circuit, and the low-side output provides a driving signal for a branch B in the power circuit, so that the on and off of 8 gallium nitride high electron mobility transistors in the power circuit are controlled;
the driving circuit includes: a power supply side, a signal input side, a gate driver U1, and an output side;
the power supply side receives an external voltage and supplies power to the gate driver U1;
the signal input side receives an externally input PWM signal and controls the duty ratio of the driving voltage;
the output side is used for outputting the driving voltage;
the VDD pin of the grid driver U1 is connected with an external power supply;
the VDD pin of the gate driver U1 is connected with the capacitor C1 in series and then grounded, and the capacitor C2 is connected to the capacitor C1 in parallel;
the SGND and PGND pins of the gate driver U1 are grounded;
the HIN pin and the LIN pin of the gate driver U1 are respectively connected with an external signal source;
the EN pin of the grid driver U1 is connected with an external power supply after being connected with a resistor R8 in series;
the EN pin of the grid driver U1 is connected with a capacitor C3 in series and then is connected with the external ground;
after the VBST pin of the gate driver U1 is connected with the resistor R7 and the diode D1 in series, the VBST pin of the gate driver U1 is connected with the VDD pin of the gate driver, and the VBST pin of the gate driver U1 is connected with the cathode of the diode D1;
after the VDDH pin of the gate driver U1 is connected with the capacitor C6 in series, the capacitor C is connected with the SW pin of the gate driver U1;
after the SW pin of the gate driver U1 is connected with the capacitor C7 in series, the capacitor C is connected with the VBST pin of the gate driver U1;
the SW pin of the gate driver U1 is connected with the resistor R1 in series and then connected with the node a;
the VDDL pin of the gate driver U1 is connected with the capacitor C5 in series and then is connected with the external ground;
the HOSRC pin and the HOSNK pin of the gate driver U1 are respectively connected with a resistor R2 and a resistor R3 in series and then connected with a node a;
the LOSRC and LOSNK pins of the gate driver U1 are respectively connected with a resistor R5 and a resistor R6 in series and then connected with a node b;
the PGND pin of the gate driver U1 is connected with the resistor R4 in series and then connected with the node b;
the upper output ports G_HS and SS_HS of the output side are connected in parallel with the left side of the first common mode inductor L1, and the right side of the first common mode inductor L1 is connected in parallel with the resistor R1; the lower output ports g_ls and ss_ls of the output side are connected in parallel with the left side of the second common-mode inductance L2, and the right side of the second common-mode inductance L2 is connected in parallel with the resistor R4.
Compared with the prior art, the invention has the beneficial effects that:
1. the GaN HEMT device with excellent parallel performance is adopted. The gallium nitride device has on-resistance with positive temperature coefficient, which is favorable for heat balance and current sharing; the transconductance of the gallium nitride device is reduced along with the temperature rise, and in the parallel connection occasion, the transconductance of the negative temperature coefficient can help the heat balance, and is favorable for the parallel connection: compared to silicon carbide, the threshold voltage of gallium nitride devices is very stable at different temperatures, and current sharing in parallel applications is highly dependent on the stable threshold voltage. And the GaN HEMT device is packaged by a patch, so that the heat dissipation performance is better, and the system loss is reduced.
2. The invention uses the magnetic flux cancellation principle to reduce the inductance of the power converter loop, and when two adjacent conductors are closely placed and the current directions are opposite, the magnetic fluxes generated by the currents in the two directions cancel each other. Meanwhile, the problem of dynamic and static non-current sharing caused by the difference of internal parameters such as threshold voltage, on-resistance, interelectrode capacitance and transconductance of the GaN HEMT is solved through the fully symmetrical circuit design, the influence of current distribution caused by the difference of circuit layout line stray inductance and circuit positions where leads are located and small change of lengths, main grid decoupling resistance of external circuit parameters, grid lead inductance, source lead inductance and drain lead inductance and the like is reduced, and thus the phenomenon of unbalance of current between parallel devices is reduced, and the method has great significance in improving current sharing distribution.
3. In the power circuit, resistors are connected in front of the gate of the gallium nitride high electron mobility transistor HEMT to eliminate gate oscillation, so that the problem of strong oscillation generated by a gate loop under the excitation of a driver driving pulse is solved, the oscillation is quickly attenuated, and the power circuit is easier to replace when the influence experiments of different gate resistors are performed.
4. In the power circuit, the GaN HEMT is packaged with the sensing source without an additional lead-out line from the source of each GaN HEMT, and the resistor is connected in front of the sensing source to form a gate loop.
5. According to the invention, on the basis of circuit design, a GaN HEMT parallel double-pulse experiment, a GaN HEMT voltage reduction circuit experiment and a GaN HEMT parallel short circuit experiment are taken into consideration, so that a multipurpose effect is achieved, and after the GaN HEMT parallel double-pulse experiment is carried out, the current equalizing effect of current can be seen, and an experiment foundation is laid for the GaN HEMT short circuit experiment.
Drawings
FIG. 1 is a power circuit diagram of an embodiment of the present invention;
fig. 2 is a driving circuit diagram in an embodiment of the present invention;
FIG. 3 is a circuit diagram of an embodiment of the present invention;
reference numerals in the drawings: 1, a direct current power interface; 2, supporting a capacitor; 3 decoupling capacitance; 4, common mode inductance; 5 gate resistance.
Detailed Description
The technical scheme of the invention will be clearly and completely described below with reference to the accompanying drawings.
In this embodiment, a dynamic current balancing circuit for a parallel gallium nitride power device is used to solve the problem that current imbalance exists when a plurality of GaN HEMT devices are connected in parallel, and meanwhile, solve the problem that a parallel chip inside a gallium nitride power module bears larger voltage overshoot and unbalanced current in a high-speed switch switching process. The GaN HEMT is selected, so that excellent parallel characteristics of the GaN HEMT can be exerted, and a better current sharing effect is achieved. Specifically, as shown in fig. 3, the control circuit includes: a power circuit and a driving circuit;
as shown in fig. 1, the power circuit consists of a direct-current bus side circuit and a GaN HEMT parallel device circuit;
the direct current bus side circuit includes: a direct current power interface 1, a supporting capacitor 2 and a decoupling capacitor 3;
the supporting capacitor 2 and the decoupling capacitor 3 are connected in parallel between the positive electrode DC+ and the negative electrode DC-of the direct current power supply interface 1; the support capacitor 2 is formed by connecting N1 capacitors in parallel, and the decoupling capacitor 3 is formed by connecting N2 capacitors in parallel;
the GaN HEMT parallel device circuit is a half-bridge circuit formed by connecting two symmetrical branches A and B in series;
as shown in fig. 1, N1 supporting capacitors are connected in parallel, and different supporting capacitor capacity values, voltage-resistant grades and numbers are selected according to actual experiment requirements; n2 decoupling capacitors are mutually connected in parallel, the decoupling capacitors are of low parasitic inductance type, and when a GaN HEMT parallel double-pulse experiment and a GaN HEMT voltage reduction circuit experiment are carried out, a patch type ceramic capacitor can be selected to play a role in voltage stabilization; when the parallel GaN HEMT short circuit test is carried out, the decoupling capacitor can be removed, so that the purpose of one-board multi-test use is achieved, and the requirements of different experiments are met.
The branch A and the branch B are formed by connecting 4 gallium nitride high electron mobility transistors in parallel;
the drain electrode of the first gallium nitride high electron mobility transistor HEMT1, the drain electrode of the second gallium nitride high electron mobility transistor HEMT2, the drain electrode of the third gallium nitride high electron mobility transistor HEMT3 and the drain electrode of the fourth gallium nitride high electron mobility transistor HEMT4 in the branch A are connected in parallel and then connected with the positive electrode DC+;
the source of the first gallium nitride high electron mobility transistor HEMT5, the source of the second gallium nitride high electron mobility transistor HEMT6, the source of the third gallium nitride high electron mobility transistor HEMT7 and the source of the fourth gallium nitride high electron mobility transistor HEMT8 in the branch B are connected in parallel and then connected with the negative electrode DC-connection;
the source electrode of the first gallium nitride high electron mobility transistor HEMT1, the source electrode of the second gallium nitride high electron mobility transistor HEMT2, the source electrode of the third gallium nitride high electron mobility transistor HEMT3 and the source electrode of the fourth gallium nitride high electron mobility transistor HEMT4 in the branch A are connected in parallel, a node A formed by connecting the source electrodes of the first gallium nitride high electron mobility transistor HEMT5, the drain electrode of the second gallium nitride high electron mobility transistor HEMT6, the drain electrode of the third gallium nitride high electron mobility transistor HEMT7 and the drain electrode of the fourth gallium nitride high electron mobility transistor HEMT8 in the branch A in a parallel is connected with a node B formed by connecting the node A and the node B in a parallel, and a neutral point MID is led out from the position between the node A and the node B;
when designing the layout of the circuit PCB circuit board, the layout of the branches a and B must be strictly symmetrical, so that the parasitic parameters in each branch are consistent. The led neutral point interface MID can be used for connecting a large inductance when a parallel GaN HEMT double pulse test experiment and a GaN HEMT voltage reduction circuit experiment are carried out; when the short circuit test experiment is carried out, the parallel GaN HEMT short circuit test experiment can be carried out only by shorting the drains and sources of the GaN HEMTs 1-4 in the branch A. In this case, the decoupling capacitor is also adapted, so that different experiments are performed.
The gates of the first gallium nitride high electron mobility transistor HEMT1 to the fourth gallium nitride high electron mobility transistor HEMT4 of the branch A are connected with the high-side positive electrode of the driving circuit, and the sensing source is connected with the negative electrode of the driving circuit;
the gates of the first gallium nitride high electron mobility transistor HEMT5 to the fourth gallium nitride high electron mobility transistor HEMT8 of the branch B are connected with the low-side positive electrode of the driving circuit, and the sensing source is connected with the negative electrode of the driving circuit;
the gates of the first gallium nitride high electron mobility transistor HEMT1 to the fourth gallium nitride high electron mobility transistor HEMT4 of the branch A are respectively connected with a resistor and are sequentially marked as R1 to R4;
the gates of the first gallium nitride high electron mobility transistor HEMT5 to the fourth gallium nitride high electron mobility transistor HEMT8 of the branch B are respectively connected with a resistor and are sequentially marked as R5 to R8;
the gate resistors R1-R8 can play a role in eliminating gate oscillation in a circuit, parasitic inductance of a gate loop of the high electron mobility transistor is unavoidable, the gate resistors can be connected in series to carry out rapid attenuation, and if the gate resistor is not provided, the gate loop can generate strong oscillation under the excitation of a driver driving pulse; the gate resistors R1-R8 can also play a role in transferring the power loss of the driver in the circuit, the capacitance and the inductance are all passive elements, and if the gate resistor is not provided, most of driving power is consumed on an output pipe inside the driver, so that the temperature of the output pipe rises greatly, and the gate resistors R1-R8 are necessary.
The first gallium nitride high electron mobility transistor HEMT5 to the fourth gallium nitride high electron mobility transistor HEMT8 of the branch B are provided with a sensing source extraction compensation branch, resistors R9 to R12 are connected to the sensing source extraction compensation branch, the upper end parts of the resistors R9 to R12 are connected with the compensation branch, and the lower end parts of the resistors R9 to R12 are connected with the low-side negative electrode of the driving circuit;
the degree of current imbalance decreases with each GaN HEMT sensing source cascode resistor used to form the gate loop, and the magnitude of the current imbalance decrease is greater as the number of parallel GaN HEMTs increases.
FIG. 2 is a diagram of a driving circuit in an embodiment of the present invention, wherein a high-side output of the driving circuit provides a driving signal for a branch A in the power circuit, and a low-side output provides a driving signal for a branch B in the power circuit, so as to control on and off of 8 GaN HEMT in the power circuit, wherein the high-side drive and the low-side drive of the driving circuit are respectively connected with the branch A and the branch B of the power circuit, and the GaN HEMT of the branch A or the branch B in the power circuit is driven; in the implementation, when the layout of 8 GaN HEMTs is carried out, the loop length of each parallel device is close according to strict vertical uniform trend, so that the parasitic parameters of the GaN HEMTs are guaranteed to be the same.
The driving circuit includes: a power supply side, a signal input side, a gate driver U1, and an output side;
the power supply side receives an external voltage and supplies power to the gate driver U1;
the signal input side receives an externally input PWM signal and controls the duty ratio of the driving voltage;
the gate driver U1 is constituted by a gate driving chip, and the model number of the driving chip is NCP51810. The pins on the left side of the grid driving chip are VDDH, HOSRC, HOSNK, SW from top to bottom in sequence; pins from left to right on the upper side of the grid driving chip are VBST and VDD in sequence; the pins on the right side of the grid driving chip U1 are EN, HIN, LIN, SGND, DT from top to bottom in sequence; the pins from left to right at the lower side of the gate driving chip U1 are VDDL, LOSRC, LOSNK, PGND in sequence;
the VDD pin of the gate driver U1 is connected with an external power supply;
the VDD pin of the gate driver U1 is connected with the capacitor C1 in series and then grounded, and the capacitor C2 is connected to the capacitor C1 in parallel;
the PGND and SGND pins of the gate driver U1 are grounded;
in the gate driving chip U1, an external power supply VDD is connected with +12V.
The upper output ports G_HS and SS_HS of the output side are connected in parallel with the left side of the first common mode inductance L1, and the right side of the first common mode inductance L1 is connected in parallel with the resistor R1; the lower output ports G_LS and SS_LS of the output side are connected in parallel with the left side of the second common-mode inductance L2, and the right side of the second common-mode inductance L2 is connected in parallel with a resistor R4; in the embodiment, two gate resistors 5 are adopted, a driving circuit provides driving signals for 8 GaN HEMTs in a power circuit, the output end of each gate resistor 5 is connected with an upper pin on the input side of a common-mode inductor, and the upper pins on the output side of the common-mode inductor are connected with G_HS and G_LS of power circuit branches A and B; GND is connected with the lower pin of the input side of the common-mode inductor, and the lower pin of the output side of the common-mode inductor is connected with S_HS and S_LS of the power circuit branches A and B. The common mode inductor can filter common mode electromagnetic interference on the signal line, inhibit the common mode interference, and simultaneously, the switching speed of the GaN HEMT can be changed by changing the size of the driving resistor.
The embodiment shows that the circuit can have a certain effect on the current sharing of the parallel GaN HEMTs.
Claims (1)
1. A dynamic current balancing circuit for a parallel gallium nitride power device, comprising: a power circuit, a driving circuit;
the power circuit consists of a direct current bus side circuit and a GaN HEMT parallel device circuit which are connected in parallel;
the direct-current bus-side circuit includes: the direct-current power supply interface (1), the supporting capacitor (2) and the decoupling capacitor (3);
the supporting capacitor (2) and the decoupling capacitor (3) are connected in parallel between the positive electrode DC+ and the negative electrode DC-of the direct current power supply interface (1); the support capacitor (2) is formed by connecting N1 capacitors in parallel, and the decoupling capacitor (3) is formed by connecting N2 capacitors in parallel;
the GaN HEMT parallel device circuit is a half-bridge circuit formed by connecting two symmetrical branches A and B in series;
the branch A and the branch B are formed by connecting 4 gallium nitride high electron mobility transistors in parallel;
the drain electrode of the first gallium nitride high electron mobility transistor HEMT1, the drain electrode of the second gallium nitride high electron mobility transistor HEMT2, the drain electrode of the third gallium nitride high electron mobility transistor HEMT3 and the drain electrode of the fourth gallium nitride high electron mobility transistor HEMT4 in the branch a are connected in parallel and then connected with the positive electrode dc+;
the source of the first gallium nitride high electron mobility transistor HEMT5, the source of the second gallium nitride high electron mobility transistor HEMT6, the source of the third gallium nitride high electron mobility transistor HEMT7 and the source of the fourth gallium nitride high electron mobility transistor HEMT8 in the branch B are connected in parallel and then connected with the negative electrode DC-;
a node a formed by connecting a source of the first gallium nitride high electron mobility transistor HEMT1, a source of the second gallium nitride high electron mobility transistor HEMT2, a source of the third gallium nitride high electron mobility transistor HEMT3 and a source of the fourth gallium nitride high electron mobility transistor HEMT4 in parallel in the branch a is connected with a drain of the first gallium nitride high electron mobility transistor HEMT5, a drain of the second gallium nitride high electron mobility transistor HEMT6, a drain of the third gallium nitride high electron mobility transistor HEMT7 and a drain of the fourth gallium nitride high electron mobility transistor HEMT8 in parallel in the branch B, and a neutral point MID is led out from between the node a and the node B;
the gates of the first gallium nitride high electron mobility transistor HEMT1 to the fourth gallium nitride high electron mobility transistor HEMT4 of the branch A are connected with the high-side positive electrode of the driving circuit, and the sensing source is connected with the negative electrode of the driving circuit;
the gates of the first gallium nitride high electron mobility transistor HEMT5 to the fourth gallium nitride high electron mobility transistor HEMT8 of the branch B are connected with the low-side positive electrode of the driving circuit, and the sensing source is connected with the negative electrode of the driving circuit;
the gates of the first gallium nitride high electron mobility transistor HEMT1 to the fourth gallium nitride high electron mobility transistor HEMT4 of the branch A are respectively connected with a resistor and are sequentially marked as R1 to R4;
the gates of the first gallium nitride high electron mobility transistor HEMT5 to the fourth gallium nitride high electron mobility transistor HEMT8 of the branch B are respectively connected with a resistor and are sequentially marked as R5 to R8;
the sensing source electrode of the first gallium nitride high electron mobility transistor HEMT 5-fourth gallium nitride high electron mobility transistor HEMT8 of the branch B is led out of a compensation branch, resistors R9-R12 are connected to the compensation branch led out of the sensing source electrode, the upper end parts of the resistors R9-R12 are connected with the compensation branch, and the lower end parts of the resistors R9-R12 are connected with the lower side negative electrode of the driving circuit;
the high-side output of the driving circuit provides a driving signal for a branch A in the power circuit, and the low-side output provides a driving signal for a branch B in the power circuit, so that the on and off of 8 gallium nitride high electron mobility transistors in the power circuit are controlled;
the driving circuit includes: a power supply side, a signal input side, a gate driver U1, and an output side;
the power supply side receives an external voltage and supplies power to the gate driver U1;
the signal input side receives an externally input PWM signal and controls the duty ratio of the driving voltage;
the output side is used for outputting the driving voltage;
the VDD pin of the grid driver U1 is connected with an external power supply;
the VDD pin of the gate driver U1 is connected with the capacitor C1 in series and then grounded, and the capacitor C2 is connected to the capacitor C1 in parallel;
the SGND and PGND pins of the gate driver U1 are grounded;
the HIN pin and the LIN pin of the gate driver U1 are respectively connected with an external signal source;
the EN pin of the grid driver U1 is connected with an external power supply after being connected with a resistor R8 in series;
the EN pin of the grid driver U1 is connected with a capacitor C3 in series and then is connected with the external ground;
after the VBST pin of the gate driver U1 is connected with the resistor R7 and the diode D1 in series, the VBST pin of the gate driver U1 is connected with the VDD pin of the gate driver, and the VBST pin of the gate driver U1 is connected with the cathode of the diode D1;
after the VDDH pin of the gate driver U1 is connected with the capacitor C6 in series, the capacitor C is connected with the SW pin of the gate driver U1;
after the SW pin of the gate driver U1 is connected with the capacitor C7 in series, the capacitor C is connected with the VBST pin of the gate driver U1;
the SW pin of the gate driver U1 is connected with the resistor R1 in series and then connected with the node a;
the VDDL pin of the gate driver U1 is connected with the capacitor C5 in series and then is connected with the external ground;
the HOSRC pin and the HOSNK pin of the gate driver U1 are respectively connected with a resistor R2 and a resistor R3 in series and then connected with a node a;
the LOSRC and LOSNK pins of the gate driver U1 are respectively connected with a resistor R5 and a resistor R6 in series and then connected with a node b;
the PGND pin of the gate driver U1 is connected with the resistor R4 in series and then connected with the node b;
the upper output ports G_HS and SS_HS of the output side are connected in parallel with the left side of the first common mode inductor L1, and the right side of the first common mode inductor L1 is connected in parallel with the resistor R1; the lower output ports g_ls and ss_ls of the output side are connected in parallel with the left side of the second common-mode inductance L2, and the right side of the second common-mode inductance L2 is connected in parallel with the resistor R4.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310314446.0A CN116317557A (en) | 2023-03-28 | 2023-03-28 | Dynamic current balancing circuit of parallel gallium nitride power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310314446.0A CN116317557A (en) | 2023-03-28 | 2023-03-28 | Dynamic current balancing circuit of parallel gallium nitride power device |
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| Publication Number | Publication Date |
|---|---|
| CN116317557A true CN116317557A (en) | 2023-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310314446.0A Pending CN116317557A (en) | 2023-03-28 | 2023-03-28 | Dynamic current balancing circuit of parallel gallium nitride power device |
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| Country | Link |
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| CN (1) | CN116317557A (en) |
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2023
- 2023-03-28 CN CN202310314446.0A patent/CN116317557A/en active Pending
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