CN116248573B

CN116248573B - Link splicing method, device and storage medium

Info

Publication number: CN116248573B
Application number: CN202211527605.7A
Authority: CN
Inventors: 倪学东; 冯毅; 王翔; 谭永涛; 田欣; 赵玮; 孙满红; 赵红睿
Original assignee: China United Network Communications Group Co Ltd
Current assignee: China United Network Communications Group Co Ltd
Priority date: 2022-12-01
Filing date: 2022-12-01
Publication date: 2024-06-18
Anticipated expiration: 2042-12-01
Also published as: CN116248573A

Abstract

The application provides a link splicing method, a device and a storage medium, relates to the technical field of communication, and is used for solving the problem that a common technology cannot accurately splice a plurality of sub-links in a transmission link. The method comprises the following steps: acquiring a plurality of link information corresponding to a plurality of sub-links one by one; when the link termination information of the other sub-links does not exist the link termination information which is the same as the link start information of the target sub-link, determining the target sub-link as the first sub-link of the target link; and determining address information of other sub-links according to the first sub-link and the logic topology tree, and splicing the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link. The application can improve the accuracy of splicing the plurality of sub-links in the transmission link.

Description

Link splicing method, device and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a link splicing method, a device, and a storage medium.

Background

With the continuous development of networks, the variety and number of network devices in the transmission network are increasing. Accordingly, link data between network devices is also increasing. In order to monitor and maintain link data in a complete transmission link, a plurality of sub-links in the complete transmission link need to be spliced.

Therefore, how to accurately splice multiple sub-links in a transmission link is a problem that needs to be solved at present.

Disclosure of Invention

The application provides a link splicing method, a device and a storage medium, which are used for solving the problem that a plurality of sub links in a transmission link cannot be spliced accurately in the general technology.

In order to achieve the above purpose, the application adopts the following technical scheme:

In a first aspect, a link splicing method is provided, including: acquiring a plurality of link information corresponding to a plurality of sub-links one by one; the link information includes link start information and link end information; when the link termination information of the other sub-links does not exist the link termination information which is the same as the link start information of the target sub-link, determining the target sub-link as the first sub-link of the target link; the other sub-links are sub-links except the target sub-link in the plurality of sub-links; determining address information of other sub-links according to the first sub-link and the logic topology tree, and splicing a plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain a target link; the logical topology tree comprises a plurality of logical nodes; the logical node is used for determining address information of a next sub-link of the sub-link successfully matched with the logical node.

Optionally, the method for determining address information of other sub-links according to the first sub-link and the logic topology tree specifically includes: inputting the link termination information of the nth sub-link into the logic topology tree; n is a positive integer; when the logic topology tree comprises a logic node successfully matched with the nth sub-link, determining whether the target logic node outputs the address information of the (n+1) th sub-link; the target logical node is a logical node successfully matched with the nth sub-link; when the target logic node outputs the address information of the (n+1) th sub-link, repeatedly inputting the link termination information of the (n+1) th sub-link into the logic topology tree until the logic topology tree cannot be matched with the sub-link; when the logic topology tree does not comprise a logic node successfully matched with the nth sub-link or the target logic node cannot output the (n+1) th sub-link, determining the nth sub-link as the last sub-link of the target link; and determining the address information of other sub-links according to the address information of the sub-links output by the logic topology tree.

Optionally, the logical topology tree includes a plurality of logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured by the logic node, and/or the time slot information of the nth sub-link is the same as the time slot information configured by the logic node; the link splicing method further comprises the following steps: when the link termination information of the nth sub-link accords with a first condition corresponding to a first logic node in the mth logic layer, determining the first logic node as a target logic node; m is a positive integer; when the link termination information of the nth sub-link does not meet the first condition corresponding to the first logic node in the mth logic layer, determining whether the (m+1) th logic layer comprises the logic node meeting the first condition or not until each logic layer does not comprise the logic node meeting the first condition, and determining that the logic topology tree does not comprise the logic node successfully matched with the nth sub-link; the (m+1) th logical layer is a sub-logical layer of the first logical node.

Optionally, the first logical node includes: matching operators, selecting operators and second conditions; the matching operator is used for: determining the sub-links corresponding to the link starting information which is the same as the link ending information of the nth sub-link in the link starting information of the rest sub-links; the rest sub-links are sub-links except the nth sub-link in the plurality of sub-links; the selection operator is used for: determining the sub-link with the largest sub-link port number value; the second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sub-link is a sub-link in the spliced target link; the link splicing method further comprises the following steps: executing a matching operator of the first logic node; executing a selection operator of the first logical node when the matching operator matches to at least one first sub-link; determining whether the second sub-link satisfies a second condition when the selection operator selects the second sub-link from the at least one first sub-link; and when the second sub-link meets the second condition, acquiring the address information of the second sub-link, and determining the address information of the second sub-link as the address information of the (n+1) th sub-link.

Optionally, after executing the matching operator of the first logical node, the link splicing method further includes: when the matching operator is not matched with the first sub-link, determining whether a sub-logic layer exists in the target logic node; and when the matching operator is matched to at least one first sub-link, and the selecting operator selects a second sub-link from the at least one first sub-link, and the second sub-link does not meet the second condition, determining whether the target logic node has a sub-logic layer.

Optionally, the link splicing method further includes: when the target logical node has a sub-logical layer, determining whether the sub-logical layer of the target logical node comprises a logical node meeting a first condition; when the target logical node does not have the sub-logical layer, it is determined that the target logical node cannot output the n+1th sub-link.

In a second aspect, a link splicing apparatus is provided, including: an acquisition unit and a processing unit; the acquisition unit is used for acquiring a plurality of link information corresponding to the plurality of sub-links one by one; the link information includes link start information and link end information; a processing unit, configured to determine the target sub-link as a first sub-link of the target link when the link termination information that is the same as the link start information of the target sub-link does not exist in the link termination information of the other sub-links; the other sub-links are sub-links except the target sub-link in the plurality of sub-links; the processing unit is further used for determining address information of other sub-links according to the first sub-link and the logic topology tree, and splicing the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain a target link; the logical topology tree comprises a plurality of logical nodes; the logical node is used for determining address information of a next sub-link of the sub-link successfully matched with the logical node.

Optionally, the processing unit is configured to: inputting the link termination information of the nth sub-link into the logic topology tree; n is a positive integer; when the logic topology tree comprises a logic node successfully matched with the nth sub-link, determining whether the target logic node outputs the address information of the (n+1) th sub-link; the target logical node is a logical node successfully matched with the nth sub-link; when the target logic node outputs the address information of the (n+1) th sub-link, repeatedly inputting the link termination information of the (n+1) th sub-link into the logic topology tree until the logic topology tree cannot be matched with the sub-link; when the logic topology tree does not comprise a logic node successfully matched with the nth sub-link or the target logic node cannot output the (n+1) th sub-link, determining the nth sub-link as the last sub-link of the target link; and determining the address information of other sub-links according to the address information of the sub-links output by the logic topology tree.

Optionally, the logical topology tree includes a plurality of logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured by the logic node, and/or the time slot information of the nth sub-link is the same as the time slot information configured by the logic node; the processing unit is further configured to determine the first logical node as a target logical node when the link termination information of the nth sub-link meets a first condition corresponding to the first logical node in the mth logical layer; m is a positive integer; the processing unit is further configured to determine whether the (m+1) th logical layer includes a logical node satisfying the first condition when the link termination information of the (n) th sub-link does not conform to the first condition corresponding to the first logical node in the (m) th logical layer, until each logical layer does not include a logical node satisfying the first condition, and determine that the logical topology tree does not include a logical node successfully matched with the (n) th sub-link; the (m+1) th logical layer is a sub-logical layer of the first logical node.

Optionally, the first logical node includes: matching operators, selecting operators and second conditions; the matching operator is used for: determining the sub-links corresponding to the link starting information which is the same as the link ending information of the nth sub-link in the link starting information of the rest sub-links; the rest sub-links are sub-links except the nth sub-link in the plurality of sub-links; the selection operator is used for: determining the sub-link with the largest sub-link port number value; the second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether the second sub-link is a sub-link in the spliced target link; the processing unit is also used for executing a matching operator of the first logic node; the processing unit is further used for executing a selection operator of the first logic node when the matching operator is matched to at least one first sub-link; the processing unit is further used for determining whether the second sub-link meets a second condition when the selection operator selects the second sub-link from the at least one first sub-link; and the processing unit is further used for acquiring the address information of the second sub-link and determining the address information of the second sub-link as the address information of the n+1th sub-link when the second sub-link meets the second condition.

Optionally, the processing unit is further configured to determine whether a sub-logical layer exists in the target logical node when the matching operator does not match the first sub-link; the processing unit is further configured to determine whether the target logical node has a sub-logical layer when the matching operator matches to at least one first sub-link, and the selection operator selects a second sub-link from the at least one first sub-link, and the second sub-link does not satisfy the second condition.

Optionally, the processing unit is further configured to determine, when the target logical node has a sub-logical layer, whether the sub-logical layer of the target logical node includes a logical node that meets the first condition; and the processing unit is also used for determining that the target logic node cannot output the (n+1) th sub-link when the target logic node does not have the sub-logic layer.

In a third aspect, a link splicing apparatus is provided, including a memory and a processor; the memory is used for storing computer execution instructions, and the processor is connected with the memory through a bus; when the link splicing device is operated, the processor executes computer-executable instructions stored in the memory to cause the link splicing device to perform the link splicing method according to the first aspect.

The link splicing device may be a network device or may be a part of a device in the network device, for example, a chip system in the network device. The system-on-chip is configured to support the network device to implement the functions involved in the first aspect and any one of its possible implementations, for example, to obtain, determine, and send data and/or information involved in the link splicing method described above. The chip system includes a chip, and may also include other discrete devices or circuit structures.

In a fourth aspect, there is provided a computer readable storage medium comprising computer executable instructions which, when run on a computer, cause the computer to perform the link splicing method of the first aspect.

In a fifth aspect, there is also provided a computer program product comprising computer instructions which, when run on a link splicing device, cause the link splicing device to perform the link splicing method according to the first aspect described above.

It should be noted that the above-mentioned computer instructions may be stored in whole or in part on the first computer readable storage medium. The first computer readable storage medium may be packaged together with the processor of the link splicing device, or may be packaged separately from the processor of the link splicing device, which is not limited by the embodiment of the present application.

The description of the second, third, fourth and fifth aspects of the present application may refer to the detailed description of the first aspect; the advantages of the second aspect, the third aspect, the fourth aspect and the fifth aspect may be referred to as analysis of the advantages of the first aspect, and will not be described here.

In the embodiment of the present application, the names of the above link splicing devices do not limit the devices or functional modules, and in actual implementation, these devices or functional modules may appear under other names. Insofar as the function of each device or function module is similar to that of the present application, it falls within the scope of the claims of the present application and the equivalents thereof.

These and other aspects of the application will be more readily apparent from the following description.

The technical scheme provided by the application has at least the following beneficial effects:

Based on any one of the above aspects, the embodiment of the present application provides a link splicing method, which may determine, after acquiring a plurality of link information corresponding to a plurality of sub-links one to one, a target sub-link as a first sub-link of the target link when there is no link termination information identical to link initiation information of the target sub-link in link termination information of other sub-links. And then, according to the first sub-link and the logic topology tree, determining address information of other sub-links, and splicing a plurality of sub-links based on the address information of other sub-links and the first sub-link to obtain a target link.

As can be seen from the above, since one complete transmission link is composed of a plurality of sub-links, it is possible to first acquire a plurality of link information corresponding to the plurality of sub-links one by one, and determine the first sub-link of the target link according to the link information. And then, according to the first sub-link and the logic topology tree, determining the address information of other sub-links, and splicing the first sub-link and the other sub-links through the address information to obtain the target link. Therefore, the link splicing method provided by the embodiment of the application can accurately and effectively splice a plurality of sub links in the target link.

Drawings

Fig. 1 is a schematic structural diagram of a link splicing system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a link splicing system according to an embodiment of the present application;

fig. 3 is a schematic hardware structure of a link splicing device according to an embodiment of the present application;

Fig. 4 is a schematic diagram of another hardware structure of the link splicing device according to the embodiment of the present application;

fig. 5 is a schematic flow chart of a link splicing method according to an embodiment of the present application;

fig. 6 is a flow chart of another link splicing method according to an embodiment of the present application;

fig. 7 is a flow chart of another link splicing method according to an embodiment of the present application;

fig. 8 is a flow chart of another link splicing method according to an embodiment of the present application;

fig. 9 is a flow chart of another link splicing method according to an embodiment of the present application;

fig. 10 is a flow chart of another link splicing method according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a link splicing device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In order to clearly describe the technical solution of the embodiment of the present application, in the embodiment of the present application, the words "first", "second", etc. are used to distinguish identical items or similar items having substantially the same function and effect, and those skilled in the art will understand that the words "first", "second", etc. are not limited in number and execution order.

Before the link splicing method provided by the application is described in detail, the application scene and the implementation environment related to the application are simply described.

As described in the background, in order to monitor and maintain link data in a complete transmission link, a plurality of sub-links in the complete transmission link need to be spliced.

In view of the above problems, an embodiment of the present application provides a link splicing method, where after acquiring multiple link information corresponding to multiple sub-links one to one, a first electronic device determines a target sub-link as a first sub-link of the target link when link termination information of other sub-links does not have link termination information identical to link start information of the target sub-link. And then, the first electronic equipment determines address information of other sub-links according to the first sub-link and the logic topology tree, and splices the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link.

As can be seen from the above, since a complete transmission link is composed of a plurality of sub-links, the first electronic device may first obtain a plurality of link information corresponding to the plurality of sub-links one by one, and determine the first sub-link of the target link according to the link information. And then, the first electronic equipment determines the address information of other sub-links according to the first sub-link and the logic topology tree, and then splices the first sub-link and the other sub-links through the address information to obtain the target link. Therefore, the link splicing method provided by the embodiment of the application can accurately and effectively splice a plurality of sub links in the target link.

The link splicing method is suitable for a link splicing system. Fig. 1 shows one configuration of the link splicing system. As shown in fig. 1, the link splicing system includes: a first electronic device 101, a second electronic device 102.

Wherein the first electronic device 101 is communicatively connected to the second electronic device 102.

In practical applications, the first electronic device 101 may be connected to a plurality of second electronic devices 102, and the second electronic device 102 may also be connected to a plurality of first electronic devices 101. For ease of understanding, the present application is described with reference to a first electronic device 101 being connected to a second electronic device 102.

In the embodiment of the present application, the second electronic device 102 is configured to provide the data for link splicing to the first electronic device 101, so that the first electronic device 101 performs link splicing according to the data sent by the second electronic device 102.

Optionally, the data for link splicing may include: link start information and link end information of a plurality of sub-links.

Alternatively, the entity devices of the first electronic device 101 and the second electronic device 102 may be servers, or may be terminals, or may be a server, or may be a terminal, which is not limited in this embodiment of the present application.

Alternatively, the terminal may be a device that provides voice and/or data connectivity to the user, a handheld device with wireless connectivity, or other processing device connected to a wireless modem. The wireless terminal may communicate with one or more core networks via a radio access network (radio access network, RAN). The wireless terminals may be mobile terminals such as mobile telephones (or "cellular" telephones) and computers with mobile terminals, as well as portable, pocket, hand-held, computer-built-in or car-mounted mobile devices which exchange voice and/or data with radio access networks, e.g. cell phones, tablet computers, notebook computers, netbooks, personal Digital Assistants (PDAs).

Alternatively, the server may be one server in a server cluster (including multiple servers), or may be a chip in the server, or may be a system on a chip in the server, or may be implemented by a Virtual Machine (VM) deployed on a physical machine, which is not limited in the embodiment of the present application.

Alternatively, when the first electronic device 101 and the second electronic device 102 are the same type of entity device (for example, the first electronic device 101 and the second electronic device 102 are both servers, or are both terminals), the first electronic device 101 and the second electronic device 102 may be two devices that are set independently from each other, or may be integrated in the same device.

It is easy to understand that when the first electronic device 101 and the second electronic device 102 are integrated in the same device, the communication manner between the first electronic device 101 and the second electronic device 102 is communication between the internal modules of the device. In this case, the communication flow therebetween is the same as "in the case where the first electronic device 101 and the second electronic device 102 are independent of each other".

For ease of understanding, the present application is described by taking the example that the first electronic device 101 and the second electronic device 102 are independent of each other.

In one implementation, in conjunction with fig. 1, as shown in fig. 2, the first electronic device 101 may include an origin scan module 201, a concatenation engine module 202, a logic topology tree 203, and a data support module 204.

The origin scanning module 201 may include an origin scanner and a database. The origin scanner may access the database by cross-connect (CrossConnection, CC) origin scanners, topology connect (TopologicalConnection, TL) origin scanners, CC & TL origin scanners of three types to scan origins from the database.

The CC start scanner may be used to query the sub-link with the connection type being cross-connected, the TL start scanner may be used to query the sub-link with the connection type being topology connected, and the CC & TL start scanner may be used to query the sub-link with the connection type being cross-connected or the sub-link with the connection type being topology connected.

Alternatively, the origin scan module 201 may select an origin scanner of a corresponding type to query a first sub-link (e.g., the scan origin shown in fig. 2) of the target link according to the connection type of the first sub-link in the target link, and send the first sub-link to the concatenation engine module 202.

Alternatively, the first sub-link of the target link may also be referred to as the path start point. The sub-link connection type can be cross connection or topological connection. The sub-links may also be referred to as pass-through nodes. A sub-link may also be referred to as a cross-connect node when the connection type of the sub-link is cross-connect. Sub-links may also be referred to as topologically connected nodes when the connection type of the sub-links is topologically connected.

The concatenation engine module 202 may include start point data, concatenation engine, complete path after concatenation is completed.

Specifically, after receiving the first sub-link (e.g., the start data shown in fig. 2) of the target link, the concatenation engine module 202 may input the first sub-link in a concatenation engine in batches (e.g., the batch mount shown in fig. 2), and then the concatenation engine inputs the first sub-link into the logical topology tree 203 (e.g., the last node currently concatenated by a path shown in fig. 2) to query other sub-links of the target link except for the first sub-link. The concatenation engine then concatenates the other sub-links queried by the logical topology tree 203 with the first sub-link of the target link to obtain the target link (e.g., the complete path after concatenation shown in fig. 2).

Alternatively, concatenation may also be referred to as stitching.

The concatenated logic topology tree 203 may include a plurality of concatenated logic layers, each of which may include a plurality of logic nodes, each of which may include a pre-condition, a match operator, a select operator, a node process, a Context, a post-condition, and a sub-logic layer.

Alternatively, the precondition may also be referred to as a first condition. The post condition may also be referred to as a second condition. Node processing may also be referred to as node processors. Context may also be referred to as a Context update policy. The logical topology tree may also be referred to as a concatenated logical topology tree.

The logical topology tree 203 may be used to query the database of the first electronic device 101 or the first electronic device 102 for whether the input sub-link has a next sub-link based on the input sub-link.

Specifically, the logical topology tree 203 may input the first sub-link into the preconditions of each logical node in the first logical layer, which in turn determines whether the first sub-link meets the preconditions of the logical node. When a first sub-link encounters a preconditioned logical node for the first time, the logical node is determined to be the target logical node.

Logical topology tree 203 may then, upon determining that the first sub-link meets the preconditions for the target logical node, execute a matching operator for the target logical node to match the plurality of sub-links in the data environment provided by data support module 204.

The logical topology tree 203 may then execute the selection operator to select one of the plurality of sub-links and determine it as the target sub-link.

The logical topology tree 203 may then perform node processing again to process unselected sub-links, such as: the unselected sub-links are marked as standby.

Then, the logical topology tree 203 may execute Context again to record the main path, the standby path, the frequency, the channel, and the number of the spliced sub-links in the target link.

Then, the logical topology tree 203 may execute the post-condition again to determine whether the number of spliced sub-links in the target link is greater than a threshold or whether the target link is a spliced sub-link in the target sub-link according to the content of the Context record.

When the number of spliced sub-links in the target link is less than or equal to the threshold and the target sub-link is not a spliced sub-link in the target link, the logical topology tree 203 sends the target sub-link to the concatenation engine module 202.

When the number of spliced sub-links in the target link is greater than a threshold value or the target sub-link is a spliced sub-link in the target link, the logic topology tree 203 executes the sub-logic layer to determine whether the target logic node has the sub-logic layer, if so, the logic topology tree 203 inputs the target sub-link into the sub-logic layer, and repeats the above operation until the logic topology tree 203 determines that the target sub-link is not found.

Data support module 204 may include a data environment, a Redis cache based data environment, a ClickHouse based data environment. Redis cache-based data environments, clickHouse-based data environments are two implementations of data environments.

The data support module 204 may be used to determine the manner in which the logical topology tree 203 accesses the database.

Alternatively, a Redis cache-based data environment may be used when the logical topology tree 203 performs a batch concatenation in units of the element management system (ELEMENT MANAGEMENT SYSTEM, EMS), and a ClickHouse-based data environment may be used when the logical topology tree 203 concatenates a target link.

The basic hardware structures of the first electronic device 101 and the second electronic device 102 in the link splicing system are similar, and each includes elements included in the link splicing apparatus shown in fig. 3 or fig. 4. The hardware configuration of the first electronic device 101 and the second electronic device 102 will be described below by taking the link splicing apparatus shown in fig. 3 and 4 as an example.

Fig. 3 is a schematic hardware structure of a link splicing device according to an embodiment of the present application. The link splicing device comprises a processor 31, a memory 32, a communication interface 33 and a bus 34. The processor 31, the memory 32 and the communication interface 33 may be connected by a bus 34.

The processor 31 is a control center of the link splicing apparatus, and may be one processor or a collective name of a plurality of processing elements. For example, the processor 31 may be a general-purpose central processing unit (central processing unit, CPU), or may be another general-purpose processor. Wherein the general purpose processor may be a microprocessor or any conventional processor or the like.

As one example, processor 31 may include one or more CPUs, such as CPU 0 and CPU 1 shown in fig. 3.

The memory 32 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

In a possible implementation, the memory 32 may exist separately from the processor 31, and the memory 32 may be connected to the processor 31 by a bus 34 for storing instructions or program code. The processor 31, when calling and executing instructions or program code stored in the memory 32, is capable of implementing the link splicing method provided in the following embodiments of the present application.

In the embodiment of the present application, the software programs stored in the memory 32 are different for the first electronic device 101 and the second electronic device 102, so that the functions implemented by the first electronic device 101 and the second electronic device 102 are different. The functions performed with respect to the respective devices will be described in connection with the following flowcharts.

In another possible implementation, the memory 32 may also be integrated with the processor 31.

The communication interface 33 is used for connecting the link splicing device with other devices through a communication network, wherein the communication network can be an ethernet, a wireless access network, a wireless local area network (wireless local area networks, WLAN) and the like. The communication interface 33 may include a receiving unit for receiving data, and a transmitting unit for transmitting data.

Bus 34 may be an industry standard architecture (industry standard architecture, ISA) bus, an external device interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 3, but not only one bus or one type of bus.

Fig. 4 shows another hardware configuration of the link splicing apparatus in the embodiment of the present application. As shown in fig. 4, the link splicing apparatus may include a processor 41 and a communication interface 42. The processor 41 is coupled to a communication interface 42.

The function of the processor 41 may be as described above with reference to the processor 31. The processor 41 also has a memory function and can function as the memory 32.

The communication interface 42 is used to provide data to the processor 41. The communication interface 42 may be an internal interface of the link splicing device or an external interface (corresponding to the communication interface 33) of the link splicing device.

It should be noted that the structure shown in fig. 3 (or fig. 4) does not constitute a limitation of the link splicing device, and the link splicing device may include more or less components than those shown in fig. 3 (or fig. 4), or may combine some components, or may be arranged in different components.

The link splicing method provided by the embodiment of the application is described in detail below with reference to the accompanying drawings.

As shown in fig. 5, the link splicing method provided by the embodiment of the present application is applied to the first electronic device 101 in the link splicing system shown in fig. 1, where the link splicing method includes: S501-S503.

S501, the first electronic device acquires a plurality of link information corresponding to a plurality of sub-links one by one.

Wherein the link information includes link start information and link end information.

In one implementation, the first electronic device first obtains the original link data from the plurality of network element management systems (ELEMENT MANAGEMENT SYSTEM, EMS), then extracts link information in the original link data to obtain link information corresponding to all sub-links in each EMS, and stores the link information in a database of the first electronic device. And then, the first electronic equipment can directly acquire a plurality of link information corresponding to the plurality of sub-links one by one from the database when performing the splicing task.

In still another implementation manner, in conjunction with fig. 1, the second electronic device first obtains the original link data from each network element management system (ELEMENT MANAGEMENT SYSTEM, EMS), extracts the link information in the original link data, so as to obtain the link information corresponding to all the sub-links in each EMS, and stores the link information in the database of the second electronic device. And then, the first electronic device can acquire a plurality of link information corresponding to the plurality of sub-links one by one from a database of the second electronic device when performing the splicing task.

S502, when the link termination information which is the same as the link start information of the target sub-link does not exist in the link termination information of other sub-links, the first electronic device determines the target sub-link as the first sub-link of the target link.

The other sub-links are sub-links except the target sub-link in the plurality of sub-links.

Specifically, after acquiring the link information corresponding to the links one to one, the first electronic device needs to determine the first sub-link of the target link.

The specific way for the first electronic device to determine the first sub-link of the target link is: the first electronic device compares whether link start information of each of the plurality of sub-links is identical to link end information of other sub-links. When the link start information of a certain sub-link (i.e., the target sub-link in the embodiment of the present application) is different from the link end information of other sub-links, the first electronic device may determine the sub-link as the first sub-link of the target link.

For example, the link start information of the sub-link 1 in the preset target link is a, the link stop information is B, the link start information of the sub-link 2 is B, the link stop information is C, the link start information of the sub-link 3 is C, and the link stop information is D. The first electronic device determines that the link start information of the sub-link 1 is different from the link end information of the sub-link 2 and the link end information of the sub-link 3, the link start information of the sub-link 2 is the same as the link end information of the sub-link 1, and the link start information of the sub-link 3 is the same as the link end information of the sub-link 2. Thus, the first electronic device finds the target sub-link as sub-link 1 and determines sub-link 1 as the first sub-link of target link 1.

S503, the first electronic device determines address information of other sub-links according to the first sub-link and the logic topology tree, and splices the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link.

Wherein the logical topology tree comprises a plurality of logical nodes. The logical node is used for determining address information of a next sub-link of the sub-link successfully matched with the logical node.

Specifically, after determining the first sub-link of the target link, the first electronic device needs to determine address information of other sub-links to obtain the target link.

First, the first electronic device inputs a first sub-link into the logical topology tree, and determines whether the logical topology tree outputs a second sub-link.

When the logic topology tree outputs the second sub-link, the first electronic device obtains address information of the first sub-link and the second sub-link by using an addressing function, then adds the address information of the second sub-link to link termination information of the first sub-link, adds the address information of the first sub-link to link start information of the second sub-link, then the first electronic device inputs the second sub-link into the logic topology tree, and repeats the above operation until the logic topology tree cannot output the n+1th sub-link after inputting the n-th sub-link into the logic topology tree. n is a positive integer.

When the logical topology tree cannot output the n+1th sub-link, the first electronic device determines the n-th sub-link as the last sub-link. n is a positive integer.

After determining the last sub-link according to the operation, the first electronic device completes the splicing from the first sub-link to the last sub-link and obtains the target link.

For example, the first sub-link of the preset target link 1 is sub-link 1. The first electronic device inputs sub-link 1 into the logical topology tree to obtain sub-link 2. Then, the first electronic device obtains address information a of the sub-link 1 and address information B of the sub-link 2 by using an addressing function, then adds the address information B of the sub-link 2 to link termination information of the sub-link 1, and adds the address information a of the sub-link 1 to link start information of the sub-link 2. The first electronic device then inputs sub-link 2 into the logical topology tree. When the logical topology tree cannot output the third sub-link, the first electronic device obtains a target link, which is a link from sub-link 1 to sub-link 2.

In one embodiment, as shown in fig. 6 in conjunction with fig. 5, in S503, the method for determining, by the first electronic device, address information of other sub-links according to the first sub-link and the logical topology tree specifically includes: S601-S605.

S601, the first electronic device inputs the link termination information of the nth sub-link into the logic topology tree.

Wherein n is a positive integer.

S602, when a logical node successfully matched with the nth sub-link is included in the logical topology tree, the first electronic equipment determines whether the target logical node outputs address information of the (n+1) th sub-link.

The target logical node is a logical node successfully matched with the nth sub-link.

Specifically, after the first electronic device inputs the link termination information of the nth sub-link into the logic topology tree, the link termination information of the nth sub-link is matched with logic nodes in the logic topology tree one by one until a first successfully matched logic node appears, the matching is stopped, and the first successfully matched logic node is determined as a target logic node. The first electronic device then determines whether the target logical node outputs address information for the n+1th sub-link.

S603, when the target logic node outputs the address information of the (n+1) th sub-link, the first electronic device repeatedly inputs the link termination information of the (n+1) th sub-link into the logic topology tree until the logic topology tree cannot be matched with the sub-link.

Specifically, when the target logical node outputs the address information of the n+1th sub-link, the first electronic device obtains the address information of the n-th sub-link. Next, the first electronic device adds the address information of the n+1th sub-link to the link termination information of the n-th sub-link, and adds the address information of the n-th sub-link to the link start information of the n+1th sub-link.

Then, the first electronic device inputs the link termination information of the n+1th sub-link into the logical topology tree, and repeatedly performs the operation of S602 described above until the logical topology tree cannot be matched to the sub-link.

S604, when the logic topology tree does not include a logic node successfully matched with the nth sub-link or the target logic node cannot output the (n+1) th sub-link, the first electronic device determines the nth sub-link as the last sub-link of the target link.

Specifically, after the first electronic device inputs the link termination information of the nth sub-link into the logic topology tree, the link termination information of the nth sub-link is matched with logic nodes in the logic topology tree one by one, and a logic node successfully matched with the link termination information of the nth sub-link is not found, so that the first electronic device determines the nth sub-link as the last sub-link of the target link.

Or the first electronic equipment finds a logical node which is successfully matched with the link termination information of the nth sub-link but the logical node which is successfully matched does not output the address information of the (n+1) th sub-link, and the first electronic equipment determines the nth sub-link as the last sub-link of the target link.

S605, the first electronic equipment determines address information of other sub-links according to the address information of the sub-links output by the logic topology tree.

Specifically, according to S603, after the address information of the last sub-link is output by the logical topology tree, the first electronic device has sequentially obtained the address information of the first sub-link and the address information of the second sub-link, until the address information of the last sub-link, so that the first electronic device may determine the address information of the other sub-links.

In one embodiment, the logical topology tree includes a plurality of logical layers. Each logical node includes a first condition. The first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured by the logic node, and/or the time slot information of the nth sub-link is the same as the time slot information configured by the logic node. In this case, the electronic device may determine whether each logical node has a sub-logical layer according to the logical topology tree. Therefore, in connection with fig. 6, as shown in fig. 7, in S601, after the link termination information of the nth sub-link is input into the logical topology tree, the link splicing method further includes: S701-S702.

And S701, when the link termination information of the nth sub-link meets a first condition corresponding to a first logic node in the mth logic layer, the first electronic equipment determines the first logic node as the target logic node.

Wherein m is a positive integer.

Specifically, after the first electronic device inputs the link termination information of the nth sub-link into the logic topology tree, the first electronic device first determines whether the link termination information of the nth sub-link satisfies the first condition of each logic node in the mth logic layer in the logic topology tree because the first condition of each logic node is different. And when the link termination information of the nth sub-link meets a first condition corresponding to the first logic node, the first electronic equipment determines the first logic node as the target logic node.

Alternatively, the link termination information may include time slot information.

For example, the link termination information of the 2 nd sub-link is preset to be input into a logic topology tree, wherein the logic topology tree is provided with a logic layer 1, a logic layer 2 and a logic layer 3, the logic layer 1 is provided with a logic node A and a logic node B, the logic layer 2 is provided with a logic node C and a logic node D, and the logic layer 3 is provided with a logic node E and a logic node F. The first electronic device first determines whether the link termination information of the 2 nd sub-link satisfies a first condition of the logical node a and the logical node B in the logical layer 1. And after determining that the link termination information of the 2 nd sub-link meets the first condition of the logic node B, the first electronic device determines the logic node B in the logic layer 1 as a target logic node.

S702, when the link termination information of the nth sub-link does not meet a first condition corresponding to a first logic node in the mth logic layer, the first electronic device determines whether the (m+1) th logic layer comprises the logic node meeting the first condition or not until each logic layer does not comprise the logic node meeting the first condition, and determines that the logic topology tree does not comprise the logic node successfully matched with the nth sub-link.

The (m+1) th logic layer is a sub-logic layer of the first logic node.

Specifically, when the first electronic device does not find the first logical node of the link termination information of the nth sub-link in the mth logical layer, which satisfies the first condition, the first electronic device continues to find whether the first logical node satisfying the first condition exists in the (m+1) th logical layer.

When there is a first logical node satisfying the first condition in the m+1th logical layer, the first logical node is determined as the target logical node.

When the first logic node meeting the first condition does not exist in the (m+1) th logic layer, the first electronic device continues to search whether the first logic node meeting the first condition exists in the (m+2) th logic layer or not until the logic node meeting the first condition is not included in each logic layer, and the first electronic device determines that the logic node meeting the first condition is not included in the logic topology tree.

For example, the link termination information of the 2 nd sub-link is preset to be input into a logic topology tree, wherein the logic topology tree is provided with a logic layer 1, a logic layer 2 and a logic layer 3, the logic layer 1 is provided with a logic node A and a logic node B, the logic layer 2 is provided with a logic node C and a logic node D, and the logic layer 3 is provided with a logic node E and a logic node F. The first electronic device first determines whether the link termination information of the 2 nd sub-link satisfies a first condition of the logical node a and the logical node B in the logical layer 1. When the link termination information of the 2 nd sub-link does not meet the first conditions of the logic node A and the logic node B, the first electronic equipment determines whether the link termination information of the 2 nd sub-link meets the first conditions of the logic node C and the logic node D in the logic layer 2. When the link termination information of the 2 nd sub-link does not meet the first conditions of the logic node C and the logic node D, the first electronic device determines whether the link termination information of the 2 nd sub-link meets the first conditions of the logic node E and the logic node F in the logic layer 3. When the link termination information of the 2 nd sub-link does not meet the first condition of the logic node E and the logic node F, the first electronic device determines that the logic node meeting the first condition is not included in the logic topology tree.

In one embodiment, a first logical node comprises: matching operators, selecting operators and second conditions. The matching operator is used for: and determining the sub-links corresponding to the link starting information which is the same as the link ending information of the nth sub-link in the link starting information of the rest sub-links. The remaining sub-links are sub-links other than the nth sub-link among the plurality of sub-links. The selection operator is used for: and determining the sub-link with the largest sub-link port number value. In this case, the electronic device may determine address information of the n+1th sub-link according to the logical node. The second condition includes: it is determined whether the number of spliced target links is greater than a threshold or whether the second sub-link is a sub-link in the spliced target link. Therefore, in connection with fig. 7, as shown in fig. 8, after determining the first logical node as the target logical node in S701, the link splicing method further includes: S801-S804.

S801, the first electronic device executes a matching operator of the first logic node.

Specifically, the first electronic device compares whether the link termination information of the nth sub-link is the same as the link start information of the rest of sub-links, and finds out the first sub-link which is the same as the link termination information of the nth sub-link.

For example, the link termination information of the 2 nd sub-link is preset to be a, the link start information of the sub-link 1 is preset to be B, the link start information of the sub-link 2 is preset to be a, the link start information of the sub-link 3 is preset to be C, and the link start information of the sub-link 4 is preset to be D. The first electronic device compares the link termination information of the 2 nd sub-link with the link start information of the sub-link 1, the link start information of the sub-link 2, the link start information of the sub-link 3, and the link start information of the sub-link 4, and further determines that the first sub-link identical to the link termination information of the 2 nd sub-link is the sub-link 2 or the sub-link 4.

S802, when the matching operator is matched to at least one first sub-link, the first electronic device executes a selection operator of the first logic node.

Specifically, after the matching operator matches to at least one first sub-link, the first electronic device determines the size of the port number of the at least one first sub-link, and determines the sub-link with the largest port number as the second sub-link.

Optionally, the termination information of the link may include a port number.

Alternatively, the selection operator may be plural. Each selection operator may correspond to a precondition. The precondition may determine whether to use its corresponding selection operator based on the number of first sub-links.

For example, the port number of the first sub-link 1 is preset to be 3, and the port number of the first sub-link 2 is preset to be 5. The first electronic device compares the sizes of the port numbers of the first sub-link 1 and the first sub-link 2 and determines the first sub-link 2 as the second sub-link.

S803, when the selection operator selects the second sub-link from the at least one first sub-link, the first electronic device determines whether the second sub-link satisfies a second condition.

Specifically, after the selection operator selects the second sub-link from the at least one first sub-link, the first electronic device determines whether the number of the spliced target links is greater than a threshold value and determines whether the second sub-link is a sub-link in the spliced target link. And then the first electronic device determines whether the second sub-link meets the second condition according to the judgment.

Optionally, the threshold may be set according to a user's requirement, and the specific value of the threshold is not limited in the embodiment of the present application.

S804, when the second sub-link meets the second condition, the first electronic device acquires the address information of the second sub-link, and determines the address information of the second sub-link as the address information of the n+1th sub-link.

Specifically, when the first electronic device determines that the number of the spliced target links is smaller than the threshold and the second sub-link is not a sub-link in the spliced target links, the first electronic device indicates that the second sub-link is the next sub-link of the nth sub-link, and therefore the first electronic device obtains the address information of the second sub-link and determines the address information of the second sub-link as the address information of the n+1th sub-link.

For example, the second sub-link is preset to be sub-link 1, the number of the spliced target links is 4, the threshold is 10, and the spliced target links include sub-link 2, sub-link 3, sub-link 4 and sub-link 5. The first electronic device determines that the number of spliced target links is less than a threshold value and that the second sub-link is not a sub-link in the spliced target links, and determines address information of the second sub-link as address information of an n+1th sub-link.

In one embodiment, in conjunction with fig. 8, as shown in fig. 9, in S801, after performing the matching operator of the first logical node, the link splicing method further includes: S901-S902.

And S901, when the matching operator is not matched with the first sub-link, the first electronic device determines whether a sub-logic layer exists in the target logic node.

Specifically, since the matching operator does not match the first sub-link, the first electronic device determines that the target logical node does not find the next sub-link of the nth sub-link. The first electronic device then determines whether the target logical node has a sub-logical layer.

S902, when a matching operator is matched to at least one first sub-link, and a selecting operator selects a second sub-link from the at least one first sub-link, and the second sub-link does not meet a second condition, the first electronic device determines whether a sub-logic layer exists in the target logic node.

In particular, although the matching operator matches to at least one first sub-link and the selection operator is able to select a second sub-link from the at least one first sub-link, the first electronic device determines that the target logical node does not find a next sub-link of the nth sub-link because the second sub-link does not satisfy the second condition. The first electronic device then determines whether the target logical node has a sub-logical layer.

In one embodiment, in conjunction with fig. 9, as shown in fig. 10, the link splicing method further includes: S1001-S1002.

S1001, when the target logical node has a sub-logical layer, the first electronic device determines whether the sub-logical layer of the target logical node includes a logical node meeting a first condition.

Specifically, when the target logical node has a sub-logical layer, the first electronic device determines whether the sub-logical layer of the target logical node includes a logical node satisfying the first condition, because the first electronic device does not find a next sub-link of the nth sub-link at the target logical node, and in order to find a next sub-link of the nth sub-link according to the sub-logical layer.

The specific description of the first electronic device determining whether the sub-logical layer of the target logical node includes a logical node satisfying the first condition may refer to the specific description of S701-S702, which is not described herein.

S1002, when the target logical node does not have a sub-logical layer, the first electronic device determines that the target logical node cannot output the n+1th sub-link.

Specifically, when the target logical node does not have a sub-logical layer, the first electronic device determines that the target logical node cannot output the n+1th sub-link because the first electronic device does not find the next sub-link of the n-th sub-link at the target logical node and cannot find the next sub-link of the n-th sub-link according to the sub-logical layer.

The foregoing description of the solution provided by the embodiments of the present application has been mainly presented in terms of a method. To achieve the above functions, it includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the application can divide the functional modules of the link splicing device according to the method example, for example, each functional module can be divided corresponding to each function, and two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. Optionally, the division of the modules in the embodiment of the present application is schematic, which is merely a logic function division, and other division manners may be implemented in practice.

Fig. 11 is a schematic structural diagram of a link splicing device according to an embodiment of the present application. The link splicing apparatus may be used to perform the method of link splicing shown in fig. 5-10. The link splicing apparatus shown in fig. 11 includes: an acquisition unit 1101 and a processing unit 1202.

An obtaining unit 1101, configured to obtain a plurality of link information corresponding to a plurality of sub-links one by one; the link information includes link start information and link end information. For example, in connection with fig. 5, the acquisition unit 1101 is configured to execute S501.

A processing unit 1102, configured to determine the target sub-link as a first sub-link of the target link when the link termination information that is the same as the link start information of the target sub-link does not exist in the link termination information of the other sub-links; the other sub-links are sub-links other than the target sub-link among the plurality of sub-links. For example, in connection with fig. 5, the processing unit 1102 is configured to execute S502.

The processing unit 1102 is further configured to determine address information of other sub-links according to the first sub-link and the logical topology tree, and splice the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain a target link; the logical topology tree comprises a plurality of logical nodes; the logical node is used for determining address information of a next sub-link of the sub-link successfully matched with the logical node. For example, in connection with fig. 5, the processing unit 1102 is further configured to execute S503.

Optionally, the processing unit 1102 is configured to:

Inputting the link termination information of the nth sub-link into the logic topology tree; n is a positive integer. For example, in connection with fig. 6, the processing unit 1102 is further configured to execute S601.

When the logic topology tree comprises a logic node successfully matched with the nth sub-link, determining whether the target logic node outputs the address information of the (n+1) th sub-link; the target logical node is a logical node successfully matched with the nth sub-link. For example, in connection with fig. 6, the processing unit 1102 is further configured to execute S602.

When the target logical node outputs the address information of the (n+1) th sub-link, the link termination information of the (n+1) th sub-link is repeatedly input into the logical topology tree until the logical topology tree cannot be matched with the sub-link. For example, in connection with fig. 6, the processing unit 1102 is further configured to execute S603.

And when the logic topology tree does not comprise the logic node successfully matched with the nth sub-link or the target logic node cannot output the (n+1) th sub-link, determining the nth sub-link as the last sub-link of the target link. For example, in connection with fig. 6, the processing unit 1102 is further configured to execute S604.

And determining the address information of other sub-links according to the address information of the sub-links output by the logic topology tree. For example, in connection with fig. 6, the processing unit 1102 is further configured to execute S605.

Optionally, the logical topology tree includes a plurality of logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured by the logic node, and/or the time slot information of the nth sub-link is the same as the time slot information configured by the logic node.

The processing unit 1102 is further configured to determine the first logical node as a target logical node when the link termination information of the nth sub-link meets a first condition corresponding to the first logical node in the mth logical layer; m is a positive integer. For example, in connection with fig. 7, the processing unit 1102 is further configured to execute S701.

The processing unit 1102 is further configured to determine whether the (m+1) th logical layer includes a logical node satisfying the first condition when the link termination information of the (n) th sub-link does not conform to the first condition corresponding to the first logical node in the (m) th logical layer, until each logical layer does not include a logical node satisfying the first condition, and determine that the logical topology tree does not include a logical node successfully matched with the (n) th sub-link; the (m+1) th logical layer is a sub-logical layer of the first logical node. For example, in connection with fig. 7, the processing unit 1102 is further configured to execute S702.

Optionally, the first logical node includes: matching operators, selecting operators and second conditions; the matching operator is used for: determining the sub-links corresponding to the link starting information which is the same as the link ending information of the nth sub-link in the link starting information of the rest sub-links; the rest sub-links are sub-links except the nth sub-link in the plurality of sub-links; the selection operator is used for: determining the sub-link with the largest sub-link port number value; the second condition includes: it is determined whether the number of spliced target links is greater than a threshold or whether the second sub-link is a sub-link in the spliced target link.

The processing unit 1102 is further configured to execute the matching operator of the first logical node. For example, in connection with fig. 8, the processing unit 1102 is further configured to perform S801.

The processing unit 1102 is further configured to execute the selection operator of the first logical node when the matching operator matches to the at least one first sub-link. For example, in connection with fig. 8, the processing unit 1102 is further configured to perform S802.

The processing unit 1102 is further configured to determine, when the selection operator selects the second sub-link from the at least one first sub-link, whether the second sub-link meets a second condition. For example, in connection with fig. 8, the processing unit 1102 is further configured to execute S803.

The processing unit 1102 is further configured to, when the second sub-link meets the second condition, obtain address information of the second sub-link, and determine the address information of the second sub-link as address information of the n+1th sub-link. For example, in connection with fig. 8, the processing unit 1102 is further configured to execute S804.

Optionally, the processing unit 1102 is further configured to determine whether the target logical node has a sub-logical layer when the matching operator does not match the first sub-link. For example, in connection with fig. 9, the processing unit 1102 is further configured to execute S901.

The processing unit 1102 is further configured to determine whether a target logical node has a sub-logical layer when the matching operator matches to at least one first sub-link, and the selection operator selects a second sub-link from the at least one first sub-link, and the second sub-link does not satisfy the second condition. For example, in connection with fig. 9, the processing unit 1102 is further configured to execute S902.

Optionally, the processing unit 1102 is further configured to determine, when the target logical node has a sub-logical layer, whether the sub-logical layer of the target logical node includes a logical node that satisfies the first condition. For example, in connection with fig. 10, the processing unit 1102 is further configured to execute S1001.

The processing unit 1102 is further configured to determine that the target logical node cannot output the n+1th sub-link when the target logical node does not have the sub-logical layer. For example, in connection with fig. 10, the processing unit 1102 is further configured to execute S1002.

The embodiment of the application also provides a computer readable storage medium, which comprises computer execution instructions, when the computer execution instructions run on a computer, the computer is caused to execute the link splicing method provided in the embodiment.

The embodiment of the application also provides a computer program which can be directly loaded into a memory and contains software codes, and the computer program can realize the link splicing method provided by the embodiment after being loaded and executed by a computer.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer-readable storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and the division of modules or units, for example, is merely a logical function division, and other manners of division are possible when actually implemented. For example, multiple units or components may be combined or may be integrated into another device, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and the parts shown as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units. The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the general technology or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a device (may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A method of link splicing, comprising:

acquiring a plurality of link information corresponding to a plurality of sub-links one by one; the link information comprises link start information and link stop information;

When the link termination information of other sub-links does not exist the link termination information which is the same as the link start information of the target sub-link, determining the target sub-link as the first sub-link of the target link; the other sub-links are sub-links except the target sub-link in the plurality of sub-links;

Determining address information of other sub-links according to the first sub-link and the logic topology tree, and splicing the plurality of sub-links based on the address information of the other sub-links and the first sub-link to obtain the target link; the logical topology tree comprises a plurality of logical nodes; the logic node is used for determining the address information of the next sub-link of the sub-link successfully matched with the logic node;

Wherein the determining address information of the other sub-links according to the first sub-link and the logical topology tree includes:

Inputting link termination information of an nth sub-link into the logical topology tree; n is a positive integer;

When the logic topology tree comprises a logic node successfully matched with the nth sub-link, determining whether a target logic node outputs address information of the (n+1) th sub-link; the target logical node is a logical node successfully matched with the nth sub-link;

When the target logic node outputs the address information of the (n+1) th sub-link, repeatedly inputting the link termination information of the (n+1) th sub-link into the logic topology tree until the logic topology tree cannot be matched with the sub-link;

When the logic topology tree does not comprise a logic node successfully matched with the nth sub-link or the target logic node cannot output the (n+1) th sub-link, determining the nth sub-link as the last sub-link of the target link;

and determining the address information of other sub-links according to the address information of the sub-links output by the logic topology tree.

2. The link splicing method according to claim 1, wherein the logical topology tree comprises a plurality of logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured by the logic node, and/or the time slot information of the nth sub-link is the same as the time slot information configured by the logic node;

after the link termination information of the nth sub-link is input into the logical topology tree, the method further comprises:

When the link termination information of the nth sub-link accords with a first condition corresponding to a first logic node in the mth logic layer, determining the first logic node as the target logic node; m is a positive integer;

When the link termination information of the nth sub-link does not meet a first condition corresponding to a first logic node in the mth logic layer, determining whether the (m+1) th logic layer comprises the logic node meeting the first condition or not until each logic layer does not comprise the logic node meeting the first condition, and determining that the logic topology tree does not comprise the logic node successfully matched with the nth sub-link; the (m+1) th logical layer is a sub-logical layer of the first logical node.

3. The link splicing method according to claim 2, wherein the first logical node includes: matching operators, selecting operators and second conditions;

The matching operator is used for: determining the sub-links corresponding to the link starting information which is the same as the link ending information of the nth sub-link in the link starting information of the rest sub-links; the rest of the sub-links are sub-links except the nth sub-link in the plurality of sub-links;

the selection operator is used for: determining the sub-link with the largest sub-link port number value;

The second condition includes: determining whether the number of spliced target links is greater than a threshold or determining whether a second sub-link is a sub-link in the spliced target link;

After the first logical node is determined to be the target logical node, the method further includes:

executing the matching operator of the first logical node;

executing the selection operator of the first logical node when the matching operator matches at least one first sub-link;

Determining whether a second sub-link satisfies the second condition when the selection operator selects the second sub-link from the at least one first sub-link;

and when the second sub-link meets the second condition, acquiring the address information of the second sub-link, and determining the address information of the second sub-link as the address information of the (n+1) th sub-link.

4. The link splicing method according to claim 3, further comprising, after said executing said matching operator of said first logical node:

When the matching operator cannot match the first sub-link, determining whether a sub-logic layer exists in the target logic node;

And when the matching operator is matched with the at least one first sub-link, and the selecting operator selects the second sub-link from the at least one first sub-link, and the second sub-link does not meet the second condition, determining whether a sub-logic layer exists in the target logic node.

5. The link splicing method according to claim 4, further comprising:

When the target logical node has a sub-logical layer, determining whether the sub-logical layer of the target logical node comprises a logical node meeting the first condition;

And when the target logic node does not have a sub-logic layer, determining that the target logic node cannot output the n+1th sub-link.

6. A link splicing apparatus, comprising: an acquisition unit and a processing unit;

The acquisition unit is used for acquiring a plurality of link information corresponding to the plurality of sub-links one by one; the link information comprises link start information and link stop information;

The processing unit is configured to determine, when link termination information that is the same as link start information of a target sub-link does not exist in link termination information of other sub-links, the target sub-link as a first sub-link of the target link; the other sub-links are sub-links except the target sub-link in the plurality of sub-links;

The processing unit is further configured to determine address information of the other sub-links according to the first sub-link and the logical topology tree, and splice the plurality of sub-links based on the address information of the other sub-links and the first sub-link, so as to obtain the target link; the logical topology tree comprises a plurality of logical nodes; the logic node is used for determining the address information of the next sub-link of the sub-link successfully matched with the logic node;

Wherein, the processing unit is used for:

7. The link splicing apparatus of claim 6, wherein the logical topology tree comprises a plurality of logical layers; each logical node includes a first condition; the first condition includes: the link connection type of the nth sub-link is the same as the link connection type configured by the logic node, and/or the time slot information of the nth sub-link is the same as the time slot information configured by the logic node;

The processing unit is further configured to determine, when the link termination information of the nth sub-link meets a first condition corresponding to a first logical node in the mth logical layer, the first logical node as the target logical node; m is a positive integer;

the processing unit is further configured to determine whether a logic node satisfying the first condition is included in an (m+1) th logic layer when the link termination information of the (n) th sub-link does not conform to the first condition corresponding to the first logic node in the (m) th logic layer, until each logic layer does not include a logic node satisfying the first condition, and determine that the logic topology tree does not include a logic node successfully matched with the (n) th sub-link; the (m+1) th logical layer is a sub-logical layer of the first logical node.

8. The link splicing apparatus of claim 7, wherein the first logical node comprises: matching operators, selecting operators and second conditions;

the processing unit is further configured to execute the matching operator of the first logical node;

the processing unit is further configured to execute the selection operator of the first logical node when the matching operator matches at least one first sub-link;

the processing unit is further configured to determine, when the selection operator selects a second sub-link from the at least one first sub-link, whether the second sub-link meets the second condition;

the processing unit is further configured to obtain address information of the second sub-link when the second sub-link meets the second condition, and determine the address information of the second sub-link as address information of the n+1th sub-link.

9. The link splicing apparatus of claim 8, wherein,

The processing unit is further configured to determine whether a sub-logical layer exists in the target logical node when the matching operator does not match the first sub-link;

The processing unit is further configured to determine whether a sub-logical layer exists in the target logical node when the matching operator matches the at least one first sub-link, the selection operator selects the second sub-link from the at least one first sub-link, and the second sub-link does not satisfy the second condition.

10. The link splicing apparatus of claim 9, wherein,

The processing unit is further configured to determine, when the target logical node has a sub-logical layer, whether the sub-logical layer of the target logical node includes a logical node that satisfies the first condition;

the processing unit is further configured to determine that the target logical node cannot output the n+1th sub-link when the target logical node does not have a sub-logical layer.

11. A link splicing device, which is characterized by comprising a memory and a processor; the memory is used for storing computer execution instructions, and the processor is connected with the memory through a bus; when the link splicing device is operated, the processor executes the computer-executable instructions stored in the memory to cause the link splicing device to perform the link splicing method according to any of claims 1-5.

12. A computer readable storage medium comprising computer executable instructions which, when run on a computer, cause the computer to perform the link splicing method of any of claims 1-5.