CN116244129B

CN116244129B - Memory performance testing method and device and computer equipment

Info

Publication number: CN116244129B
Application number: CN202310221391.9A
Authority: CN
Inventors: 刘蔓莉; 鹿存义; 郭锐; 王马俊; 柴兆文
Original assignee: Zhongke Controllable Information Industry Co Ltd
Current assignee: Zhongke Controllable Information Industry Co Ltd
Priority date: 2023-03-09
Filing date: 2023-03-09
Publication date: 2024-08-23
Anticipated expiration: 2043-03-09
Also published as: CN116244129A

Abstract

The application relates to a memory performance test method, a memory performance test device and computer equipment. The method comprises the following steps: according to the characteristic information of the processing cores in the current access module node in the computer equipment, configuring different processing core group numbers for various different performance test environments, performing memory performance test on the computer equipment in each performance test environment, and determining the optimal test result of the computer equipment according to the memory performance test result in each performance test environment. By adopting the method, the performance testing environment can be configured before the performance testing of the memory, all the processing cores in the memory access module node of the computer equipment are configured into a plurality of processing core groups, and parallel processing can be realized through the plurality of processing cores in the processing core groups in the process of the performance testing of the memory, so that the testing performance of the memory performance is improved.

Description

Memory performance testing method and device and computer equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and apparatus for testing memory performance, and a computer device.

Background

With the development of computer technology, computer devices are increasingly performing data processing. The memory is one of the key components in the computer equipment, all programs in the computer equipment are run in the memory, and processing data of the processor in the computer equipment are temporarily stored in the memory in the service processing process, so that the performance of the memory has a certain influence on the performance of the computer equipment, and the performance of the memory needs to be tested when the performance of the computer equipment is determined.

The memory delay is one of performance indexes of the memory, taking the test of the memory delay of the computer device as an example, the memory delay test method provided in the related art has the problem of lower memory delay test performance.

Disclosure of Invention

Accordingly, it is necessary to provide a method, an apparatus and a computer device for testing memory performance, which can improve the testing performance of memory latency.

In a first aspect, an embodiment of the present application provides a method for testing performance of a memory, where the method includes:

Configuring different numbers of processing core groups for a plurality of different performance test environments according to characteristic information of processing cores in current access module nodes in computer equipment;

under each performance test environment, performing memory performance test on the computer equipment;

and determining the optimal test result of the computer equipment according to the memory performance test results in each performance test environment.

According to the technical scheme, different processing core group numbers can be configured for various different performance test environments according to the characteristic information of the processing cores in the current access module node in the computer equipment, the memory performance test is carried out on the computer equipment under each performance test environment, and the optimal test result of the computer equipment is determined according to the memory performance test result under each performance test environment; by adopting the method, the performance test environment can be configured before the performance test of the memory, all the processing cores in the memory access module node of the computer equipment are configured into a plurality of processing core groups, and parallel processing can be realized through the plurality of processing cores in the processing core groups in the process of the performance test of the memory, so that the test performance of the memory performance is improved; meanwhile, the method can be applied to computer equipment of any type of processor, so that the universality of the memory performance testing method is improved; in addition, the method does not need to manually participate in the test process, so that the test cost can be saved, the manual error can be reduced, and the accuracy of the test result can be improved.

In one embodiment, configuring different numbers of processing core groups for a plurality of different performance test environments according to characteristic information of processing cores in current access module nodes in computer equipment includes:

And carrying out core binding operation on the processing cores in the access module node according to the characteristic information of the processing cores in the access module node, wherein the core binding operation is used for configuring different processing core group numbers for various different performance test environments.

According to the technical scheme provided by the embodiment of the application, the processing cores in the access module node can be subjected to core binding operation according to the characteristic information of the processing cores in the access module node; by adopting the method, all processing cores in each access module node in the computer equipment can be subjected to core binding operation to obtain a plurality of processing core groups in the access module nodes, so that parallel processing can be realized through the plurality of processing cores in the processing core groups in the process of testing the memory performance, and the testing performance of the memory performance is improved.

In one embodiment, the characteristic information includes a total number of processing cores; according to the characteristic information of the processing cores in the access module node, performing a core binding operation on the processing cores in the access module node, including:

Grouping all the processing cores in the access module node according to the total number of the processing cores in the access module node to obtain a plurality of processing core groups in the access module node;

and performing core binding operation on the processing cores in each processing core group.

According to the technical scheme provided by the embodiment of the application, all the processing cores in the access module node can be grouped according to the total number of the processing cores in the access module node to obtain a plurality of processing core groups in the access module node, and the processing cores in each processing core group are subjected to core binding operation; according to the method, all the processing cores in the access module nodes can be grouped through the total number of the processing cores in each access module node, so that the grouping process is simplified, the grouping speed of the processing cores can be improved, and the speed of configuring the number of different processing core groups is improved.

In one embodiment, before performing the memory performance test on the computer device in each performance test environment, the method further includes:

And determining a plurality of different memory insertion modes according to the attribute information of the memory slot in the computer equipment.

According to the technical scheme provided by the embodiment of the application, a plurality of different memory insertion modes can be determined according to the attribute information of the memory slot in the computer equipment, so that the computer equipment can be subjected to memory performance test in different memory insertion modes, the memory insertion mode corresponding to the optimal test result is obtained, the memory can be configured directly according to the insertion mode corresponding to the optimal test result when the subsequent memory performance test is convenient, the optimal test result can be obtained once, and the test steps of the memory performance are reduced.

In one embodiment, the attribute information includes a total number of memory slots and a total number of pluggable memory for each memory slot; according to the attribute information of the memory slot in the computer equipment, a plurality of different memory insertion modes are determined, including:

Acquiring the total amount of memory to be inserted into the computer equipment according to each performance test environment configuration;

according to a preset insertion rule, determining the insertion position of each memory insertion corresponding to the memory slots according to the total number of the memories, the total number of the memory slots and the total number of the memory which can be inserted into each memory slot;

And determining a plurality of different memory insertion modes according to the insertion positions of the memories.

According to the technical scheme, the configuration can be carried out according to each performance test environment, the total amount of the memories of the computer equipment to be inserted is obtained, according to a preset insertion rule, the insertion positions of the memory slots corresponding to the insertion of each memory are determined according to the total amount of the memories, the total amount of the memory slots and the total amount of the insertable memories of each memory slot, and according to the insertion positions of each memory, a plurality of different memory insertion modes are determined; according to the method, various different memory insertion modes can be rapidly determined according to the total number of the memories, the total number of the memory slots and the total number of the insertable memories of each memory slot, various different memory insertion modes are determined according to the priority of each position on the memory slot in the preset insertion rule, and the optimal memory environment is configured for the computer equipment according to the determined various different memory insertion modes, so that the testing performance of the memory performance can be improved.

And configuring system operation modes for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node.

According to the technical scheme provided by the embodiment of the application, before the performance test of the memory is executed, the system operation mode can be configured for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node, so that the performance test of the memory can be further carried out on the computer equipment in the system operation mode, and the performance test performance of the memory can be improved.

In one embodiment, the system operation mode is configured for a plurality of different performance test environments according to the characteristic information of the processor in the computer device and the characteristic information of the access module node, and the system operation mode comprises:

Determining a system operation mode according to the total number of processors in the computer equipment and the total number of access module nodes;

based on the mode configuration interface, a system operating mode is configured for a plurality of different performance testing environments.

According to the technical scheme provided by the embodiment of the application, the system operation mode can be determined according to the total number of processors in the computer equipment and the total number of access module nodes, and the system operation mode is configured for a plurality of different performance test environments based on the mode configuration interface; the method can determine the system operation mode in real time according to the total number of the processors in the computer equipment and the total number of the current access module nodes, so that the accuracy of the determined system operation mode is higher, and the problem that the computer equipment does not receive the relevant configuration instruction of the system operation mode is avoided by configuring the system operation mode based on the mode configuration interface, so that the computer equipment can receive and respond to the relevant configuration instruction of the system operation mode, and the testing performance of the memory performance is improved.

In one embodiment, the method further comprises:

detecting whether a hyper-thread of the computer device is closed;

If the hyper-threading is not closed, closing the hyper-threading, and executing the step of configuring the system operation mode for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node.

According to the technical scheme, whether the hyper-thread of the computer equipment is closed or not can be detected, when the hyper-thread is not closed, the hyper-thread is closed, and the step of configuring the system operation mode for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node is executed; the method can ensure that the hyper-threading is closed in a detection mode before the memory performance test is executed, and the memory performance test threads work independently, so that the speed and the efficiency of the memory performance test can be improved, the operation of the memory performance test threads can be prevented from being influenced by closing the hyper-threading, and the accuracy of the memory performance test result can be further improved.

In a second aspect, an embodiment of the present application provides a memory performance testing apparatus, where the apparatus includes:

the configuration module is used for configuring different numbers of processing core groups for various different performance test environments according to the characteristic information of the processing cores in the current access module node in the computer equipment;

the performance test module is used for testing the memory performance of the computer equipment under each performance test environment;

and the test result determining module is used for determining the optimal test result of the computer equipment according to the memory performance test results in each performance test environment.

In a third aspect, embodiments of the present application also provide a computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of the method of any of the embodiments of the first aspect described above when executing the computer program.

In a fourth aspect, embodiments of the present application also provide a computer readable storage medium having a computer program stored thereon, which when executed by a processor, implements the steps of the method of any of the embodiments of the first aspect described above.

In a fifth aspect, embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of the method of any of the embodiments of the first aspect described above.

The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.

Drawings

FIG. 1 is an internal block diagram of a computer device in one embodiment;

FIG. 2 is a flow chart of a method for testing memory performance in one embodiment;

FIG. 3 is a flow chart of a method for testing memory performance in another embodiment;

FIG. 4 is a flow chart of a method for testing memory performance according to another embodiment;

FIG. 5 is a flow chart of a method for testing memory performance according to another embodiment;

FIG. 6 is a flowchart of a memory performance testing method according to another embodiment;

FIG. 7 is a block diagram of a memory performance testing apparatus according to an embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In computer technology, memory is one of the important components in computer equipment, and in order to meet the performance requirements of computer equipment, it is most critical to ensure the performance of the memory in the computer equipment through a memory performance test technology.

The memory latency is one of the main performance indicators of the memory, and the memory latency of the computer device is tested as an example. In the related art, a memory delay and bandwidth testing tool is used to test the memory delay of the computer device, but the related art has the problem of lower memory delay testing performance. Based on this, the embodiment of the application provides a memory performance testing method, which can be applied to the computer equipment shown in fig. 1. Alternatively, the computer device may be, but not limited to, various personal computers, notebook computers, smartphones, and tablet computers, and may be implemented by a stand-alone server or a server cluster formed by a plurality of servers, and the specific form of the computer device is not limited in this embodiment.

In the embodiment of the present application, the method for testing the memory performance may be applicable to any type of computer equipment with a processor (Central Processing Unit, CPU), and the embodiment of the present application is not limited thereto. The following describes a method for testing memory performance by using a computer device as an execution body.

As shown in fig. 2, a flow chart of a memory performance testing method according to an embodiment of the present application is shown, and the method may be implemented by the following steps:

s100, configuring different numbers of processing core groups for various different performance test environments according to characteristic information of processing cores in current access module nodes in computer equipment.

Wherein at least one processor (Central Processing Unit, CPU) may be included within the computer device, each CPU may include multiple processing cores (i.e., CPU cores or CPU cores). Alternatively, the characteristic information of the processing core may be a clock frequency, a constituent material, a design structure, or the like.

In practical application, before executing the memory performance test method, all processing cores in the computer device may be grouped to obtain a plurality of memory access module nodes (Non-Uniform Memory Access node, NUMA nodes). Alternatively, the access module node may also be referred to as a non-coherent memory access node. It should be noted that, the computer device may group all the processing cores in the computer device according to the service processing requirement, and determine each group of processing cores as one access module node, where the total number of access module nodes obtained after grouping all the processing cores of the same computer device at different times may be the same or different.

Specifically, the computer device may group all the processing cores in each current access module node according to the same condition of the feature information of the processing cores, and configure different numbers of processing core groups for different performance test environments according to the obtained number of groups.

In addition, the computer device can determine a preset grouping rule according to the characteristic information of the processing cores in the current access module nodes in the computer device, then group all the processing cores in the current access module nodes according to the grouping rule, and then configure different numbers of processing core groups for various different performance test environments according to the obtained grouping number. Alternatively, a grouping rule may be understood as a rule that groups all processing cores in each memory module node.

Alternatively, the performance test environment may be generated after completing configuration of hardware modules in the computer device prior to performing the memory performance test. The number of the processing core groups configured differently is only a part of the configuration performance test environment, and in the test process, the number of the processing core groups correspondingly configured in the different performance test environments can be the same or different. Alternatively, the hardware module may be a processor, a processing core, a memory access module node, a memory, a network card, a graphics card, or the like.

S200, under each performance test environment, performing memory performance test on the computer equipment.

In practical application, after the computer equipment is configured with a performance test environment each time, a performance test tool can be used for testing the memory performance of the computer equipment. Alternatively, the memory performance may include memory bandwidth, memory pressure, pending applications and speed and memory bandwidth references, etc., and the performance test tools may be memory bandwidth test tools (e.g., lmbench, mbw, stream, etc.), memory pressure test tools (e.g., runMemtestpro, memtester, etc.), memory application (sequential/random) and (read/write) speed test tools (e.g., sysbench), memory bandwidth reference test tools (e.g., bendwidth), etc., accordingly.

In the embodiment of the present application, if the memory performance is a memory latency, the performance test tool is Multichase.

S300, determining an optimal test result of the computer equipment according to the memory performance test results in each performance test environment.

Based on the memory performance test results under each performance test environment obtained by the steps, the memory performance test results under each performance test environment can be processed to obtain the optimal test results of the computer equipment. Optionally, the memory performance test result may include a memory performance test result between each hardware module, such as a memory performance test result between the graphics card and the processor, a memory performance test result between the network card and the processor, a memory performance test result between the graphics card and the processing core, a memory performance test result between the network card and the processing core, a memory performance test result between the graphics card and the access module node, and a memory performance test result between the network card and the access module node.

In an embodiment, the method for processing the memory performance test results under each performance test environment may be to pre-train an algorithm model, and then input the memory performance test results under each performance test environment into the algorithm model, where the algorithm model outputs an optimal test result.

In still another embodiment, the method for processing the memory performance test result under each performance test environment may further be to compare the memory performance test result under each performance test environment to obtain an optimal test result.

It should be noted that, the computer device may include a CPU, a memory access module node and a processing core, and in the running process of the computer device, the CPU, the memory access module node and the processing core in the computer device all have data interaction with the memory, so the memory performance test of the computer device is actually a test of the memory performance when the CPU in the computer device interacts with the CPU, a test of the memory performance when the memory access module node interacts with the memory access module node and a test of the memory performance when the processing core interacts with the processing core, and naturally, the memory performance test result may include a first memory performance test result when the CPU interacts with the CPU, a second memory performance test result when the memory access module node interacts with the memory access module node and a third memory performance test result when the processing core interacts with the processing core.

In the embodiment of the application, the memory performance test result may be a performance test index value. In practical application, the computer device may sort the first memory performance test result, the second memory performance test result and the third memory performance test result in each performance test environment, and then select an optimal group of the first memory performance test result, the second memory performance test result and the third memory performance test result from the sorted results according to the optimal screening condition, i.e. the optimal test result. Optionally, the optimal screening condition may be generated by comprehensively considering the optimal memory performance of the historical test results when the CPUs interact with each other, the optimal memory performance of the memory access module node when the memory access module node interacts with the memory access module node, and the optimal memory performance of the processing core when the processing core interacts with the processing core.

After determining the optimal test result of the computer equipment, a log file of the test can be generated, wherein the log file comprises the optimal test result obtained by the current test, the memory performance test result corresponding to each performance test environment and the like. In practical application, before executing the step in S200, the log file generated in the previous test may be copied and stored to the target position, so as to avoid that when the log file generated in the next test covers the log file generated in the previous test, the log file is used for comparing the subsequent multiple test results; it should be noted that, the log file generated by each test is stored in the same location, and the location is different from the target location.

In some scenarios, since the memory performance test requirement is higher, the test performance of the memory performance needs to be improved, based on which a better performance test environment can be configured before the memory performance test, and the process of configuring the processing core in the performance test environment is described below. In an embodiment, the step in S100 may include: and carrying out core binding operation on the processing cores in the access module node according to the characteristic information of the processing cores in the access module node. The core binding operation is used for configuring different numbers of processing core groups for a plurality of different performance test environments.

Specifically, the computer device may group all the processing cores in each access module node according to the feature information of the processing cores in each access module node, and then perform a core binding operation on the same class of processing cores in each access module node according to the grouping result, so as to complete configuring different numbers of processing core groups for multiple different performance test environments.

Meanwhile, the computer equipment can also search the characteristic information of the processing cores in the access module nodes in the mapping relation respectively, acquire the identification information of the processing core groups corresponding to the searched characteristic information of the processing cores from the mapping relation, and then perform core binding operation on all the processing cores with the same identification information so as to finish configuring different processing core groups for various different performance test environments. Optionally, the mapping relationship may include different processing cores, feature information of each processing core, identification information of a processing core group corresponding to each feature information, and a correspondence relationship between the three. Alternatively, the identification information may be a character formed by combining at least one of a number, a letter, and a symbol.

The core binding operation may be understood as an operation of binding a plurality of processing cores together, so that the plurality of processing cores bound together implement parallel processing in a testing process, so as to improve the speed and efficiency of testing the performance of the memory, that is, improve the testing performance of the memory. Alternatively, the number of the above-mentioned processing core groups may be equal to the number of packets obtained by grouping all the processing cores in the access module node.

The following describes the process of performing the core binding operation on the processing core in the access module node according to the characteristic information of the processing core in the access module node. In one embodiment, the characteristic information includes a total number of processing cores; as shown in fig. 3, the step of performing the core binding operation on the processing core in the access module node according to the feature information of the processing core in the access module node may include:

S110, grouping all the processing cores in the access module node according to the total number of the processing cores in the access module node to obtain a plurality of processing core groups in the access module node.

Specifically, the computer device may obtain the total number of processing cores in each access module node, and then, according to the total number of processing cores in each access module node, respectively group all processing cores in each access module node, to obtain a plurality of processing core groups in each access module node.

The method for obtaining the total number of the processing cores in each access module node may be obtained by a user looking up attribute information of the computer device, or may be obtained by calling a feature information looking up tool, where the feature information looking up tool may be a numactl tool.

S120, performing core binding operation on the processing cores in each processing core group.

Based on the plurality of processing core groups in each access module node obtained in the steps, the core binding operation can be performed on the processing cores in each processing core group.

In practical application, the memory performance test results corresponding to the memory insertion modes on the computer device will also be different, and in order to obtain the optimal test result, a plurality of different memory insertion modes can be configured, and a process of how to configure a plurality of different memory insertion modes is described below. In an embodiment, before performing the step in S200, the method may further include: and determining a plurality of different memory insertion modes according to the attribute information of the memory slot in the computer equipment.

It should be noted that, according to the attribute information of the memory slot in the computer device, the step of determining the plurality of different memory insertion modes may be performed before the step in S200, or may be performed before the step in S100, which is not limited to this embodiment of the present application.

Specifically, the computer device may obtain attribute information of all memory slots in the computer device, and then determine a plurality of different memory insertion modes according to the attribute information of each memory slot in the computer device. Optionally, at least one memory slot may be included in the computer device, and attribute information of the memory slot may be information of a type, a material, a color, a shape, and the like of the memory slot.

For example, a method for determining multiple different memory insertion modes according to the attribute information of each memory slot in the computer device may be to pre-train an algorithm model, and then input the attribute information of each memory slot in the computer device into the algorithm model, where the algorithm model outputs multiple different memory insertion modes.

For example, the method for determining multiple different memory insertion modes according to the attribute information of each memory slot in the computer device may further determine the priority of inserting each memory slot into the memory according to the attribute information of each memory slot in the computer device, and then determine multiple different memory insertion modes according to the priority of inserting each memory slot into the memory.

The following describes the process of determining a plurality of different memory insertion modes according to the attribute information of the memory slot in the computer device. In an embodiment, the attribute information includes a total number of memory slots and a total number of insertable memories of each memory slot; as shown in fig. 4, the step of determining a plurality of different memory insertion modes according to the attribute information of the memory slot in the computer device may include:

s400, aiming at each performance test environment configuration, obtaining the total amount of the memory to be inserted into the computer equipment.

In order to determine the optimal test result, in the process of configuring different performance test environments before the performance test of the memories, different numbers of memories can be configured in different performance test environments. Correspondingly, the computer device may obtain the total amount of memory to be inserted into the computer device in different performance testing environments.

Alternatively, the total amount of memory to be inserted into the computer device may be 1 or more, which is not limited in the embodiment of the present application.

S500, according to a preset insertion rule, determining the insertion position of each memory insertion corresponding to the memory slots according to the total number of the memories, the total number of the memory slots and the total number of the memory which can be inserted into each memory slot.

In practical applications, before the memory performance test is performed, the computer device is fixed, and correspondingly, all the memory slots in the computer device are also fixed, that is, the total number of all the memory slots in the computer device and the total number of insertable memories in each memory slot are fixed.

If the number of the memories to be inserted into the memory slots in the computer device is plural, the sizes of the memories to be inserted may be the same or different. Alternatively, any size memory may be inserted at each location on the memory slot.

Specifically, the preset insertion rule may include the total number of memory to be inserted, the total number of memory slots in the computer device, the total number of memory that each memory slot can insert, the insertion position of each memory slot to be inserted, and the correspondence between the four. Correspondingly, the computer device may search for an insertion position of each memory insertion corresponding to the total amount of memory, the total amount of memory slots, and the total amount of insertable memory of each memory slot in a preset insertion rule.

In the embodiment of the application, the computer device can determine the total amount of the memory to be inserted in each memory slot according to the total amount of the memory, the total amount of the memory slots and the total amount of the memory which can be inserted in each memory slot, and then determine the insertion position of each memory slot corresponding to the memory insertion according to the total amount of the memory to be inserted in each memory slot according to a preset insertion rule. Alternatively, the total amount of memory to be inserted in each memory slot may or may not be equal.

The preset insertion rule may be user-defined, but in order to improve accuracy of the determined memory insertion position, the preset insertion rule may be determined by a history test result; the insertion rules may include a priority for each pluggable memory location on the memory slot.

It should be noted that, the memory is inserted into the higher level position of the memory slot, so that the testing performance of the corresponding memory performance is higher; and inserting the memory into a position with a lower level on the memory slot, wherein the test performance corresponding to the memory performance is lower. Naturally, the insertion positions of the memories to be inserted into the corresponding memory slots can be determined in sequence according to the priority of each insertable memory position on each memory slot in the preset insertion rule.

S600, determining a plurality of different memory insertion modes according to the insertion positions of the memories.

The computer device may determine insertion positions of the memories corresponding to the different numbers of memories to be inserted into the memory device as a plurality of different memory insertion modes.

Correspondingly, in the step S200, under each performance test environment, the step of performing the memory performance test on the computer device may include: and under each performance test environment, performing memory performance test on the computer equipment in different memory insertion modes.

In the embodiment of the application, the computer equipment can configure different amounts of memories for the computer equipment in different memory insertion modes under different performance test environments, and then perform memory performance test on the computer equipment in different memory insertion modes.

Alternatively, configuring different amounts of memory for a computer device by different memory insertion means may also be understood as configuring a part of different performance testing environments. That is, each performance test environment may include a memory environment configured by any memory insertion method and/or a processing core environment configured after performing different core binding operations on all processing cores in each memory access module node. In the embodiment of the application, the memory insertion mode is the same regardless of the total number of processors in the computer device.

For example, if the computer device has eight memory slots, the total number of insertable memories in each memory slot is 2, and the identifiers of the memory slots are respectively memory slot a, memory slot B, memory slot C,..and memory slot H, and correspondingly, the positions of insertable memories in each memory slot may be respectively 0 and 1, where (1) when the total number of memories to be inserted into the computer device is 1, determining that the insertion positions of the memories inserted into the corresponding memory slots may be C0 according to a preset insertion rule; (2) When the total number of the memories to be inserted into the computer equipment is 2, determining that the insertion positions of the memories to be inserted into the corresponding memory slots can be C0 and D0 according to a preset insertion rule; (3) When the total number of the memories to be inserted into the computer equipment is 4, determining that the insertion positions of the memories to be inserted into the corresponding memory slots can be C0, D0, G0 and H0 according to a preset insertion rule; (4) When the total amount of the memories to be inserted into the computer equipment is 6, determining that the insertion positions of the memories to be inserted into the corresponding memory slots can be A0, C0, D0, E0, G0 and H0 according to a preset insertion rule; (5) When the total amount of the memories to be inserted into the computer device is 8, determining that the insertion positions of the memories into the corresponding memory slots according to the preset insertion rule may be A0, B0, C0, D0, E0, F0, G0 and H0. Alternatively, when the position of the memory inserted into the memory slot is set, the method may not be limited to the first position 0 of the memory slot, and specifically the position of the preferential insertion may be determined according to a preset insertion rule.

In an embodiment, before performing the step in S200, the method may further include: and configuring system operation modes for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node.

In the embodiment of the present application, the step in S100, the step of configuring the system operation mode (i.e. NPS) for a plurality of different performance test environments, and the step of determining a plurality of different memory insertion modes according to the attribute information of the memory slot in the computer device may be the same, and the execution sequence in the memory performance test method may be the same, which is not limited in the embodiment of the present application, so long as the step in S200 is completed before the execution.

The configuration system operation mode may be a part of the configuration performance test environment, that is, each performance test environment may include a memory environment configured by any memory insertion method, a processing core environment configured after performing different core binding operations on all processing cores in each memory module node, and/or a configured system operation mode. However, in practical application, the performance of testing the memory performance can be improved only by executing the core binding operation on all the processing cores in the access module nodes in the computer equipment and configuring any one of the memory and the operation mode of the system according to different memory insertion modes, but the performance of testing the memory performance can be improved to a great extent by the executor. Alternatively, the above system operation mode may be understood as a configuration mode of the access module node.

Specifically, before executing the step in S200, the computer device may further search the feature information of each processor in the computer device and the feature information of each access module node in the computer device in the operation mode library, then obtain a system operation mode corresponding to the feature information of each processor and the feature information of each access module node in the operation mode library, and then configure the same system operation mode for a plurality of different performance test environments according to the obtained system operation modes.

Optionally, the operation mode library may include different system operation modes, feature information of each processor in the computer device, feature information of each access module node in the computer device, and correspondence between the three. The configuration system operation mode can comprise the processes of regrouping access module nodes in the computer equipment and setting memory sharing access in the computer equipment according to a processor in the computer equipment during the memory performance test.

Alternatively, the characteristic information of the processor may be information such as a main frequency, an external frequency, a buffer size, and an idle time of the processor; the characteristic information of the access module node may include information such as an operation speed of the access module node and a total number of processing cores included.

In addition, the computer equipment can also carry out arithmetic operation on the characteristic information of the processor and the characteristic information of the access module node in the computer equipment to obtain the identification information of the system operation mode, and then configures the corresponding system operation mode for a plurality of different performance test environments according to the identification information of the system operation mode. Alternatively, the arithmetic operations may be addition operations, subtraction operations, multiplication operations, exponential operations, and/or logarithmic operations, and the like.

The following describes the process of configuring the system operation mode according to the characteristic information of the processor and the characteristic information of the access module node in the computer device. In one embodiment, as shown in fig. 5, the step of configuring the system operation mode for a plurality of different performance test environments according to the feature information of the processor in the computer device and the feature information of the access module node may include:

S700, determining a system operation mode according to the total number of processors in the computer equipment and the total number of access module nodes.

Specifically, the computer device may obtain the total number of processors and the total number of current access module nodes in the computer device, then make a quotient between the total number of access module nodes and the total number of processors to obtain identification information of a system operation mode, and then determine the system operation mode according to the identification information of the system operation mode.

It should be noted that, in step S700, the total number of current access module nodes in the computer device may be the same as or different from the total number of access module nodes in the computer device before the execution of the above memory performance test method. In the embodiment of the present application, the total number of the processors may be understood as the total number of sockets (i.e. sockets) of the computer device; the identification information of the system operation mode is a number.

Optionally, the total number of processors and the total number of access module nodes in different computer devices may be different, and the total number of access module nodes in the same computer device may also be different at different moments, so the system operation modes may be multiple, and in practical application, the corresponding system operation mode may be determined according to the obtained identification information of the system operation mode.

The identification information of the system operation mode may be equal to 1, 2, 4, etc., and correspondingly, the system operation mode may be NPS 1, NPS 2, NPS 4, etc., in addition, the system operation mode may also be NPS 0, NPS 0 is not suitable for a process of determining the system operation mode according to the total number of processors in the computer device and the total number of access module nodes, and the system operation mode may be NPS 0 as long as the computer device is a dual CPU system.

In the embodiment of the application, NPS 0 represents that a dual CPU system is configured as 1 memory access module node, and all memories in the computer equipment can share staggered access; NPS 1 represents that each CPU in the computer equipment is configured into 1 memory access module node, and all memories connected with the same CPU can share staggered access; NPS 2 means that each CPU in the computer device is configured as 2 memory access module nodes, and all processing cores in the computer device are configured to be connected to 24 memories, and these 24 memories can share interleaved access; NPS 4 represents configuring each CPU in the computer device as 4 memory module nodes, and configuring each memory module node to be connected with 2 memories, and2 memories corresponding to each memory module node may share interleaved access. Alternatively, the multiple memories may share interleaved access, which is understood as that the read-write functions of the multiple memories are not different and are identical when data is written into the memories or read from the memories.

S800, configuring a system operation mode for a plurality of different performance test environments based on the mode configuration interface.

Based on the system operation mode obtained in the steps, a user can input relevant configuration instructions of the system operation mode to the computer equipment, and the computer equipment receives and responds to the relevant configuration instructions of the system operation mode to configure the system operation mode for each performance test environment respectively.

In embodiments of the present application, a computer device may configure a system operating mode for a plurality of different performance testing environments based on a mode configuration interface. Alternatively, a system operation mode setting area, a test time setting area, a confirmation cancellation area, and the like may be included on the mode configuration interface.

Under each different performance test environment, the computer equipment can receive and respond to a mode configuration interface opening instruction input by a user, output a mode configuration interface, and then receive and respond to a related configuration instruction of a corresponding system operation mode set by a system operation mode setting area in the mode configuration interface by the user so as to complete the configuration of the system operation mode for the performance test environment.

After the corresponding system operation mode is set by the system operation mode setting area in the mode configuration interface, the user can submit a confirmation instruction by triggering a confirmation control in the confirmation cancellation area on the mode configuration interface, or input the confirmation instruction by other input modes, so that the computer equipment receives the set system operation mode. Alternatively, the input modes may be input modes such as voice, gesture, action, and the like.

In an embodiment, before performing all the steps, as shown in fig. 6, the method may further include:

s10, detecting whether the hyper-thread of the computer equipment is closed.

Specifically, the computer device may receive and respond to a detection instruction input by a user, and detect whether a hyper-thread (SimulateMulti Threading, SMT) of the computer device has been turned off. Meanwhile, the computer equipment can also automatically trigger a detection instruction to detect whether the hyper-thread of the computer equipment is closed.

In this embodiment of the present application, the above-mentioned hyper-thread may be understood as all other threads except the memory performance test thread currently running on the computer device.

And S20, if the hyper-threading is not closed, closing the hyper-threading, and executing the step of configuring the system operation mode for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node.

It should be noted that, when it is determined that the hyper-threading is not closed, the computer device may automatically close the hyper-threading; in addition, when the hyper-thread is not closed, the computer equipment can also output relevant prompt information that the hyper-thread is not closed, then the user inputs a closing hyper-thread instruction according to the relevant prompt information, and the computer equipment receives and responds to the closing hyper-thread instruction.

In practical application, if the system operation mode is configured preferentially in the process of configuring the performance test environment, if the hyper-threading is determined not to be closed, the hyper-threading can be closed, and after the closing is finished, the step of configuring the system operation mode for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node is executed.

If the configuration of the insertion position of the memory is performed preferentially in the process of configuring the performance test environment, when the hyper-threading is determined not to be closed, the hyper-threading can be closed, and after the closing is finished, the step of determining a plurality of different memory insertion modes according to the attribute information of the memory slot in the computer equipment is executed.

If the process of configuring the performance test environment preferentially configures the processing core group, after determining that the hyper-threading is not closed, closing the hyper-threading, and executing the steps of configuring different numbers of the processing core groups for a plurality of different performance test environments according to the characteristic information of the processing cores in the current access module node in the computer equipment after closing.

In the embodiment of the application, before the memory performance testing method is executed, whether the necessary program dependent package is installed or not when the performance testing tool runs on the computer equipment can be detected, and if not, the program dependent package is installed first, and then the performance testing tool is installed after the installation is completed. Alternatively, the program dependency package may include a GCC compiling tool and a numactl tool, where the GCC compiling tool is a compiler suite developed by GNU, and the numactl tool is a tool capable of viewing the configuration and running state of access module nodes in the current computer device.

Before the performance test tool is installed, the installed program dependent package is ensured to ensure that the memory performance test process is successfully executed; the process of installing the program dependency package may include downloading the program dependency package, then decompressing the program dependency package to obtain a decompressed file, and then finding a corresponding installation package operation installation in the decompressed file.

In addition, before the memory performance test is executed, the number of pages of a large memory page of the memory in the computer equipment can be configured, so that the memory addressing times of the CPU in the memory performance test process are reduced, and the test performance of the computer equipment can be improved.

In one embodiment, the embodiment of the application further provides a memory performance testing method, which comprises the following steps:

(1) It is detected whether a hyper-thread of the computer device has been shut down.

(2) If the hyper-thread is not closed, the hyper-thread is closed.

(3) And determining a system operation mode according to the total number of processors in the computer equipment and the total number of access module nodes.

(4) Based on the mode configuration interface, a system operating mode is configured for a plurality of different performance testing environments.

(5) And acquiring the total amount of the memory to be inserted into the computer equipment according to each performance test environment configuration.

(6) According to a preset insertion rule, determining the insertion position of each memory insertion corresponding to the memory slots according to the total number of the memories, the total number of the memory slots and the total number of the memory which can be inserted into each memory slot.

(7) And determining a plurality of different memory insertion modes according to the insertion positions of the memories.

(8) And grouping all the processing cores in the access module node according to the total number of the processing cores in the access module node to obtain a plurality of processing core groups in the access module node.

(9) And performing core binding operation on the processing cores in each processing core group.

(10) And under each performance test environment, performing memory performance test on the computer equipment in different memory insertion modes.

(11) And determining the optimal test result of the computer equipment according to the memory performance test results in each performance test environment.

The implementation process of the above (1) to (11) may be specifically referred to the description of the above embodiment, and its implementation principle and technical effects are similar, and will not be described herein again.

It should be understood that, although the steps in the flowcharts related to the above embodiments are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

Based on the same inventive concept, the embodiment of the application also provides a memory performance testing device for realizing the memory performance testing method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation of one or more embodiments of the memory performance testing device provided below may refer to the limitation of the memory performance testing method described above, and will not be repeated herein.

In one embodiment, fig. 7 is a schematic structural diagram of a memory performance testing apparatus according to an embodiment of the application. As shown in fig. 7, the memory performance test apparatus according to the embodiment of the present application may include: a configuration module 11, a performance test module 12 and a test result determination module 13, wherein:

The configuration module 11 is configured to configure different numbers of processing core groups for a plurality of different performance test environments according to characteristic information of processing cores in current access module nodes in the computer equipment;

a performance test module 12, configured to perform a memory performance test on the computer device under each performance test environment;

And the test result determining module 13 is configured to determine an optimal test result of the computer device according to the memory performance test results under each performance test environment.

The memory performance testing device provided by the embodiment of the application can be used for executing the technical scheme in the embodiment of the memory performance testing method, and the implementation principle and the technical effect are similar, and are not repeated here.

In one embodiment, the configuration module 11 comprises: a binding core unit, wherein:

The core binding unit is used for carrying out core binding operation on the processing cores in the access module node according to the characteristic information of the processing cores in the access module node, and the core binding operation is used for configuring different processing core group numbers for various different performance test environments.

In one embodiment, the characteristic information includes a total number of processing cores; the binding core unit is specifically used for:

In one embodiment, the memory performance test device includes: a determination unit in which:

and the determining unit is used for determining a plurality of different memory inserting modes according to the attribute information of the memory slot in the computer equipment.

In one embodiment, the attribute information includes a total number of memory slots and a total number of pluggable memory for each memory slot; the determining unit is specifically configured to:

In one embodiment, the performance test module 12 is specifically configured to:

And under each performance test environment, performing memory performance test on the computer equipment in different memory insertion modes.

In one embodiment, the memory performance test device includes: a configuration unit, wherein:

The configuration unit is used for configuring the system operation mode for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node.

In one embodiment, the configuration unit is specifically configured to:

In one embodiment, the memory performance test device includes:

detecting whether a hyper-thread of the computer device is closed;

For specific limitations of the memory performance test apparatus, reference may be made to the above limitation of the memory performance test method, and no further description is given here. The modules in the memory performance testing device may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in FIG. 1. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide processing power. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer equipment is used for storing the memory performance test results under each performance test environment and the optimal test results of the computer equipment. The network interface of the computer device is for communicating with an external endpoint via a network connection. The computer program, when executed by a processor, implements a memory performance test method.

It will be appreciated by those skilled in the art that the architecture shown in fig. 1 is merely a block diagram of some of the architecture relevant to the present inventive arrangements and is not limiting as to the computer device to which the present inventive arrangements may be implemented, as a particular computer device may include more or less components than those shown, or may be combined with some components, or may have a different arrangement of components.

In one embodiment, there is also provided a computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:

In one embodiment, there is also provided a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:

In one embodiment, there is also provided a computer program product comprising a computer program which, when executed by a processor, performs the steps of:

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory. By way of illustration, and not limitation, RAM can be in various forms such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. The method for testing the memory performance is characterized by comprising the following steps:

Grouping each processing core in a memory access module node according to the total number of the processing cores in the current memory access module node in computer equipment, obtaining the number of a plurality of processing core groups, and configuring different processing core group numbers for a plurality of different performance test environments; under the condition that the hyper-threading of the computer equipment is closed, configuring a system operation mode for each performance test environment according to the total number of processors in the computer equipment and the total number of access module nodes; the system operation mode represents a configuration mode of access module nodes and memory sharing access in the computer equipment;

Performing a memory performance test on the computer device in each performance test environment, including: under each performance test environment, respectively performing memory performance test on the computer equipment in different memory insertion modes;

and determining the optimal test result of the computer equipment according to the memory performance test result in each performance test environment.

2. The method of claim 1, wherein configuring different numbers of processing core groups for a plurality of different performance test environments based on a total number of processing cores in a current access module node within the computer device comprises:

And carrying out core binding operation on the processing cores in the access module node according to the total number of the processing cores in the access module node, wherein the core binding operation is used for configuring different processing core group numbers for various different performance test environments.

3. The method according to claim 2, wherein the performing a core binding operation on the processing cores in the access module node according to the total number of processing cores in the access module node includes:

4. A method according to any one of claims 1-3, wherein prior to performing memory performance testing on the computer device in each of the performance testing environments, the method further comprises:

5. The method of claim 4, wherein the attribute information includes a total number of the memory slots and a total amount of insertable memory for each memory slot; the determining a plurality of different memory insertion modes according to the attribute information of the memory slot in the computer device includes:

According to a preset insertion rule, determining the insertion position of each memory insertion corresponding to the memory slot according to the total number of the memories, the total number of the memory slots and the total number of the memories which can be inserted into each memory slot;

and determining the plurality of different memory insertion modes according to the insertion positions of the memories.

6. A method according to any of claims 1-3, wherein said configuring system operation modes for a plurality of different said performance test environments based on characteristic information of a processor in said computer device and characteristic information of said access module node comprises:

Determining a system operation mode according to the total number of the processors and the total number of the access module nodes in the computer equipment;

The system operating mode is configured for a plurality of different performance testing environments based on a mode configuration interface.

7. The method of claim 6, wherein the method further comprises:

detecting whether a hyper-thread of the computer device has been closed;

if the hyper-thread is not closed, closing the hyper-thread, and executing the step of configuring the system operation mode for a plurality of different performance test environments according to the characteristic information of the processor in the computer equipment and the characteristic information of the access module node.

8. A memory performance testing apparatus, the apparatus comprising:

The configuration module is used for grouping each processing core in the access module node according to the total number of the processing cores in the current access module node in the computer equipment, obtaining a plurality of processing core group numbers, and configuring different processing core group numbers for a plurality of different performance test environments; under the condition that the hyper-threading of the computer equipment is closed, configuring a system operation mode for each performance test environment according to the total number of processors in the computer equipment and the total number of access module nodes; the system operation mode represents a configuration mode of access module nodes and memory sharing access in the computer equipment;

the performance test module is used for respectively performing memory performance test on the computer equipment in different memory insertion modes under each performance test environment;

9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1-7 when the computer program is executed.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.