CN116204465A

CN116204465A - Design of multi-channel DDR and PCIE data exchange module

Info

Publication number: CN116204465A
Application number: CN202310207952.XA
Authority: CN
Inventors: 许川佩; 马贤; 王阳
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2023-03-07
Filing date: 2023-03-07
Publication date: 2023-06-02

Abstract

The invention provides a design of a multi-channel DDR and PCIE data exchange module. The method is characterized in that: the system consists of DDR3 memory 1, DMA engine 2, interrupt engine 3, sending interface 4, PCIE IP core 5 channel arbiter 6, receiving interface 7 and register file 8. The method aims at realizing multi-channel bidirectional data transmission between the DDR memory and the PCIE bus, and packaging the designed data transmission channel into a reconfigurable IP core. In practical use, the number of transmission channels and the DMA transmission length thereof can be configured by the user through the reserved interface. The invention can be used in the fields of high data acquisition, high-speed data transmission and the like.

Description

Design of multi-channel DDR and PCIE data exchange module

Technical Field

The invention relates to a design of a multi-channel DDR and PCIE data exchange module, which can be used in the fields of high data acquisition, high-speed data transmission and the like.

Background

The DDR memory and the PCIE protocol are widely applied to the fields of data acquisition and high-speed data transmission, and for data transmission between the DDR memory and the PCIE protocol, the traditional scheme generally adopts a FIFO buffer memory mode to perform read-write operation on the DDR memory, so that the DDR memory can exist, when multi-channel data needs to perform read-write request on the DDR memory, a plurality of FIFO modules are required to be designed, and the multi-channel data cannot be simultaneously subjected to read-write operation, so that delay of data transmission is increased, and the transmission rate is reduced.

The design controls the data transmission process through the data exchange module to realize multi-channel streaming data transmission.

For streaming data, the data has the characteristics of continuous transmission, large transmission bandwidth, high real-time requirement and multiple channels, the design adopts a direct memory access technology to transmit the high-speed streaming data, and a channel arbiter 6 of a dynamic priority arbitration mechanism based on signal bandwidth is designed to improve the channel arbitration efficiency; the detailed partition is carried out on the file register, so that the transmission information in the transmission process is centralized and modularized, and the data transmission efficiency is improved; the interrupt engine 3 sets multiple channels to quickly receive the interrupt of the DMA engine 2, and sends the interrupt to the PCIE IP core 5 in time for interrupt processing, so that the system interrupt response rate is improved.

Disclosure of Invention

The invention aims to provide a data exchange module design based on multi-channel DDR and PCIE.

The purpose of the invention is realized in the following way:

a design of a multi-channel DDR and PCIE data exchange module is characterized in that: the system consists of a DDR3 memory controller 1, a DMA engine 2, an interrupt engine 3, a sending interface 4, a PCIE IP core 5, a channel arbitration 6, a receiving interface 7 and a register file 8; the data transmission links in the module are divided into an uplink and a downlink; the uplink data sequentially passes through the DDR3 memory controller, the DMA engine 2, the sending interface 4 and the PCIE IP core 5; downlink data sequentially pass through the PCIE IP core 5, the receiving interface 7 and the DDR3 memory controller;

wherein the uplink transmission is described as: when data is cached in the DDR3 memory, the DDR3 memory controller monitors the data cache quantity of each channel in the DDR3, when the cache data of a channel corresponding to a cache area reaches the length of one DMA transmission, the DDR3 memory controller puts forward a transmission application to the channel arbiter 6, the channel arbiter 6 selects one channel for transmission authorization through arbitration, and outputs the channel number and the DMA transmission destination address read out from the register file 8 to the DMA engine 2, the DMA engine 2 takes out the data from the DDR3 according to the information output by the channel arbiter 6, and sends the data to the sending interface 4 to form a memory write request TLP, and then sends the memory write request TLP to the PCIE IP core 5;

the downlink transmission is described as: when data is cached in the DDR3 memory, the DDR3 memory controller monitors the data cache quantity of each channel in the DDR3, when the residual cache space of a corresponding cache area of one channel is enough to hold data of one DMA transmission, the DDR3 memory controller puts forward a transmission application to the channel arbiter 6, the channel arbiter 6 selects one channel for transmission authorization through arbitration, and outputs the channel number and DMA transmission destination address read out from the register file 8 to the DMA engine 2, the DMA engine 2 generates a memory read request TLP header according to the information output by the channel arbiter 6, and sends the memory read request TLP to the sending interface 4, and then sends the memory read request TLP to the PCIE IP core 5;

the channel arbiter 6 employs a dynamic priority arbitration mechanism based on signal bandwidth. The arbiter divides the 8 lanes into 4 priority groups (i, ii, iii, iv), each priority group comprising a number of lanes. Each priority group specifically contains which channels are determined by the signal bandwidth of each channel, with channels having the same signal bandwidth in one priority group. And each priority group adopts a polling mode to carry out channel arbitration, for example, the priority group I comprises a channel 1 and a channel 3, when the priority group I is authorized last time, the channel 1 is authorized, and when the priority group I is authorized again, the channel 3 is authorized.

The interrupt engine 3 is configured to process an interrupt request from the DMA engine 2, send the interrupt request to the PCIE IP core 5, monitor, by the DMA engine 2, a status of a DMA data transfer process of each channel, and when the DMA transfer is finished, the interrupt engine 3 sends the interrupt request to the PCIE IP core 5.

The register file 8 is connected with the receiving interface 7 module, the sending interface 4 module and the channel arbiter 6, stores the address, the data bit width, the transmission state and other information required by each data transmission, the ports of the register file 8 are mainly divided into two types, one type is given in the form of an address line and a data line, and the sending interface 4 module and the receiving interface 7 module are connected with the register file 8 through the interfaces and transmit the information to the PCIE IP core 5; the other type of ports are given in the form of specific signal lines, and the modules of the channel arbiter 6 and the like are connected with the register file 8 through the interfaces. [13] Compared with the advanced technology, the invention has the following advantages:

(1) The channel arbiter 6 adopts a dynamic priority arbitration mechanism of signal bandwidth, which can reduce transmission delay caused by switching of data channels in the multi-channel data transmission process and improve the multi-channel data transmission rate.

(2) The interrupt engine 3 encapsulates an independent interface to receive the interrupt information of each channel of the DMA engine 2, and simultaneously ensures that the interrupt information of each channel is independently and quickly sent to the PCIE IP core 5, thereby reducing interrupt response time and improving data transmission rate.

(3) The register file 8 stores all the information of each DMA transfer, reduces the bandwidth load on the data link, and improves the data transfer efficiency.

Drawings

Fig. 1 is a diagram showing an embodiment of a design of a multi-channel DDR and PCIE data switch module.

Shown in fig. 2 is a priority table of the lanes of the lane arbiter 6.

Shown in fig. 3 is a diagram of the primary ports of the interrupt engine 3 and their definitions.

Shown in fig. 4 is a diagram of the primary ports of register file 8 and their definitions.

Fig. 5 shows a spatial configuration of the register file 8.

Fig. 6 is a transmission sequence diagram of each channel of the channel arbiter 6.

Fig. 7 is a state transition diagram of the interrupt engine 3 state machine, which is: an IDLE state (msi_int_idle), an interrupt request transmission state (msi_int_send), an interrupt request transmission completion state (msi_int_send), an interrupt LOCK state (msi_int_lock).

Detailed Description

The invention is further illustrated below in conjunction with specific examples.

The principles of the present invention are first described in detail with reference to the drawings.

The invention mainly adopts a channel arbiter 6, an interrupt engine 3, a register file 8 and other peripheral modules to realize multi-channel data transmission, and the internal structure is shown in figure 1. The data transmission link is divided into an uplink data transmission link and a downlink data transmission link. The modules through which the uplink data passes are the DDR3 memory controller 1, the DMA engine 2, the sending interface 4 and the PCIEIP core 5 in sequence, and the interrupt information is sent to the PCIE IP core 5 by the DMA engine 2 through the interrupt engine 3. The downlink data sequentially passes through the PCIE IP core 5, the receiving interface 7 and the DDR3 memory controller.

The priority of the channel arbiter 6 is set by a priority table, as shown in fig. 2, and if the channel belongs to a certain priority group, 1 is filled in the corresponding position, otherwise 0 is filled, for example, the channel group i includes channel 0, channel 2 and channel 5.

The main port of the interrupt engine 3 and its definition are shown in fig. 3, and the port names wchn_dmadone_ch0-7 in the table represent wchn_dmadone port signals of 8 channels. The cfg_interrupt signal and cfg_interrupt_rdy signal connect to PCIE IP core 5. The user logic pulls the cfg_interrupt signal high to inform the pcie ip core that there is an interrupt to send.

The register file 8 main ports and their definitions are shown in fig. 4. In the figure, the port names of wdm_start_addr_ch0 to ch7 are shown to indicate that the signals exist in each channel. The ports of the register file 8 are mainly divided into two types, one type is given in the form of an address line and a data line, and the sending interface 4 module and the receiving interface 7 module are connected with the register file 8 through the interfaces and transmit the interfaces to the PCIE IP core 5. The other type of ports are given in the form of specific signal lines, and the modules of the channel arbiter 6 and the like are connected with the register file 8 through the interfaces. The spatial structure of the register file 8 is shown in fig. 5. The register file 8 mainly comprises 4 areas: endpoint device information area, each channel write DMA register area, each channel read DMA register area, each channel status area.

Examples:

in a transmission task, the priority table contents for the channel arbiter 6 are shown in fig. 2, and in the transmission process, no signal bandwidth of the channel is changed, the data buffer is no longer receiving new data, and the transmission sequence of the channels is shown in fig. 6. Channel group i is granted priority, then channel 0 is transmitted a first time, channel 2 is transmitted a second time, and channel 5 is retransmitted. And after the channel group I is transmitted, sequentially transmitting the channel group II, the channel group III and the channel group IV.

For the interrupt engine 3, if an interrupt request is generated by a certain channel of transmission channel in the dma engine, the interrupt request is transmitted to the interrupt engine 3 through a corresponding transmission port, and the interrupt engine 3 can quickly send interrupt information to the PCIE IP core 5 for corresponding interrupt reaction. The state transition diagram of the state machine of the interrupt engine 3 is shown in fig. 7, which contains 4 states: an IDLE state (msi_int_idle), an interrupt request transmission state (msi_int_send), an interrupt request transmission completion state (msi_int_send), an interrupt LOCK state (msi_int_lock). The definition and conversion relation of each state are as follows: msi_int_idle state: this state is the initial state of the state machine. The state machine waits for the completion of the DMA transfer transaction in this state, and when the DMA transfer of one of the channels is completed, jumps to the msi_int_send state, and otherwise continues to wait in this state.

MSI_INT_SEND state: in this state, the user logic issues an interrupt request to the PCIE IP core 5, and then always jumps to the msi_int_send state.

MSI_INT_SENT: in this state, the PCIE IP core 5 internally generates an MSI interrupt message, and when the PCIE IP core 5 successfully transmits the MSI interrupt message, the state jumps to the msi_int_lock state.

Msi_int_lock: in this state, PCIE IP core 5 is responding to the interrupt, and the state machine waits in this state until it successfully responds to the interrupt, and no new interrupt request is issued at this time.

For the file register, when data is transferred through the DMA engine 2, information such as the PGA type of the user equipment, the data bit width of the PCIE IP core 5, etc. is stored in the DMA register area of the register file 8, and the information of the area is used for initializing the driver. And storing the information such as the DMA transmission address, the DMA transmission length and the like into the DMA register area of the corresponding channel, wherein the information of the areas is used for controlling the reading and writing DMA transmission process of each channel.

Claims

1. A design of a multi-channel DDR and PCIE data exchange module is characterized in that: the system consists of a DDR3 memory controller 1, a DMA engine 2, an interrupt engine 3, a sending interface 4, a PCIE IP core 5 channel arbiter 6, a receiving interface 7 and a register file 8; the data transmission links in the module are divided into an uplink and a downlink; the uplink data sequentially passes through the DDR3 memory controller, the DMA engine 2, the sending interface 4 and the PCIE IP core 5; downlink data sequentially pass through the PCIE IP core 5, the receiving interface 7 and the DDR3 memory controller;

the downlink transmission is described as: when data is cached in the DDR3 memory, the DDR3 memory controller monitors the data cache quantity of each channel in the DDR3, when the residual cache space of a corresponding cache area of one channel is enough to hold data of one DMA transmission, the DDR3 memory controller puts forward a transmission application to the channel arbiter 6, the channel arbiter 6 selects one channel for transmission authorization through arbitration, and outputs the channel number and DMA transmission destination address read out from the register file 8 to the DMA engine 2, the DMA engine 2 generates a memory read request TLP header according to the information output by the channel arbiter 6, and sends the memory read request TLP to the sending interface 4, and then sends the memory read request TLP to the PCIE IP core 5.

2. The multi-channel DDR and PCIE data switch module design of claim 1 wherein: channel arbitration 6 employs a dynamic priority arbitration mechanism based on signal bandwidth. The arbiter divides the 8 lanes into 4 priority groups (i, ii, iii, iv), each priority group comprising a number of lanes. Each priority group specifically contains which channels are determined by the signal bandwidth of each channel, with channels having the same signal bandwidth in one priority group.

3. The multi-channel DDR and PCIE data switch module design of claim 1 wherein: the interrupt engine 3 is configured with multiple channels to independently receive the interrupt request from the DMA engine 2, and send the interrupt request to the PCIE IP core 5.

4. The multi-channel DDR and PCIE data switch module design of claim 1 wherein: the register file 8 is connected to the receiving interface 7 module, the transmitting interface 4 module, and the channel arbiter 6, and stores information such as address, data bit width, transmission status, and the like required for each data transmission.