CN116166581A - Queue type DMA controller circuit for PCIE bus and data transmission method - Google Patents

Abstract

The application discloses a queue type DMA controller circuit and data transmission method for PCIE bus, the circuit includes: an interface module, a description Fu Yinqing module, a channel module, a completion engine module, an axijfull MASTER interface module, and an axijstream MASTER interface module. During transmission, the descriptor list is sent to the DMA control circuit for processing through the TLP packet format of the PCIE, the DMA control circuit analyzes the information in the descriptor after processing and arranging the descriptor, forms a queue according to the transaction information, sequentially executes the descriptors in the queue, and completes data transmission of each transaction. By the application of the scheme, multiple transaction transmission can be realized at one time, the problem of discontinuous address data transmission is solved, the load of a CPU is released, and the data processing efficiency is improved.

Description

Queue type DMA controller circuit for PCIE bus and data transmission method

Technical Field

The application belongs to the technical field of digital circuits, relates to the technical field of DMA (direct memory access) transmission of PCIE (peripheral component interconnect express) buses, and particularly relates to a queue type DMA controller circuit for a PCIE bus and a data transmission method.

Background

The development of computer technology and bus technology has driven the widespread use of data transmission in various fields at present. Along with the development of data transmission technology, the high-speed interface bus is updated rapidly, the transmission data bandwidth is larger and larger, PCIE is taken as a new generation bus interface standard, is influenced by the rapidly developed industrial technology, and has the advantages of high bandwidth, high performance, low power consumption, low delay, high transmission reliability and the like compared with the prior generation bus PCI.

DMA (direct memory access) technology is an excellent and important technology for modern computer systems. Before the DMA technology appears, the data transmission modes between the CPU and the peripheral equipment include a polling transmission mode and an interrupt transmission mode, and the CPU is directly connected with other components through a system bus and performs data transmission. The processor needs to spend a large number of clock cycles waiting for data and interrupts to adapt to the operating frequency of the external device, resulting in inefficiency in the process of acquiring data. The DMA technology can effectively avoid the occupation of the working period of the CPU by the data access transaction, and the CPU gives the task of data transmission to the DMA to finish, thereby indirectly improving the working processing capacity of the CPU. In today's high-speed bus interface systems, the transfer and processing of large volumes of data is an important factor in system design. The DMA transmission circuit applied to PCIE bus technology provides excellent technical support for high-speed transmission and efficient processing of data.

In the prior art, a DMA controller of an SOC chip generally adopts a register type DMA, that is, a CPU core configures information such as a destination address, a source address, a data length and the like to the DMA controller to perform data transmission, and after each transaction transmission is finished, an interrupt signal is sent to the CPU, so that data transmission of discontinuous addresses cannot be performed, and the CPU is not well liberated.

Disclosure of Invention

In order to solve the defects in the prior art, the queue type DMA controller circuit and the data transmission method for the PCIE bus can realize multiple transaction transmission at one time by combining the characteristics of the TLP packet data format of the PCIE bus, solve the problem of discontinuous address data transmission, are beneficial to relieving the load of a CPU and improve the data processing efficiency.

In order to achieve the above object, the present invention adopts the following technique:

a queued DMA controller circuit for a PCIE bus, connected between a PCIE and a functional module, comprising: an interface module, a description Fu Yinqing module, a channel module, a completion engine module, an axi_full_master interface module, and an axi_stream_master interface module;

the interface module comprises an AXI_STREAM read interface and an AXI_STREAM write interface, wherein the AXI_STREAM read interface is connected with the PCIE bus, the description Fu Yinqing module and the channel module, and the AXI_STREAM write interface is connected with the PCIE bus, the completion engine module and the channel module; the descriptor engine module is connected with the channel module and the completion engine module; the channel module is connected with the descriptor engine module, the completion engine module, the AXI_FULL_MASTER interface module and the AXI_STREAM_MASTER interface module; an axijfull_master interface module and an axijstream_master interface module are connected between the channel module and the function module.

The axi_stream read interface is configured to receive a TLP packet of the PCIE bus, and parse the TLP packet according to a TLP packet format: if the data is the descriptor, the descriptor is sent to a description Fu Yinqing module, and if the data is the transaction data, the data is sent to a channel module;

the descriptor engine module is used for carrying out queue ordering on the received descriptors, and taking one at a time according to the queue order and transmitting the one to the channel module;

the channel module is used for receiving the descriptor transmitted by the descriptor engine module, selecting an AXI_FULL_MASTER interface module to perform data transmission with the function module in an address mapping addressing mode according to information in the descriptor, or selecting the AXI_STREAM_MASTER interface module to perform data transmission with the function module in a data STREAM mode, and transmitting the data transmission information to the completion engine module after each read-write operation is completed;

the completion engine module is used for receiving the information sent by the channel module, making a making completion descriptor after each time of receiving, and informing the descriptor engine module of transmitting the next descriptor; when all the transactions are completed, making all the completion descriptors into descriptor queues, transmitting the descriptor queues to an AXI_STREAM write interface, generating TLP packets through the AXI_STREAM write interface, and sending the TLP packets to the PCIE bus.

A data transmission method for a queue type DMA controller circuit of a PCIE bus, comprising the steps of:

the interface module obtains the TLP packet from the PCIE bus in a data flow mode by using an AXI_STREAM read interface, and analyzes the TLP packet according to the TLP packet format: if the data is the descriptor, the descriptor is sent to a description Fu Yinqing module, and if the data is the transaction data, the data is sent to a channel module;

two-bit transaction ids are designed in the format of the descriptor and are used for judging the priority of the transaction described by the descriptor, and when the descriptor is subjected to queue ordering by the description Fu Yinqing module, the received descriptor is subjected to queue ordering according to the priority, and one is fetched and transmitted to the channel module at each time according to the queue order;

the channel module receives the descriptor transmitted by the descriptor engine module, and selects an AXI_FULL_MASTER interface module to perform data transmission with the function module in an address mapping addressing mode according to information in the descriptor, or selects the AXI_STREAM_MASTER interface module to perform data transmission with the function module in a data STREAM mode; after finishing each read-write operation, the channel module sends the data transmission information to the finishing engine module;

the completion engine module receives the information sent by the channel module, makes a making completion descriptor after each time of receiving, and notifies the descriptor engine module to transmit the next descriptor;

after all the transactions are completed, the completion engine module makes all the completion descriptors into descriptor queues, transmits the descriptor queues to the AXI_STREAM write interface, generates TLP packets through the AXI_STREAM write interface and sends the TLP packets to the PCIE bus.

The invention has the beneficial effects that:

1. the queue type DMA controller circuit applied to the PCIE bus is mainly used for carrying and transmitting data through the packet format of the PCIE protocol, before data transmission, a CPU opens up a section of memory space in a host space, information of transactions needing to be transmitted is written into a descriptor, a plurality of descriptors form a descriptor list and are stored in the section of memory space, and a descriptor engine module of the design circuit is used for carrying out queue ordering on the descriptors in the descriptor list to finish data transmission of a plurality of transactions, so that the data transmission of a plurality of transactions can be realized at one time, the problem of discontinuous address is solved, the load of the CPU is released, and the data processing efficiency is improved;

2. the method and the device have the advantages that the data type judgment bits are preset in the first frame format of the TLP packet header, so that the interface module can conveniently transmit data to the description engine module or the channel module respectively, meanwhile, the interface type judgment bits and the read-write state judgment bits are preset in the descriptor format, different interfaces can be conveniently selected, data transmission is realized in an address mapping mode or a data stream mode, and read-write transactions can be well managed respectively;

3. the method conforms to the data packet format for processing the PCIE protocol, and the configuration can be changed in subsequent development, so that the circuit is applicable to other interface types, and has high efficiency and flexibility.

Drawings

Fig. 1 is a schematic diagram of an application scenario of a queue type DMA controller circuit for a PCIE bus and an overall structure of a DMA controller circuit according to an embodiment of the present application.

Fig. 2 is a block diagram of a queue type DMA controller circuit for a PCIE bus according to an embodiment of the present application.

FIG. 3 is a PCI E transaction layer TLP packet format according to an embodiment of the present application

Fig. 4 is a TLP header format of an embodiment of the present application.

Fig. 5 is a design of a descriptor format of an embodiment of the present application.

Fig. 6 is a block diagram of a descriptor engine module according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings, but the described embodiments of the present invention are some, but not all embodiments of the present invention.

The embodiment of the application provides a queue type DMA controller circuit for a PCIE bus, and fig. 1 shows a circuit environment of an application scenario of the queue type DMA controller circuit. Specifically, the method is applied to a scenario that two PCIE devices perform data transmission, one PCIE device is a host end, the other PCIE device is an endpoint end device, the two PCIE devices are communicated through a PCIE bus, the address of the endpoint end device is mapped into a memory address of the host end, the host end can operate data in the address of the endpoint end device according to the mapped address, and the endpoint end device performs data reading and writing through a PCIE port under the control of the host end. The DMA controller circuit of the embodiment is configured at the endpoint end, is connected between a PCIE bus of the endpoint end and the functional module, and is used as bridging between a PCIE port and user logic; under the configuration of the CPU at the host end, the bus can be temporarily acquired from the CPU hand to replace the CPU to carry out data transmission among different devices.

Before data transmission is carried out once, a CPU of a host writes a source address, a destination address, a data length and configuration information of transaction data to be transmitted into a descriptor, and a plurality of descriptors form a section of descriptor list to be stored into a section of memory space of the host. The TLP packet of the PCIE transaction layer is 32bits per frame, so the size of each descriptor is set to 32 x 3bits. A segment of the descriptor list may contain a maximum number of descriptor settings of 1024. When the host needs to perform a transaction data transmission, the descriptor list is sent to the PCIE interface to form a TLP packet, and then the TLP packet is transmitted to the endpoint device through the PCIE bus, and then the DMA controller circuit performs data transmission.

Specifically, as shown in fig. 2, the DMA controller circuit of this embodiment is connected between the PCIE bus and the functional module/USER LOGIC, and includes: an interface module, a description Fu Yinqing module, a channel module, a completion engine module, an axijfull MASTER interface module, and an axijstream MASTER interface module.

The interface module comprises an AXI_STREAM read interface and an AXI_STREAM write interface, wherein the AXI_STREAM read interface is connected with the PCIE bus, the description Fu Yinqing module and the channel module, and the AXI_STREAM write interface is connected with the PCIE bus, the completion engine module and the channel module; the descriptor engine module is connected with the channel module and the completion engine module; the channel module is connected with the descriptor engine module, the completion engine module, the AXI_FULL_MASTER interface module and the AXI_STREAM_MASTER interface module; an axijfull_master interface module and an axijstream_master interface module are connected between the channel module and the function module.

The axi_stream read interface is configured to receive a TLP packet of the PCIE bus, and parse the TLP packet according to a TLP packet format: if the data is the descriptor, the descriptor is sent to a description Fu Yinqing module, and if the data is the transaction data, the data is sent to a channel module; the axi_stream write interface is configured to generate a TLP packet from the data or descriptor queue and send the TLP packet to the PCIE bus.

The descriptor engine module is used for carrying out queue ordering on the received descriptors, and taking one at a time according to the queue order and transmitting the one to the channel module.

The channel module is used for receiving the descriptor transmitted by the descriptor engine module, selecting the AXI_FULL_MASTER interface module to perform data transmission with the function module through an address mapping addressing mode according to the information in the descriptor, or selecting the AXI_STREAM_MASTER interface module to perform data transmission with the function module through a data STREAM mode, and sending the data transmission information to the completion engine module after each read-write operation is completed.

The completion engine module is used for receiving the information sent by the channel module, making a making completion descriptor after each time of receiving, and informing the descriptor engine module of transmitting the next descriptor; when all the transactions are completed, making all the completion descriptors into descriptor queues, transmitting the descriptor queues to an AXI_STREAM write interface, generating TLP packets through the AXI_STREAM write interface, and sending the TLP packets to the PCIE bus.

When the DMA controller circuit of this example is used to perform the data transfer method:

after the interface module obtains a section of TLP packet from the PCIE bus by using the axi_stream read interface in a data flow manner, the information in the packet is disassembled according to the format of the TLP packet, and two data type judgment bits are preset in the first frame of the TLP packet header format obtained by the axi_stream read interface, and when the axi_stream read interface analyzes the TLP packet, the TLP packet is judged to be a descriptor or transaction data according to the data type judgment bits. For example, the TLP packet format of PCIE transaction layer is shown in fig. 3, and the TLP packet header format is shown in fig. 4. Setting the 17 th bit and the 18 th bit of the first frame of the TLP packet header as judgment bits, if the TLP packet header is 01, the segment of data is a descriptor, and if the TLP packet header is 10, the segment of data is transaction data needing to be transmitted. If the descriptor is a descriptor, the descriptor is sent to the description Fu Yinqing module, and if the descriptor is transaction data, the data is sent to the channel module.

The description Fu Yinqing module processes the descriptors, manages through queue ordering, and fetches one at a time in queue order for transmission to the channel module. The DMA transfer of this example may be performed for multiple transactions at a time, while completion of a discontinuous address data transfer in one transaction requires multiple descriptors to participate. And if the priority is high, the transaction is processed first. As shown in fig. 5, the descriptor format is designed to be 32 x 3bits, each layer is 32bits, and three layers are provided. The first layer of the descriptor is the transmission information, and the low sixteen bits from the 0 th bit to the 15 th bit are the data length of the data transmission; bits 16 and 17 represent transaction ids of the descriptor for judging priority, and two bits can represent 4 states, so that a maximum of 4 DMA transmission transactions are set; bits 18 and 19 are read-write status judgment, if 01 is read transmission/read transaction, 10 is write transmission/write transaction, 11 is reserved, and 00 is default value; bits 20 and 21 are interface type judgment, if 01 is used for identifying data transmission, an AXI_FULL_MASTER interface module and a function module are used for carrying out, if 10 is used for identifying data transmission, an AXI_STREAMING_MASTER interface module and a function module are used for carrying out, 11 is reserved, and 00 is a default value; the remaining upper ten bits are reserved. The second layer 32bits of the descriptor are used to store the source address from which data is read during data transfer. The third layer of 32bits of the descriptor is used for storing a target address, and data read from a source address is written into the address during data transmission.

As shown in fig. 6, the descriptor engine module includes an arbiter and a descriptor FIFO, where the arbiter is configured to determine the transaction id in the descriptor to obtain the priority of the transaction described by the descriptor, and place the descriptor into the descriptor FIFO according to the priority to form a queue, so as to be transferred to the channel module in order one at a time. Specifically, after the descriptor engine module obtains the descriptors from the interface module, the descriptors are stored in an internally arranged space, and the space is set to 96×1024bit because the number of descriptors which can be generated by the host side is 1024 at maximum. Then judging ids of the descriptors through an arbiter, putting the descriptors into a subsequent FIFO (first in first out) according to the order of priority to form a descriptor queue, sending the descriptors to a channel module according to the order each time, and sending a signal to a descriptor engine through a completion engine by the channel module after the information contained by each descriptor is transmitted, so as to send the next descriptor until all the descriptors are consumed.

The channel module receives the descriptor transmitted by the descriptor engine module, and selects an AXI_FULL_MASTER interface module to perform data transmission with the function module in an address mapping addressing mode according to information in the descriptor, or selects the AXI_STREAM_MASTER interface module to perform data transmission with the function module in a data STREAM mode; and after finishing each read-write operation, the channel module sends the data transmission information to the finishing engine module.

As shown in fig. 2, the channel module includes a control module, two read FIFOs, and two write FIFOs, wherein one read FIFO is connected to an axi_stream read interface and an axi_full_master interface module, the other read FIFO is connected to an axi_stream read interface and an axi_stream_master interface module, one write FIFO is connected to an axi_stream write interface and an axi_full_master interface module, and the other write FIFO is connected to an axi_stream write interface and an axi_stream_master interface module.

Specifically, the axi_full_master interface module includes an axi_full read interface and an axi_full write interface, and when the axi_full_master interface module is selected to perform data transmission in an address mapping addressing mode, the axi_full read interface processes data read operation conforming to an AXI4 bus protocol, and the axi_full write interface processes data write operation conforming to the AXI4 bus protocol.

The AXI_stream_MASTER interface module comprises an AXI_stream read interface and an AXI_stream write interface, and when the AXI_stream_MASTER interface module is selected to transmit data in a data STREAM mode, the AXI_stream_MASTER interface module is used for transmitting data in a mode conforming to an AXI_stream protocol.

The format of the descriptor is designed with two read-write state judgment bits, and when the channel module performs each read-write operation, the channel module judges that the current read-write operation belongs to a write transaction or a read transaction according to the read-write state judgment bits: if the data is a writing transaction, reading the data through an AXI_STREAM read interface and performing writing operation through a writing FIFO in the channel module; if the data is a read transaction, the data is read through an AXI_FULL_MASTER interface module or an AXI_STREAMING_MASTER interface module, passes through a read FIFO in the channel module and performs a read operation through an AXI_STREAMING interface.

Two interface type judgment bits are designed in the format of the descriptor, and when the channel module performs each read-write operation, the AXI_FULL_MASTER interface module or the AXI_STREAM_MASTER interface module is selected according to the interface type judgment bits.

(1) When an axi_full_master interface module is selected:

if the data is a read transaction, the control module reads the data from the functional module through the AXI_FULL_MASTER interface module according to the source address and the data length information, and puts the data into a read FIFO, and then the read data, the destination address and the device information are made into a TLP packet through the interface module, and sent to the PCIE bus for transmission through the AXI_STREAM write interface;

if the transaction is a write transaction, the control module transmits source address and data length information to the interface module, the interface module writes the source address and the data length information into a TLP packet, a read request is sent out through a PCIE bus, a host end sends required transaction data to the interface module according to the request through a format of the TLP packet, the interface module judges that the data in the TLP packet received currently is the transaction data, the data is sent to the channel module, and the AXI_FULL_MASTER interface module writes the data into a target address according to the destination address information after writing the FIFO;

(2) When the axi_stream_master interface module is selected:

if the data is a read transaction, the data of the functional module is transmitted to a read FIFO of the channel module through the AXI_stream_MASTER interface module in a data STREAM form, and then is transmitted to the interface module, and the interface module makes the read data, the destination address and the equipment information into a TLP packet and transmits the TLP packet to the PCIE bus through the AXI_stream write interface for transmission;

if the data transmission is a write transaction and the data transmission has no target address, the control module transmits the source address and the data length information to the interface module, the interface module writes the source address and the data length information into the TLP packet, a read request is sent out through the PCIE bus, the host end sends the required transaction data to the interface module according to the request through the format of the TLP packet, the interface module judges the data in the currently received TLP packet as the transaction data, the data is sent to the channel module, and the data is written into the functional module through the data flow form by the AXI_stream_MASTER interface module after the FIFO is written.

The completion engine module receives the information sent by the channel module, makes a making completion descriptor after each time of receiving, and notifies the descriptor engine module to transmit the next descriptor; after all the transactions are completed, the completion engine module makes all the completion descriptors into descriptor queues, transmits the descriptor queues to the AXI_STREAM write interface, generates TLP packets through the AXI_STREAM write interface, and sends the TLP packets to the PCIE bus to announce the completion of DMA transmission.

By the design of the queue type DMA controller proposed by the example, the CPU writes the information of destination address, source address, data length and the like of the transmission data into one descriptor, and a plurality of descriptors form a descriptor list to contain the transmission of a plurality of transactions. And by combining the characteristics of the PCIE bus, sending the descriptor list to the DMA for processing through the TLP packet format of the PCIE, analyzing the information in the descriptor list after the DMA processes and arranges the descriptors, forming a queue by the descriptors according to the transaction information, and sequentially executing the descriptors in the queue to complete the data transmission of each transaction.

The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit and scope of the present application.

Claims (10)

1. A queue type DMA controller circuit for a PCIE bus, connected between the PCIE bus and a functional module, comprising: an interface module, a description Fu Yinqing module, a channel module, a completion engine module, an axi_full_master interface module, and an axi_stream_master interface module;

the interface module comprises an AXI_STREAM read interface and an AXI_STREAM write interface, wherein the AXI_STREAM read interface is connected with the PCIE bus, the description Fu Yinqing module and the channel module, and the AXI_STREAM write interface is connected with the PCIE bus, the completion engine module and the channel module; the descriptor engine module is connected with the channel module and the completion engine module; the channel module is connected with the descriptor engine module, the completion engine module, the AXI_FULL_MASTER interface module and the AXI_STREAM_MASTER interface module; the AXI_FULL_MASTER interface module and the AXI_STREAM_MASTER interface module are connected between the channel module and the function module;

the axi_stream read interface is configured to receive a TLP packet of the PCIE bus, and parse the TLP packet according to a TLP packet format: if the data is the descriptor, the descriptor is sent to a description Fu Yinqing module, and if the data is the transaction data, the data is sent to a channel module;

the descriptor engine module is used for carrying out queue ordering on the received descriptors, and taking one at a time according to the queue order and transmitting the one to the channel module;

the channel module is used for receiving the descriptor transmitted by the descriptor engine module, selecting an AXI_FULL_MASTER interface module to perform data transmission with the function module in an address mapping addressing mode according to information in the descriptor, or selecting the AXI_STREAM_MASTER interface module to perform data transmission with the function module in a data STREAM mode, and transmitting the data transmission information to the completion engine module after each read-write operation is completed;

the completion engine module is used for receiving the information sent by the channel module, making a making completion descriptor after each time of receiving, and informing the descriptor engine module of transmitting the next descriptor; when all the transactions are completed, making all the completion descriptors into descriptor queues, transmitting the descriptor queues to an AXI_STREAM write interface, generating TLP packets through the AXI_STREAM write interface, and sending the TLP packets to the PCIE bus.

2. The queued DMA controller circuit for the PCIE bus of claim 1 wherein the descriptor engine module includes an arbiter and a descriptor FIFO, the arbiter being configured to determine the transaction id in the descriptor to derive the priority of the transaction described by the descriptor, and to place the descriptor in the descriptor FIFO by priority to form a queue for transfer to the channel module one at a time in order.

3. The queued DMA controller circuit for the PCIE bus of claim 2 wherein the lane module comprises a control module, two read FIFOs, two write FIFOs, wherein one read FIFO connects the axi_stream read interface and the axi_full_master interface module, the other read FIFO connects the axi_stream read interface and the axi_stream_master interface module, one write FIFO connects the axi_stream write interface and the axi_full_master interface module, and the other write FIFO connects the axi_stream write interface and the axi_stream_master interface module.

4. The method for data transfer for a PCIE bus queued DMA controller circuit of claim 3, comprising the steps of:

the interface module obtains the TLP packet from the PCIE bus in a data flow mode by using an AXI_STREAM read interface, and analyzes the TLP packet according to the TLP packet format: if the data is the descriptor, the descriptor is sent to a description Fu Yinqing module, and if the data is the transaction data, the data is sent to a channel module;

the description Fu Yinqing module performs queue ordering on the descriptors, and takes one at a time according to the queue order and transmits the descriptors to the channel module;

the channel module receives the descriptor transmitted by the descriptor engine module, and selects an AXI_FULL_MASTER interface module to perform data transmission with the function module in an address mapping addressing mode according to information in the descriptor, or selects the AXI_STREAM_MASTER interface module to perform data transmission with the function module in a data STREAM mode; after finishing each read-write operation, the channel module sends the data transmission information to the finishing engine module;

the completion engine module receives the information sent by the channel module, makes a making completion descriptor after each time of receiving, and notifies the descriptor engine module to transmit the next descriptor;

after all the transactions are completed, the completion engine module makes all the completion descriptors into descriptor queues, transmits the descriptor queues to the AXI_STREAM write interface, generates TLP packets through the AXI_STREAM write interface and sends the TLP packets to the PCIE bus.

5. The data transmission method of claim 4, wherein the method is applied to a scenario that two PCIE devices perform data transmission, one PCIE device is a host side, the other PCIE device is an endpoint side device, the two PCIE devices communicate through a PCIE bus, an address of the endpoint side device is mapped to a memory address of the host side, the host side may operate data in the address of the endpoint side device according to the mapped address, and the endpoint side performs data reading and writing through a PCIE port under control of the host side;

the DMA controller circuit is configured at the end point, is connected between a PCIE bus of the end point and the functional module, and is used as bridging between a PCIE port and user logic;

before carrying out one-time data transmission, a CPU of a host writes a source address, a destination address, a data length and configuration information of transaction data to be transmitted into a descriptor, a plurality of descriptors form a descriptor list and are stored into a section of memory space of the host, when the host needs to carry out one-time transaction data transmission, the descriptor list is sent to a PCIE interface to form a TLP packet, and then the TLP packet is transmitted to an endpoint device through a PCIE bus, and then data transmission is carried out through a DMA controller circuit.

6. The data transmission method according to claim 4, wherein the descriptor format is provided with a two-bit transaction id for determining the priority of the transaction described by the descriptor, and the description Fu Yinqing module queues the received descriptor according to the priority when queuing the descriptor.

7. The method according to claim 5, wherein the first frame of the TLP packet header format acquired by the axi_stream read interface is pre-designed with two data type judgment bits, and when the axi_stream read interface parses the TLP packet, the axi_stream read interface judges whether the TLP packet is a descriptor or transaction data according to the data type judgment bits.

8. The data transmission method according to claim 7, wherein two read-write status judgment bits are designed in the format of the descriptor, and the channel module judges that the current read-write operation belongs to a write transaction or a read transaction according to the read-write status judgment bits when each read-write operation is performed: if the data is a writing transaction, reading the data through an AXI_STREAM read interface and performing writing operation through a writing FIFO in the channel module; if the data is a read transaction, the data is read through an AXI_FULL_MASTER interface module or an AXI_STREAMING_MASTER interface module, passes through a read FIFO in the channel module and performs a read operation through an AXI_STREAMING interface.

9. The data transmission method according to claim 8, wherein two interface type judgment bits are designed in the format of the descriptor, and the channel module selects an axi_full_master interface module or an axi_stream_master interface module according to the interface type judgment bits when performing each read/write operation;

when an axi_full_master interface module is selected:

if the data is a read transaction, the control module reads the data from the functional module through the AXI_FULL_MASTER interface module according to the source address and the data length information, and puts the data into a read FIFO, and then the read data, the destination address and the device information are made into a TLP packet through the interface module, and sent to the PCIE bus for transmission through the AXI_STREAM write interface;

if the transaction is a write transaction, the control module transmits source address and data length information to the interface module, the interface module writes the source address and the data length information into a TLP packet, a read request is sent out through a PCIE bus, a host end sends required transaction data to the interface module according to the request through a format of the TLP packet, the interface module judges that the data in the TLP packet received currently is the transaction data, the data is sent to the channel module, and the AXI_FULL_MASTER interface module writes the data into a target address according to the destination address information after writing the FIFO;

when the axi_stream_master interface module is selected:

if the data is a read transaction, the data of the functional module is transmitted to a read FIFO of the channel module through the AXI_stream_MASTER interface module in a data STREAM form, and then is transmitted to the interface module, and the interface module makes the read data, the destination address and the equipment information into a TLP packet and transmits the TLP packet to the PCIE bus through the AXI_stream write interface for transmission;

if the data transmission is a write transaction and the data transmission has no target address, the control module transmits the source address and the data length information to the interface module, the interface module writes the source address and the data length information into the TLP packet, a read request is sent out through the PCIE bus, the host end sends the required transaction data to the interface module according to the request through the format of the TLP packet, the interface module judges the data in the currently received TLP packet as the transaction data, the data is sent to the channel module, and the data is written into the functional module through the data flow form by the AXI_stream_MASTER interface module after the FIFO is written.

10. The data transmission method according to any one of claims 4 to 9, wherein the axi_full_master interface module includes an axi_full read interface and an axi_full write interface, and when the axi_full_master interface module is selected to perform data transmission in an address mapping addressing manner, the axi_full read interface processes a data read operation conforming to an AXI4 bus protocol, and the axi_full write interface processes a data write operation conforming to the AXI4 bus protocol;

the AXI_stream_MASTER interface module comprises an AXI_stream read interface and an AXI_stream write interface, and when the AXI_stream_MASTER interface module is selected to transmit data in a data STREAM mode, the AXI_stream_MASTER interface module is used for transmitting data in a mode conforming to an AXI_stream protocol.

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