CN116154022B - Double-layer SiO 2 Isolated photodiode structure, array and method of manufacture - Google Patents
Double-layer SiO 2 Isolated photodiode structure, array and method of manufacture Download PDFInfo
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- 229910004298 SiO 2 Inorganic materials 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 32
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 103
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 238000002161 passivation Methods 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 17
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- 239000004065 semiconductor Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a double-layer SiO 2 Isolated photodiode structure, array and method of manufacture, one of which is a bilayer SiO 2 The isolated photodiode structure comprises a substrate, wherein a silicon dioxide insulating layer is arranged in the substrate; the photodiode is arranged in the substrate, and a silicon dioxide isolation layer is arranged outside the photodiode and isolated from the substrate; the photodiode array of the invention has smaller leakage current, smaller noise, higher light response sensitivity, better compatible integration with other devices and strong practicability.
Description
Technical Field
The invention relates to the technical field of photodiode arrays, in particular to a double-layer SiO 2 Isolated photodiode structures, arrays, and methods of fabrication.
Background
Photodiode arrays refer to a series of photodiodes closely arranged on crystalline silicon, referred to as photodiode arrays PDA (photo-diode array). As with other types of photodetectors, are widely used for photoresistors, photosensitive coupling elements, photomultiplier tubes, and other devices. The research on the photodiode array at home and abroad is extensive and in depth.
There are several ways to manufacture PDA arrays. As shown in fig. 5, a high temperature N-type impurity implant is performed on a P-type substrate A1, the structure comprising a plurality of N-wells B1 and a plurality of PN junctions to form a photodiode array, each PN junction in the array being parallel without specific isolation. As shown in fig. 6, N-type diffusion is performed on a P-type substrate A1, an N-type epitaxial layer A2 is deposited on the surface of the P-type substrate after the N-type diffusion, P-type ion implantation is performed to form P-type regions B1 after the epitaxial layer deposition, and P-heavy doping is performed on the N-epitaxial layer between each P-type region to form an isolation B2, so that each PN junction is isolated from each other. This structure has high parasitic capacitance, high leakage current, high power consumption, and is liable to generate latch-up. And a PN junction can be formed between the P substrate and the N epitaxial layer, which clamps the cathode voltage to-0.7V, so that the PN junction is always in an off state.
For this reason, a new photodiode array structure is required to be designed to solve the above problems.
Disclosure of Invention
This section is intended to summarize some aspects of embodiments of the invention and to briefly introduce some preferred embodiments, which may be simplified or omitted from the present section and description abstract and title of the application to avoid obscuring the objects of this section, description abstract and title, and which is not intended to limit the scope of this invention.
The present invention has been made in view of the above and/or problems occurring in the prior art.
Therefore, the invention aims to solve the technical problems of large dark current, large parasitic capacitance, slow response speed, low sensitivity, poor compatibility with other devices and the like of the existing photodiode array.
In order to solve the technical problems, the invention provides the following technical scheme: double-layer SiO 2 An isolated photodiode structure comprising,
a substrate in which a silicon dioxide insulating layer is provided;
the photodiode is arranged in the substrate, and a silicon dioxide isolation layer is arranged outside the photodiode and isolated from the substrate.
As the double-layer SiO of the present invention 2 A preferred embodiment of the isolated photodiode structure, wherein: the substrate further comprises a base and an effective silicon layer, and the silicon dioxide insulating layer is embedded between the base and the effective silicon layer.
As the double-layer SiO of the present invention 2 Isolated optoelectronicsA preferred embodiment of the diode structure, wherein: the effective silicon layer is provided with a trapezoid groove, and the silicon dioxide isolation layer is paved on the inner surface layer of the trapezoid groove.
As the double-layer SiO of the present invention 2 A preferred embodiment of the isolated photodiode structure, wherein: the photodiode comprises polysilicon arranged in the trapezoid groove and an N region arranged on the polysilicon.
As the double-layer SiO of the present invention 2 A preferred embodiment of the isolated photodiode structure, wherein: a first passivation layer covering the photodiode is arranged on the effective silicon layer, and the first passivation layer is silicon dioxide.
As the double-layer SiO of the present invention 2 A preferred embodiment of the isolated photodiode structure, wherein: and a second passivation layer is arranged on the first passivation layer, and the second passivation layer is silicon dioxide doped with phosphorus.
The invention also discloses a double-layer SiO 2 An isolated photodiode array comprising a plurality of the aforementioned bilayer SiO 2 The isolated photodiodes are connected in series through metal, and share a substrate.
As the double-layer SiO of the present invention 2 A preferred embodiment of the isolated photodiode array, wherein: the N region is provided with a first metal connecting port, the polysilicon is provided with a second metal connecting port, and the metal is connected with the first metal connecting port of the photodiode and the second metal connecting port of the adjacent photodiode.
The invention also discloses a double-layer SiO as described above 2 A method of fabricating an isolated photodiode array, comprising: the substrate is adopted as a connecting layer,
a plurality of photodiodes are formed on the connection layer,
providing a first passivation layer and a second passivation layer;
a first metal connection port and a second metal connection port are arranged, and adjacent photodiodes are connected through metal.
As the double-layer SiO of the present invention 2 IsolatedA preferred embodiment of the method for manufacturing a photodiode array, wherein: the formation of the photodiode includes:
a trapezoid groove is formed on the substrate, and a silicon dioxide layer isolation layer is arranged on the substrate;
the trapezoid groove is refilled with polysilicon through chemical physical deposition;
and (4) performing N-type ion implantation on the polysilicon after the refilling to form an N region.
The invention has the beneficial effects that: the photodiode array of the invention has smaller leakage current, smaller noise, higher light response sensitivity, better compatible integration with other devices and strong practicability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 shows a double layer SiO according to an embodiment of the present invention 2 A schematic structural diagram of an isolated photodiode structure;
FIG. 2 shows a double layer SiO according to an embodiment of the present invention 2 A schematic structural diagram of an isolated photodiode array;
FIG. 3 is a schematic top view of a layout of a dual-layer silicon dioxide isolated photodiode array according to the present invention;
FIG. 4 is a schematic diagram of an equivalent circuit of a dual-layer silicon dioxide isolated photodiode array according to the present invention;
FIG. 5 is a schematic diagram of a conventional P-type substrate photodiode array structure according to the present invention;
FIG. 6 is a schematic diagram of a photodiode array structure of a conventional SOI substrate according to the present invention;
FIG. 7 shows a double layer SiO according to the present invention 2 A basic characteristic diagram of an isolated photodiode structure;
FIG. 8 is a dark current contrast diagram of different structures;
FIG. 9 is a graph showing the comparison of voltammetric characteristics of different structures;
FIG. 10 shows a double layer SiO according to the present invention 2 And after the isolated photodiode array manufacturing chip is finished, driving an output voltage, an output current, an on time and an off time schematic diagram of the MOS transistor.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration only, and in which is shown by way of illustration only, and in which the scope of the invention is not limited for ease of illustration. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Further still, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Example 1
Referring to FIGS. 1, 5-8, the embodiment provides a dual-layer SiO 2 The isolated photodiode structure comprises a substrate 100, wherein a silicon dioxide insulating layer 101 is arranged in the substrate 100; photodiode 200, photodiode 200 is disposed in substrate 100, and isThe external device of the diode 200 is a silicon dioxide isolation layer 201 isolated from the substrate 100.
Preferably, the substrate 100 is a P-type substrate, and the pn junction can be reverse biased by grounding the substrate during use, so that the circuit design is simplified, because the minority carrier of the P-substrate is electrons and the minority carrier of the N-substrate is holes. The mobility of electrons is greater than that of holes, and the MOS device is minority carrier conductive, so that an NMOSFET with higher integration speed on a P substrate is adopted.
Further, the substrate 100 further includes a base 102 and an active silicon layer 103, and the silicon oxide insulating layer 101 is embedded between the base 102 and the active silicon layer 103; a trapezoid groove is arranged on the effective silicon layer 103, and a silicon dioxide isolation layer 201 is paved on the inner surface layer of the trapezoid groove.
The photodiode 200 includes polysilicon 202 disposed inside the trapezoid trench and an N region 203 disposed on the polysilicon 202.
A first passivation layer 300 is disposed on the active silicon layer 103 to cover the photodiode 200, the first passivation layer 300 being silicon dioxide.
A second passivation layer 301 is disposed on the first passivation layer 300, and the second passivation layer 302 is phosphorus doped silicon dioxide.
Double-layer SiO of the present invention 2 The isolated photodiode structure is based on an SOI substrate, employs double-layer silicon dioxide to isolate PN junctions, and the novel design exhibits less leakage current, less noise, higher photo-response sensitivity, and better compatible integration with other devices than existing single-isolation photodiode arrays, and has a dark current less than nanoampoules (10 -9 A) The device has the advantages of 1000 times smaller leakage current and higher sensitivity than other structures, and response speed of less than 200ns. Has practical significance and good application prospect.
Referring to FIGS. 7 and 8, a double layer SiO of the present invention is shown 2 The isolated photodiode structure was tested accordingly to verify its performance.
In fig. 7, fig. 7 (a) is a dc simulation of current output as a function of light intensity. I.e. as the intensity of the light increases, the current increases linearly;
FIG. 7 (b) is a transient simulation of light off, with zero light power after 1ns and a short duration current output, the transient response time of the device being 200ns;
fig. 7 (c) is an ac signal response of the photodiode. The output current drops at the high frequency of the optical oscillation, and the cut-off frequency of the device is 109Hz;
fig. 7 (d) is the spectral response of the photodiode. The current output is reduced at high wavelength, the device irradiates at monochromatic light wavelength of 1000nm with illumination intensity of 2W/cm2, the wavelength of 0.1-0.8 um is adopted, and the device shows good efficiency in the wavelength range of about 500 nanometers.
From the above, it can be seen that the photodiode structure of the structure has a good response speed, and can reach nanosecond level.
In fig. 8, fig. 8 (a'): with double layers of SiO 2 An isolated photodiode structure;
fig. 8 (b'): a photodiode structure of an isolation trench structure;
fig. 8 (c'): photodiode structure of SOI substrate;
fig. 8 (d'): a photodiode structure of a P-type substrate;
dark current simulation corresponding to the above structures;
fig. 8 (a): the dark current of the double-isolated photodiode is about 2×10 -11 A—3×10 -11 A；
Fig. 8 (b): the dark current of the photodiode of the isolation trench structure is about 2×10 -8 A—3×10 -8 A；
Fig. 8 (c): dark current of photodiode of SOI substrate was 1×10 -8 A—2×10 -8 A；
Fig. 8 (d): dark current of photodiode of P-type substrate is 3×10 -7 A—4×10 -7 A
According to the simulation result, the double-isolation photodiode has smaller dark current which is at least 1000 times smaller than that of other structures.
Example 2
Referring to FIGS. 2 to 4, 9 and 10, the present embodimentProvides a double-layer SiO 2 An isolated photodiode array comprising a plurality of the aforementioned bilayer SiO 2 Isolated photodiode structure, in particular:
multiple double-layer SiO 2 The isolated photodiode structures share the substrate 100, with the photodiodes 200 connected in series by the metal 400;
the N region 203 is provided with a first metal connection port 401, the polysilicon 202 is provided with a second metal connection port 402, and the metal 400 is connected to the first metal connection port 401 of the photodiode 200 and the second metal connection port 402 of the adjacent photodiode 200.
Referring to FIGS. 9 and 10, a double layer SiO of the present invention is shown 2 The isolated photodiode structure and array were tested accordingly to verify their performance.
In FIG. 9, the bilayer SiO of the invention is shown without illumination 2 The isolated photodiode structure is the same as a common diode, has unidirectional conductivity, and when a forward voltage is applied, the current and the voltage are in an exponential relationship; when a reverse voltage is applied, the reverse current is a dark current.
In the presence of illumination, the characteristic curve shifts down giving a light intensity of 2W/cm 2 The reverse voltage range (-1V) generates photocurrent, and the shorter the wavelength, the stronger the light intensity and the larger the photocurrent. The reverse voltage is about 0.5V, the diode is conducted, and the photocurrent is in linear relation with the illumination.
As can be seen from FIG. 9, the double layer SiO shown in FIG. 9 (a) is formed under the same light intensity 2 The isolated structure has better voltammetric properties than the single layer isolated structure shown in fig. 9 (b), with a linear increase in intensity being more pronounced, and the structure has better voltammetric properties.
In FIG. 10, it can be seen from graph 10 (a) that when the input voltage V F When the voltage is about 1.138 plus or minus 0.02V, the output voltage is stable, the stable value is about 2V,
the wave equation is defined as:
degree of fluctuation m1=quench /> M2= QUOTE/> The method comprises the steps of carrying out a first treatment on the surface of the Wherein N is a variable which is the number of times,
maximum deviation p=quench />W is a parameter; k is the value with the largest difference from W,
calculating the input voltage V from the above formula F The degree of fluctuation m1=8.41% of the curve of the output voltage V, m2=6.05%, the maximum degree of fluctuation of the output voltage ±0.06V; the maximum deviation p=8.85%, so that the output voltage of the chip is relatively stable;
as can be seen from graph 10 (b), when the current I is input F When the output current is about 1.138+/-0.02V, the output current is stable, the stable value is about 1.5MA, and the input voltage V is calculated by the formula F The extent of fluctuation m1= 38.16% of the curve of the output electrical current I; m2=14.47%; maximum fluctuation degree of output current + -0.38 MA; the maximum deviation p=40%, and the output current of the chip is unstable compared with the output voltage, and the test data shows that when the input voltage VF is 1.137V, the larger output current 2.1V/2V appears.
As can be seen from graph 10 (c), when the current I is input F When the power tube is about 1.3+/-0.2 MA, the power tube switch is turned on for a time T ON Stabilized at 141us, and the input current I is calculated by the above formula FON -on time T ON The degree of fluctuation m1=0.42% of the curve, m2=1.48%; maximum fluctuation degree of the opening time is +/-0.015 us; the maximum deviation p=1.52%, so the on-time of the power tube is stable.
As can be seen from graph 10 (d), when the current I is input F When the power tube switch is about 0.75+/-0.15 MA, the power tube switch is turned off for the turn-off time T OFF About420us-580 us.
In summary, compared with the prior art, the invention has the following characteristics:
1. the design of the present invention shows less leakage current, less noise, higher photo-response sensitivity, and better compatible integration with other devices. The dark current of the structure is smaller than that of nanoampere culture (10 -9 A) Its advantages are less leakage current (1000 times than other structures), high sensitivity and response speed (less than 200 ns).
2. Has strong practicability. The device was fabricated and characterized, and both the doping concentration and the structural profile were characterized. The manufactured device is packaged together with a photosensitive diode and an MOS device and consists of an MOS relay driver, and the photodiode structure can be used for driving the MOS device and driving the output voltage V of the MOS device OUT Stable at 2V, fluctuation degree of + -0.06V, stable output voltage; switching time T ON About 141us with good switching times.
Example 3
The embodiment provides the double-layer SiO 2 A method of fabricating an isolated photodiode array, comprising: the substrate 100 is used as a connection layer,
a plurality of photodiodes 200 are formed on the connection layer,
providing a first passivation layer 300 and a second passivation layer 301;
a first metal connection port 401 and a second metal connection port 402 are provided, and adjacent photodiodes 200 are connected with the metal 400.
Further: the formation of the photodiode 200 includes:
a trapezoid groove is arranged on the substrate 100, and a silicon dioxide layer isolation layer 201 is arranged;
refilling the trapezoid groove with polysilicon through chemical physical deposition;
after the refilling, the polysilicon is subjected to N-type ion implantation to form an N region 203.
Specific:
an SOI substrate is used as a connecting layer, a photodiode array is formed on the connecting layer, each photodiode is arranged in an independent trapezoid groove, a silicon dioxide isolation layer is filled in the trapezoid groove, the groove is refilled with polysilicon through chemical physical deposition, N-type ion implantation is carried out after the refilling to form an N region, a first surface passivation layer is silicon dioxide, a second surface passivation layer is silicon dioxide doped with phosphorus, a second metal connection port 402 is formed in a P-type polysilicon semiconductor region, a first metal connection port 401 is formed in the first surface passivation layer and the second surface passivation layer in the N-type polysilicon semiconductor region, the photodiodes are respectively arranged in the independent trapezoid groove, and each photodiode is connected through an opening position metal to form the photodiode array.
The SOI substrate can be manufactured by bonding two silicon wafers with oxide layers grown on the silicon wafers, and bonding the two oxide layers to form a buried oxide layer.
Formation of the trapezoid groove: firstly, coating photoresist on a silicon wafer, irradiating the photoresist by ultraviolet rays through a mask, printing a pre-designed pattern on the mask, dissolving the photoresist exposed to the ultraviolet rays, and cleaning. And dissolving the exposed part by chemical substances, and cleaning the etching area without photoresist protection to obtain the trapezoid gully shape.
The silicon dioxide isolation layer is formed by thermally growing a thin and uniform silicon dioxide isolation layer on the side wall and the bottom of each trapezoid-shaped ravine. And filling polysilicon by groove CVD, and using chemical mechanical polishing to make the filling surface of the trapezoid groove flat.
N-type ion implantation is carried out at each groove position, annealing is carried out to ensure that the implanted ions are uniformly distributed, PN junctions are formed in each groove, photoresist is coated on the surface of a chip, ultraviolet rays are irradiated through a mask, photoresist patterns are left in P and N areas of each groove after the ultraviolet rays are removed, silicon dioxide is oxidized in other areas to form a first passivation film, phosphorus is added into the silicon dioxide, and a phosphosilicate glass layer is formed as a second passivation film. The photoresist is cleaned off. And sequentially connecting the opening positions reserved on each PN junction by using metal aluminum.
Finally, the device is manufactured, the manufactured device, the photodiode and the MOS device are packaged together, the device is composed of a MOS relay driver, and the photodiode structure can be used for driving the MOS device.
It is important to note that the construction and arrangement of the present application as shown in a variety of different exemplary embodiments is illustrative only. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be reversed or otherwise varied, and the nature or number of discrete elements or positions may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of present invention. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any means-plus-function clause is intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present inventions. Therefore, the invention is not limited to the specific embodiments, but extends to various modifications that nevertheless fall within the scope of the appended claims.
Furthermore, in an effort to provide a concise description of the exemplary embodiments, all features of an actual implementation may not be described (i.e., those not associated with the best mode presently contemplated for carrying out the invention, or those not associated with practicing the invention).
It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.
Claims (7)
1. Double-layer SiO 2 Isolated photodiode structure, characterized by: comprising the steps of (a) a step of,
a substrate (100), wherein a silicon dioxide insulating layer (101) is arranged in the substrate (100);
a photodiode (200), the photodiode (200) is arranged in the substrate (100), and a silicon dioxide isolation layer (201) is arranged outside the photodiode (200) and isolated from the substrate (100);
the substrate (100) further comprises a base (102) and an effective silicon layer (103), and the silicon dioxide insulating layer (101) is embedded between the base (102) and the effective silicon layer (103);
a trapezoid groove is formed in the effective silicon layer (103), and the silicon dioxide isolation layer (201) is paved on the inner surface layer of the trapezoid groove;
the photodiode (200) includes polysilicon (202) disposed inside the trapezoid trench and an N region (203) disposed on the polysilicon (202).
2. The bilayer SiO according to claim 1 2 Isolated photodiode structure, characterized by: a first passivation layer (300) covering the photodiode (200) is arranged on the effective silicon layer (103), and the first passivation layer (300) is silicon dioxide.
3. The bilayer SiO according to claim 2 2 Isolated photodiode structure, characterized by: a second passivation layer (301) is arranged on the first passivation layer (300), and the second passivation layer (301) is silicon dioxide doped with phosphorus.
4. Double-layer SiO 2 An isolated photodiode array characterized by: comprising a plurality of double-layer SiO as claimed in any of claims 1 to 3 2 The isolated photodiode structures share a substrate (100), and the photodiodes (200) are connected in series by metal (400).
5. The bilayer SiO according to claim 4 2 An isolated photodiode array characterized by: the N region (203) is provided with a first metal connection port (401), the polysilicon (202) is arranged on a second metal connection port (402), and the metal (400) is connected with the first metal connection port (401) of the photodiode (200) and the second metal connection port (402) of the adjacent photodiode (200).
6. A double-layer SiO as claimed in claim 4 or 5 2 A method of fabricating an isolated photodiode array, characterized by:
a substrate (100) is used as a connection layer,
a plurality of photodiodes (200) are formed on the connection layer,
providing a first passivation layer (300) and a second passivation layer (301);
a first metal connection port (401) and a second metal connection port (402) are provided, and adjacent photodiodes (200) are connected by a metal (400).
7. A bilayer SiO according to claim 6 2 A method of fabricating an isolated photodiode array, characterized by: the formation of the photodiode (200) includes:
a trapezoid groove is arranged on the substrate (100), and a silicon dioxide layer isolation layer (201) is arranged on the substrate;
the trapezoid groove is refilled with polysilicon through chemical physical deposition;
after the refilling, N-type ion implantation is performed on the polysilicon to form an N region (203).
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