CN115864503A - Fault ride-through system and method based on double-synchronous unified virtual oscillation controller - Google Patents
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Abstract
The invention relates to the technical field of a network-forming inverter, in particular to a fault ride-through system and a method based on a double-synchronous unified virtual oscillation controller, which comprises a double-sequence current reference generator, a double-synchronous unified virtual oscillation controller and a double-synchronous unified virtual oscillation controller, wherein the double-sequence current reference generator acquires a power reference value when a fault is detected, and determines a positive-sequence current reference value and a negative-sequence current reference value by combining the power reference value; the double-sequence vector limiter is connected with the double-sequence current reference generator to realize overcurrent limitation under symmetrical and asymmetrical faults and output limited positive and negative sequence saturated current reference values; the positive sequence space vector oscillator and the negative sequence space vector oscillator are both connected with the double-sequence vector limiter to realize double-sequence synchronous operation. The present invention can suppress over-current under both symmetric and asymmetric fault conditions, and combines enhanced synchronization capability with fast over-current limiting, providing voltage support and imbalance mitigation fault ride-through without switching to a back-end controller or current source type control.
Description
Technical Field
The invention relates to the technical field of a network-forming inverter, in particular to a fault ride-through system and a fault ride-through method based on a double-synchronous unified virtual oscillation controller.
Background
In recent years, with the widespread of power electronic inverters, the proportion of distributed power sources in a power distribution system is gradually increased, and a grid-structured inverter becomes a key technology for large-scale new energy to highly penetrate into the power system. The new energy source is changed from an additional-passive-network-following access type to a main-active-network-constructing support type, provides the support capability of the voltage and the frequency of a power grid, and becomes a main power supply. According to the safety and stability guide rule of the power system, various requirements such as power angle stability, frequency stability, voltage stability, transient overvoltage, multi-band oscillation and the like are provided for a new energy station, wherein the problem of fault ride-through related to voltage stability is a relatively mature method in a follow-up network access type, but a method for limiting overcurrent in a network construction support type still needs to be solved.
The external characteristic of the grid-structured inverter is equivalent to a voltage source, the grid voltage can be structured in transient response, the internal potential is kept constant, and therefore the grid-structured inverter has outstanding grid supporting capacity, such as voltage and frequency regulation and inertia support. But the disadvantage is that instantaneous overcurrent is very easily generated under fault conditions, so that hardware is tripped to avoid damage of the converter, and further the safe operation of a regional power grid is threatened. Traversing symmetric and asymmetric faults has remained one of the key challenges for grid-type inverters to date.
While early research on grid-connected inverters mainly focused on Virtual synchronous Control technology, the work focus on fault ride-through at low voltage is on balanced power Control or suppression of active power oscillation, such as switching Control strategy and Virtual impedance increase, currently in the context of weak power networks, research on grid-connected inverters mainly focuses on non-linear time domain controllers, such as Virtual Oscillator Control (VOC) and schedulable Virtual Oscillator Control (dcoc), which are designed to guarantee almost global synchronization in any N number of converter networks with zero inertia. Compared with droop control and virtual synchronous generator control, the nonlinear time domain controller greatly improves the synchronization speed. For the grid-structured inverter based on the oscillator control, symmetrical fault ride-through can be realized without switching a controller switch or adding dynamic virtual impedance, however, no compatible asymmetrical fault ride-through method is researched currently.
Disclosure of Invention
The invention provides a fault ride-through system and a fault ride-through method based on a double-synchronous unified virtual oscillation controller, which overcome the defects of the prior art and can effectively solve the problem that the conventional network-structured inverter cannot inhibit over-current in symmetric and asymmetric faults.
One of the technical schemes of the invention is realized by the following measures: a fault ride-through system based on a double-synchronous unified virtual oscillation controller comprises the double-synchronous unified virtual oscillation controller, an active resistor and a virtual impedance; the double-synchronous unified virtual oscillation controller comprises a double-sequence current reference generator, a double-sequence vector limiter, a positive-sequence space vector oscillator and a negative-sequence space vector oscillator;
the double-sequence current reference generator is used for acquiring a power reference value when a fault is detected and determining a positive sequence current reference value and a negative sequence current reference value by combining the power reference value;
the double-sequence vector limiter is connected with the double-sequence current reference generator to realize overcurrent limitation under symmetrical and asymmetrical faults and output limited positive and negative sequence saturated current reference values;
the positive sequence space vector oscillator and the negative sequence space vector oscillator are both connected with the double-sequence vector limiter to realize double-sequence synchronous operation;
the active resistor and the dummy impedance combine to quickly limit the overcurrent.
The following is further optimization or/and improvement of the technical scheme of the invention:
the double-sequence current reference generator calculates the positive sequence current reference value and the negative sequence current reference value by using the following formula;
the calculation formulas of the reference values of the double-sequence current are respectively as follows:
i 0+ ＝i α0+ +ji β0+
i 0- ＝i α0- +ji β0-
wherein, the positive sequence current calculation formula and the negative sequence current calculation formula under the alpha beta static coordinate system are respectively as follows:
wherein D is p ＝k p+ ||v + || 2 +k p- ||v - || 2 ，D q ＝k q+ ||v + || 2 +k q- ||v - || 2 。
The double-sequence vector limiter carries out overcurrent limitation under a symmetric and asymmetric fault, namely, a current reference vector is limited to be below a maximum value Im allowed by inverter hardware, wherein positive and negative sequence saturated current reference values after limitation are output, and the method comprises the following steps:
the current reference is limited to:
i 0 ＝{[i a0 i b0 i c0 ] T :max{I a0 ，I b0 ，I c0 }≤I m }
wherein the three-phase unsaturated current reference value is expressed as:
I x0 ＝[{||i 0+ || 2 +||i 0- || 2 +2(ξ 1 cos2γ-ξ 2 sin2γ)}/2] 1/2
wherein ξ 1 ＝(i α0+ i α0- -i β0+ i β0- )，ξ 2 ＝(i β0+ i α0- +i α0+ i β0- ) γ = {0, -2 π/3,2 π/3}, x is a, b, c, I max ＝max{I a0 ,I b0 ,I c0 }；
And combining the limited current reference values to obtain positive and negative sequence saturated current reference values:
[i 0+ i 0- ] T ＝k sat [i 0+ i 0- ] T ；k sat ＝I m /I max 。
the positive sequence space vector oscillator realizes positive sequence synchronous operation by using the following dynamic equation;
or/and the negative sequence space vector oscillator realizes the negative sequence synchronous operation by using the following dynamic equation;
the above further includes a power reference value setting unit that sets a power reference value set under a pre-failure condition.
The second technical scheme of the invention is realized by the following measures: a use method of a fault ride-through system based on a double-synchronous unified virtual oscillation controller comprises the following steps:
acquiring a power reference value after a fault is detected;
the double-sequence current reference generator determines a positive sequence current reference value, a negative sequence current reference value and an unbalance coefficient UF reflecting the voltage unbalance degree by combining the power reference value after the fault is detected, and prepares for overcurrent suppression and unbalanced voltage compensation;
the double-sequence vector limiter realizes overcurrent limitation under symmetrical and asymmetrical faults and outputs the limited positive and negative sequence saturated current reference values to the positive sequence space vector oscillator and the negative sequence space vector oscillator;
the positive sequence space vector oscillator and the negative sequence space vector oscillator receive the limited positive sequence saturated current reference value and negative sequence saturated current reference value, and the dynamic equation of internal control is utilized to realize double-sequence synchronous operation.
The fault ride-through system based on the double-synchronous unified virtual oscillation controller is constructed by utilizing the double-sequence current reference generator, the double-sequence vector limiter, the positive-sequence space vector oscillator and the negative-sequence space vector oscillator, so that overcurrent can be inhibited under symmetrical or asymmetrical fault conditions, the enhanced synchronization capacity is combined with the rapid overcurrent limitation, and the fault ride-through of voltage support and unbalance mitigation is provided without switching to a back controller or current source type control.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention.
Fig. 2 is an explanatory diagram of the mode switching signal xr generated by the controller failure signal xf of the present invention.
Fig. 3 is a power synchronization diagram of the positive sequence space vector oscillator of the present invention.
Fig. 4 is a power synchronization diagram of the negative sequence space vector oscillator of the present invention.
FIG. 5 is a schematic flow diagram of the process of the present invention.
Detailed Description
The present invention is not limited by the following examples, and specific embodiments may be determined according to the technical solutions and practical situations of the present invention.
The invention is further described with reference to the following examples and figures:
example 1: as shown in fig. 1, the embodiment of the invention discloses a fault ride-through system based on a double-synchronous unified virtual oscillation controller, which comprises the double-synchronous unified virtual oscillation controller, an active resistor and a virtual impedance; the double-synchronous unified virtual oscillation controller comprises a double-sequence current reference generator, a double-sequence vector limiter, a positive-sequence space vector oscillator and a negative-sequence space vector oscillator;
the double-sequence current reference generator is used for acquiring a power reference value when a fault is detected and determining a positive sequence current reference value and a negative sequence current reference value by combining the power reference value;
the double-sequence vector limiter is connected with the double-sequence current reference generator to realize overcurrent limitation under symmetrical and asymmetrical faults and output limited positive and negative sequence saturated current reference values;
the positive sequence space vector oscillator and the negative sequence space vector oscillator are both connected with the double-sequence vector limiter to realize double-sequence synchronous operation;
the active resistor and the dummy impedance combine to quickly limit the over-current.
The above further includes a power reference value setting unit that sets a power reference value when the fault is detected.
The fault ride-through system based on the double-synchronous unified virtual oscillation controller is constructed by utilizing the double-sequence current reference generator, the double-sequence vector limiter, the positive-sequence space vector oscillator and the negative-sequence space vector oscillator, so that overcurrent can be inhibited under symmetrical or asymmetrical fault conditions, the enhanced synchronization capacity is combined with the rapid overcurrent limitation, and the fault ride-through of voltage support and unbalance mitigation is provided without switching to a back controller or current source type control.
Example 2: as shown in fig. 1 to 4, an embodiment of the present invention discloses a fault ride-through system based on a dual-synchronous unified virtual oscillation controller, which includes a dual-synchronous unified virtual oscillation controller, an active resistor and a virtual impedance; the double-synchronous unified virtual oscillation controller comprises a double-sequence current reference generator, a double-sequence vector limiter, a positive-sequence space vector oscillator and a negative-sequence space vector oscillator;
(1) The double-sequence current reference generator is used for acquiring a power reference value when a fault is detected and determining a positive sequence current reference value and a negative sequence current reference value by combining the power reference value;
the dual-sequence current reference generator is used for calculating current reference values under a static reference frame, and for a given set of active power reference values P 0 And a reactive power reference value Q 0 The positive sequence reference current value and the negative sequence reference current value fed into the double-sequence vector limiter are calculated through a dynamic equation of positive sequence voltage and negative sequence voltage inside the double-sequence current reference generator, compared with symmetric fault ride-through, power flows in two sequences in the operation of the asymmetric fault ride-through are mutually coupled, so that the calculation of the current reference values is more complex, and the calculation formulas of the double-sequence current reference values are respectively as follows:
i 0+ ＝i α0+ +ji β0+
i 0- ＝i α0- +ji β0-
further, the positive sequence current calculation formula and the negative sequence current calculation formula under the alpha beta static coordinate system are respectively as follows:
wherein D is p ＝k p+ ||v + || 2 +k p- ||v - || 2 ，D q ＝k q+ ||v + || 2 +k q- ||v - || 2 By appropriate selection of k p+ 、k p- 、k q+ And k q- Different control objectives can be achieved, where | () | represents the euclidean norm in the form of an operation
The obtaining of the power reference values (active power reference value and reactive power reference value) when the fault is detected is to set the power reference values before the fault, and once the fault is detected, the reactive power reference value Q is obtained 0 Is arranged as
The dynamic equation of the positive and negative sequence voltages in the double-sequence current reference generator can calculate the positive and negative sequence reference current values fed into the double-sequence vector limiter and an unbalance coefficient UF reflecting the voltage unbalance degree, and provides for the next overcurrent suppression and unbalanced voltage compensation.
(2) The double-sequence vector limiter is connected with the double-sequence current reference generator to realize overcurrent limitation under symmetrical and asymmetrical faults and output limited positive and negative sequence saturated current reference values;
the double-sequence vector limiter is used for limiting the current reference vector to be below the maximum value Im allowed by inverter hardware so as to prevent the overcurrent output by the inverter during fault, and the current reference value after passing through the double-sequence vector limiter is limited as follows:
i 0 ＝{[i a0 i b0 i c0 ] T :max{I a0 ，I b0 ，I c0 }≤I m }
wherein the three-phase unsaturated current reference value is expressed as:
I x0 ＝[{||i 0+ || 2 +||i 0- || 2 +2(ξ 1 cos2γ-ξ 2 sin2γ)}/2] 1/2
in which ξ 1 ＝(i α0+ i α0- -i β0+ i β0- )，ξ 2 ＝(i β0+ i α0- +i α0+ i β0- ) γ = {0, -2 π/3,2 π/3}, x is a, b, c.
Next, positive and negative sequence saturated current reference values are obtained:
[i 0+ i 0- ] T ＝k sat [i 0+ i 0- ] T ；k sat ＝I m /I max
wherein, I m ＝max{I a0 ,I b0 ,I c0 }。
The dual-sequence vector limiter shown in fig. 1 is applicable to both symmetric and asymmetric fault conditions, and the unbalanced degree of the grid-connected point voltage is characterized by an unbalanced coefficient (UF), which is defined as UF = | | v g- ||/||v g+ I | Vg is the voltage of the network side, and when the voltage of the network is balanced or symmetrical, the negative sequence current reference value i of the controller 0- =0, once overcurrent is detected in any phase or voltage imbalance is detected to exceed a threshold (UF)>K UF ) The fault signal is locked, i.e. x f =1, when the positive sequence voltage returns to within the specified range and UF is below the threshold (UF)<K UF ) Then the fault is cleared, i.e. x f And =0. In addition, by applying a fault signal x f Followed by a falling ramp to generate a mode switching signal x r Time of ramp down t F Providing a smooth transition period when the fault clears.
(3) The positive sequence space vector oscillator and the negative sequence space vector oscillator are both connected with the double-sequence vector limiter to realize double-sequence synchronous operation;
the positive sequence space vector oscillator is used for synchronization when new energy is connected to the power grid, any low voltage of the power grid is limited by rapid overcurrent, and effective fault ride-through can be realized without switching an inverter controlled by the oscillator to a standby controller during a fault period. The positive sequence space vector oscillator is realized according to a standard virtual oscillator (uVOC) control rule applied to a network-forming inverter, and a dynamic equation of internal control can be described as follows:
wherein a positive sequence current component of the inverter output current is decomposed into i in a stationary alpha beta reference frame + ＝i α+ +ji β+ I α +, i β + are expressed as:
i α+ ＝0.5(i α -i β⊥ )，i β+ ＝0.5(i β +i α⊥ )
where (·) ″) represents a quadrature signal obtained by delaying an original signal by T0/4, T0 is a fundamental period, η + and μ + are used for the amplitude correction gain of the positive sequence SVO, and the expression is:
η + ＝(1+x r /τ f )η 0 ，μ + ＝(1-x r )μ 0
the SVO parameters η 0, μ 0 are typically selected based on the rated capacity of the power system and the desired steady state response, and are calculated with specific reference to the derivation process in the design guidelines, the parameters τ f The stabilization time is controlled.
The virtual oscillator realizes power synchronization with a power grid through droop response of power-frequency, a unified virtual oscillation controller in the prior research adopts pure sequence configuration, a negative sequence SVO is added, and in order to deduce a synchronization mechanism of the negative sequence SVO, the working principle of the positive sequence space vector oscillator for realizing power synchronization is reviewed firstlyOrder k p+ ＝1，k p- ＝0，k q+ ＝1，k q- =0, excluding negative-sequence SVO and double-sequence vector limiters on the current reference generator, the dynamic equations can be rearranged as:
wherein,
P + +jQ + ＝v + i' + ，P 0+ +jQ 0+ ＝v + i' 0+
where (') denotes the complex conjugate of the complex vector, a graphical representation of SVO dynamics given by the rearranged dynamic equations is shown in FIG. 3, where v is g+ As a grid voltage vector, e i+ As a current error, e i+ ＝i 0+ -i + The real and imaginary parts of the V + complex coefficients in the rearranged dynamic equation represent the instantaneous frequency ω + and the normalized rate of change of the instantaneous vector magnitude (1/V), respectively + )d(V + )/d t Wherein
Obviously, the active power-frequency P of the analog synchronous generator is observed along the synchronous q + and d + axes on the SVO output voltage vector respectively + -ω + Reactive power-voltage Q + -V + 2 The droop characteristic transient droop response helps power to synchronize to a positive sequence grid voltage vector vg +, and the synchronization mechanism is as follows.
And the negative sequence space vector oscillator is used for providing overcurrent limitation and power grid support under the unbalanced fault. The positive sequence SVO is rotated counter-clockwise,clockwise component η of synchronous feedback term + e iP+ v + With counter-clockwise rotation of the resonator term η + e iP+ v + In contrast, the amplitude correction term μ + e v+ v + With the radial component- η of the synchronous feedback term + e iQ+ v + Instead (see fig. 3), these terms achieve a relative balance of stable operation in the radial and tangential directions. To ensure stable balance of the negative sequence SVO rotating clockwise, the harmonic oscillator term and the synchronization feedback term are opposite in sign and are implemented as
In the formula, the synchronization and amplitude correction gain eta-/mu-of the negative sequence SVO is consistent with the positive sequence SVO; the negative sequence current component, defined as the inverter output current, is decomposed into i in the stationary α β reference frame - ＝i α- +ji β- ，i α- 、i β- Expressed as:
i α- ＝0.5(i α +i β⊥ )，i β- ＝0.5(i β -i α⊥ )
the working principle of power synchronization is realized by referring to the positive sequence space vector oscillator, and the synchronization capability of the negative sequence SVO under the condition of asymmetric grid voltage without limitation on current amplitude is deduced. First, the positive sequence SVO is eliminated, and k is taken p+ ＝0，k p- ＝1，k q+ ＝0，k q- =1, the negative sequence SVO dynamics of the above equation of dynamics may be rearranged as:
wherein,
P - +jQ - ＝v - i' - ，P 0- +jQ 0- ＝v - i' 0-
for any negative sequence source voltage vector v g- Current error e i- Graphical representation of SVO dynamics in a negative sequence synchronous framework corresponding to v-As shown in FIG. 4, the dynamics along the q-and d-axes define the transient P, respectively --ω- And Q - -V - 2 Droop response, two series droop responses contributing to the negative sequence grid voltage vector v g- Synchronization, which can be expressed as:
during a fault event, the current limiter will force current limited operation to protect the converter. Next, a further discussion of the dual sequence synchronization with current constraint is presented. Firstly, a given total power reference P0 and Q0 is split into sequence reference power, and the expression is as follows:
in conjunction with positive and negative sequence current references, and considering a double sequence vector limiter, the positive and negative sequence droop responses during current limited operation can be derived as:
from the above equation, during current limited operation, P- ω and Q-V in two sequences 2 The droop response is not affected, the output current can only be kept within the limit range if the power reference is scaled, the coupling between the two sequences is reflected in the power reference, and therefore the proposed controller is capable of performing double synchronization operation simultaneously.
(4) The active resistor and the dummy impedance combine to quickly limit the overcurrent.
Active resistor R 0 For fast overcurrent limiting in fault conditions. The virtual impedance Zv(s) is composed of a virtual resistor Rv and a virtual inductor Lv, and the expression is as follows:
the virtual resistor Rv is used for enhancing system damping, the virtual inductor Lv is used for rapidly limiting overcurrent at fault moment, and the resonant filter Σ Z h (s) for suppressing harmonic currents.
Example 5: as shown in fig. 5, the embodiment of the present invention discloses a method for using a fault ride-through system based on a double synchronous unified virtual oscillation controller, which comprises:
step S101, acquiring a power reference value after a fault is detected;
where a power reference is set before a fault and upon detection of a fault, a reactive power reference Q 0 Is arranged as
Step S102, the double-sequence current reference generator determines a positive sequence current reference value, a negative sequence current reference value and an unbalance coefficient UF reflecting the voltage unbalance degree by combining the power reference value after the fault is detected, and preparation is made for overcurrent suppression and unbalanced voltage compensation; as shown in FIG. 2, when a voltage imbalance exceeding a threshold value (UF) is detected in any phase>KUF), the fault signal is locked, i.e., x f =1, when UF is below thresholdValue (UF)<KUF), the fault is cleared, i.e., x f And the mode conversion signal is multiplied by the active resistor and is connected to the output signal, so that two functions of quickly limiting the overcurrent and compensating the voltage unbalance can be realized.
Step S103, the double-sequence vector limiter realizes overcurrent limitation under symmetrical and asymmetrical faults and outputs the limited positive and negative sequence saturated current reference values to the positive sequence space vector oscillator and the negative sequence space vector oscillator;
and step S104, the positive sequence space vector oscillator and the negative sequence space vector oscillator receive the limited positive sequence saturated current reference value and negative sequence saturated current reference value, and the double-sequence synchronous operation is realized by utilizing a dynamic equation of internal control. Thus, fault ride-through for symmetric and asymmetric short circuit faults is better achieved through the combination of enhanced synchronization capability and fast overcurrent limiting.
The technical characteristics form the best embodiment of the invention, the best embodiment has stronger adaptability and best implementation effect, and unnecessary technical characteristics can be increased or decreased according to actual needs to meet the requirements of different situations.
Claims (7)
1. A fault ride-through system based on a double-synchronous unified virtual oscillation controller is characterized by comprising the double-synchronous unified virtual oscillation controller, an active resistor and a virtual impedance; the double-synchronous unified virtual oscillation controller comprises a double-sequence current reference generator, a double-sequence vector limiter, a positive-sequence space vector oscillator and a negative-sequence space vector oscillator;
the double-sequence current reference generator is used for acquiring a power reference value when a fault is detected and determining a positive sequence current reference value and a negative sequence current reference value by combining the power reference value;
the double-sequence vector limiter is connected with the double-sequence current reference generator to realize overcurrent limitation under symmetrical and asymmetrical faults and output limited positive and negative sequence saturated current reference values;
the positive sequence space vector oscillator and the negative sequence space vector oscillator are both connected with the double-sequence vector limiter to realize double-sequence synchronous operation;
the active resistor and the dummy impedance combine to quickly limit the overcurrent.
2. The dual synchronous unified virtual oscillation controller based fault ride-through system of claim 1, wherein the dual sequence current reference generator calculates positive and negative sequence current reference values using the following equation;
the calculation formula of the reference value of the double-sequence current is respectively as follows:
i 0+ ＝i α0+ +ji β0+
i 0- ＝i α0- +ji β0
wherein, the positive sequence current calculation formula and the negative sequence current calculation formula under the alpha beta static coordinate system are respectively as follows:
wherein D is p ＝k p+ ||v + || 2 +k p- ||v - || 2 ，D q ＝k q+ ||v + || 2 +k q- ||v - || 2 。
3. The double-synchronous unified virtual oscillation controller based fault ride-through system according to claim 1 or 2, wherein the double-sequence vector limiter performs overcurrent limiting under a symmetric and asymmetric fault, namely limiting a current reference vector to be below a maximum value Im allowed by inverter hardware, wherein the output of the limited positive and negative sequence saturated current reference values comprises:
the current reference is limited to:
i 0 ＝{[i a0 i b0 i c0 ] T :max{I a0 ，I b0 ，I c0 }≤I m }
wherein the three-phase unsaturated current reference value is expressed as:
I x0 ＝[{||i 0+ || 2 +||i 0- || 2 +2(ξ 1 cos2γ-ξ 2 sin2γ)}/2] 1/2
wherein ξ 1 ＝(i α0+ i α0- -i β0+ i β0- )，ξ 2 ＝(i β0+ i α0- +i α0+ i β0- ) γ = {0, -2 π/3,2 π/3}, x is a, b, c, I max ＝max{I a0 ,I b0 ,I c0 }；
And combining the limited current reference values to obtain positive and negative sequence saturated current reference values:
[i 0+ i 0- ] T ＝k sat [i 0+ i 0- ] T ；k sat ＝I m /I max 。
4. the fault ride-through system based on the double-synchronous unified virtual oscillator controller according to claim 1 or 2, wherein the positive sequence space vector oscillator implements positive sequence synchronous operation by using the following dynamic equation;
or/and the negative sequence space vector oscillator realizes the negative sequence synchronous operation by using the following dynamic equation;
5. the double-synchronous unified virtual oscillation controller based fault ride-through system of claim 3, wherein the positive sequence space vector oscillator implements positive sequence synchronous operation by using the following dynamic equation;
or/and the negative sequence space vector oscillator realizes the negative sequence synchronous operation by using the following dynamic equation;
6. the double-synchronous unified virtual oscillation controller based fault ride-through system according to any one of claims 1 to 5, further comprising a power reference value setting unit for setting a power reference value set under a pre-fault condition.
7. A method for using the fault ride-through system based on the double synchronous unified virtual oscillation controller according to any one of claims 1 to 6, comprising:
acquiring a power reference value after a fault is detected;
the double-sequence current reference generator determines a positive sequence current reference value, a negative sequence current reference value and an unbalance coefficient UF reflecting the voltage unbalance degree by combining the power reference value after the fault is detected, and prepares for overcurrent suppression and unbalanced voltage compensation;
the double-sequence vector limiter realizes overcurrent limitation under symmetrical and asymmetrical faults and outputs the limited positive and negative sequence saturated current reference values to the positive sequence space vector oscillator and the negative sequence space vector oscillator;
the positive sequence space vector oscillator and the negative sequence space vector oscillator receive the limited positive sequence saturated current reference value and negative sequence saturated current reference value, and the dynamic equation of internal control is utilized to realize double-sequence synchronous operation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116742661A (en) * | 2023-08-14 | 2023-09-12 | 国网山西省电力公司临汾供电公司 | Three-phase unbalance treatment device based on three-sagging control |
| CN116742661B (en) * | 2023-08-14 | 2023-10-27 | 国网山西省电力公司临汾供电公司 | Three-phase unbalance treatment device based on three-phase sagging control |
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