CN115800999B - Phase-locked loop system and chip - Google Patents
Phase-locked loop system and chip Download PDFInfo
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- CN115800999B CN115800999B CN202211429288.5A CN202211429288A CN115800999B CN 115800999 B CN115800999 B CN 115800999B CN 202211429288 A CN202211429288 A CN 202211429288A CN 115800999 B CN115800999 B CN 115800999B
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Abstract
The invention discloses a phase-locked loop system and a chip, the phase-locked loop system comprises: a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a multi-modulus divider, a delta sigma modulator, and a controller. According to the phase-locked loop system and the chip, the controller is used for generating the first control signal with the duty ratio changing along with the change of the frequency division ratio of the multi-mode frequency divider based on the first frequency division clock signal generated by the multi-mode frequency divider, and the current unit is adjusted through the first control signal to adaptively adjust the magnitude of the bias current, so that the adaptive adjustment of the linearity of the charge pump is realized, and when the phase-locked loop with broadband output is applied, the linearity of the charge pump can be automatically calibrated to an optimal effect for all frequency output.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a phase locked loop system and a chip.
Background
The charge pump is a core submodule of the phase-locked loop system, and its performance has a great influence on the performance of the whole phase-locked loop. The charge pump mainly functions to convert the phase difference value of an input clock into electric charge and transmit the electric charge to the loop filter, so that the control of the tuning voltage of the voltage-controlled oscillator is realized. For a charge pump, two of our most interesting indicators are noise and linearity, where the nonlinearity of the charge pump can cause noise folding of the delta-sigma modulator (DSM), degrading noise at low frequencies of the phase-locked loop output; and meanwhile, fractional spurious and migration spurious are deteriorated, and the performance of the phase-locked loop is obviously affected.
The more common method for improving the linearity of the charge pump is to introduce a static bias current into the output end of the charge pump, and introduce an adjustable bias current to the power supply or to the ground, so that when the phase-locked loop enters a locked steady state, the output end of the phase-frequency detector can generate a static phase difference delta t0, and the static phase difference can be changed by adjusting the magnitude of the bias current so as to improve the linearity of the charge pump.
For a wide frequency output phase locked loop, the frequency division ratio varies relatively much with the same reference clock, and the required offset current varies relatively much. The conventional method needs to manually configure the bias current, is inconvenient to operate (especially when applied to wide frequency sweeping and the like), and cannot ensure that the bias current can reach an optimal value under all frequency dividing ratios.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a phase-locked loop system and a chip, which can automatically adjust bias current under different frequency division ratios so as to reduce nonlinearity of a charge pump.
To achieve the above object, an embodiment of the present invention provides a phase locked loop system including: a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a multi-modulus divider, a delta sigma modulator, and a controller.
The phase frequency detector is used for comparing a reference signal with a first frequency division clock signal generated by the multi-mode frequency divider in phase to output a phase difference signal; the charge pump is used for converting a phase difference signal into a current signal, and a current unit for providing bias current is connected between the output end of the charge pump and a power supply voltage and/or between the output end of the charge pump and a ground voltage; the loop filter is used for integrating and filtering the current signal to output a control voltage signal; the voltage-controlled oscillator is used for outputting an oscillating signal with adjustable frequency based on the control voltage signal; the multi-mode frequency divider is used for dividing the frequency of the oscillation signal to output a first frequency division clock signal; the delta-sigma modulator is used for adjusting the frequency division ratio of the multi-modulus frequency divider; the controller is used for generating a first control signal with the duty ratio changing along with the change of the frequency division ratio of the multi-mode frequency divider based on the first frequency division clock signal, and adjusting the current unit through the first control signal to adaptively adjust the magnitude of the bias current.
In one or more embodiments of the present invention, the phase-locked loop system further includes a frequency divider for dividing the oscillation signal to output a second divided clock signal, and the controller is configured to generate a second control signal having a duty ratio varying with a division ratio of the frequency divider based on the second divided clock signal, and adjust the current unit to adaptively adjust the magnitude of the bias current by the second control signal.
In one or more embodiments of the invention, the phase-locked loop system further comprises a selector, a first input of the selector being coupled to the multi-modulus divider, a second input of the selector being coupled to the divider, and an output of the selector being coupled to the controller.
In one or more embodiments of the invention, the current cell includes a first current cell disposed between an output of the charge pump and a supply voltage for providing a first bias current and/or a second current cell disposed between the output of the charge pump and a ground voltage for providing a second bias current.
In one or more embodiments of the invention, the first current cell comprises a first controllable current source and the second current cell comprises a second controllable current source.
In one or more embodiments of the invention, the phase locked loop system further comprises a register coupled to the controller.
In one or more embodiments of the invention, the controller is a logic controller.
In one or more embodiments of the invention, the divide ratio of the multi-modulus divider and the divider is the same.
In one or more embodiments of the present invention, the bias current provided by the current unit isWherein I cp is the output current of the charge pump, x is the proportional relationship between the duty cycle of the first control signal and the frequency division ratio of the multi-mode frequency divider or the proportional relationship between the duty cycle of the second control signal and the frequency division ratio of the frequency divider.
The invention also discloses a chip comprising the phase-locked loop system.
Compared with the prior art, according to the phase-locked loop system of the embodiment, the controller generates the first control signal with the duty ratio changing along with the change of the frequency division ratio of the multi-mode frequency divider based on the first frequency division clock signal generated by the multi-mode frequency divider, and the current unit is adjusted through the first control signal to adaptively adjust the magnitude of the bias current, so that the adaptive adjustment of the linearity of the charge pump is realized, and when the phase-locked loop system with broadband output is applied, the linearity of the charge pump can be automatically calibrated to an optimal effect for all frequency outputs.
Drawings
Fig. 1 is a first circuit schematic of a phase locked loop system according to an embodiment of the invention.
Fig. 2 is a second circuit schematic of a phase locked loop system according to an embodiment of the invention.
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" or "connected to" another element, or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
The invention will be further described with reference to the drawings and examples.
As shown in fig. 1, a phase locked loop system includes: a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a multi-modulus divider, a delta sigma modulator, and a controller.
The frequency and phase discriminator is used for comparing the phase of a reference signal Fref with the phase of a first frequency division clock signal generated by the multi-mode frequency divider to output a phase difference signal; the charge pump is used for converting the phase difference signal into a current signal; the loop filter is used for integrating and filtering the current signal to output a control voltage signal; the voltage-controlled oscillator is used for outputting an oscillating signal with adjustable frequency based on the control voltage signal; the multi-mode frequency divider is used for dividing the frequency of the oscillation signal to output a first frequency division clock signal; delta-sigma modulators are used to adjust the divide ratio of a multi-modulus divider.
A current unit for providing bias current is connected between the output end of the charge pump and the power supply voltage and/or between the output end of the charge pump and the ground voltage. In this embodiment, a first current unit 11 for providing a first bias current I OFFSET1 is connected between the output terminal of the charge pump and the power supply voltage, and a second current unit 12 for providing a second bias current I OFFSET2 is connected between the output terminal of the charge pump and the ground voltage. The first current unit 11 comprises a first controllable current source A1, the first controllable current source A1 generating a first bias current I OFFSET1. The second current unit 12 includes a second controllable current source A2, and the second controllable current source A2 generates a second bias current I OFFSET2.
In other embodiments, one of the first current cell 11 and the second current cell 12 may be selected for setting.
The controller is used for generating a first control signal with the duty ratio changing along with the change of the frequency division ratio of the multi-mode frequency divider based on a first frequency division clock signal generated by the multi-mode frequency divider, and adjusting the first controllable current source A1 or the second controllable current source A2 through the first control signal to adaptively adjust the magnitude of the first bias current I OFFSET1 or the second bias current I OFFSET2.
In this embodiment, the controller is connected to the register I OFFSET_CTRL<n:0> at the same time, and the first control signal can be generated by the combination of the register I OFFSET_CTRL<n:0> and the controller to adjust the duty ratio of the first bias current I OFFSET1 or the second bias current I OFFSET2.
In the present embodiment of the present invention,Let α=x/N div, thenWherein I cp is the output current of the charge pump, Δt 0 is the phase difference of the output of the phase frequency detector, T ref is the reference clock period, α is the duty cycle of the first control signal, N div is the frequency division ratio of the multi-mode frequency divider, and x is the proportional relationship between the duty cycle of the first control signal and the frequency division ratio of the multi-mode frequency divider.
For a certain initial frequency division ratio of the multi-mode frequency divider, the first bias current I OFFSET1 or the second bias current I OFFSET2 is adjusted to a fixed value by adjusting the register I OFFSET_CTRL<n:0> to enable the controller to output a first control signal; then the frequency dividing ratio of the multi-mode frequency divider is changed according to the requirement, the duty ratio of the first control signal is also changed along with the different frequency dividing ratios of the multi-mode frequency divider, and the first control signal is used for adjusting the conduction time of the first controllable current source A1 or the second controllable current source A2, so that the automatic adjustment of the first bias current I OFFSET1 or the second bias current I OFFSET2 introduced into the charge pump can be completed. The controller is a logic controller, and the duty ratio of the first bias current I OFFSET1 or the second bias current I OFFSET2 can be adjusted by outputting the first control signal through the combinational logic, so that the first bias current I OFFSET1 or the second bias current I OFFSET2 can be accurately adjusted, and the linearity of the charge pump can be optimized.
In addition, as shown in fig. 2, the phase-locked loop system in the present embodiment further includes a frequency divider and a selector. The frequency divider is used for dividing the oscillating signal output by the voltage-controlled oscillator and outputting a second frequency division clock signal. The first input end of the selector is connected with the multi-mode frequency divider, the second input end of the selector is connected with the frequency divider, the output end of the selector is connected with the controller, and the second frequency division clock signal output by the frequency divider or the first frequency division clock signal output by the multi-mode frequency divider can be selected to the controller through the selector.
In some practical applications, in order to optimize the noise of the multi-modulus divider in the pll system, the output of the multi-modulus divider is processed to affect the duty ratio of the first divided clock signal output by the multi-modulus divider, at this time, the first divided clock signal generated by processing the output of the multi-modulus divider cannot be accurately adjusted by using the first divided clock signal to the first bias current I OFFSET1 or the second bias current I OFFSET2, so that the degree of freedom of the multi-modulus divider is limited by considering its own noise and other factors.
Thus, in this embodiment, the frequency divider is provided, the frequency division ratio of the multi-modulus frequency divider and the frequency divider is the same, and the selector may select the frequency divider in some applications where it is desirable to optimize the noise of the multi-modulus frequency divider itself in the phase-locked loop system. If the selector selects the second divided clock signal output by the frequency divider to the controller, the controller generates a second control signal with a duty ratio varying with the divided ratio of the frequency divider based on the second divided clock signal, and adjusts the first controllable current source A1 or the second controllable current source A2 by the second control signal to adaptively adjust the magnitude of the first bias current I OFFSET1 or the second bias current I OFFSET2.
The above formula: and x is the proportional relation between the duty ratio of the second control signal and the frequency dividing ratio of the frequency divider.
For a certain initial frequency division ratio of the frequency divider, the controller outputs a second control signal by adjusting the register I OFFSET_CTRL<n:0>, so that the first bias current I OFFSET1 or the second bias current I OFFSET2 is adjusted to be a fixed value; then changing the frequency dividing ratio of the multi-mode frequency divider and the frequency divider according to the requirement, aiming at different frequency dividing ratios of the multi-mode frequency divider and the frequency divider, the duty ratio of the second control signal can be changed, and the second control signal is used for adjusting the conduction time of the first controllable current source A1 or the second controllable current source A2, so that the automatic adjustment of the first bias current I OFFSET1 or the second bias current I OFFSET2 introduced into the charge pump can be completed. The controller is a logic controller, and the duty ratio of the first bias current I OFFSET1 or the second bias current I OFFSET2 can be adjusted by outputting the second control signal through the combinational logic, so that the first bias current I OFFSET1 or the second bias current I OFFSET2 can be accurately adjusted, and the linearity of the charge pump can be optimized.
The invention also discloses a chip comprising the phase-locked loop system.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (5)
1. A phase locked loop system, comprising:
The phase frequency detector is used for comparing a reference signal with a first frequency division clock signal generated by the multi-mode frequency divider in phase to output a phase difference signal;
The charge pump is used for converting the phase difference signal into a current signal, and a current unit for providing bias current is connected between the output end of the charge pump and the power supply voltage and/or between the output end of the charge pump and the ground voltage;
The current unit comprises a first current unit arranged between the output end of the charge pump and the power supply voltage and used for providing a first bias current and/or a second current unit arranged between the output end of the charge pump and the ground voltage and used for providing a second bias current;
A loop filter for integrating and filtering the current signal to output a control voltage signal;
A voltage-controlled oscillator for outputting an oscillating signal with an adjustable frequency based on the control voltage signal;
A multi-modulus divider for dividing the oscillation signal to output a first divided clock signal; and a delta-sigma modulator for adjusting a divide ratio of the multi-modulus divider;
The phase-locked loop system further comprises a controller, wherein the controller is used for generating a first control signal with the duty ratio changing along with the change of the frequency division ratio of the multi-mode frequency divider based on the first frequency division clock signal, and adjusting the current unit through the first control signal so as to adaptively adjust the magnitude of the bias current;
the bias current provided by the current unit is Wherein I cp is the output current of the charge pump, x is the product of the duty cycle of the first control signal and the frequency division ratio of the multi-mode frequency divider;
The phase-locked loop system further comprises a frequency divider and a selector, wherein a first input end of the selector is connected with the multi-mode frequency divider, a second input end of the selector is connected with the frequency divider, an output end of the selector is connected with the controller, the frequency division ratios of the multi-mode frequency divider and the frequency divider are the same, the frequency divider is used for dividing an oscillating signal to output a second divided clock signal, the controller is used for generating a second control signal with a duty ratio changing along with the frequency division ratio of the frequency divider based on the second divided clock signal, and the current unit is adjusted through the second control signal to adaptively adjust the magnitude of the bias current, and the bias current provided by the current unit is that Wherein I cp is the output current of the charge pump, and x is the product of the duty cycle of the second control signal and the frequency division ratio of the frequency divider.
2. The phase-locked loop system of claim 1, wherein the first current cell comprises a first controllable current source and the second current cell comprises a second controllable current source.
3. The phase-locked loop system of claim 1, further comprising a register coupled to the controller.
4. The phase-locked loop system of claim 1, wherein the controller is a logic controller.
5. A chip comprising a phase locked loop system as claimed in any one of claims 1 to 4.
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| CN202211429288.5A CN115800999B (en) | 2022-11-15 | 2022-11-15 | Phase-locked loop system and chip |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944909A (en) * | 2009-07-10 | 2011-01-12 | 智迈微电子科技(上海)有限公司 | Phase frequency detector and charge pump circuit for phase locked loop |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FR2869173B1 (en) * | 2004-04-20 | 2006-10-20 | St Microelectronics Sa | PHASE LOCKED LOOP AND METHOD OF CONTROLLING AN OSCILLATOR OF SAID PHASE LOCKED LOOP |
| US7548123B2 (en) * | 2007-07-13 | 2009-06-16 | Silicon Laboratories Inc. | Dividerless PLL architecture |
| CN204425319U (en) * | 2015-03-26 | 2015-06-24 | 成都爱洁隆信息技术有限公司 | The fractional frequency division frequency synthesizer with charge pump linearization technique is compensated with DAC |
| CN105634475B (en) * | 2015-12-24 | 2018-10-30 | 西安电子科技大学 | A kind of charge pump ring-oscillating phase-locking ring |
| CN107634759B (en) * | 2017-09-15 | 2020-07-28 | 北京华大九天软件有限公司 | Phase-locked loop circuit capable of adapting to loop bandwidth |
| US10615809B2 (en) * | 2017-09-28 | 2020-04-07 | Stmicroelectronics International N.V. | Calibration of a voltage controlled oscillator to trim the gain thereof, using a phase locked loop and a frequency locked loop |
| CN113541681B (en) * | 2021-06-08 | 2023-03-14 | 西安电子科技大学 | Automatic current calibration charge pump circuit applied to dual-path phase-locked loop |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944909A (en) * | 2009-07-10 | 2011-01-12 | 智迈微电子科技(上海)有限公司 | Phase frequency detector and charge pump circuit for phase locked loop |
| CN102970031A (en) * | 2012-11-05 | 2013-03-13 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer and method for keeping bandwidth of frequency synthesizer loop to be stable |
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