CN115763543A - Composite shielded gate field effect transistor - Google Patents
Composite shielded gate field effect transistor Download PDFInfo
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- CN115763543A CN115763543A CN202310024068.2A CN202310024068A CN115763543A CN 115763543 A CN115763543 A CN 115763543A CN 202310024068 A CN202310024068 A CN 202310024068A CN 115763543 A CN115763543 A CN 115763543A
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Abstract
The invention relates to the technical field of semiconductors, and discloses a composite shielded gate field effect transistor, which comprises: a number of electrode structures, each electrode structure comprising: the grid electrode, the shielding grid and the first source electrode contact layer; the shielding grids are arranged in sections through the grooves; the grid electrode is arranged above the shielding grid; the first source electrode contact layer is arranged above each section of shielding grid, the grid electrode comprises a groove end arranged in the groove and a first side end and a second side end which are arranged outside the groove, the first side end and the second side end are both connected with the groove end, and the first side end and the second side end are arranged on two sides of the shielding grid in a staggered mode. According to the invention, the first source electrode contact layer is arranged above each section of the shielding grid, and the first side end and the second side end outside the grid groove are arranged on two sides of the shielding grid, so that the phenomenon of mistaken opening of the grid caused by grid voltage change due to parasitic resistance effect and coupling capacitance effect of the traditional shielding grid field effect transistor is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a composite shielded gate field effect transistor.
Background
In the traditional shielded gate field effect transistor, a shielded gate is introduced on the basis of a trench gate structure, and is equivalent to a field plate structure, so that transverse auxiliary depletion can be provided, two-dimensional electric field depletion is realized in a drift region, and the EPI resistance of the drift region is greatly reduced.
However, in the conventional shielded gate field effect transistor, due to the blocking of the gate, the shielded gate can only be led out at two ends, so that a large parasitic resistance exists, and meanwhile, a large coupling capacitance exists in an oxide layer between the gate and the shielded gate, when the voltage of a drain terminal changes, the voltage of the gate changes due to the parasitic resistance effect and the coupling capacitance effect, so that the gate is turned on by mistake.
Disclosure of Invention
The invention mainly aims to provide a composite shielded gate field effect transistor, and aims to solve the technical problem that the shielded gate field effect transistor in the prior art can cause the change of gate voltage due to parasitic resistance effect and coupling capacitance effect, so that the gate is turned on by mistake.
To achieve the above object, the present invention provides a composite shielded gate field effect transistor comprising: a number of electrode structures, each electrode structure comprising: the grid electrode, the shielding grid and the first source electrode contact layer;
the shielding grids are arranged in a segmented mode through grooves;
the grid electrode is arranged above the shielding grid;
the first source electrode contact layer is arranged above each section of shielding grid, the grid electrode comprises a groove end arranged in the groove and a first side end and a second side end outside the groove, the first side end and the second side end are connected with the groove end, and the first side end and the second side end are arranged on two sides of the shielding grid in a staggered mode.
Optionally, the electrode structure further comprises: an oxide layer;
the oxide layer is arranged on the other parts of the electrode structure except the shielding grid and the grid.
Optionally, the composite shielded gate field effect transistor further comprises: an isolation layer;
the isolation layer is arranged above each electrode structure;
the first source contact layer is arranged in the isolation layer.
Optionally, the composite shielded gate field effect transistor further comprises: a gate contact layer;
the gate contact layer is disposed on the first side end or the second side end of the two ends of each electrode structure and located in the isolation layer.
Optionally, the composite shielded gate field effect transistor further comprises: a body region;
the body region is arranged between every two adjacent electrode structures;
the adjacent electrode structures are symmetrically distributed by taking the direction of the body region as an axis.
Optionally, the composite shielded gate field effect transistor further comprises: a second source contact layer;
the second source contact layer is arranged in the isolation layer and extends into the body region.
Optionally, the composite shielded gate field effect transistor further comprises: a source region;
a first vacant region and a second vacant region are arranged on two sides of the second source metal layer in the body region;
between adjacent ones of the electrode structures, a body region in which the first and second vacant regions exist is disposed between the gates disposed oppositely and adjacently;
the source region is disposed in the first and second vacant regions.
Optionally, the composite shielded gate field effect transistor further comprises: a source metal;
the source metal is disposed over the isolation layer;
the source metal is in contact with the first source contact layer and the second source contact layer.
Optionally, the composite shielded gate field effect transistor further comprises: a drift region;
the drift region is arranged below the body region and is in contact with the body region.
Optionally, the composite shielded gate field effect transistor further comprises: a substrate;
the substrate is arranged at the bottom of the drift region and is in contact with the drift region.
The invention provides a composite shielded gate field effect transistor, comprising: a number of electrode structures, each electrode structure comprising: the grid electrode, the shielding grid and the first source electrode contact layer; the shielding grids are arranged in sections through the grooves; the grid electrode is arranged above the shielding grid; the first source electrode contact layer is arranged above each section of shielding grid, the grid electrode comprises a groove end arranged in the groove and a first side end and a second side end which are arranged outside the groove, the first side end and the second side end are both connected with the groove end, and the first side end and the second side end are arranged on two sides of the shielding grid in a staggered mode. According to the invention, the first source electrode contact layer is arranged above each section of the shielding grid, and the first side end and the second side end outside the grid groove are arranged on two sides of the shielding grid, so that the phenomenon of mistaken opening of the grid caused by grid voltage change due to parasitic resistance effect and coupling capacitance effect of the traditional shielding grid field effect transistor is avoided.
Drawings
FIG. 1 is a schematic structural diagram of a composite shielded gate field effect transistor according to an embodiment of the present invention;
FIG. 2 is a schematic plan view of a composite shielded gate field effect transistor according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of coupling capacitors of a conventional structure in an embodiment of a composite shielded gate field effect transistor according to the present invention;
FIG. 4 is a schematic diagram of the parasitic resistance of a conventional structure in an embodiment of a composite shielded gate field effect transistor according to the present invention;
FIG. 5 is a schematic diagram of a first cross-section of a composite shielded gate field effect transistor according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a second cross-section of a composite shielded gate field effect transistor according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a third cross-section of a composite shielded gate field effect transistor according to an embodiment of the present invention;
FIG. 8 is a fourth cross-sectional view of a composite shielded gate field effect transistor according to an embodiment of the present invention.
The reference numbers illustrate:
| reference numerals | Name(s) | Reference numerals | Name (R) |
| 10 | |
101 | |
| 102 | |
103 | |
| 20 | Shielding grid | 31 | A first |
| 40 | Oxide layer | AA' | A first direction |
| BB' | The second direction | CC' | Third direction |
| DD' | |
50 | |
| 11 | |
60 | |
| 32 | Second |
601 | The first |
| 602 | Second |
70 | |
| 80 | |
90 | Substrate |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments based on the embodiments of the present invention, and all embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that the descriptions relating to "first", "second", etc. in the embodiments of the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features, and technical solutions between the respective embodiments may be combined with each other, but must be based on the realization of the capability of a person skilled in the art, and when the technical solutions are contradictory or impossible to realize, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a composite shielded gate field effect transistor according to an embodiment of the present invention.
As shown in fig. 1, in the present embodiment, the composite shielded gate field effect transistor includes: a number of electrode structures, each electrode structure comprising: a gate electrode 10, a shield gate 20, and a first source contact layer 31.
Wherein, the shielding grids 20 are arranged by sections through grooves; the gate electrode 10 is disposed above the shield gate 20; the first source contact layer 31 is disposed above each segment of the shielding gate 20, and the gate 10 includes a groove end 103 disposed in the groove and a first side end 101 and a second side end 102 outside the groove, wherein the first side end 101 and the second side end 102 are both connected to the groove end, and the first side end 101 and the second side end 102 are alternately disposed on two sides of the shielding gate 20.
For ease of understanding, the description is made with reference to fig. 2, but this scheme is not limited thereto. Fig. 2 is a schematic plane structure diagram of an embodiment of a composite shielded gate field effect transistor according to the present invention, where AA ' is a first direction along a direction of an electrode structure, BB ' is a second direction perpendicular to the first direction AA ' at a middle portion of the electrode structure, CC ' is a third direction parallel to the second direction BB ' at a position of a groove in the electrode structure, DD ' is a fourth direction parallel to the third direction CC ' at a position of a first source contact layer 31 in the electrode structure, grooves on the shielded gate 20 are alternately arranged, there are spaces between the grooves, groove ends of the gate 10 are all disposed in the grooves, and first side ends 101 and second side ends 102 of the gate are alternately disposed at two sides of the shielded gate 20.
It should be noted that fig. 1 and fig. 2 both show partial structures of electrode positions, and in the chip crystal structure, a plurality of grooves may be provided, which are both arranged according to the structures shown in fig. 1 and fig. 2, and this embodiment is not described again.
In this embodiment, the electrode structure further includes: and (3) oxidizing the layer 40.
Wherein, the oxide layer 40 is disposed on the electrode structure except for the shielding gate 20 and the gate 10.
It can be understood that, referring to fig. 2, the gate electrode 10 and the shield gate 20 are not in contact with each other, and the oxide layer 40 is disposed to isolate the gate electrode 10 from the shield gate 20, so as to improve the performance of the chip.
For ease of understanding, the description will be made with reference to fig. 3, but this scheme is not limited thereto. Fig. 3 is a schematic diagram of a coupling capacitance of a conventional structure in an embodiment of the composite shielded gate field effect transistor of the present invention, in which the composite shielded gate field effect transistor is a partial sectional diagram, which can be flattened with reference to the third direction CC 'in fig. 2, and the sectional diagram shown in fig. 3 can be obtained by cutting in the third direction CC', in which a coupling capacitance exists between the oxide layer 40 between the gate 10 and the shielded gate 20, and the coupling capacitance is large, and the generated coupling capacitance effect may cause a change in gate voltage, resulting in a gate false turn-on.
It should be noted that in the composite shielded gate field effect transistor in the embodiment, the gate electrodes 10 are alternately arranged, that is, the first side end 101 and the second side end 102 of the gate electrode 10 are alternately arranged on two sides of the shielded gate 20, so that the capacitive coupling area between the gate electrode 10 and the shielded gate 20 can be effectively reduced, and the problem of coupling capacitance can be reduced.
For ease of understanding, reference is made to fig. 4, but this solution is not limited thereto. Fig. 4 is a schematic diagram of parasitic resistance of a conventional structure in an embodiment of the composite shielded gate field effect transistor of the present invention, in the conventional shielded gate field effect transistor, a shielding gate 20 is introduced on the basis of a gate 10, and the shielding gate 20 is disposed below the gate 10, because the gate 10 is above the shielding gate 20 and blocks the shielding gate 20, the shielding gate 20 can only be led out at two ends, that is, led out through a first source contact layer 31 in fig. 4, a large parasitic resistance exists, and the parasitic resistance effect generated by the parasitic resistance effect can cause a change in gate voltage, which results in a gate being turned on by mistake.
It should be noted that, in the composite shielded gate field effect transistor in this embodiment, the shielding gate 20 is disposed in segments through the above-mentioned groove in the electrode structure, and the first side end 101 and the second side end 102 of the gate 10 outside the groove are parallel to the shielding gate 20 and block the shielding gate 20, so that the first source contact layer 31 may be disposed above the shielding gate 20 outside the groove, and the source metal contacted by the shielding gate 20 is led out through the first source contact layer 31, thereby avoiding the above-mentioned parasitic resistance problem.
It is understood that the first source contact layer 31 may be disposed on the shielding gate 20 outside the recess, which is not limited in the embodiment.
In this embodiment, the composite shielded gate field effect transistor further includes: an isolation layer 50.
Wherein the isolation layer 50 is disposed above each of the electrode structures; the first source contact layer 31 is disposed in the isolation layer 50.
For ease of understanding, the description will be made with reference to fig. 5, but this scheme is not limited thereto. Fig. 5 is a schematic cross-sectional view of a composite shielded gate field effect transistor according to an embodiment of the present invention, where fig. 5 is a cross-sectional view obtained by cutting along a first direction AA' shown in fig. 2, in which an oxide layer is present between a recessed end 103 of a gate 10 and a shielded gate 20, the recessed end 103 is disposed in a recess on the shielded gate 20, an isolation layer 50 is disposed above an electrode structure, that is, above the shielded gate 20 and the gate 10, a first source contact layer 31 is disposed in the isolation layer 50 and contacts with the shielded gate 20 outside the recess, and the first source contact layer 31 can be disposed above the shielded gate 20 outside the recess, so as to lead out the shielded gate 20, and the isolation layer 50 can also serve as an isolation function to contact the isolated gate 10 and a source metal.
In this embodiment, the composite shielded gate field effect transistor further comprises: a gate contact layer 11.
The gate contact layer 11 is disposed on the first side end 101 or the second side end 102 at two ends of each of the electrode structures, and is located in the isolation layer 50.
It should be noted that, since the first source contact layer 31 is led out from the shielding gate 20 outside the groove of the embodiment, the first side end 101 and the second side end 102 of the gate 10 alternately disposed at two sides of the shielding gate 20 cannot be led out to contact the gate metal, and therefore, the gate contact layer 11 can be led out from the first side end 101 or the second side end 102 at two ends of the electrode structure to contact the gate metal.
It will be understood that if the first side end 101 of the gate electrode 10 is at both ends of the electrode structure, the gate contact layer 11 is disposed on the first side end 101, and correspondingly, if the second side end 102 of the gate electrode 10 is at both ends of the electrode structure, the gate contact layer 11 is disposed on the second side end 102.
The gate contact layer 11 is also disposed in the isolation layer 50 to contact the first side end 101 or the second side end 102.
In this embodiment, the composite shielded gate field effect transistor further includes: body region 60.
Wherein the body region 60 is disposed between each adjacent electrode structure; the adjacent electrode structures are distributed symmetrically with the direction of the body region 60 as an axis.
For ease of understanding, referring to fig. 6 for a description, fig. 6 is a schematic second cross-sectional view of the composite shielded gate field effect transistor according to the embodiment of the present invention, and fig. 6 may be a cross-sectional view obtained by cutting along the second direction BB' shown in fig. 2, in which the body region 60 is disposed between the adjacent electrode structures, and disposed below the isolation layer 50, and in contact with the oxide layer 50 between the adjacent electrodes.
It should be noted that, referring to fig. 2, in fig. 2, the body regions 60 are located between the electrode structures, the arrangement direction is consistent with AA', and the electrode structures are distributed about the direction of the body region 60, so as to form a symmetrical structure as shown in fig. 2, wherein the first side ends 101 of the gate electrodes 10 are all located at the right side of the shielding gate 20, and correspondingly, the second side ends 102 are all located at the left side of the shielding gate 20.
It can be understood that, for both fig. 1 and fig. 3 to 6, the above symmetrical structures can be explained according to the above content, and the symmetry of this embodiment is not repeated.
In this embodiment, the composite shielded gate field effect transistor further includes: a second source contact layer 32.
As shown in fig. 6, the second source contact layer 32 is disposed in the isolation layer 50 and extends into the body region 60.
It should be noted that, since the gate metal is led out from the first side end 101 or the second side end 102 at both ends of the electrode structure, the source metal should be disposed on the rest portions, and therefore, the second source contact layer 32 and the first source contact layer 31 on the outer shielding gate 20 of the groove are both connected to the same source metal, so as to reduce the area of the chip.
The present embodiment provides a composite shielded gate field effect transistor, including: a number of electrode structures, each electrode structure comprising: the grid electrode, the shielding grid and the first source electrode contact layer; the shielding grids are arranged in sections through the grooves; the grid electrode is arranged above the shielding grid; the first source electrode contact layer is arranged above each section of shielding grid, the grid electrode comprises a groove end arranged in the groove and a first side end and a second side end which are arranged outside the groove, the first side end and the second side end are both connected with the groove end, and the first side end and the second side end are arranged on two sides of the shielding grid in a staggered mode. In the embodiment, the first source contact layer is arranged above each section of the shielding grid, and the first side end and the second side end outside the grid groove are arranged on two sides of the shielding grid, so that the phenomenon that the grid of the traditional shielding grid field effect transistor is mistakenly opened due to the change of the grid voltage caused by the parasitic resistance effect and the coupling capacitance effect is avoided.
Referring to fig. 7, fig. 7 is a schematic diagram of a third cross-section of the composite shielded gate field effect transistor according to the embodiment of the invention.
In this embodiment, the composite shielded gate field effect transistor further comprises: a source region.
A first vacant region 601 and a second vacant region 602 are arranged on two sides of the second source metal layer 32 in the body region 60; between the adjacent electrode structures, a body region where the first vacant region 601 and the second vacant region 602 exist is disposed between the gates 10 disposed oppositely and adjacently; the source regions are disposed in the first vacant region 601 and the second vacant region 602.
It should be noted that fig. 7 is a cross-sectional view obtained by cutting along the third direction CC 'shown in fig. 2 in the present embodiment, in which the recessed end 103 of the gate 10 is located above the shielding gate 20, so that the body region 60 in the third direction CC' can be located in the first vacant region 601 and the second vacant region 602, in accordance with the conventional structure.
For ease of understanding, the description will be made with reference to fig. 8, but this scheme is not limited thereto. Fig. 8 is a schematic fourth cross-sectional view of an embodiment of the composite shielded gate field effect transistor of the present invention, which can be obtained by cutting along the fourth direction DD 'shown in fig. 2 in this embodiment, wherein the first vacant region 601 and the second vacant region 602 exist in the body region 60 between the first side end 101 on the right side of the shielded gate 20 and the first side end 102 on the left side of the shielded gate in the fourth direction DD'.
It is understood that the first vacant regions 601 and the second vacant regions 602 may also exist in the body region 60 in the fourth direction DD ' shown in fig. 2 between the adjacent electrode structures, and accordingly, since the electrodes are symmetrically distributed, the first side end 101 and the next electrode structure on the right side in the second direction BB ' in fig. 2 are also adjacent to each other through the second side end 102 (not shown in the figure, this case can refer to the distribution of the first side end 101 and the second side end 102 in the fourth direction DD ' in fig. 2, and will not be described again here). Therefore, the first dummy region 601 and the second dummy region 602 exist in the body region 60 between the gates 10 (including the first side end 101, the second side end 102, and the third side end 103) disposed relatively adjacent to each other.
It should be noted that the first Dummy region 601 and the second Dummy region 602 do not exist in the body region 60 which is not located between the gates 10 which are relatively adjacently disposed, but referring to the structure shown in fig. 6, the body region in fig. 6 is disposed between the shield gates 20 which are relatively adjacently disposed in each of the adjacent structures, and since the body region 60 in this case does not include the first Dummy region 601 and the second Dummy region 602, the body region cannot be filled with the source region, and the region in this direction is an invalid structure or a Dummy structure, that is, a Dummy cell structure, which can effectively suppress the latch-up effect of the NPN and improve the short-circuit capability.
In this embodiment, the composite shielded gate field effect transistor further comprises: the source metal 70.
Wherein the source metal 70 is disposed over the isolation layer 50; the source metal 70 is in contact with the first source contact layer 31 and the second source contact layer 32.
As shown in fig. 8, the source metal 70 is located above the isolation layer 50 and contacts the isolation layer 50, the shield gate 20 is drawn out through the first source contact layer 31 and contacts the source metal 70, and the body region 60 is drawn out through the second source contact layer 32 and contacts the source metal 70.
In this embodiment, the composite shielded gate field effect transistor further comprises: a drift region 80.
The drift region 80 is disposed under the body region 60 and contacts the body region 60.
As shown in fig. 8, the drift region 80 is between the oxide layers 50 of the electrode structures and contacts the body region 60 below the body region 60.
The drift region 80 may be an N-type semiconductor thin film grown on a substrate.
In this embodiment, the composite shielded gate field effect transistor further comprises: a substrate 90.
Referring to fig. 8, the substrate 90 is disposed at the bottom of the drift region 80 and is in contact with the drift region 80.
The substrate 90 may be a structure for carrying the above components, wherein the substrate 90 in this embodiment may be an N-type substrate.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or system comprising the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A composite shielded gate field effect transistor, comprising: a number of electrode structures, each electrode structure comprising: the grid electrode, the shielding grid and the first source electrode contact layer;
the shielding grids are arranged in a segmented mode through grooves;
the grid electrode is arranged above the shielding grid;
the first source electrode contact layer is arranged above each section of shielding grid, the grid comprises a groove end arranged in the groove and a first side end and a second side end arranged outside the groove, the first side end and the second side end are connected with the groove end, and the first side end and the second side end are arranged on two sides of the shielding grid in a staggered mode.
2. The composite shielded gate field effect transistor of claim 1 wherein said electrode structure further comprises: an oxide layer;
the oxide layer is arranged on the other parts of the electrode structure except the shielding grid and the grid.
3. The composite shielded gate field effect transistor of claim 2 further comprising: an isolation layer;
the isolation layer is arranged above each electrode structure;
the first source contact layer is arranged in the isolation layer.
4. The composite shielded gate field effect transistor of claim 3 further comprising: a gate contact layer;
the gate contact layer is disposed on the first side end or the second side end at both ends of each of the electrode structures, and is located in the isolation layer.
5. The composite shielded gate field effect transistor of claim 4 further comprising: a body region;
the body region is arranged between the adjacent electrode structures;
the adjacent electrode structures are symmetrically distributed by taking the direction of the body region as an axis.
6. The composite shielded gate field effect transistor of claim 5 further comprising: a second source contact layer;
the second source contact layer is arranged in the isolation layer and extends into the body region.
7. The composite shielded gate field effect transistor of claim 6 further comprising: a source region;
a first vacant region and a second vacant region are arranged on two sides of the second source metal layer in the body region;
between adjacent ones of the electrode structures, a body region in which the first and second vacant regions exist is disposed between the gates disposed oppositely and adjacently;
the source region is disposed in the first and second vacant regions.
8. The composite shielded gate field effect transistor of claim 7 further comprising: a source metal;
the source metal is disposed over the isolation layer;
the source metal is in contact with the first source contact layer and the second source contact layer.
9. A composite shielded gate field effect transistor according to any of claims 5 to 8 further comprising: a drift region;
the drift region is arranged below the body region and is in contact with the body region.
10. The composite shielded gate field effect transistor of claim 9 further comprising: a substrate;
the substrate is arranged at the bottom of the drift region and is in contact with the drift region.
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| CN202310024068.2A CN115763543B (en) | 2023-01-09 | 2023-01-09 | Composite shielded gate field effect transistor |
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| CN202310024068.2A CN115763543B (en) | 2023-01-09 | 2023-01-09 | Composite shielded gate field effect transistor |
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| CN115763543A true CN115763543A (en) | 2023-03-07 |
| CN115763543B CN115763543B (en) | 2023-04-18 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130200451A1 (en) * | 2012-02-02 | 2013-08-08 | Hamza Yilmaz | Nano mosfet with trench bottom oxide shielded and third dimensional p-body contact |
| US10103257B1 (en) * | 2017-11-10 | 2018-10-16 | Nxp Usa, Inc. | Termination design for trench superjunction power MOSFET |
| CN109037335A (en) * | 2017-06-08 | 2018-12-18 | 力祥半导体股份有限公司 | Power transistor device |
| CN111415992A (en) * | 2020-04-20 | 2020-07-14 | 安建科技(深圳)有限公司 | Shielding gate MOSFET device and preparation method thereof |
| US20210343834A1 (en) * | 2020-04-30 | 2021-11-04 | Cree, Inc. | Trenched power device with segmented trench and shielding |
-
2023
- 2023-01-09 CN CN202310024068.2A patent/CN115763543B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130200451A1 (en) * | 2012-02-02 | 2013-08-08 | Hamza Yilmaz | Nano mosfet with trench bottom oxide shielded and third dimensional p-body contact |
| CN109037335A (en) * | 2017-06-08 | 2018-12-18 | 力祥半导体股份有限公司 | Power transistor device |
| US10103257B1 (en) * | 2017-11-10 | 2018-10-16 | Nxp Usa, Inc. | Termination design for trench superjunction power MOSFET |
| CN111415992A (en) * | 2020-04-20 | 2020-07-14 | 安建科技(深圳)有限公司 | Shielding gate MOSFET device and preparation method thereof |
| US20210343834A1 (en) * | 2020-04-30 | 2021-11-04 | Cree, Inc. | Trenched power device with segmented trench and shielding |
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| CN115763543B (en) | 2023-04-18 |
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