CN115695517A - High-speed digital dimming interface compatible with DALI transceiver - Google Patents
High-speed digital dimming interface compatible with DALI transceiver Download PDFInfo
- Publication number
- CN115695517A CN115695517A CN202211356548.0A CN202211356548A CN115695517A CN 115695517 A CN115695517 A CN 115695517A CN 202211356548 A CN202211356548 A CN 202211356548A CN 115695517 A CN115695517 A CN 115695517A
- Authority
- CN
- China
- Prior art keywords
- dali
- bus
- digital dimming
- data
- dimming interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Selective Calling Equipment (AREA)
Abstract
The invention discloses a high-speed digital dimming interface compatible with a DALI transceiver, which comprises a bus power supply, a control device, an application controller, input equipment and a bus, wherein the bus power supply is connected with the control device; the digital dimming interface is also internally provided with a bottom layer transmission protocol, the bottom layer transmission protocol comprises a bit code, a data frame and a receiving and transmitting time sequence, the bit code adopts frequency modulation, and the frequency modulation is to take a period formed by continuously variable high and low levels as a data bit. The invention enables all the current devices meeting the DALI standard to realize the transmission rate 2 to 8 times higher than the current DALI standard by modifying the receiving, detecting and sending and encoding mechanism of the bus transmission signal under the condition of not changing the physical circuit design, and meanwhile, by using the data frame format provided by the invention, the command interaction modes of control, query, configuration and the like in the current DALI standard can be simplified, and the efficiency of controlling query and configuration tasks is further improved.
Description
Technical Field
The invention relates to the technical field of lighting control, in particular to a high-speed digital dimming interface compatible with a DALI transceiver.
Background
DALI (Digital Addressable Lighting Interface) is a Lighting standard defined by IEC62386, and one DALI bus can access up to 64 controlled Lighting devices (e.g., LED lamps, relays, etc.) and 64 control devices (e.g., switches, sensors, etc.). DALI is widely used in large venues, commercial lighting, and office lighting control systems as the mainstream intelligent lighting technology.
The color control function defined in the DALI standard IEC 62386-209 allows a DALI control device to accept rgbw af (up to 6 color channels) control commands, but is limited by IEC62386-102 to control only usable 16-bit forward frames and 8-bit backward frames for the control device, and generally requires multiple data frames to be transmitted between a host and a control device to perform a simple function when the control device supporting rgbw is configured and controlled. This greatly reduces the real-time nature of the control and also increases the complexity of the control interaction.
The DALI standard IEC 62386-103 defines a 24-bit forward frame communication format for the control device, however, the parameter configuration of the input device such as the sensor and the input key is more complicated than the control device, and in order to implement the parameter configuration and monitoring of the input device by the host, a plurality of commands are often required to be combined to complete a simple function.
The firmware update protocol defined in the DALI standard IEC 62386-105 allows online firmware upgrades for DALI devices, which takes around 15 minutes for a typical 64KB DALI device firmware upgrade, due to the standard DALI transmission rate of only 1200bps, and thus takes a very long time if there are a large number of DALI devices that need to upgrade the firmware.
The reason why DALI takes this low rate is mainly the following: at the beginning of the establishment of DALI technical standards in the 1990 s, the performance of a microcontroller which can be adopted by the implementation technology is generally weaker, and the lower transmission rate is beneficial to implementation; the low transmission rate is beneficial to the design of a transceiver circuit of a DALI product, and the simple transceiver circuit scheme can ensure the stability of communication; DALI technology was mainly used for control of lighting lights with no more than 2 bytes per transmission at the time, and there were no application scenarios requiring large amounts of data for RGBW tinting, sensor configuration monitoring, and firmware upgrades. Therefore, there is a need in the market for a method that can achieve faster transmission rate without changing the original DALI protocol or most of the original DALI protocols.
The existing method for improving the transmission rate does not change the original coding mode of the DALI usually, but the inherent characteristics of an optical coupler in a general design circuit of the DALI transceiver can cause the change range of the rising and falling edge widths of transmitting and receiving waveforms along with the temperature to be overlarge, so that under the condition that the DALI standard has requirements on the high and low level width specifications of manchester coding, the bit width is not excessively reduced, otherwise, the design scheme of the conventional transceiver of the DALI equipment at present cannot meet the requirements, and further, a more complicated transceiver design scheme with higher cost must be adopted. Some methods also need to sacrifice the transmission distance or improve the dynamic characteristics of the bus power supply to improve the transmission rate, and the implementation has a great limitation.
Disclosure of Invention
In view of the above technical problems, the present invention is directed to provide a High Speed digital dimming Interface (Hi-Li) compatible with a DALI transceiver, where the Interface enables all current devices meeting the DALI standard to achieve a transmission rate 2 to 8 times higher than the current DALI standard by only modifying a protocol detection mechanism for bus transmission signals without changing a physical circuit design, and meanwhile, by using the data frame format provided by the present invention, command interaction modes such as control, query, and configuration in the current DALI standard can be simplified.
In order to solve the technical problems, the invention adopts the following technical scheme: a DALI transceiver compatible high speed digital dimming interface, comprising: the system comprises a bus power supply, a control device, an application controller, input equipment and a bus, wherein the bus power supply, the control device, the application controller and the input equipment are all connected through the bus; the digital dimming interface is also internally provided with a bottom layer transmission protocol, the bottom layer transmission protocol comprises bit coding, a data frame and a transceiving time sequence, the bit coding adopts frequency modulation, and the frequency modulation takes a period formed by continuously changing high and low levels as a data bit.
Furthermore, the physical layer transceiver electrical specification of the control device, the application controller and the input device is the same as the transceiver electrical specification of the DALI standard control device, the application controller and the input device, and the requirements of the bus power supply and the bus are the same as the requirements of the DALI standard bus power supply and the bus.
Further, the T0 with the shorter period length of the data bit is defined as logic "0", and the T1 with the longer period length is defined as logic "1"; the data frame includes a start condition, data bits of 1-N bits, a 1-bit check bit, and a stop condition.
Further, the starting condition is that the bus changes from high level to low level and keeps the length Ts; the stop condition is that the bus changes from low level to high level and maintains the length Tp.
Further, the length Ts has a minimum value of 2T1 and a maximum value of 4T1.
Further, the parity bits are checked in an odd check mode or an even check mode, the odd check mode is that the total number of logic "1" in the data bits and the parity bits is an odd number, and the even check mode is that the total number of logic "1" in the data bits and the parity bits is an even number.
Further, tp is 2T1.
Further, bus standing time is set between the data frames.
Furthermore, the number of the data bits is M times of 8, wherein M is an integer from 1 to 32.
Further, the application layer data frames of the control device, the application controller and the input device are defined to directly adopt the existing command definition in the DALI standard, or perform optimization supplement based on the DALI standard command or define a completely new application command set.
Has the advantages that: since the characteristics of the electronic components of the DALI product transceiver mainly affect the position shift of the rising and falling edges within the period of the bus signal, the length of the period is less affected by the electronic components and temperature drift, and can be controlled to be below 5%. Different from communication modes such as UART or RS485, the coding mode provided by the invention ensures that the error only needs to be controlled in one transmission bit and is not accumulated in a data frame. Therefore, the width specification of the data bits can be defined as about 100us at the lowest, and the definition of the width error of the transmitting end can be reduced to about 10us (i.e. +/-10%). The definition of the receiver width error can be reduced to around 15us (i.e. +/-15%). Compared with the transmission rate of 1200bps of the DALI standard, the width of each data bit is 833us, and the dimming interface provided by the invention can improve the transmission rate by about 8 times of the DALI standard.
Compared with the prior art, the invention ensures that all the current devices meeting the DALI standard realize the transmission rate 2 to 8 times higher than the current DALI standard by modifying the detection mechanism of the bus transmission signal under the condition of not changing the physical circuit design, and simultaneously, the data frame format provided by the invention can simplify the command interaction of control, query, configuration and the like in the current DALI standard, and the efficiency improvement realized by completing complex tasks can reach 35 times from the perspective of upper-layer application.
Drawings
FIG. 1 is a schematic diagram of the overall system application of the present invention.
Fig. 2 is a schematic diagram of the underlying transport protocol of the present invention.
FIG. 3 is a schematic diagram of the data bit frequency modulation encoding of the present invention.
Detailed Description
In order that the invention may be more fully understood, reference will now be made to the accompanying drawings. The invention may be embodied in different forms and is not limited to the embodiments described herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete.
As shown in the figure, the high-speed digital dimming interface compatible with the DALI transceiver comprises a bus power supply, a control device, an application controller, input equipment and a bus, wherein the bus power supply, the control device, the application controller and the input equipment are all connected through the bus; and a bottom layer transmission protocol is also arranged in the digital dimming interface.
The physical layer transceiver electrical specification of the control device, the application controller and the input equipment is the same as the transceiver electrical specification of the DALI standard control device, the application controller and the input equipment, and the requirements of the bus power supply and the bus are the same as the requirements of the DALI standard bus power supply and the bus.
The bottom layer transmission protocol comprises bit encoding, data frames and transceiving time sequences.
The bit encoding adopts frequency modulation, namely, a period consisting of high and low levels which are continuously changed is used as a data bit. The T0 with the shorter period length of the data bit is defined as logic '0', and the T1 with the longer period length is defined as logic '1'; the period T1 of the data bit "1" may be set to 1.5 times "0" in general. The high and low level pulse widths within the data bit are typically set to be no less than 0.2 times T0.
The data frame includes a start condition, data bits of 1-N bits, a 1-bit check bit, and a stop condition. The start condition is that the bus goes from high to low and holds for a length Ts, indicating the start of a data frame. Ts is typically set to a minimum value of 2T1 and a maximum value of 4T1. The parity bits adopt parity check mode of odd parity check or even parity check, the odd parity check is that the total number of logic '1' in the data bits and the parity bits is odd number, and the even parity check is that the total number of logic '1' in the data bits and the parity bits is even number. The stop condition is that the bus changes from low level to high level and holds a length Tp, which is generally set to 2T1.
The number of bits of the data frame is usually M times 8, M is an integer from 1 to 32, and is converted into usable bytes, i.e. data representing 1 to 32 bytes. And bus standing time is also set between the data frames, so that the bus standing time is used for supplementing power supply from bus power-taking equipment in time on one hand, and is used for collision avoidance control of data frame transmission on the other hand.
When the high-speed digital dimming interface is implemented, the same DALI transceiver circuit design conforming to the DALI standard product is adopted, and only a receiving detection and sending coding mechanism of a bus transmission signal is changed.
The parity bits of the data frame are used as the odd parity for example.
1. The DALI transmission speed is increased by using the DALI data frames.
For example, T0 is set to 104.2us for each data bit transmission at a standard baud rate of 9600bps, and the minimum width of the high-level pulse and the low-level pulse in the data bit period is 0.2xt0=20.8us.
T1=1.5 × T0, 156.3us; ts ranges from 2T1 to 4T1, i.e., 312.5us to 625us, and typically has a value of 3T1, i.e., 468.8us; tp is 2t1=312.5us.
For the transmitter, T0, T1 needs to be controlled between 90% and 110% of the rated value, ts needs to be between 2.5T1 and 3.5T1, and Tp is 2.0T1.
For the receiver, T0, T1 needs to be controlled between 85% and 115% of the rated value, ts needs to be between 2.0T1 and 4.0T1, and Tp is 1.5T1.
Defining a data frame containing 8-bit data as a backward frame defined in IEC 62386-101;
defining a data frame containing 16-bit data as a forward frame defined in IEC62386-102 for a control device;
the command definitions of the application controller and the control device to the application layer are in accordance with the provisions of IEC62386-102 and the control device extension protocol IEC 62386-2 xx.
(1) The application controller sends a broadcast dimming command DAPC (254) to dim all the controls to 100% brightness,
the 16-bit data 0xFEFE is sent encoded as 0b1111 1110 1111 1110.
Transmission time sequence: start condition, 7 bit '1',1 bit '0', check bit '1', stop condition.
According to the above specification, the typical transmission time of the transmitting end is defined as:
Ts+15*T1+2*T0+Tp＝468.8us+15*156.4us+2*104.2us+312.5us＝3335.7us。
(2) The application controller sends a unicast dimming command DAPC (0) to dim the control device addressed to 0% brightness (off),
16-bit data 0x0000 is transmitted, encoded as 0b0000 0000 0000 0000.
Transmission time sequence: start condition, 16 '0's, check bit '1', stop condition.
According to the above specification, the typical transmission time of the transmitting end is defined as follows:
Ts+16*T0+T1+Tp＝468.8us+16*104.2us+1*156.4us+312.5us＝2604.9us；
from the above two simple commands, it can be seen that the transmission time for the 16-bit forward frame command is about 2.6-3.3 ms, and compared with the transmission time of 16.6ms of this DALI standard, 5-6.4 times of absolute speed increase is still achieved despite the difference in actual transmission time due to the introduction of the check bits and the logic bits '0' and '1'.
2. On the basis of the DALI standard data frame, a longer data frame is defined for a complex interaction function, and the interaction times are reduced.
The data frame transmission bit timing is still defined using T0, T1, ts and Tp as in the previous example.
Defining a 64-bit data frame as a newly increased forward frame type, and defining part of newly increased instructions for controlling the parameter configuration of the device and the data reading and writing of a Memory Bank. The general format is:
Address，OpCode，Data Byte 0～5
address: the address byte of the target device, bit 7-1 is the address, and Bit0 is always 1. Adopting an addressing mode compatible with DALI, 0-63 are unicast addresses, 63-79 are multicast addresses (corresponding grouping 0-15), 126 are device broadcast addresses of unallocated addresses, and 127 are broadcast addresses.
OpCode: a command code in which the SetBasicVars command is defined as 0x55.
(1) SetBasicVars: setting basic parameters of a control device, and setting 6 parameters including maximum brightness level, minimumLevel, powerOnLevel, systemFailureLevel, fadeTime/FadeRate, extendedFadeTime and the like at one time.
The data portion of the command is:
Data Byte 0：MaximumLevel；
Data Byte 1：MinimumLevel；
Data Byte 2：PowerOnLevel；
Data Byte 3：SystemFailureLevel；
Data Byte 4：FadeTime/FadeRate；
Data Byte 5：ExtendedFadeTime；
if the 6 parameters are written using the command combination defined in the DALI standard, "SET MAX LEVEL (DTR 0)", "SET MIN LEVEL (DTR 0)", are executed in sequence,
7 independent commands such as "SET POWER LEVEL (DTR 0)", "SET SYSTEM FAILURE LEVEL (DTR 0)", "SET FADE TIME (DTR 0)", "SET FADE RATE (DTR 0)", "SET EXTENDED FAILE TIME (DTR 0)", and the 7 commands need to be sent with the value of "DTR0 (data)" instruction pre-written in DTR0 register before each execution, and the 16-bit forward frame command needs to be executed 14 TIMEs in total, and each 16-bit forward frame transmission needs 16.6ms, and the DALI standard requires that 13.5ms of standing TIME (minus 2.4ms of stop condition) must be reserved between the forward frames, and also needs to wait for 11.1ms to be sent with the next instruction) to be actually completed by 14.6 ms plus (14-1) = 11.1) = 3.376.144 ms.
While the maximum time required to write these 6 parameters at once using the newly added 64-bit SetBasicVars command (assuming both address and parameter data bits are logic "1"):
the 64-bit code is: 0x55FF FFFF FFFF
Transmission time sequence: <xnotran> ,0x55,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, '1', . </xnotran>
According to the above specification, the typical transmission time of the transmitting end is defined as:
Ts+61*T1+4*T0+Tp＝468.8us+61*156.4us+4*104.2us+312.5us＝10738.5us～＝10.74ms。
therefore, the execution efficiency of completing the same task is greatly optimized by the newly added command under the support of multi-byte transmission, the speed is improved by far exceeding the improvement multiple of the transmission rate, and the speed reaches 376.7ms/10.74ms =35 times.
The meaning of the data frame format of the high-speed digital dimming interface at the upper layer can adopt the same definition as the corresponding part in the DALI standard, namely, a data frame containing 8-bit data with 1 byte length is used as an 8-bit backward frame in the DALI standard, a data frame containing 16-bit data with 2 byte length is defined as a 16-bit forward frame in the DALI standard, a data frame containing 24-bit data with 3 byte length is defined as a 24-bit forward frame in the DALI standard, and a data frame containing 32-bit data with 4 byte length is defined as a 32-bit forward frame in the DALI standard.
The data frame format meaning of the high-speed digital dimming interface at the upper layer can also adopt a data frame optimally designed by utilizing the advantages of a high-speed underlying transmission protocol, for example, the data frame containing more than 4 bytes of data is used as a forward frame for issuing control, query and configuration instructions in one transmission, and the data frame containing more than 2 bytes of data is used as backward frame reply response data and reporting event information.
The high-speed digital dimming interface provided by the invention supports a multi-host collision avoidance, detection and recovery mechanism defined in the DALI standard, when a plurality of devices on the bus try to initiate transmission, the change of a data bit period on the bus is easily caused, and the change is more easily detected compared with the DALI standard due to the stricter specification limit of the length of the data bit period.
The high-speed digital dimming interface provided by the invention has no limitation on the definition and use of an upper layer data frame, and all data transmission protocols based on the bottom layer coding idea belong to the specific implementation application thereof.
In the above embodiments, all functions may be implemented, or a part of the functions may be implemented as necessary.
It should be noted that the various features described in the foregoing embodiments may be combined in any suitable manner without contradiction. The invention is not described in detail in order to avoid unnecessary repetition.
Claims (10)
1. A DALI transceiver compatible high speed digital dimming interface, comprising: the system comprises a bus power supply, a control device, an application controller, input equipment and a bus, wherein the bus power supply, the control device, the application controller and the input equipment are all connected through the bus; the digital dimming interface is also internally provided with a bottom layer transmission protocol, the bottom layer transmission protocol comprises bit coding, a data frame and a transceiving time sequence, the bit coding adopts frequency modulation, and the frequency modulation takes a period formed by continuously changing high and low levels as a data bit.
2. The DALI transceiver compatible high speed digital dimming interface of claim 1, further comprising: the physical layer transceiver electrical specification of the control device, the application controller and the input equipment is the same as the transceiver electrical specification of the DALI standard control device, the application controller and the input equipment, and the requirements of the bus power supply and the bus are the same as the requirements of the DALI standard bus power supply and the bus.
3. The DALI transceiver compatible high speed digital dimming interface of claim 1, further comprising: the T0 with the shorter period length of the data bit is defined as logic '0', and the T1 with the longer period length is defined as logic '1'; the data frame includes a start condition, data bits of 1-N bits, a 1-bit check bit, and a stop condition.
4. A DALI transceiver compatible high speed digital dimming interface as claimed in claim 3, wherein: the starting condition is that the bus is changed from a high level to a low level and keeps a length Ts; the stop condition is that the bus changes from low level to high level and holds the length Tp.
5. A DALI transceiver compatible high speed digital dimming interface as claimed in claim 3, wherein: the length Ts has a minimum value of 2T1 and a maximum value of 4T1.
6. A DALI transceiver compatible high speed digital dimming interface as claimed in claim 3, wherein: the parity bits adopt parity check mode of odd parity check or even parity check, the odd parity check is that the total number of logic '1' in the data bits and the parity bits is odd number, and the even parity check is that the total number of logic '1' in the data bits and the parity bits is even number.
7. The DALI transceiver compatible high speed digital dimming interface of claim 4, wherein: tp is 2T1.
8. A DALI transceiver compatible high speed digital dimming interface as claimed in any one of claims 1 or 3, wherein: and bus standing time is set between the data frames.
9. A DALI transceiver-compatible high-speed digital dimming interface as claimed in any one of claims 1, 3 or 6, wherein: the number of the data bits is M times of 8, wherein M is an integer from 1 to 32.
10. A DALI transceiver compatible high speed digital dimming interface as claimed in any one of claims 1 to 9, wherein: the application layer data frame definitions of the control device, the application controller and the input equipment are defined by directly adopting the existing command definition in the DALI standard, or are optimized and supplemented on the basis of the DALI standard command or define a brand-new application command set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211356548.0A CN115695517A (en) | 2022-11-01 | 2022-11-01 | High-speed digital dimming interface compatible with DALI transceiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211356548.0A CN115695517A (en) | 2022-11-01 | 2022-11-01 | High-speed digital dimming interface compatible with DALI transceiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115695517A true CN115695517A (en) | 2023-02-03 |
Family
ID=85047646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211356548.0A Pending CN115695517A (en) | 2022-11-01 | 2022-11-01 | High-speed digital dimming interface compatible with DALI transceiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115695517A (en) |
-
2022
- 2022-11-01 CN CN202211356548.0A patent/CN115695517A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8519819B2 (en) | System including reply signal that at least partially overlaps request | |
| JP4999006B2 (en) | Serial bus transmission system | |
| CN108449117B (en) | Internet of things system based on PLC and network access method | |
| US5160929A (en) | System for parallel communication of binary data via trinary transmission lines | |
| CN105474758B (en) | The method that data are sent for the drive circuit of light source and on power line | |
| CN113572674A (en) | Chain connection communication method of single-wire bus | |
| CN201893962U (en) | Control device for light-emitting diode (LED) street lamps | |
| WO2018095181A1 (en) | Data transmission method and device | |
| US8307137B2 (en) | Remote communication method of a network | |
| CN104332135A (en) | Parallel display circuit and display device thereof | |
| CN115695517A (en) | High-speed digital dimming interface compatible with DALI transceiver | |
| CN103476187B (en) | Tunnel LED lighting dimming device and dimming method | |
| CN110223620B (en) | Drive control method, drive control assembly and display device | |
| CN105610451A (en) | Receiver, sender, method for retrieving an additional, datum from a signal and method for transmitting a datum and an additional datum in a signal | |
| CN111627200A (en) | Signal modulation method and circuit based on infrared protocol and remote control terminal | |
| CN114999409A (en) | Mini LED backlight control circuit, display device and method | |
| CN107548183A (en) | LED driving light modulation chips based on radio communication | |
| CN103325237B (en) | The generation method of infrared carrier signal and device | |
| CN104486181A (en) | Modbus protocol-based slave unit | |
| WO2017104440A1 (en) | Communication device, communication method, program, and communication system | |
| US20230129498A1 (en) | Apparatus for a single edge nibble transmission (sent) multi transmission mode | |
| CN116561041B (en) | Single bus communication system and method | |
| CN201248172Y (en) | Digital address lighting control system having remote and local control function | |
| JP6771791B2 (en) | Energy efficient data frame exchange | |
| US7287208B2 (en) | Two-wire interface having embedded per frame reliability information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |