CN115643137B

CN115643137B - Apparatus and method for multi-stage sampler with greater gain

Info

Publication number: CN115643137B
Application number: CN202211275535.0A
Authority: CN
Inventors: 阿明·塔亚丽
Original assignee: Kandou Labs SA
Current assignee: Kandou Labs SA
Priority date: 2017-05-22
Filing date: 2018-05-22
Publication date: 2024-06-07
Anticipated expiration: 2038-05-22
Also published as: WO2018217786A1; CN111034137A; CN111034137B; DE112018002645T5; CN115643137A

Abstract

The invention discloses a device and a method for a multi-stage sampler with larger gain. The device comprises: a memory for storing previous data values; a Decision Feedback Equalization (DFE) computation circuit for generating a differential DFE magnitude; a decision feedback offset generator for receiving the differential DFE magnitude and the previous data value at first and second differential transistor pairs and responsively generating an analog DFE correction value, the polarity of the analog DFE correction value being determined by selecting either the first or second differential transistor pair based on the previous data value received from the memory; an input differential transistor pair for receiving an analog input signal and responsively generating an analog output signal; and a pair of common output nodes connecting the differential output of the decision feedback offset generator and the input differential transistor pair, the pair of common output nodes for forming an analog sum of the analog DFE correction value and the analog output signal.

Description

Apparatus and method for multi-stage sampler with greater gain

The application is a divisional application of patent application with the application number 201880046748.1 and the application date of 2018, 05 and 22, and the name of the patent application of 'multi-stage sampler with larger gain'.

Cross Reference to Related Applications

The application claims the benefit of U.S. provisional patent application No. 62/509713, filing date 2017, month 5, 22, inventor Armin Tajalli, entitled "multisampler with greater gain," the contents of which are incorporated herein by reference in their entirety for all purposes.

Reference to the literature

The following prior applications are incorporated by reference herein in their entirety for all purposes:

Publication No. 2011/0268225, application No. 12/784414, application day 5/20/2010, U.S. patent application nos. Harm Cronie and Amin Shokrollahi, entitled "orthogonal differential vector signaling", hereinafter "Cronie 1;

Publication No. 2011/0302478, application No. 12/982777, application day 12/30 of 2010, U.S. patent application entitled "high pin utilization, high power utilization inter-chip communications with common mode noise and synchronous switch output noise resistance," titled "Cronie 2" by the inventors Harm Cronie and Amin Shokrollahi;

U.S. patent application No. 13/549599, application day 2012, 7/5, inventor Armin Tajalli, harm Cronie and Amin Shokrollahi, entitled "method and circuit for efficient balanced code processing and detection," hereinafter "Tajalli 1;

The inventor is Brian Holden, amin Shokrollahi and ANANT SINGH, U.S. patent application entitled "vector signaling code time bias tolerance method and System for inter-chip communication and vector signaling code advanced Detector for inter-chip communication", hereinafter referred to as "Holden 1";

The application number is 61/946574, the application date is 28 days of 2014 2, the inventor is Amin Shokrollahi, brian Holden and Richard Simpson, and the U.S. provisional patent application is named "clock embedded vector signaling code", and is named "Shokrollahi 1" below;

U.S. patent application No. 14/612241, application day 2015, 8/4, and by Amin Shokrollahi, ali Hormati and Roger Ulrich entitled "Low inter-symbol interference ratio Low Power inter-chip communication method and device", hereinafter "Shokrollahi 2";

U.S. patent application No. 13/895206, filing date of 2013, 5, 15, and entitled "Circuit for detecting vector signaling codes for inter-chip communication by Difference and high efficiency", hereinafter referred to as "Ulrich1", by the inventors Roger Ulrich and Peter Hunt;

U.S. patent application No. 14/816896, application day 2015, 8/3, inventor BrianHolden and Amin Shokrollahi, entitled "orthogonal differential vector Signaling code with embedded clock", hereinafter "Holden 2";

U.S. patent application Ser. No. 14/926958, application Ser. No. 2015, 10/29, richard Simpson, ANDREW STEWART and Ali Hormati, entitled "clock data alignment System for vector Signaling code communication Link," Stewart 1, "below;

U.S. patent application No. 14/925686, application day 2015, 10 month and 28 day, inventor Armin Tajalli, entitled "improved phase interpolator", hereinafter referred to as "Tajalli 2;

U.S. provisional patent application No. 62/286717, date of application 2016, month 1, 25, inventor Armin Tajalli entitled "voltage sampling driver with greater high frequency gain," hereinafter Tajalli 3;

U.S. provisional patent application No. 62/326593, date of application 2016, month 4, 22, inventor Armin Tajalli, entitled "sampler with greater high frequency gain and longer evaluation time", hereinafter referred to as "Tajalli 4";

U.S. provisional patent application No. 62/326591, date of application 2016, month 4 and 22, inventor Armin Tajalli, entitled "high Performance phase locked Loop", hereinafter "Tajalli 5;

the application number is 62/41920, the application date is 2016, 10, 22, armin Tajalli, and U.S. provisional patent application entitled "multistage sampler with greater gain", hereinafter Tajalli 6.

Technical Field

Embodiments of the present invention relate generally to communication system circuits and, more particularly, to enabling instantaneous measurement and filtering of received signal voltage with respect to a given clock signal as a loop for detection of communication signals received from a high-speed multi-line interface for inter-chip communication.

Background

In modern digital systems, digital information must be processed efficiently and reliably. In this context, digital information is understood to be information contained within discrete values (i.e., non-continuous values). Digital information may be represented not only by bits and sets of bits, but also by numbers within a limited set.

To increase the overall bandwidth, most inter-chip or inter-device communication systems employ multiple lines for communication. Each of these lines or each pair may be referred to as a channel or link, and the plurality of channels constitute a communication bus between the electronic devices. At the physical circuit level, buses within an inter-chip communication system are typically made up of packaged electrical conductors between the chip and the motherboard, packaged electrical conductors on a Printed Circuit Board (PCB), or packaged electrical conductors within an inter-PCB cable and connector. In addition, microstrip or strip PCB lines may also be used in high frequency applications.

Common bus line signaling methods include single ended signaling and differential signaling. In applications requiring high speed communications, these methods may be further optimized in terms of power consumption and pin utilization, especially in high speed communications. Recently proposed vector signaling approaches may achieve more optimal trade-offs in terms of power consumption, pin utilization, and noise robustness of the inter-chip communication system. Such vector signaling systems convert the digital information of the transmitter into a different representation space in the form of vector codewords and select the different vector codewords according to the characteristics of the transmission channel and the design constraints of the communication system to make a better trade-off between power consumption, pin utilization and speed. This process is referred to herein as "encoding". The encoded codewords are transmitted from a transmitter to one or more receivers in the form of a set of signals. The receiver inverts the received signal corresponding to the codeword into the original digital information representation space. This process is referred to herein as "decoding".

Whatever the coding method, the signal received by the receiver is sampled (or otherwise recorded) at intervals that are sufficient to optimally represent the original transmitted value, regardless of the delay, interference and noise conditions of the transmission channel. The timing of this sampling (or slicing) operation is controlled by a corresponding Clock Data Recovery (CDR) timing system and the appropriate sampling time is determined by the system. Examples of such CDR systems are found in Stewart 1 and Tajalli.

Disclosure of Invention

In order to reliably detect data values transmitted via a communication system, the receiver has to accurately measure the amplitude of the received signal values at carefully selected points in time. In some embodiments, the received signal value is first captured at a selected point in time using an existing sample-and-hold circuit or track-and-hold circuit (or other form of amplification or integration hold circuit thereof), and then the resulting value is measured with an existing voltage comparison circuit and relative to one or more reference values. In other embodiments, the analog signal is first "sliced" by a comparator to obtain a digital result value, and then the resulting binary value is digitally sampled by a clocked digital latch.

In other embodiments, the resulting value representing the particular point in time input value relative to a given reference level is generated using circuitry capable of applying both time domain and amplitude domain constraints. Several examples of such embodiments are given in Taj alli 3, wherein the high frequency gain of the sampling circuit is advantageously increased over a narrower frequency range by means of a so-called high frequency peaking action, schematically shown by the gain versus frequency diagram of fig. 6A.

In addition, increasing the signal gain over a wide frequency range can be achieved as shown in the gain versus frequency plot of fig. 6B and described in embodiments of the present application. In other embodiments, the clocked sampling operation is further improved by replacing the static mode of operation used in Tajalli by dynamic circuit operation.

Drawings

Fig. 1 is a schematic diagram of a voltage sampler with high frequency peaking and offset compensation.

FIG. 2 is a schematic diagram of an embodiment of a voltage sampler with greater signal gain over a wide frequency range and with offset compensation.

FIG. 3 is a schematic diagram of an embodiment of a dynamic mode CMOS sampling circuit for extending the evaluation time of an input signal.

Fig. 4 is a block diagram of a cascaded sampling integrator/amplifier acting on a single input signal and generating four results suitable for processing with four processing stages.

Fig. 5 is a schematic diagram of one dynamic mode CMOS self-retiming integrator embodiment suitable for use as the sampler/integrator of fig. 4.

FIG. 6A is a graph of gain versus frequency showing the high frequency "peaking" gain boosting effect achieved by the circuit of FIG. 1.

Fig. 6B is a graph of gain versus frequency showing the wideband gain boosting effect achieved by the circuit of fig. 2.

Fig. 7 illustrates one embodiment of a series of cascaded discrete time domain samplers providing greater wideband and high frequency gain and offset compensation functions.

Fig. 8 shows a second embodiment of a series of cascaded discrete time domain samplers providing greater wideband and high frequency gain and supporting a dc signal correction function, wherein each sample processing stage has a differential input and output.

Fig. 9 is a graph of gain versus frequency for one embodiment of a cascade sampler.

FIG. 10 is a schematic diagram of an embodiment of a sample processing stage with greater high frequency gain and controllable polarity offset compensation.

Fig. 11A is a block diagram of a cascade system employing the sampling processing stage of fig. 10.

Fig. 11B is a block diagram of a clock delay circuit according to some embodiments.

Fig. 11C is a block diagram of a local oscillator for generating various clock circuit phases according to some embodiments.

Fig. 12 is a flow chart of a method 1200 according to some embodiments.

Fig. 13A and 13B illustrate a multi-level sampling clock relationship according to some embodiments.

Fig. 14 is a flowchart of a method 1400 according to some embodiments.

Fig. 15 illustrates a sampler/integrator processing stage for driving a plurality of samplers in accordance with some embodiments.

Fig. 16 illustrates a sampler/integrator processing stage as an integral hold processing stage according to some embodiments.

Fig. 17 illustrates pre-receiver compensation according to some embodiments.

Fig. 18 is a block diagram of a single integrator driving multiple latches according to some embodiments.

Fig. 19 is a flow chart of a method 1900 according to some embodiments.

Detailed Description

In order to reliably detect data values transmitted via a communication system, the communication receiver must accurately measure the magnitude of the received signal values at carefully selected points in time, and the points in time tend to be at or near the center of the settling period between the points in time at which the received signal transitions. This point in time is commonly referred to as the "eye center" (i.e., the well-known "eye diagram" that represents the change in signal amplitude over clock intervals), and is often determined using a local "receive clock" set to occur at the desired sampling point in time described above. The generation and subsequent control of such a receive clock schedule is well known in the art, i.e., the sampling time is measured by a Clock Data Recovery (CDR) system and adjusted progressively with respect to the receive signal settling time, thereby achieving optimization of the sampling time.

In some embodiments, the received signal value is first captured at a selected point in time using a sample-and-hold circuit or a track-and-hold circuit, then the resulting value is measured with an existing voltage comparison circuit and relative to one or more reference values.

In other embodiments, the resulting value representing the particular point in time input value relative to a given reference level is generated using circuitry capable of applying both time-domain and amplitude-domain constraint values. Several examples of such voltage sampler embodiments are given in Tajalli, wherein the high-frequency gain of the sampling circuit is advantageously increased over a narrower frequency range by means of a so-called high-frequency peaking action, schematically shown in the gain versus frequency diagram of fig. 6A. This high frequency peaking effect is extremely helpful for receiver frequency compensation of the communication channel characteristics. In another embodiment of the present application, the clocked sampling operation is further improved by replacing the static mode of operation used in Tajalli by dynamic circuit operation.

As shown in fig. 6B, the gain versus frequency plot, and as described in embodiments of the present application, dynamic circuit operation may also be applied to wideband amplification to increase signal gain over a wide frequency range.

The input signal source of the embodiments of the present application may be derived from either a single line signal or a weighted linear combination of multiple line signals provided by a multiple input comparator or multiple input Mixer (MIC) or the like used for vector signaling code detection.

Sampler with high-frequency peaking function

The operating data transmission rate of a communication link is typically located at or near the decreasing portion of the link response versus frequency curve. Thus, the receiver needs to be able to provide additional high frequency gain to compensate for the reduced portion of the communication link response.

An exemplary sampler circuit capable of providing additional narrowband high frequency gain using a secondary gain path implemented by a frequency selective RC network is presented in Tajalli. The circuit of fig. 1 is another embodiment of this type of circuit that is capable of reducing quiescent current consumption by virtue of the dynamic switching pattern of all transistors. Wherein CK turns on transistors 110 and 111 in the forward phase to precharge nodes vout+ and Vout-; CK enables transistors 150 and 160 in complementary or inverted phases such that the precharge charge flows to ground through two pairs of differential transistors 120/121 and 140/141, and the two transient currents are controlled by the voltage levels provided by inputs Vin + and Vin-. Since the operating times of the charge source and the discharge source do not overlap, the circuit consumes little quiescent current and is capable of effectively sampling the input signal at the falling edge of CK.

In the present embodiment, since the input terminals of the pair of parallel differential transistors 140/141 are turned from the frequency response to the corner frequencyVin+ and Vin-shaped, thus in accordance with the circuit of Tajalli, the pair of differential transistors also provides an additional high-frequency peaking function and optionally an offset voltage compensation function to effect adjustment of the differential output Vout balance point by progressive adjustment of the offset correction voltages voc+ and Voc "as required.

As shown in fig. 6A, in order to achieve the desired peaking characteristics, f _z is typically selected to be at or near the natural high-frequency attenuation point of the received signal amplitude versus frequency curve, as is common practice.

Sampler with greater broadband gain

The same dynamic mode operation can also be used for sampling circuits with wideband gain, as shown schematically in fig. 2.

Wherein while a similar progressive linear analysis may be employed as in the above example, another way of understanding may be more valuable in terms of description, especially in operational configurations where the clock frequency is much higher than the corner frequency f _z. In this further analysis, the first processing stage 210 in fact acts as a high frequency mixer to generate differential output signals vm+ and Vm-, which are in fact carriers CK mixed with or modulated by the differential input Vin. Subsequently, the second processing stage 220 effectively acts as a synchronous demodulator to regenerate the differential output Vout by mixing Vm with CK. Since the modulated carrier frequency involved is higher than the corner frequency f _z, the modulated signal is virtually unaffected when passing through the capacitor C, enabling both pairs of differential transistors in 220 to provide gain at all signal frequencies. In one embodiment, as shown in fig. 6B, the resulting signal transmission curve remains virtually flat over a wide frequency range, with a gain increase of about 6dB. Consistent with the previous example, the offset correction voltages Voc+ and Voc-may be incrementally adjusted as needed to achieve adjustment of the differential output Vout balance point.

Sampler with longer evaluation time

In the switched-mode dynamic circuit shown in fig. 2, the internal node quiescent voltages vm+ and Vm-etc. depend not only on the transistor action of the pair of differential transistors, but also on the integral action of the respective distributed node capacitances on the charge transferred during CK transitions. This integration effect can sometimes become more pronounced, especially when multiple dynamically clocked processing stages are cascaded in accordance with this embodiment.

Fig. 3 is a schematic diagram of a modification of the above sampler, in which the input evaluation time is prolonged by two partially overlapped clocks CK and CK'. For purposes of illustration and not limitation, in the following description, CK and CK' are assumed to have approximately orthogonal relationships as shown in the timing diagram of fig. 3. In practice, both clocks may be generated by a multi-stage clock generator, or one of the clocks may be synthesized by delaying the other clock by a delay element. During the first 90 degrees of the clock cycle, the sampler is reset by turning on the top three PMOS FETs that charge the Vs node to the supply voltage. During the rising edge of CK (during the second 90 degrees of the clock cycle), the Vs output assumes a differential output level proportional to Vin-and vin+ voltage levels, with one of the two voltage levels discharging to ground and the other remaining charged to the supply voltage. These levels remain unchanged when CK or CK' is high. Specifically, during the third 90 degrees, by adding a top PMOS FET driven by the quadrature (or other delay amount) clock CK', the recharge/reset action that would be induced if CK falls back low is prevented (bottom wake is turned off and Vs is recharged by turning on the middle PMOS FET). The output nodes Vs+ and Vs-are precharged to a high level during the reset interval only when CK' and CK are simultaneously reduced to a low level during the last 90 degrees. In this manner, the period of power supply voltage sampling starts from the rising edge of CK and remains until the falling edge of CK' (rather than just the falling edge of CK). This extended output duration allows for a longer setup time for subsequent integrator/samplers or latch elements. In other embodiments of the application, similar output duration extension effects may be achieved by similarly modifying clock signals including, but not limited to, overlapping or non-overlapping portions of clock duty cycle, relative clock phase.

Cascading of clocked samplers

Consistent with the embodiment shown in the block diagram of fig. 4, a clocked sampler having the above-described function is adapted for cascade operation. A sampler operating in the complementary phases of two-stage sampling clocks at a frequency Fck/2 samples the input signal Vin at 410 and 415. Each of the obtained sampling results itself is sampled twice by a sampler operating at the complementary phase of the sampling clock at a frequency of Fck/4. That is, the sampling result provided by 410 is alternately sampled by 420 or 425 (since its sampling clock operating frequency is half that of the upstream sampling clock). Similarly, each sampling result provided by 415 is alternately sampled by 430 or 435. The four results thus obtained are further resampled at 440, 445, 450, 455 and the final sampled results are digitally latched at 460, 465, 470, 475 to generate digital outputs Vout1, vout2, vout3, vout4.

In a practical implementation, by splitting the data processing operation between a two-stage operation where the clocking mechanism is simpler and a four-stage (or more) operation where the time delay is looser, a trade-off between power, speed and complexity will be facilitated. Such cascaded samplers may be designed with any number of resulting stages through prior art clock division and/or clock conditioning logic, and thus neither "two-stage" nor "four-stage" should be construed as limiting the present description.

Fig. 5 is a schematic diagram of one CMOS sampler/integrator implementation that is well suited for cascade operation as shown in fig. 4. The input clock CK and its complementary clock C' K control the first sample processing stage 510 and the second sample processing stage 520, respectively. In practice, this alternating arrangement of complementary processing stages enables an advantageous self-retiming characteristic which can simplify the scheduling scheme with two or more of the aforementioned sampler/integrator processing stages in succession, wherein said processing stages are also referred to in the present application as integrating hold processing stages, since this arrangement enables an extension of the effective output duration. In addition, the cascade sampler structure can obtain larger gain. In one embodiment, by providing a series of the above processing stages, the resulting gain is 27dB and the RMS noise is only 0.5mV.

Fig. 16 shows another embodiment of the sampler/integrator 510 of fig. 5, wherein additional serial pass transistors 1611 and 1612 are provided in the discharge path of the first sampling processing stage 1610 corresponding to the processing stage 510 of fig. 5. Unlike the case where the precharged output terminals vo+ and Vo-are continuously discharged to Vss when the clock CK rises to the high level in the unmodified embodiment of fig. 5. In this modified embodiment, when the clock CK rises to a high level, the precharged output terminals vo+ and Vo-are rapidly changed to an effective output result. In this further embodiment, pass transistors 1611 and 1612 stop discharging instantaneously when the common mode output voltage at outputs vo+ and Vo-decays below their threshold voltage, thereby allowing this embodiment to have a longer evaluation time. The second sample processing stage 1620 employs a similar mechanism in which pass transistors 1621 and 1622 cease discharging in a similar manner when the common mode output voltages of vout+ and Vout-decay below their threshold voltages, such that the voltage is at Vdd. The desired effective output duration extension effect is accompanied by an integral hold feature and is generated by processing stage 1610 and processing stage 1620 separately or by a cascade sequence of processing stages 1610 and 1620.

Decision feedback equalization

Decision Feedback Equalization (DFE) is a common technique for improving the signal detection capability of a serial communication system. This technique assumes that the transmission line characteristics of the communication channel between the transmitter and the receiver are imperfect, such that energy associated with previously transmitted bits may remain in the channel (e.g., as reflected waves from impedance disturbances) and negatively impact the reception of subsequent bits. The DFE system provided in the receiver processes each bit detected in the previous Unit Interval (UI) by simulating the communication channel, thereby estimating the effect of the bit on the next unit interval. The resulting estimate is referred to herein as a "DFE correction value" and the predicted value of the intersymbol interference may be compensated for by subtracting the DFE correction value from the received signal. In practice, the DFE system generates DFE correction values based on a plurality of previous unit intervals.

When the data rate is very high, there may not be enough time for detecting the received bits, calculating the corresponding DFE correction value, and detecting the next bit by applying the correction value to the next receiving unit interval. Thus, some embodiments employ a so-called "spread-out DFE method" in which correction values for some or all possible combinations of a plurality of previous data values are determined and then the resulting predictive correction values are applied to a plurality of copies of the received signal and the predictive detection values obtained from the corresponding resulting corrected signal forms. After the final solution of the previous data values, the correct predictive detection output value may be selected as the received data value for the corresponding unit interval.

It is readily appreciated that in this approach, even if DFE "unrolling" is performed for a relatively small number of previous unit intervals, a large number of virtually parallel predictors are generated, thus making the circuit complexity and corresponding power consumption large.

Cascaded sampler with DFE function

The cascade sampler embodiment shown in fig. 7 provides an interesting alternative to the spread DFE approach. Consistent with the foregoing embodiments, each primary discrete-time integration element (e.g., 710) is associated with a secondary discrete-time integration element (decision feedback offset generator 715) for implementing offset compensation (DFE correction value VDC 1) and for increasing high frequency gain (determined by RC time constants).

Because of the cascade of the first processing stage of 710/715 with the second processing stage of 720/725 and the third processing stage of 730/735, a greater signal gain may be produced between the input Vin and the final data result sampled at latch 740. A gain versus frequency plot for one such embodiment is shown in fig. 9, where "G" is the typical gain for a single processing stage consisting of two discrete time integration elements, each of which has a typical gain contribution of about 0.5G.

Each discrete-time integration element 710, 715, 720, 725, 730, 735 of fig. 7 may correspond to 210 described above in fig. 2. In an alternative embodiment, the alternately arranged processing stages 510 and 520 of FIG. 5 may be used for successive processing stages of FIG. 7.

It will be readily appreciated by those skilled in the art that the differential input of the illustrative discrete time integration element may be used as a single ended input by connecting the unused second input of the discrete time integration element to a suitable dc bias source and ac virtual ground. Alternatively, the fully differential embodiment of fig. 8 may be shared with any of the elements of fig. 2 and 5, all of which are considered equivalents in the present application.

The DFE voltage magnitudes VDC1, VDC2, VDC3 in fig. 7 (and the differential signal equivalent of these voltage values in fig. 8) may be used to correct for fixed offset voltage errors or as input values for the DFE correction signal.

It should be noted that the series of cascaded discrete-time integrators constitutes an analog signal memory or analog delay line form, as they deliver voltage output sample values in successive clock intervals. As such, when voltage input values are used for DFE correction, these input values may take the appropriate DFE correction value (i.e., the DFE correction value associated with the appropriate previous data value) at or before the sampling time point, where the correlation is with respect to the sampled signal being processed by the processing stage at that time point. For the embodiment shown in fig. 8 in which the correction voltage input value is a differential value, it is actually observed that when the previous bit is "1", the DFE correction value can be expressed as a pair of differential voltages { VDCa, VDCb }; when the previous bit is "0," the DFE correction value may be represented as an interchanged version of the pair of differential voltages { VDCb, VDCa }. Based thereon, the single DFE voltage amplitude VDC may be processed by an equivalent form of double pole double throw switch to direct the original value or the interchangeable value (of opposite polarity) to a system processing stage controlled by the previous data bit associated with the previous unit time interval.

In one embodiment, the DFE amplitude of { VDCa, VDCb } is selected to be a value such that the resulting voltages (directly obtained and obtained after the differential interchange process described above) not only meet the rules of the desired DFE correction value, but also normalize the undesired dc offset within the cascaded discrete-time integrator. In some embodiments, the DFE amplitude VDC may include a direct voltage offset component.

Another embodiment employs a modified discrete-time integrator embodiment as shown in fig. 10. Consistent with the situation of fig. 8, all signals are differential signals. To avoid confusion, it should be noted that the schematic diagram of fig. 10 corresponds to one complete processing stage 801, 802, 803 of fig. 8, which includes not only two discrete time integrators, RC filters, etc., but also the addition of switching elements for selectively interchanging the polarity of the DFE correction magnitudes controlled by the previous data input.

In this embodiment, the received analog input voltage Vin is sampled by transistors 1001, 1002, 1003, 1004, 1005 and amplified by the high frequency peaking provided by one of the differential pair of transistors 1011/1012 or 1021/1022 in the filter network RC, DFE offset generator, and transistor 1040. The pair of differential transistors is selected by transistors 1031/1032 based on the previous data DH [ N ] + and DH [ N ] -, and the high frequency peaking result amplifies the sampled analog voltage output values Vout+ and Vout-by direct analog forms of VDC+ and VDC-voltages or differential interchangeable equivalents thereof.

In some embodiments, an apparatus comprises: a memory 1160 for storing one or more previous data values; a Decision Feedback Equalization (DFE) computation circuit 1150 for generating DFE magnitudes; a decision feedback offset generator (e.g., 1110, 1120, 1130) for receiving a DFE amplitude VDC and a previous data value DH N among the one or more previous data values, and for responsively generating an analog DFE correction value having a voltage amplitude equal to the DFE amplitude and a polarity determined by the previous data value received from the memory; and an analog sampler for receiving an analog addition signal of the analog DFE correction signal and the analog input signal Vin, and for generating a sampling voltage output signal Va according to a sampling clock Ck 1. In the above embodiment, the analog input signal Vin and the sampling voltage output signal Va are both for the decision feedback offset generator 1110.

In some embodiments, the analog input signal is a sampled voltage output signal received from a cascaded analog sampler. In other embodiments, the analog input signal corresponds to an analog output signal of a multi-input comparator.

In some embodiments, the decision feedback offset generator includes: a pair of decision feedback branches 1011/1012 and 1021/1022, each receiving DFE magnitudes for a corresponding structure having opposite polarities, respectively; and a selection circuit 1031/1032 for receiving a previous data value and enabling one of the pair of decision feedback branches to determine a polarity of the DFE correction value accordingly. In some embodiments, the decision feedback offset generator is further configured to receive a high frequency injected analog input signal Vin. In some embodiments, the analog input signal injected at high frequency is received by a resistive-capacitive high pass filter. In some embodiments, the decision feedback offset generator is further configured to voltage offset signals.

In some embodiments, the sampled voltage output signal has a propagation delay of less than one unit interval relative to the received analog input signal. In other embodiments, the sampled voltage output signal has a propagation delay greater than one unit interval relative to the received analog input signal. In some embodiments, the memory includes a shift register.

The complete multi-stage embodiment shown in fig. 11A employs three of the processing stages of fig. 10, shown as 1110, 1120, 1130, respectively, and utilizes the analog delay characteristics of a cascaded discrete-time integrator by constructing as follows: the differential input VDC1 is composed of a DFE correction calculation value of the previous unit interval [ N-3] and a third previous data value DH < -3 >; VDC2 is composed of a DFE correction calculation value of the previous unit interval [ N-2] and a second previous data value DH < -2 >; VDC3 is composed of the DFE correction calculation value of the previous unit interval [ N-1] (i.e., the previous unit interval) and the previous data value DH < -1 > (all of these time representations are for the current signal input Vin). As such, for a given data value, the data value may be provided with a full period of three unit intervals in duration before it is used by the DFE system. As a non-limiting example, a digital shift register 1160 is shown for storing the previous data values and providing them to the processing stages 1130, 1120, 1110 (i.e., 1160 shifted to the left in this example), each data value being sampled and detected by a latch 1140 and provided to the data output Vout. The DFE calculation 1150 is illustrated as providing the aforementioned DFE correction magnitudes VDC1, VDC2, VDC3 that represent the contribution of a given previous unit interval to the observed degree of disturbance of the received signal at the current unit interval. In some embodiments, VDC1, VDC2, VDC3 may be represented as voltage magnitudes, the polarity of which is determined by previous data values. Each such voltage, when combined with the polarity determined by the selection information provided by the previous data bit of the respective previous unit time interval, produces a DFE correction value (also referred to herein as a DFE compensation value) suitable for the respective processing stage to correct the signal being sampled. As shown, each of the processing stages 1110-1130 receives a clock having a corresponding amount of delay. In some embodiments, the delay between any adjacent clocks (CK 1/CK2, CK2/CK 3) may be on the order of 5 to 15 picoseconds. Or each clock may have a fixed phase relationship, such as a quadrature phase relationship generated by a local oscillator within a phase locked loop. Such an oscillator may take the form of a ring oscillator, such as ring oscillator 1180 shown in fig. 11C.

For descriptive purposes, the embodiments in the present application show a case where three cascaded processing stages are employed, but this is not meant to be limiting. But other processing stages may be added as needed, for example, to provide additional gain and/or to support more distant DFE correction of previous values by providing additional corrected dc voltage magnitude input values; or fewer processing stages may be used, for example, when less gain and/or less corrected dc voltage magnitude input values are sufficient. Similarly, the various apparatus and methods disclosed herein may be combined with one another and with the prior art, for example, to achieve offset voltage adjustment, and additionally introduce DFE correction value voltages within a single processing stage, which may be an element of a multi-stage system.

For descriptive purposes, embodiments of the present application describe cascaded processing stages consisting of a single clock-triggered sampling element to introduce a delay of one clock cycle at each processing stage. However, this is not meant to be limiting, and the triggering of the individual processing stages can also be achieved by a plurality of clock phases with any desired time relationship, as long as the setting and holding times required by the specific embodiment are met. As such, the total delay time of the entire cascade may be either a fraction of a clock cycle or multiple clock cycles, provided that the clock phase setting for triggering is reasonable.

In some implementations, for the first processing stage 1110, there may be a group delay t ₁ from the output Va as a function of the input Vin. In such an embodiment, CK2 may be delayed by an amount of time of at least t ₁ in order to stabilize the input signal Va of the processing stage 1120 by maintaining the charge of VDD at the output node of 1120 for a sufficiently long time. In some implementations, CK1 may be passed through delay elements (not shown) to generate clocks CK2, CK3, CK4, where the delay elements introduce at least a delay amount t _n,t_n within each clock as a group delay associated with a given processing stage. In some implementations, the group delay value may be associated with the transistor capacitance of each processing stage, as well as various other factors known to be capable of causing group delay. In most practical embodiments, t _n is about the same. In some embodiments, t _n is about 5 to 15 picoseconds, although this should not be taken as limiting. Fig. 11B shows a delay buffer for generating clock signals CK2 to CK4 from CK 1. As shown, a plurality of serially connected buffer gates 1171-1173 are used to provide clock signals CK 2-CK 4, respectively, according to CK 1. Each buffer gate provides a delay corresponding to the group delay value t _n. Fig. 13A illustrates an exemplary relationship between clocks CK1 and CK2 according to some embodiments. Or clocks CK 1-CK 4 may be local oscillator clocks in various phases, which are generated by a phase-locked loop, as a non-limiting example. Fig. 11C illustrates one such embodiment, in which a local oscillator 1180 provides clock signals CK 1-CK 4 in four phases, respectively. In some implementations, consistent with the embodiment shown in fig. 11C, all adjacent clock signals may have a relative phase relationship of 45 degrees. In other implementations, all adjacent clock signals may have a relative phase relationship of 90 degrees (not shown). The conditions of use of such embodiments may be: the analog sample voltage on the output node of a given processing stage does not begin to decay toward VSS until the rising edge clock CK of the next processing stage. Fig. 13B shows an embodiment in which the phase difference between the clocks CK1 and CK2 is 45 degrees, but it should be noted that any phase difference relationship may be employed as long as the phase difference relationship satisfies the above rule.

Improvement of driving capability

It should also be noted that the results produced by the dynamic sampler/integrator processing stage and the integral hold processing stage of the present application are less affected by the output load, for example, compared to the output of a Continuous Time Linear Equalizer (CTLE) circuit operating in a linear amplification mode. In a linear amplifier, the additional load capacitance reduces the high frequency response of the circuit, and compensating for this characteristic tends to result in a significant increase in the power consumption of the linear circuit. In contrast, the extra sampler/integrator output capacitance delays the time interval at most when the output value is active. As a means of correction of this delay, the output drive current can be moderately increased (much lower than that of an equivalent continuous-time circuit), or small adjustments can be made to the clock timing pattern used for result latching or sampling.

This greater resistance to output loading is particularly helpful in cases where the signal fans out to multiple subsequent processing stages, as shown in fig. 4, transitioning from a two-stage clock domain to a four-stage clock domain.

Fig. 15 shows another receiver embodiment comprising a sampler 1510 comprising a plurality of cascaded integrating processing stages downstream of which are a plurality of slicing circuits, wherein the data slicing circuits comprising a sampler/integrator 1520 and corresponding latch 1550 are aided by a clock data recovery slicing circuit comprising a sampler/integrator 1530 and corresponding latch 1560 and a statistical monitoring slicing circuit comprising a sampler/integrator 1540 and corresponding latch 1570, each slicing circuit generating received data results, respectively, timing information enabling clock/data recovery adjustment of the clock generator and statistical receive "eye" information of the command/control/monitoring subsystem. If the received signal 1515 is derived directly from an output value in the form of a continuous-time analog differential voltage of a linear amplification processing stage such as a CTLE or MIC mixer, the total capacitive load of the plurality of slicing circuits will result in a very large frequency domain pole-affecting high frequency response. Further, as the load on the CTLE processing stage increases, the current used to maintain the load increases in a non-linear manner, thereby significantly increasing power consumption. However, by introducing the sampler 1510 (in this embodiment, two integration processing stages are illustrated in tandem, but this is not meant to be limiting), not only can the signal 1515 be driven in the form of an integrated analog differential voltage, but also a relative resistance to the loading effects described above can be achieved, thereby improving the overall received signal quality while also enabling other continuous time designs with less power consumption than the same class.

In some embodiments, a method comprises: a continuous-time analog differential voltage Vin is obtained at the input processing stage of the sampler 1510 and an integrated analog differential voltage 1515 is generated by discharging a pair of pre-charged output nodes from the continuous-time analog differential voltage during an integration period. The integration period is started by a sampling clock. The integrated analog differential voltage is then provided to a plurality of slicing circuits (such as, but not limited to, a data slicing circuit comprising a sampler/integrator 1520 and a latch 1550), each of which has an input connected to the pair of output nodes, and generates a respective slice output signal in accordance with a respective slice threshold from among a set of slice thresholds. As shown in fig. 15, the integrated analog differential voltage on node 1515 may correspond to a hold voltage Vb generated by an integrated hold processing stage, each of the slicing circuits including a respective sampler/integrator 1520, 1530, 1540 for applying the offset of the respective slice and generating a respective local differential voltage vc_data, vc_cdr, vc_eye on a fully discharged node, each local differential voltage being latched in a respective latch 1550, 1560, 1570, respectively.

Preferably, the latch is connected to a pair of output nodes that are fully discharged, because the fully discharged nodes can prevent problems of increased current dissipation time and power that may result from holding a differential voltage at the latch inputs. It should be noted, however, that some embodiments may provide the hold integral analog differential voltage generated by the integral hold processing stage directly to the latch. In some embodiments, it may be advantageous to provide a multi-stage sampler consisting of an odd number of cascaded integrating processing stages upstream of the latches used to generate the slice output. In fig. 15, three cascaded processing stages are provided upstream of each latch to ensure that the node connected to the latch input is fully discharged. Specifically, as can be seen from an analysis of fig. 15, the node generating the intermediate voltage Va is completely discharged, so that eventually the integrating processing stage generating the voltage Vb achieves the retention of the differential voltage due to Va provided at the input of the second processing stage falling below the threshold voltage of the corresponding transistor. The sampler/integrators 1520, 1530, 1540 within each slicing circuit will then all generate local differential voltages for supply to latches 1550, 1560, 1570 on the nodes to be fully discharged. In some embodiments, the cascade processing stages of the multi-stage sampler alternate between: (i) an integration stage in which the output node is fully discharged; and (ii) an integral holding stage that stops discharging the output node when the input voltage connected to the previous integral processing stage drops below the input transistor operating threshold voltage. In the example of fig. 18 described below, a single integration processing stage for providing integrated analog differential voltages to the full discharge nodes of the plurality of slicing circuits of latches is employed, along with additional analog adders for adjusting the respective slicing thresholds by applying offset correction values.

In the example of fig. 15, the integration processing stages within samplers 1510, 1520, 1530, 1540 support analog voltage offset inputs, such as those described above with reference to the fig. 10 embodiment. As shown, the offset input of the cascaded integrator stage within sampler 1510 is used to receive the previous DFE correction value, while the slice offset inputs of samplers 1520 and 1530 determine the slice threshold levels for detecting the data value and timing signal edges, respectively. Integrated analog differential voltage 1515 sampling for data, CDR, and eye patterns can be achieved by introducing prior DFE correction values within multiple cascaded integrating processing stages at 1510, whereas prior art methods employ the addition of multiple DFE correction value components to be added to the respective sampler threshold inputs, respectively. This structural flexibility is applicable to a number of aspects. In some embodiments, the data sampler 1520 and CDR sampler 1530 are configured to receive predicted DFE correction values that are inverted with respect to each other. In such embodiments, a first predictive DFE correction for the data sampler 1520 may provide transition information by comparing the detected data result with a previous data result, while a second (i.e., inverted) predictive DFE correction for the CDR sampler 1530 may provide information indicative of timing early/late for the CDR circuit to adjust the phase of the baud rate clock. Such implementations may select one predictive DFE correction value for use by the data slicing circuit and another predictive DFE correction value for use by the edge slicing circuit based on a previous detected data value.

In one embodiment, DFE correction value 1 and DFE correction value 2 represent previous DFE correction values associated with data values received within the third and second nearest unit intervals, respectively. The data sample slice threshold is comprised of a sampler correction offset voltage, a sampler threshold voltage, and a DFE correction calculation associated with a data value received within a last unit interval. The edge sampling slice threshold is composed of a sampler correction offset voltage and a sampler threshold voltage. It has been observed that baud rate CDR sampling (e.g., the baud rate CDR sampling method employed by the present application) can be facilitated by ignoring the most recently received CDR correction component. The eye sample slice threshold is comprised of a sampler correction offset voltage, an adjustable eye sample threshold voltage, and a DFE correction calculation associated with a received data value of a previous unit interval, wherein the DFE correction calculation is an optional component. In some implementations, the integration periods of samplers 1520 and 1530 are triggered by a baud rate clock that occurs at or near the "eye center".

In one embodiment, all samplers are triggered by a single baud rate clock, wherein the offset input of sampler/integrator 1540 may be adjusted, for example, by a command/control/monitoring subsystem, to obtain the received signal level statistical samples required for generation of the statistical signal amplitude data pattern. In another embodiment, in addition to triggering the data sampler 1520 with a baud rate clock, for example, acquisition of statistical signal samples representing both amplitude and phase information is accomplished by triggering the eye sampler 1540 with an optional phase-adjustable eye sampling clock.

In the existing DFE embodiment, a single result is obtained by summing or combining the compensation value calculation results of a plurality of unit intervals in an inherent manner. In the second embodiment, the correction value obtained by the above-described combination is applied to the processing stage 1510, and the correction value for the previous unit interval data is optionally negated or the inverted value thereof is applied to the sampler 1530. Further, 1510, 1520, 1530, 1540 other combinations of the respective DFE correction values, the DFE correction values obtained by combination or addition, and a fixed or adjustable offset voltage may be applied thereto, but this is not a limitation.

Fig. 18 is a block diagram of another embodiment, wherein the slicing circuit is comprised of latches 1820/1830/1840, one non-limiting example of which is a logic SR latch, and a corresponding analog adder 1817/1827/1837. As shown in fig. 18, a sampler 1810 receives a continuous time analog differential voltage Vin at an input processing stage and generates an integrated analog differential voltage Va on a differential output node 1815. After each slice threshold is offset by analog adder 1817/1827/1837, the resulting corrected integrated differential voltage is provided to a corresponding latch 1820, 1830, 1840. When the integration period is started by the sampling clock, the input processing stage 1810 begins to discharge the pair of output nodes 1815 at different rates due to the continuous-time differential voltage Vin applied to the input, thereby achieving integration. During discharge of the output node 1815, the latch generates a slice output from the corrected integrated analog differential voltage and maintains the slice output all the time even after the pair of output nodes are completely discharged.

DFE pre-correction

The DFE correction described above is applied to the receiver and is used to correct the abnormality of the current detection signal caused by the received signal in the previous unit interval. In general terms in the art, such corrections may be referred to as "post" corrections. In addition to this, there is also a "pre" correction, and in fact, the "pre" correction is often applied in the transmitter (from time to time, the transmitter gets the previous data value and the subsequent data value to be sent) as a loop of so-called finite impulse response compensation or "pre-shaping" implemented on the transmitted waveform.

A method of applying a pre-correction at a receiver may include: passing the actual signal value to be detected through a delay; using the "subsequent" received value, i.e., the undelayed received value, as a correction value for the delayed received value; the received values are then delayed for sampling.

In the case of the pre-correction of a single unit interval, the received signal may be delayed by one unit interval. In this way, in one non-limiting embodiment, a 25 Gbps/line received signal stream and a delay of 40 picoseconds may be achieved.

The received signal values may be delayed by a series of cascaded processing stages, which may include, for example, a sample-and-hold (SIH) processing stage, a sample-and-hold (SH) processing stage, or a combination of both. This use is readily available with the various dynamic sampler embodiments described above and shown in fig. 3, 5, 16, as well as other prior art SIH and SH embodiments. It should be noted that a single fig. 5 sampler (e.g., 510) can only provide a short effective hold time because its integrated analog differential voltage continues to decay to ground voltage after it decays out of its linear region from its precharge value. However, in a plurality of integrating processing stages 510 that are sequentially cascaded, clocked in a substantially synchronous or group delay manner as described above, the second sampler stops attenuating once the first sampler drops sufficiently to turn off its input transistor during its attenuation toward ground, effectively extending the hold time of the second sampler.

The embodiment of fig. 16 provides a series of crystals within each sampler controlled by the output of that sampler to further enhance the above effect. Wherein for each output, as it decays, it may cut off the discharge path of the respective sampler, thereby extending its effective hold time.

Fig. 17 shows a receiver implementation employing both pre-compensation and post-DFE correction as shown in fig. 15. Wherein the continuous-time analog differential voltage Vin passes through cascaded sample-and-integrate-and-hold processing stages 1705, which together represent a delay of one unit interval. The undelayed continuous-time analog differential voltage is added 1706 to the delayed signal after amplification 1702 to achieve the desired pre-compensation. Subsequently, as described above with reference to fig. 15, the downstream sample-and-hold processing stage 1710 may implement DFE correction values 1,2,3 and the addition of slicing circuits 1720, 1730, 1740 to capture data, clock errors, and eye values.

Receiving method

Fig. 12 is a flow chart of a method 1200 according to some embodiments. As shown, the method 1200 includes, in step 1202, receiving a previous data value from a memory storing one or more previous data values and receiving a DFE magnitude from a Decision Feedback Equalization (DFE) calculation circuit. In step 1204, an analog DFE correction value is generated by a decision feedback offset generator, the analog DFE correction value having a voltage magnitude equal to the DFE magnitude and a polarity determined by previous data values received from the memory. In step 1206, an analog input signal is received. In step 1208, the addition of the analog DFE correction value to the received analog input signal is responsively generated. In step 1210, the sampler generates a sampling voltage output signal by sampling the analog addition result according to a sampling clock.

In some embodiments, the analog input signal is a sampled voltage output signal received from a cascaded analog sampler. In other embodiments, the analog input signal corresponds to an analog output of a multi-input comparator.

In some embodiments, generating the DFE correction value includes: receiving, by a pair of decision feedback branches, DFE magnitudes having respective opposite polarity configurations; and selecting one of the pair of decision feedback branches by a selection circuit for receiving the previous data value to determine a polarity of the DFE correction value.

In some embodiments, the DFE magnitude includes a high frequency injection of the analog input signal. In some embodiments, the high frequency injection of the analog input signal is received by a resistive-capacitive high pass filter. In some embodiments, the DFE magnitude includes a voltage offset signal.

In some embodiments, the propagation delay of the sampled voltage output signal relative to the received analog input signal is less than one unit interval. In other embodiments, the propagation delay of the sampled voltage output signal relative to the received analog input signal is greater than one unit interval. In some embodiments, the memory includes a shift register.

Fig. 14 is a flowchart of a method 1400 according to some embodiments. As shown, the first amplification stage receives a first analog input signal and a first Decision Feedback Equalization (DFE) correction value in step 1402 and generates a first analog output voltage responsive to a rising edge of a first sampling clock in step 1404, the first output voltage having a corresponding group delay value relative to the first input signal. In step 1406, the second amplification stage receives the first analog output voltage and the second DFE correction value and generates a second analog output voltage in step 1408 in response to a rising edge of a second sampling clock having a delay amount relative to the rising edge of the first sampling clock that is greater than the corresponding group delay value. In step 1410, a sampled output data bit is generated by a preset latch by sampling the second analog output voltage according to a rising edge of a third clock signal, the third clock signal rising edge having a delay relative to the second clock signal rising edge.

In some embodiments, the method includes generating the second and third clock signals by a delay element that receives the first clock signal as an input signal. In such embodiments, the delay values may be arbitrarily adjusted by adjusting parameters (capacitive parameters, etc.) of the delay elements.

In some embodiments, the first, second, and third clock signals have respective fixed phase differences. In such embodiments, the clock signal with the fixed phase difference is generated by a Phase Locked Loop (PLL).

In some implementations, each DFE correction value has: (1) an amplitude associated with the DFE amplitude calculation; and (ii) symbols determined from previous data bits.

In some embodiments, the first received analog input signal is an analog voltage output signal received from a third amplification processing stage.

Fig. 19 is a flow chart of a method 1900 according to some embodiments. In method 1900, a continuous-time analog differential voltage is obtained 1902 by an input processing stage of a sampler for responsively generating an integrated analog differential voltage by discharging a pair of pre-charged output nodes from the continuous-time analog differential voltage over an integration period, the integration period being initiated by a sampling clock. The integrated analog differential voltage provides 1904 to a plurality of slicing circuits having inputs connected to the pair of output nodes, each slicing circuit of the plurality of slicing circuits generating a respective slice output signal from a respective slice threshold of a set of slice thresholds.

In some embodiments, the method further comprises generating one or more intermediate signals (as Va in fig. 15) by one or more cascaded processing stages connected to the sampler input processing stage, the one or more cascaded processing stages applying respective amplification operations to the integrated analog differential voltages, respectively. In some such embodiments, the one or more intermediate signals include a held differential voltage Vb generated by an integral holding processing stage of the one or more cascaded processing stages. In another embodiment, the method includes generating the integrated analog differential voltage by integrating a hold differential voltage generated by an integrated hold processing stage of the one or more cascaded processing stages.

In some implementations, the slicing circuit includes latches for generating respective slicing output signals. In some implementations, the set of slice thresholds includes a predictive DFE offset correction value. In some implementations, the set of slice thresholds includes edge sampling correction values. In some implementations, the method further includes introducing, by the input processing stage, a previous DFE correction value to the continuous-time analog differential voltage.

Claims

1. An apparatus, comprising:

a memory for storing one or more previous data values;

A Decision Feedback Equalization (DFE) computation circuit for generating a differential DFE magnitude;

A decision feedback offset generator for receiving said differential DFE magnitude and one of said one or more previous data values at first and second differential transistor pairs and responsively generating an analog DFE correction value having a voltage magnitude equal to said differential DFE magnitude, the polarity of said analog DFE correction value being determined by selecting said first or second differential transistor pair based on said previous data value received from said memory;

An input differential transistor pair for receiving an analog input signal and responsively generating an analog output signal; and

And a pair of common output nodes connected to the differential output of the decision feedback offset generator and the input differential transistor pair, the pair of common output nodes for forming an analog sum of the analog DFE correction value and the analog output signal.

2. The apparatus of claim 1, wherein the analog input signal is an analog voltage output signal received from a cascaded analog sampler.

3. The apparatus of claim 1, wherein the analog input signal corresponds to an analog voltage output signal of a multi-input comparator.

4. The apparatus of claim 1, wherein the first and second differential pairs of the decision feedback offset generator are further for receiving a high frequency injection of the analog input signal.

5. The apparatus of claim 4, wherein the high frequency injection of the analog input signal is received by a resistive-capacitive high pass filter.

6. The apparatus of claim 1, wherein the first and second differential pairs of the decision feedback offset generator are further for receiving a voltage offset signal.

7. The apparatus of claim 6, wherein the voltage offset signal is associated with a sampling offset value.

8. The apparatus of claim 1, wherein the memory comprises a shift register.

9. The apparatus of claim 1, further comprising a reset circuit to precharge the common output node based on a sampling clock.

10. The apparatus of claim 9, wherein the analog DFE correction value and the analog addition result of the analog output signal are formed in response to the sampling clock.

11. A method, comprising:

Retrieving (i) prior data values from a memory storing one or more prior data values, and (ii) a differential DFE magnitude from a Decision Feedback Equalization (DFE) calculation circuit;

Providing the differential DFE amplitude to first and second differential pairs of transistors of a decision feedback offset generator, and responsively generating an analog DFE correction value having a voltage amplitude equal to the differential DFE amplitude, the polarity of the analog DFE correction value being determined by selecting the first or second differential pair based on the previous data value received from the memory;

Receiving an analog input signal at an input differential transistor pair and responsively generating an analog output signal; and

An analog sum of the analog DFE correction value and the analog output signal is generated on a pair of common output nodes connecting the differential output of the decision feedback offset generator and the input differential transistor pair.

12. The method of claim 11, wherein the analog input signal is an analog voltage output signal received from a cascaded analog sampler.

13. The method of claim 11, wherein the analog input signal corresponds to an analog voltage output signal of a multi-input comparator.

14. The method of claim 11, further comprising receiving a high frequency injection of the analog input signal at the first and second differential pairs of the decision feedback offset generator.

15. The method of claim 14, wherein the high frequency injection of the analog input signal is received by a resistive-capacitive high pass filter.

16. The method of claim 11, further comprising receiving a voltage offset signal at the first and second differential pairs of the decision feedback offset generator.

17. The method of claim 16, wherein the voltage offset signal is associated with a sampling offset value.

18. The method of claim 11, wherein the memory comprises a shift register.

19. The method of claim 11, further comprising precharging the common output node with a reset circuit according to a sampling clock.

20. The method of claim 19, wherein the analog DFE correction value and the analog addition result of the analog output signal are formed in response to the sampling clock.