CN115603767B

CN115603767B - A broadband tunable receiver

Info

Publication number: CN115603767B
Application number: CN202211229211.3A
Authority: CN
Inventors: 高志强; 杨静致; 翁振豪
Original assignee: Harbin Institute of Technology Shenzhen
Current assignee: Harbin Institute of Technology Shenzhen
Priority date: 2022-10-09
Filing date: 2022-10-09
Publication date: 2025-02-11
Anticipated expiration: 2042-10-09
Also published as: CN115603767A

Abstract

The invention discloses a broadband tunable receiver, which includes a low noise amplifier unit, a mixer unit, and an active low pass filter unit, wherein: the mixer unit includes a mixer 1 and a mixer 2; the active low pass filter unit includes an active low pass filter 1 and an active low pass filter 2; the output positive end of the low noise amplifier is simultaneously connected to the input positive ends of the mixer 1 and the mixer 2, and the output negative end is simultaneously connected to the input negative ends of the mixer 1 and the mixer 2; the output negative end of the mixer 1 is connected to the input positive end of the active low pass filter 1, and the output positive end is connected to the input negative end of the active low pass filter 1; the output negative end of the mixer 2 is connected to the input positive end of the active low pass filter 2, and the output positive end is connected to the input negative end of the active low pass filter 2. The invention has the characteristics of high gain, high bandwidth, high linearity, and low noise on the basis of realizing signal reception, down conversion, and clutter suppression.

Description

Broadband tunable receiver

Technical Field

The invention belongs to the field of electronic information, and relates to a receiver, in particular to a broadband tunable receiver.

Background

With the development of wireless communication technology, the wide coexistence of multi-band, multi-mode and multi-standard wireless communication applications will become an important trend. Integrating systems supporting multiple communication standards on a single chip at low cost is a current research hotspot.

The receiver structure adopting the integrated N-channel filter can accurately control the center frequency through the digital switch to adjust the position of the passband, and has the advantages of good frequency selectivity, high linearity, strong out-of-band rejection capability and the like, so that the receiver integrating the N-channel filter has wide application prospect in a multimode and multifrequency radio communication system.

Disclosure of Invention

The invention aims to provide a broadband tunable receiver, which adopts a low-noise amplifier with an embedded balun as an input stage, reduces the extra area required by the external balun and has lower noise, adopts an N-channel filter structure as a mixer, and can realize quadrature modulation signals by means of a single clock source in a tunable manner without consuming extra power compared with the traditional mixer, and adopts an active low-pass filter structure at an output stage, thereby further enhancing the out-of-band rejection capability of the receiver and having higher in-band gain compared with the traditional passive mixing receiver.

The invention aims at realizing the following technical scheme:

A wideband tunable receiver comprising a low noise amplifier unit, a mixer unit, an active low pass filter unit, wherein:

The low-noise amplifier unit is a single-ended input and differential output low-noise amplifier;

The mixer unit comprises a mixer 1 and a mixer 2 which are identical in structure, each mixer is driven by a group of clock signals with the same frequency and the phase difference of 180 DEG, and the mixers of different channels are driven by the clock signals with the same frequency and the phase difference of 90 DEG;

The active low-pass filter unit comprises an active low-pass filter 1 and an active low-pass filter 2 which have the same structure;

The output positive end of the low-noise amplifier is simultaneously connected with the input positive end of the mixer 1 and the input positive end of the mixer 2, and the output negative end of the low-noise amplifier is simultaneously connected with the input negative end of the mixer 1 and the input negative end of the mixer 2;

the output negative end of the mixer 1 is connected with the input positive end of the active low-pass filter 1, the output positive end of the mixer 1 is connected with the input negative end of the active low-pass filter 1, and the active low-pass filter 1 outputs fully-differential signals I+ and I-;

The negative output end of the mixer 2 is connected with the positive input end of the active low-pass filter 2, the positive output end of the mixer 2 is connected with the negative input end of the active low-pass filter 2, and the active low-pass filter 2 outputs fully-differential signals Q+ and Q-.

In the invention, one path of input signal is converted into two paths of fully differential signals through a low noise amplifier unit, the two paths of fully differential signals are simultaneously input into two paths of mixer units, four paths of low-pass filtering channels are formed through connecting an active low-pass filter unit, and the four paths of output signals are formed through the active low-pass filter unit, wherein the signals output by a single active low-pass filter unit are differential signals, and the signals output by different active low-pass filter units are mutually orthogonal.

In the present invention, the mixer 1 and the mixer 2 are each realized by a switch constituted by NMOS transistors.

In the invention, the frequency modulation function is realized by driving the mixer 1 and the mixer 2 by square wave clock signals.

In the invention, the mixer 1 is driven by square wave clock signals with the frequency of flo initial phase of 0 degrees and the frequency of flo initial phase of 180 degrees together, and the mixer 2 is driven by square wave clock signals with the frequency of flo initial phase of 90 degrees and the frequency of flo initial phase of 270 degrees together.

In the invention, the active low-pass filter unit adopts a parallel resistance-capacitance network as a feedback form of a transimpedance amplifier to form a first-stage filter, the passive resistance-capacitance network forms a second-stage filter, and the active low-pass filter unit is a second-order filter.

Compared with the prior art, the invention has the following advantages:

1. compared with the traditional radio frequency receiver, the invention has the advantage of being tunable and can receive signals in a broadband range.

2. Compared with the traditional radio frequency receiver, the invention adopts a multi-stage active structure and has the characteristic of high gain.

3. Compared with a receiver integrated with a Gilbert mixer unit, the invention adopts an N-channel mixer, has higher linearity, simpler structure and smaller area, and does not need to consume extra power.

4. Compared with the low-noise amplifier at the front end of the traditional radio frequency receiver, the low-noise amplifier has the characteristic of embedded balun, avoids the extra area of the on-chip balun, and has the characteristics of high gain, large bandwidth and high linearity.

Drawings

Fig. 1 is a block diagram of a wideband tunable receiver.

Fig. 2 is a circuit diagram of a balun-embedded low noise amplifier cell.

Fig. 3 is a circuit diagram of a mixer.

Fig. 4 is a circuit diagram of an active low pass filter.

Fig. 5 is a circuit diagram of a transimpedance amplifier.

Fig. 6 is a receiver transient simulation diagram.

Fig. 7 is a simulation diagram of the noise figure of the receiver.

Fig. 8 is a simulation diagram of receiver linearity.

Detailed Description

The following description of the present invention is provided with reference to the accompanying drawings, but is not limited to the following description, and any modifications or equivalent substitutions of the present invention should be included in the scope of the present invention without departing from the spirit and scope of the present invention.

The invention provides a wideband tunable receiver, as shown in fig. 1, comprising a low noise amplifier unit, a mixer unit, an active low pass filter unit, wherein:

The negative output end of the mixer 1 is connected with the positive input end of the active low-pass filter 1, and the positive output end of the mixer 1 is connected with the negative input end of the active low-pass filter 1;

the negative output end of the mixer 2 is connected with the positive input end of the active low-pass filter 2, and the positive output end of the mixer 2 is connected with the negative input end of the active low-pass filter 2.

As shown in fig. 2, the low noise amplifier unit includes 4 NMOS transistors NM1 to NM4,2 PMOS transistors PM1, PM2,3 resistors R1, R2, rf, wherein:

the source of the NMOS transistor NM1, the source of the NMOS transistor NM2 and the source of the NMOS transistor NM3 are simultaneously connected with VSS;

the source of the PMOS transistor PM1, the source of the PMOS transistor PM2, one end of the resistor R1 and one end of the resistor R2 are simultaneously connected with the VDD;

the drain of the PMOS transistor PM1 and the drain of the NMOS transistor NM1 are simultaneously connected to the source of the NMOS transistor NM 4;

the drain of the NMOS transistor NM2 and the drain of the PMOS transistor PM2 are simultaneously connected with the grid electrode of the transistor NM 3;

The gate of the NMOS transistor NM1, the gate of the PMOS transistor PM1, the gate of the NMOS transistor NM2, and the gate of the PMOS transistor PM2 are connected to each other and serve as the low noise amplifier input terminal VIN;

the drain electrode of the NMOS transistor NM3 is connected with the other end of the resistor R1 and is used as a positive output end VO+ of the low-noise amplifier;

The drain electrode of the NMOS transistor NM4 is connected with the other end of the resistor R2 and is used as a negative output end VO-of the low-noise amplifier;

the grid electrode of the NMOS transistor NM4 is connected with a bias voltage VB;

One end of the resistor Rf is connected with the input end VIN of the low noise amplifier, and the other end of the resistor Rf is connected with the grid electrode of the NMOS transistor NM 3.

As shown in fig. 3, the mixer 1 and the mixer 2 are each composed of 4 NMOS transistors NM5 to NM8, wherein:

the source electrode of the NMOS transistor NM5 is connected with the source electrode of the NMOS transistor NM7 and is used as a positive input end RF+ of the mixer;

the source of the NMOS transistor NM6 is connected with the source of the NMOS transistor NM8 and is used as a negative input end RF-of the mixer;

The drain electrode of the NMOS transistor NM5 is connected with the drain electrode of the NMOS transistor NM8 and is used as a positive output end VO+ of the mixer;

the drain of the NMOS transistor NM6 is connected with the drain of the NMOS transistor NM7 and is used as a negative output end VO-of the mixer;

The gates of the NMOS transistor NM5 and the NMOS transistor NM8 are connected with a digital clock CLK1;

the gates of the NMOS transistor NM6 and the NMOS transistor NM7 are connected to the digital clock CLK2.

As shown in fig. 4, the active low-pass filter 1 and the active low-pass filter 2 are each composed of 4 resistors R3 to R6,4 capacitors C1 to C3, CL, and a transimpedance amplifier TIA, wherein:

One end of the capacitor CL, one end of the capacitor C2 and one end of the resistor R4 are connected with the positive input end of the transimpedance amplifier TIA and serve as the positive input end VI+ of the active low-pass filter;

The other end of the capacitor CL, one end of the capacitor C1 and one end of the resistor R3 are connected with the negative input end of the transimpedance amplifier TIA and serve as the negative input end VI-of the active low-pass filter;

The other end of the capacitor C1, the other end of the resistor R3 and the negative output end of the transimpedance amplifier TIA are connected with one end of a resistor R6;

The other end of the capacitor C2, the other end of the resistor R4 and the positive output end of the transimpedance amplifier TIA are connected with one end of the resistor R5;

The other end of the resistor R5 is connected with one end of the capacitor C3 and is used as a negative output end VO-of the active low-pass filter;

the other end of the resistor R6 is connected with the other end of the capacitor C3 and is used as the positive output end VO+ of the active low-pass filter.

As shown in fig. 5, the transimpedance amplifier includes two NMOS transistors NM9, NM10, two PMOS transistors PM3, PM4, two resistors R7, R8, and a two-terminal input two-terminal output operational amplifier, wherein:

the source of the NMOS transistor NM9 and the source of the NMOS transistor NM10 are connected with VSS;

the source of the PMOS transistor PM3 and the source of the PMOS transistor PM4 are connected with VDD;

The grid electrode of the NMOS transistor NM9 is connected with the grid electrode of the PMOS transistor PM3 and is used as a positive input end IP of the transimpedance amplifier;

The gate of the NMOS transistor NM10 is connected with the gate of the PMOS transistor PM4 and is used as a negative input end IN of the transimpedance amplifier;

the drain electrode of the NMOS transistor NM9 and the drain electrode of the PMOS transistor PM3 are connected with one end of R7 and serve as a negative output end ON of the transimpedance amplifier;

The drain electrode of the NMOS transistor NM10 and the drain electrode of the PMOS transistor PM4 are connected with one end of R8 and serve as a positive output end OP of the transimpedance amplifier;

The other end of R7 and the other end of R8 are connected with the positive input end of an operational amplifier, the negative input end of the operational amplifier is connected with the common mode level Vcm, the negative output end of the operational amplifier is connected with the drain electrode of an NMOS transistor NM9 and the drain electrode of a PMOS transistor PM3, and the positive output end of the operational amplifier is connected with the drain electrode of an NMOS transistor NM10 and the drain electrode of a PMOS transistor PM 4.

The working principle is as follows:

As shown in fig. 1, the input signal enters the low noise amplifier unit, and is output as two differential signals, which enter the positive and negative input terminals of the mixer 1 and the mixer 2, respectively. Since each mixer is driven by a set of clock signals of the same frequency and with a phase difference of 180 °, the mixers of different channels are driven by clock signals of the same frequency and with a phase difference of 90 °, the signals output by a single mixer are 180 ° out of phase, the down-converted signals of the four signal paths are in quadrature with each other, and the phase difference is 90 °. And then the two fully differential active low-pass filters respectively carry out low-pass filtering on the four down-conversion signals, the fully differential signals output by the active low-pass filter 1 are I+ and I-, belong to I branches, and the fully differential signals output by the active low-pass filter 2 are Q+ and Q-, and belong to Q branches. I. The Q branch signals are mutually orthogonal.

As shown in fig. 2, the balun functions to convert a single-ended input signal into a positive and negative fully differential signal. The NMOS tube is connected with the grid electrode and the drain electrode of the PMOS tube to form the most basic AB class amplifier, the positive power supply voltage VDD is directly applied to the source electrode of the PMOS tube, and the negative power supply voltage VSS is directly applied to the source electrode of the NMOS tube, so that the maximum transconductance value is realized in the mode, and the amplifier has the characteristics of high gain and large bandwidth. The left half branch is connected with a common source common grid tube on the basis of an AB amplifier, so that the signal inversion characteristic is maintained and the gain is increased. The right half branch is added with a first-stage common source amplifier on the basis of the AB amplifier, and the signal inverted by the AB amplifier is inverted again to become an in-phase signal while the gain is increased, so that the characteristic of converting a single-ended input signal into positive and negative two paths of fully-differential signals is realized. By introducing the feedback resistor Rf, the equivalent noise of the input end is in opposite phase after passing through the right half branch, and the noise is still in opposite phase after passing through the left half branch, so that the aim of noise elimination is achieved in the differential operation of the input end, and the characteristic of low noise is realized.

As shown in FIG. 3, the mixer of the invention is composed of NMOS transistors, when the driving signal is at low level, the NMOS transistors work in the cut-off area to present high impedance, namely the switch is cut off and the frequency is cut off, when the driving signal is at high level, the NMOS transistors work in the deep triode area, the W/L value of the NMOS transistors is reasonably selected, the on-resistance of the NMOS transistors is smaller, the low impedance is presented, the switch is turned on, the frequency is passed, and the mixer composed of the NMOS transistor switches has the characteristics of simple structure and lower power consumption.

As shown in fig. 3, when the NMOS transistors are connected in the illustrated manner, the NMOS transistors have smaller on-resistance than when the NMOS transistors are directly used as the switches, and meanwhile, due to non-ideal factors of the switches, high-frequency clock signals may be coupled in the signal paths, and due to the adoption of cross coupling of the mixers, two pairs of inverted clocks are eliminated after the input ends are overlapped, so that the clock feedthrough is inhibited.

As shown in fig. 4, the mixed down-converted signal is affected by out-of-band interference, clock feedthrough, and harmonic components, so low pass filtering is required to suppress out-of-band influencing factors. The invention adopts an active low-pass filter structure based on a transimpedance amplifier TIA, a load capacitor CL firstly eliminates a high-frequency clock feed-through signal, a parallel resistor-capacitor network is used as a feedback network of the transimpedance amplifier, a main pole point of the low-pass filter is determined, the input impedance of the amplifier is reduced, and the low-impedance passive mixer structure is matched. The second stage adopts a resistance-capacitance low-pass filtering structure to increase out-of-band rejection capability.

As shown in fig. 5, the main body of the transimpedance amplifier is a class AB amplifier, and has the characteristics of high gain and large bandwidth. In order to stably output the common mode point, a common mode feedback structure is formed by a common mode detection resistor and an operational amplifier.

The invention adopts an amplifier with high gain as an input stage, adopts a transimpedance amplifier as an output stage to further improve the gain, and has the characteristic of high gain, and an input high-frequency signal, a clutter-containing down-conversion signal passing through a passive mixer and an output signal passing through a two-stage low-pass filter are shown in figure 6.

The invention adopts the connection mode of fig. 1, so that noise is mainly concentrated in the input stage, and the whole noise is very low due to the adoption of the low-noise amplifier, as shown in fig. 7.

The invention realizes a receiver with single-ended input and IQ branch output through a passive mixing channel formed by 4 NMOS transistors, improves the overall gain through a low noise amplifier and a transimpedance amplifier, reduces input noise, improves out-of-band rejection capability and linearity by using an active low-pass filter, and has higher out-of-band linearity as shown in figure 8.

The above embodiment shows that the invention has the characteristics of high gain, high bandwidth, high linearity and low noise on the basis of realizing signal receiving, down-conversion and clutter suppression, thereby meeting the use requirements of a multimode and multifrequency radio communication system.

Claims

1. A wideband tunable receiver, characterized in that the receiver comprises a low noise amplifier unit, a mixer unit, an active low pass filter unit, wherein:

the output negative end of the mixer 2 is connected with the input positive end of the active low-pass filter 2, the output positive end of the mixer 2 is connected with the input negative end of the active low-pass filter 2, and the active low-pass filter 2 outputs fully-differential signals Q+ and Q-;

The low noise amplifier unit comprises 4 NMOS transistors NM 1-NM 4,2 PMOS transistors PM1, PM2,3 resistors R1, R2, rf, wherein:

One end of the resistor Rf is connected with the input end VIN of the low noise amplifier, and the other end of the resistor Rf is connected with the grid electrode of the NMOS transistor NM 3;

the mixer 1 and the mixer 2 are each composed of 4 NMOS transistors NM5 to NM8, wherein:

the gates of the NMOS transistor NM6 and the NMOS transistor NM7 are connected with a digital clock CLK2;

The active low-pass filter 1 and the active low-pass filter 2 are composed of 4 resistors R3-R6, 4 capacitors C1-C3 and CL and a transimpedance amplifier TIA, wherein:

2. The wideband tunable receiver of claim 1, wherein the mixer 1 and the mixer 2 are driven by a square wave clock signal, thereby implementing a frequency modulation function.

3. The wideband tunable receiver of claim 1, wherein the mixer 1 is driven by a square wave clock signal having a frequency of flo initial phase of 0 ° and a frequency of flo initial phase of 180 °, and the mixer 2 is driven by a square wave clock signal having a frequency of flo initial phase of 90 ° and a frequency of flo initial phase of 270 °.

4. The wideband tunable receiver of claim 1, wherein the transimpedance amplifier comprises two NMOS transistors NM9, NM10, two PMOS transistors PM3, PM4, two resistors R7, R8 and a two-terminal-input-two-terminal-output operational amplifier, wherein: