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CN115443505A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN115443505A
CN115443505A CN202180029048.3A CN202180029048A CN115443505A CN 115443505 A CN115443505 A CN 115443505A CN 202180029048 A CN202180029048 A CN 202180029048A CN 115443505 A CN115443505 A CN 115443505A
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China
Prior art keywords
transistor
oxide
insulator
semiconductor device
terminal
Prior art date
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Pending
Application number
CN202180029048.3A
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Chinese (zh)
Inventor
广濑丈也
米田诚一
池田隆之
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of CN115443505A publication Critical patent/CN115443505A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Semiconductor Memories (AREA)

Abstract

A semiconductor device capable of holding analog data is provided, which uses four transistors and two capacitors to constitute two holding circuits, two bootstrap circuits, and one source follower circuit. The two holding circuits are respectively provided with storage nodes, one of which is written with a data potential and the other of which is written with a reference potential. In reading out data, the potential of one storage node in one bootstrap circuit is boosted, and the potential of the other storage node in the other bootstrap circuit is boosted. A source follower circuit is used to output a potential difference between two storage nodes. By using the source follower circuit, the output impedance can be reduced.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
One embodiment of the present invention relates to a semiconductor device.
One embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method or a method of manufacture. Further, an embodiment of the present invention relates to a process (process), a machine (machine), a product (manufacture), or a composition (material). Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in the present specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an image pickup device, a storage device, a signal processing device, a processor, an electronic apparatus, a system, a driving method thereof, a manufacturing method thereof, and an inspection method thereof.
Background
In recent years, electronic components such as a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), a storage device, and a sensor have been used in various electronic apparatuses such as a personal computer, a smart phone, and a digital camera. The electronic component is improved in miniaturization, low power consumption and the like.
In particular, in recent years, the amount of data used by electronic devices has increased, and therefore, a storage device having a large storage capacity has been required. Therefore, a memory device holding multi-valued data or analog data by one memory element has been studied and developed. Patent documents 1 and 2 disclose semiconductor devices capable of writing and reading multi-valued data.
[ Prior Art documents ]
[ patent document ]
[ patent document 1] Japanese patent application laid-open No. 2012-256400
[ patent document 2] Japanese patent application laid-open No. 2014-199707
Disclosure of Invention
Technical problem to be solved by the invention
There is a need for a semiconductor device capable of holding analog data for a long period of time and accurately reading the held analog data.
In a transistor in which a semiconductor layer forming a channel contains silicon (also referred to as a "Si transistor"), the size of the element is reduced with the reduction of process rules. In addition, as the miniaturization of the device progresses, the gate insulating film is becoming thinner, and a leakage current through the gate insulating film becomes a problem.
An object of one embodiment of the present invention is to provide a semiconductor device capable of holding analog data. Another object of one embodiment of the present invention is to provide a semiconductor device capable of accurately reading analog data held therein. Another object of one embodiment of the present invention is to provide a semiconductor device having a reduced occupied area. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device having a large storage capacity. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device.
Note that the object of one embodiment of the present invention is not limited to the above object. The above object does not hinder the existence of the other objects. The other objects refer to objects other than the above which will be described in the following description. A person skilled in the art can derive and appropriately extract objects other than those described above from the description of the specification, the drawings, and the like. One embodiment of the present invention achieves at least one of the above and other objects. In addition, it is not necessary for one embodiment of the present invention to achieve all of the above and other objects.
Means for solving the problems
One embodiment of the present invention is a semiconductor device in which two holding circuits, two bootstrap circuits, and one source follower circuit are formed using four transistors and two capacitors. The two holding circuits are respectively provided with storage nodes, one of which is written with a data potential and the other of which is written with a reference potential. In reading out data, the potential of one storage node in one bootstrap circuit is boosted, and the potential of the other storage node in the other bootstrap circuit is boosted. A source follower circuit is used to output a potential difference between two storage nodes. By using the source follower circuit, the output impedance can be reduced.
Another embodiment of the present invention is a semiconductor device including first to fifth circuits, in which the first circuit has a function of holding a first potential, the second circuit has a function of boosting the first potential, the third circuit has a function of holding a second potential, the fourth circuit has a function of boosting the second potential, and the fifth circuit has a function of outputting a third potential corresponding to a potential difference between the boosted first potential and the boosted second potential.
The semiconductor device may include, for example, first to fourth transistors, a first capacitor, and a second capacitor. The first circuit may include a first transistor and a first capacitor, the second circuit may include a second transistor and a first capacitor, the third circuit may include a third transistor and a second capacitor, the fourth circuit may include a fourth transistor and a second capacitor, and the fifth circuit may include a second transistor and a fourth transistor.
Another embodiment of the present invention is a semiconductor device including first to fourth transistors, a first capacitor, and a second capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first terminal, the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, the gate of the first transistor is electrically connected to a second terminal, one of a source and a drain of the third transistor is electrically connected to a third terminal, the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor, the gate of the third transistor is electrically connected to a fourth terminal, one of the source and the drain of the second transistor is electrically connected to a fifth terminal, the other of the source and the drain of the second transistor is electrically connected to a seventh terminal, the one of the source and the drain of the fourth transistor is electrically connected to a sixth terminal, the other of the source and the drain of the fourth transistor is electrically connected to a seventh terminal, one electrode of the first capacitor is electrically connected to the gate of the second transistor, the other electrode of the first capacitor is electrically connected to the seventh terminal, and the second capacitor is electrically connected to the second terminal.
The third terminal may be electrically connected to the sixth terminal. The first transistor and the third transistor preferably include an oxide semiconductor in a semiconductor layer which forms a channel. In addition, the second transistor and the fourth transistor preferably include an oxide semiconductor in a semiconductor layer in which a channel is formed. The oxide semiconductor preferably contains at least one of indium and zinc.
Effects of the invention
According to one embodiment of the present invention, a semiconductor device capable of holding analog data can be provided. Further, according to an embodiment of the present invention, a semiconductor device capable of accurately reading analog data held therein can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a reduced occupied area can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a large storage capacity can be provided. Further, according to an embodiment of the present invention, a highly reliable semiconductor device can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided.
Note that the effect of one embodiment of the present invention is not limited to the above-described effect. The above effects do not hinder the existence of other effects. The other effects refer to effects other than the above described ones which will be described in the following description. A person skilled in the art can derive and appropriately extract effects other than those described above from the description of the specification, drawings, and the like. One embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the above-described effect.
Brief description of the drawings
Fig. 1A and 1B are circuit diagrams of a semiconductor device according to one embodiment of the present invention.
Fig. 2A and 2B are circuit diagrams of a semiconductor device according to one embodiment of the present invention.
Fig. 3A and 3B are circuit diagrams of a semiconductor device according to one embodiment of the present invention.
Fig. 4A and 4B are diagrams showing circuit symbols of transistors.
Fig. 5A and 5B are diagrams illustrating a source follower circuit.
Fig. 6 is a timing chart illustrating an operation example of the semiconductor device.
Fig. 7A and 7B are diagrams illustrating an operation example of the semiconductor device.
Fig. 8A and 8B are diagrams illustrating an operation example of the semiconductor device.
Fig. 9 is a circuit diagram of a semiconductor device according to one embodiment of the present invention.
Fig. 10A is a block diagram illustrating a configuration example of a semiconductor device. Fig. 10B is a perspective view of the semiconductor device.
Fig. 11 is a block diagram illustrating a CPU.
Fig. 12A and 12B are perspective views of the semiconductor device.
Fig. 13A and 13B are perspective views of the semiconductor device.
Fig. 14A and 14B are perspective views of the semiconductor device.
Fig. 15A and 15B are diagrams illustrating examples of the configuration of the neural network.
Fig. 16 is a diagram showing a configuration example of the semiconductor device.
Fig. 17A to 17C are diagrams illustrating a structure example of a transistor.
Fig. 18A is a diagram illustrating the classification of the crystal structure of IGZO, fig. 18B is a diagram illustrating an XRD spectrum of crystalline IGZO, and fig. 18C is a diagram illustrating a nanobeam electron diffraction pattern of crystalline IGZO.
Fig. 19A is a perspective view showing an example of a semiconductor wafer, fig. 19B is a perspective view showing an example of a chip, and fig. 19C and 19D are perspective views showing an example of an electronic component.
Fig. 20A to 20J are diagrams illustrating an example of an electronic device.
Fig. 21A to 21E are diagrams illustrating an example of an electronic device.
Fig. 22A to 22C are diagrams illustrating an example of an electronic device.
Fig. 23A and 23B are diagrams according to an embodiment.
Fig. 24 is a diagram according to an embodiment.
Fig. 25 is a diagram according to an embodiment.
Modes for carrying out the invention
The following describes embodiments of the present invention. However, one embodiment of the present invention is not limited to the following description, and a person skilled in the art can easily understand that the present invention can be changed in various forms in its aspects and details without departing from the spirit and scope thereof. Therefore, the present invention should not be construed as being limited to the embodiments described below.
In this specification and the like, a semiconductor device refers to a device utilizing semiconductor characteristics, a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like), a device including the circuit, and the like. The semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, as an example of the semiconductor device, there is an integrated circuit, a chip having an integrated circuit, an electronic component in which a chip is housed in a package, or the like. Note that the memory device, the display device, the light-emitting device, the lighting device, the electronic device, and the like are semiconductor devices themselves or include semiconductor devices in some cases.
In addition, in the present specification and the like, when it is described that "X is connected to Y", it means that the following cases are disclosed in the present specification and the like: the case where X and Y are electrically connected; the case where X and Y are functionally linked; and X is directly linked to Y. Therefore, the connection relationships are not limited to the predetermined connection relationships such as those shown in the drawings or described herein, and connection relationships other than those shown in the drawings or described herein are disclosed in the drawings or described herein. X and Y are both objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
As an example of the case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display device, a light-emitting device, a load, or the like) capable of electrically connecting X and Y may be connected between X and Y. In addition, the switch has a function of controlling the on state and the off state. In other words, the switch has a function of controlling whether or not to cause a current to flow by being turned to a conductive state (on state) or a non-conductive state (off state).
As an example of the case where X and Y are functionally connected, for example, one or more circuits (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, or the like), a signal conversion circuit (a digital-analog conversion circuit, an analog-digital conversion circuit, a gamma correction circuit, or the like), a potential level conversion circuit (a power supply circuit (a voltage boosting circuit, a voltage dropping circuit, or the like), a level shift circuit that changes a potential level of a signal, or the like), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase a signal amplitude, a current amount, or the like, an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, or the like), a signal generation circuit, a memory circuit, a control circuit, or the like) that can functionally connect X and Y may be connected between X and Y. Note that, for example, even if there is another circuit interposed between X and Y, when a signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.
When it is explicitly stated that "X is electrically connected to Y", the following cases are included: a case where X and Y are electrically connected (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); and X and Y are directly connected (in other words, X and Y are connected without interposing another element or another circuit).
For example, the expression "X, Y" may be used, in which a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected in this order ". Alternatively, the expression "a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected in this order" may be used. Alternatively, the expression "X is electrically connected to Y via a source (or a first terminal or the like) and a drain (or a second terminal or the like) of the transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided in this order of connection" may be used. By specifying the order of connection in the circuit configuration using the same expression method as in this example, the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor can be distinguished to specify the technical range. Note that this expression method is an example, and is not limited to the above expression method. Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).
In addition, even if independent components are electrically connected to each other in the circuit diagram, one component may have functions of a plurality of components. For example, when a part of the wiring is used as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the term "electrically connected" in the present specification also includes a case where one conductive film has a function of a plurality of components.
In this specification and the like, "resistor" includes, for example, a circuit element, a wiring, and the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, "resistor" includes a wiring having a resistance value, a source through which a current flows, andtransistors, diodes, coils, etc. between the drains. Therefore, "resistor" may be referred to as "resistance", "load", "region having a resistance value", and the like, and conversely, "resistance", "load", "region having a resistance value" may be referred to as "resistor" and the like. The resistance value is, for example, preferably 1m Ω to 10 Ω, more preferably 5m Ω to 5 Ω, and still more preferably 10m Ω to 1 Ω. For example, the value may be 1 Ω to 1 × 10 9 Omega is less than or equal to.
In addition, in this specification and the like, "a capacitor" includes, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of a wiring having an electrostatic capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification and the like, "a capacitor" includes a parasitic capacitance generated between a wiring and the wiring, a gate capacitance generated between one of a source and a drain of a transistor and a gate, and the like in addition to a circuit element having a pair of electrodes and a dielectric between the electrodes. "capacitor", "parasitic capacitance", "gate capacitance" and the like may be referred to as "capacitance" and the like, and conversely, "capacitance" may be referred to as "capacitor", "parasitic capacitance", "gate capacitance" and the like. The "pair of electrodes" of the "capacitor" may be referred to as "a pair of conductors", "a pair of conductive regions", "a pair of regions", or the like. The capacitance value may be, for example, 0.05fF or more and 10pF or less. For example, the amount may be 1pF or more and 10 μ F or less.
In addition, in this specification and the like, a transistor includes three terminals of a gate, a source, and a drain. The gate serves as a control terminal for controlling the conductive state of the transistor. The two terminals serving as a source or a drain are input/output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor, one of the two input/output terminals serves as a source and the other serves as a drain. Therefore, in this specification and the like, the source and the drain may be interchanged with each other. In this specification and the like, in describing a connection relationship of the transistor, a description is given of "one of a source and a drain" (a first electrode or a first terminal) and "the other of the source and the drain" (a second electrode or a second terminal). Depending on the structure of the transistor, the back gate may be included in addition to the three terminals. In this case, in this specification and the like, one of a gate and a back gate of a transistor is sometimes referred to as a first gate, and the other of the gate and the back gate of the transistor is sometimes referred to as a second gate. Also, in the same transistor, the "gate" and the "back gate" may be sometimes exchanged with each other. In the case where a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, or the like in this specification or the like.
Further, in this specification and the like, "on-state current" sometimes refers to current flowing between a source and a drain when a transistor is in an on state. Further, "off-state current" sometimes refers to a current flowing between a source and a drain when a transistor is in an off state.
Note that in this specification and the like, a node may be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit structure, a device structure, or the like. In addition, a terminal, a wiring, or the like may be referred to as a node.
In this specification and the like, the "voltage" and the "potential" may be appropriately exchanged. The "voltage" is a potential difference from a reference potential, and may be referred to as "potential" when the reference potential is, for example, ground potential (ground potential). The ground potential does not necessarily mean 0V. Further, the potential is relative, and the potential supplied to the wiring, the potential applied to the circuit or the like, the potential output from the circuit or the like, and the like also change in accordance with the change in the reference potential.
In this specification and the like, the high power supply potential VDD (hereinafter, abbreviated as "VDD") refers to a power supply potential higher than the low power supply potential VSS (hereinafter, abbreviated as "VSS"). VSS is a power supply potential lower than VDD. Further, a ground potential (hereinafter, simply referred to as "GND") may be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.
The "current" refers to a movement phenomenon (conduction) of electric charges, and for example, the description of "conduction of a positively charged body occurs" may be replaced with the description of "conduction of a negatively charged body occurs in a direction opposite thereto". Therefore, in this specification and the like, unless otherwise specified, "current" refers to a movement phenomenon (conduction) of electric charges when carriers move. Here, the carriers include electrons, holes, anions, cations, complex ions, and the like, and the carriers vary depending on the system in which current flows (for example, a semiconductor, a metal, an electrolyte, vacuum, and the like). The "direction of current" in the wiring or the like is a direction in which positive carriers move, and is described as a positive current amount. In other words, the direction in which the negative current carriers move is opposite to the direction of current flow, and is described as a negative current amount. Therefore, in this specification and the like, unless otherwise specified, the description of "current flows from the element a to the element B" and the like may be replaced with the description of "current flows from the element B to the element a" and the like with respect to the positive and negative of the current (or the direction of the current). Note that the description of "inputting a current to the element a" or the like may be replaced with the description of "outputting a current from the element a" or the like.
In the present specification and the like, ordinal numbers such as "first", "second", "third", and the like are added to avoid confusion of constituent elements. Therefore, the ordinal number does not limit the number of components. The ordinal number does not limit the order of the constituent elements. For example, a component attached with "first" in one of the embodiments in the present specification and the like may be attached with a ordinal number of "second" in another embodiment or claims. For example, in this specification and the like, a constituent element referred to as "first" in one embodiment may be omitted in another embodiment or claims.
The terms "above" and "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and the components are in direct contact with each other. For example, if the expression "the electrode B on the insulating layer a" is used, the electrode B does not necessarily have to be formed in direct contact with the insulating layer a, and a case where another constituent element is included between the insulating layer a and the electrode B may be included.
Further, the positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words are not limited to the words described in the specification and the like, and words may be appropriately changed depending on the case. For example, in the present specification and the like, for convenience, positional relationships of components may be described using terms such as "upper" and "lower" to indicate arrangement, with reference to the drawings. Therefore, in the expression "insulator on the top surface of the conductor", it is also possible to refer to "insulator on the lower surface of the conductor" by rotating the direction of the illustrated drawing by 180 degrees. In the expression "insulator on the top surface of the conductor", the insulator on the left (or right) side of the conductor may be referred to as "insulator on the right (or left) side of the conductor" by rotating the direction of the drawing shown by 90 degrees.
Similarly, in this specification and the like, the terms such as "overlap" and the like do not limit the state of the order of lamination of the constituent elements and the like. For example, "the electrode B overlapping with the insulating layer a" is not limited to a state of "the electrode B is formed on the insulating layer a", and includes a state of "the electrode B is formed under the insulating layer a" or a state of "the electrode B is formed on the right side (or left side) of the insulating layer a".
In the present specification and the like, the words such as "adjacent" or "close to" do not limit the state in which the constituent elements are in direct contact. For example, if the expression "the electrode B is adjacent to the insulating layer a", the insulating layer a and the electrode B do not necessarily have to be in direct contact with each other, and a case where another component is included between the insulating layer a and the electrode B may be included.
In this specification and the like, terms such as "film" and "layer" may be interchanged depending on the situation. For example, the "conductive layer" may be sometimes changed to a "conductive film". In addition, for example, the "insulating film" may be converted into an "insulating layer". Further, other words may be used instead of words such as "film" and "layer" depending on the situation or state. For example, a "conductive layer" or a "conductive film" may be sometimes converted into a "conductor". Further, for example, an "insulating layer" or an "insulating film" may be sometimes converted to an "insulator".
Note that in this specification and the like, terms such as "electrode", "wiring", and "terminal" are not intended to functionally limit constituent elements thereof. For example, an "electrode" is sometimes used as part of a "wiring", and vice versa. The terms "electrode" and "wiring" also include a case where a plurality of "electrodes" and "wirings" are formed integrally. In addition, for example, a "terminal" is sometimes used as a part of a "wiring" and an "electrode", and vice versa. The term "terminal" includes a case where a plurality of "electrodes", "wirings", "terminals", and the like are integrally formed. Thus, for example, an "electrode" may be part of a "wiring" or a "terminal", for example, a "terminal" may be part of a "wiring" or an "electrode". In addition, terms such as "electrode", "wiring", "terminal", and the like may be replaced with terms such as "region".
In this specification and the like, terms such as "wiring", "signal line", and "power supply line" may be interchanged depending on the situation or state. For example, the "wiring" may be converted into a "signal line". In addition, for example, the "wiring" may be converted into a "power supply line". Vice versa, a "signal line" or a "power supply line" may be sometimes converted to a "wiring". The "power line" may sometimes be converted to a "signal line". Vice versa, the "signal line" may sometimes be converted to a "power line". In addition, "potentials" applied to wirings can be mutually converted into "signals" according to the situation or the state. Vice versa, a "signal" may sometimes be converted into an "electric potential".
In this specification and the like, the impurity of a semiconductor means a substance other than a main component constituting a semiconductor layer. For example, elements with a concentration of less than 0.1atomic% are impurities. When impurities are contained, for example, the defect state density in the semiconductor may be increased, the carrier mobility may be decreased, or the crystallinity may be decreased. When the semiconductor is an oxide semiconductor, examples of the impurities that change the semiconductor characteristics include a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and transition metals other than main components, and in particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is silicon, as impurities which change the semiconductor characteristics, for example, oxygen, a group 1 element other than hydrogen, a group 2 element, a group 13 element, a group 15 element, and the like are given.
In this specification and the like, a switch is an element having a function of controlling whether or not to allow a current to flow by being turned into an on state (on state) or an off state (off state). Alternatively, the switch refers to an element having a function of selecting and switching a current path. As an example of the switch, an electric switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific element as long as it can control the current.
Examples of the electric switch include a transistor (e.g., a bipolar transistor, a MOS transistor, or the like), a diode (e.g., a PN diode, a PIN diode, a schottky diode, an MIM (Metal Insulator Metal) diode, an MIS (Metal Insulator Semiconductor) diode, or a diode-connected transistor, or the like), or a logic circuit combining these elements, or the like. When a transistor is used as a switch, the "on state (on state)" of the transistor means a state in which a source and a drain of the transistor are electrically short-circuited. The "non-conductive state (off state)" of the transistor means a state in which a source and a drain of the transistor are electrically disconnected. When a transistor is used only as a switch, the polarity (conductivity type) of the transistor is not particularly limited.
As an example of the mechanical switch, a switch using MEMS (micro electro mechanical system) technology can be given. The switch has an electrode that is mechanically movable, and operates by moving the electrode to control conduction and non-conduction.
In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less. Therefore, the state where the angle is-5 ° or more and 5 ° or less is also included. The term "substantially parallel" means a state in which the angle formed by two straight lines is-30 ° or more and 30 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less. Therefore, the angle is 85 ° or more and 95 ° or less. The term "substantially perpendicular" refers to a state in which the angle formed by two straight lines is 60 ° or more and 120 ° or less.
In this specification and the like, a metal oxide (metal oxide) refers to an oxide of a metal in a broad sense. The metal Oxide is classified into an Oxide insulator, an Oxide conductor (including a transparent Oxide conductor), an Oxide Semiconductor (which may also be simply referred to as OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying action, a rectifying action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor). In addition, the OS transistor may be referred to as a transistor including a metal oxide or an oxide semiconductor.
In this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide (metal oxide) in some cases. In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).
Note that in this specification and the like, the configurations described in the respective embodiments may be combined with the configurations described in the other embodiments as appropriate to configure one embodiment of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, these configuration examples may be combined as appropriate.
Further, the content (or a part of the content) described in a certain embodiment may be applied to/combined with/replaced with at least one of the other content (or a part of the content) described in the embodiment and the content (or a part of the content) described in another or more other embodiments.
Note that the content described in the embodiments refers to content described in each embodiment (or example) with reference to various drawings or content described with reference to a text described in the specification.
Further, by combining a drawing (or a part) shown in a certain embodiment with at least one drawing among other parts of the drawing, other drawings (or a part) shown in the embodiment, and drawings (or a part) shown in another or more other embodiments, more drawings can be configured.
Embodiments described in the present specification will be described with reference to the drawings. Note that a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the modes and details can be changed into various forms without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. Note that, in the structure of the invention in the embodiment, the same reference numerals are used in common in different drawings to denote the same portions or portions having the same functions, and repeated explanation is omitted. In the perspective view, the plan view, and the like, some components may not be illustrated for clarity.
In this specification and the like, constituent elements are classified according to functions and are represented as blocks independent of each other in a block diagram. However, in an actual circuit or the like, it is difficult to classify components according to functions, and one circuit may involve a plurality of functions or a plurality of circuits may involve one function. Therefore, the blocks in the block diagrams are not limited to the constituent elements described in the specification, and may be expressed in an alternative manner as appropriate.
In the drawings, the size, the thickness of layers, or regions may be exaggerated for clarity. Therefore, the dimensions and aspect ratios are not limited to those shown in the drawings. In addition, since the ideal example is schematically shown in the drawings, the shape, the numerical value, and the like shown in the drawings are not limited. For example, unevenness of a signal, voltage, or current due to noise or timing deviation, or the like may be included.
In this specification and the like, when a plurality of constituent elements are denoted by the same reference numeral and it is necessary to distinguish them from each other, a symbol for identification such as "_1", "[ n ]", "[ m, n ]" may be added to the reference numeral. For example, the two wirings GL may be referred to as a wiring GL [1] and a wiring GL [2], respectively.
(embodiment mode 1)
A semiconductor device 100 according to one embodiment of the present invention will be described with reference to the drawings.
< example of Structure of semiconductor device 100 >
Fig. 1A shows a circuit diagram of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 can be used as a memory circuit capable of holding analog data. In addition, the semiconductor device 100 can be used as a memory element capable of holding analog data. The semiconductor device 100 includes a transistor Tr11, a transistor Tr12, a transistor Tr21, a transistor Tr22, a capacitor Cb1, and a capacitor Cb2.
The semiconductor device 100 includes a holding circuit 110a, a holding circuit 110b, a bootstrap circuit 120a, a bootstrap circuit 120b, and a source follower circuit 130.
The holding circuit 110a includes a transistor Tr11 and a capacitor Cb1, and the holding circuit 110b includes a transistor Tr21 and a capacitor Cb2. The bootstrap circuit 120a includes a transistor Tr12 and a capacitor Cb1, and the bootstrap circuit 120b includes a transistor Tr22 and a capacitor Cb2. The source follower circuit 130 includes a transistor Tr12 and a transistor Tr22.
A gate of the transistor Tr11 is electrically connected to the terminal WW1, one of a source and a drain of the transistor Tr11 is electrically connected to the terminal IN1, and the other is electrically connected to a gate of the transistor Tr 12. One of a source and a drain of the transistor Tr12 is electrically connected to the terminal PS1, and the other is electrically connected to the terminal OUT.
The gate of the transistor Tr21 is electrically connected to the terminal WW2, one of the source and the drain of the transistor Tr21 is electrically connected to the terminal IN2, and the other is electrically connected to the gate of the transistor Tr22. One of a source and a drain of the transistor Tr22 is electrically connected to the terminal OUT, and the other is electrically connected to the terminal PS 2.
One electrode constituting the capacitor Cb1 is electrically connected to the gate of the transistor Tr12, and the other electrode is electrically connected to the terminal OUT. One electrode constituting the capacitor Cb2 is electrically connected to the terminal OUT, and the other electrode is electrically connected to the gate of the transistor Tr22.
A node at which the other of the source and the drain of the transistor Tr11, the gate of the transistor Tr12, and one electrode constituting the capacitor Cb1 are electrically connected is used as the node SN1. A node at which the other of the source and the drain of the transistor Tr21, the gate of the transistor Tr22, and the other electrode constituting the capacitor Cb2 are electrically connected is used as the node SN2. A node at which the other electrode constituting the capacitor Cb1 and the one electrode constituting the capacitor Cb2 are electrically connected to the terminal OUT is used as the node BN. In addition, both the node SN1 and the node SN2 function as storage nodes.
The holding circuit 110a has a function of holding the potential (charge) written to the node SN1 through the transistor Tr 11. The holding circuit 110b has a function of holding the potential (charge) written to the node SN2 through the transistor Tr 21.
Specifically, a potential for turning on the transistor Tr11 is supplied to the gate of the transistor Tr11, and a charge for turning the node SN1 to a predetermined potential is supplied to the node SN1 via the source and the drain of the transistor Tr 11. Then, a potential for turning off the transistor Tr11 is supplied to the gate of the transistor Tr 11. When the transistor Tr11 is in an off state, the electric charge written to the node SN1 is held.
Similarly, a potential for turning on the transistor Tr21 is supplied to the gate of the transistor Tr21, and electric charge for turning the node SN2 to a predetermined potential is supplied to the node SN2 via the source and drain of the transistor Tr 21. Then, a potential for turning off the transistor Tr21 is supplied to the gate of the transistor Tr 21. When the transistor Tr21 is in the off state, the electric charge written to the node SN2 is held. Therefore, the node SN1 and the node SN2 are also referred to as "holding nodes". The transistor Tr11 and the transistor Tr21 are also referred to as "write transistors".
As semiconductor layers of the transistor Tr11, the transistor Tr12, the transistor Tr21, and the transistor Tr22, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon, germanium, or the like can be used. In addition, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor may be used.
In addition, the semiconductor layer used for the transistor may be a stack of a plurality of semiconductor layers. When semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials can be used.
In particular, the transistor Tr11 and the transistor Tr21 are preferably transistors (also referred to as "OS transistors") including an oxide semiconductor in a semiconductor layer in which a channel is formed. The oxide semiconductor has a band gap of 2eV or more, and thus has extremely small off-state current. When the transistor Tr11 and the transistor Tr21 are each an OS transistor, the charge written in the holding node can be held for a long period of time. When the transistor Tr11 and the transistor Tr21 are each an OS transistor, the semiconductor device 100 can be referred to as an "OS memory".
The OS memory can hold the written information for 1 year or more, even 10 years or more, even if the power supply is stopped. Thus, the OS memory can be regarded as a nonvolatile memory.
Further, since the amount of charge written to the OS memory is not easily changed for a long period of time, the OS memory can hold information of multiple values (multiple bits) without being limited to 2 values (1 bit).
Further, since the OS memory writes charges to the node through the OS transistor, a high voltage required for a conventional flash memory is not required, and a high-speed write operation can be realized. Further, the OS memory does not require a deletion work before data rewriting required for the flash memory. Further, since charge injection into and extraction of charge from the floating gate or the charge trapping layer are not performed, the OS memory can write and read data substantially indefinitely. The OS memory is less degraded and can achieve higher reliability than the existing flash memory.
Further, the OS memory does not undergo structural change at an atomic level like a Magnetoresistive Random Access Memory (MRAM) or a variable resistance memory (ReRAM). Therefore, the OS memory has higher resistance to rewriting than the magnetoresistive random access memory and the variable resistance memory.
In addition, the off-state current of the OS transistor hardly increases even under a high-temperature environment. Specifically, the off-state current hardly increases even at an ambient temperature of room temperature or higher and 200 ℃ or lower. In addition, the on-state current is not easily decreased even in a high-temperature environment. The memory device including the OS memory stably operates even in a high-temperature environment and has high reliability. Further, the breakdown voltage between the source and the drain of the OS transistor is high. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device which operates stably even under a high-temperature environment and has high reliability can be realized. Therefore, it is preferable to use OS transistors as the transistor Tr11, the transistor Tr21, the transistor Tr12, and the transistor Tr22.
When the gate insulating films of the transistor Tr12 and the transistor Tr22 are extremely thin, the charges written into the node SN1 and the node SN2 may leak through the gate insulating films (also referred to as "gate leakage currents"). The thickness of the gate insulating films of the transistor Tr12 and the transistor Tr22 is preferably substantially the same as the thickness of the gate insulating films of the transistor Tr11 and the transistor Tr 21.
For example, an OS transistor may be used as the transistor Tr11 and the transistor Tr21, and an Si transistor may be used as the transistor Tr12 and the transistor Tr22. As the Si transistors used for the transistor Tr12 and the transistor Tr22, si transistors having a structure with less gate leakage current may be used.
Since the Si transistor operates at a higher speed than the OS transistor, the use of the Si transistor in the transistor Tr12 and the transistor Tr22 can improve the data reading speed.
As shown in fig. 1B, the gate of the transistor Tr11 and the gate of the transistor Tr21 may be electrically connected to the wiring WWL.
As shown in fig. 2A, a transistor including a back gate may be used as the transistor Tr12 and the transistor Tr22. Fig. 2A shows an example in which the back gate of the transistor Tr12 is electrically connected to the terminal BG14 and the back gate of the transistor Tr22 is electrically connected to the terminal BG 24. By controlling the potential of the terminal BG14, the threshold voltage of the transistor Tr12 can be changed. By controlling the potential of the terminal BG24, the threshold voltage of the transistor Tr22 can be changed.
As shown in fig. 2B, a transistor including a back gate may be used as the transistor Tr11 and the transistor Tr 21. Fig. 2B shows an example in which the back gate of the transistor Tr11 is electrically connected to the terminal BG13 and the back gate of the transistor Tr21 is electrically connected to the terminal BG 23. By controlling the potential of the terminal BG13, the threshold voltage of the transistor Tr11 can be changed. By controlling the potential of the terminal BG23, the threshold voltage of the transistor Tr21 can be changed.
In addition, fig. 3A shows an example in which a gate and a back gate are electrically connected in each of the transistor Tr11, the transistor Tr12, the transistor Tr21, and the transistor Tr22. Fig. 3B shows an example in which the back gate of the transistor Tr22 is electrically connected to the other of the source and the drain of the transistor Tr22. By providing the back gate, an electric field generated outside the transistor is less likely to affect the channel formation region, and therefore, the semiconductor device operates stably, and the reliability of the semiconductor device can be improved.
The transistor Tr11, the transistor Tr12, the transistor Tr21, and the transistor Tr22 may be double-gate transistors. Fig. 4A shows an example of a circuit symbol of the double-gate transistor 180A.
The transistor 180A has a structure in which a transistor Tr1 and a transistor Tr2 are connected in series. In fig. 4A, the following state is shown: one of a source and a drain of the transistor Tr1 is electrically connected to the terminal S, the other of the source and the drain of the transistor Tr1 is electrically connected to one of a source and a drain of the transistor Tr2, and the other of the source and the drain of the transistor Tr2 is electrically connected to the terminal D. In addition, in fig. 4A, a state in which the gates of the transistor Tr1 and the transistor Tr2 are electrically connected to each other and to the terminal G is shown.
The transistor 180A shown in fig. 4A has a function of switching a conductive state or a non-conductive state between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, the transistor 180A of the double gate type transistor includes the transistor Tr1 and the transistor Tr2 and is used as one transistor. That is, in fig. 4A, one of a source and a drain of the transistor 180A is electrically connected to the terminal S, the other of the source and the drain is electrically connected to the terminal D, and a gate is electrically connected to the terminal G.
The transistor Tr11, the transistor Tr12, the transistor Tr21, and the transistor Tr22 may be triple-gate transistors. Fig. 4B shows an example of a circuit symbol of the tri-gate transistor 180B.
The transistor 180B has a structure in which a transistor Tr1, a transistor Tr2, and a transistor Tr3 are connected in series. In fig. 4B, the following state is shown: one of the source and the drain of the transistor Tr1 is electrically connected to the terminal S, the other of the source and the drain of the transistor Tr1 is electrically connected to one of the source and the drain of the transistor Tr2, the other of the source and the drain of the transistor Tr2 is electrically connected to one of the source and the drain of the transistor Tr3, and the other of the source and the drain of the transistor Tr3 is electrically connected to the terminal D. Fig. 4B shows a state in which the gates of the transistors Tr1, tr2, and Tr3 are electrically connected to each other and to the terminal G.
The transistor 180B shown in fig. 4B has a function of switching a conductive state or a non-conductive state between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, the transistor 180B of the triple-gate transistor includes the transistor Tr1, the transistor Tr2, and the transistor Tr3 and is used as one transistor. That is, in fig. 4B, one of the source and the drain of the transistor 180B is electrically connected to the terminal S, the other of the source and the drain is electrically connected to the terminal D, and the gate is electrically connected to the terminal G.
A transistor including a plurality of gates and electrically connecting the plurality of gates like the transistor 180A and the transistor 180B is sometimes referred to as a "multi-gate transistor" or a "multi-gate transistor".
< working example of semiconductor device 100 >
An operation example of the semiconductor device 100 will be described with reference to the drawings. As described above, the semiconductor device 100 according to one embodiment of the present invention uses the transistor Tr12 and the transistor Tr22 to configure the source follower circuit 130.
Here, a source follower circuit is explained. Fig. 5A is a circuit diagram of a source follower circuit 901 including a transistor M1 and a resistor R1. The transistor M1 is an n-channel transistor. In the source follower circuit 901 shown in fig. 5A, the source of the transistor M1 is electrically connected to one terminal of the resistor R1. In addition, the drain of the transistor M1 is supplied with VDD, and the other terminal of the resistor is supplied with VSS. The gate of the transistor M1 is electrically connected to the terminal IN and is inputted with the input voltage Vin through the terminal IN. The source of the transistor M1 is electrically connected to the terminal OUT, and outputs the output voltage Vout through the terminal OUT.
The transistors constituting the source follower circuit need to operate in a saturation region. Therefore, when the threshold voltage of the transistor M1 is Vth, the transistor M1 needs to operate under the condition that the relationship of equation 1 is satisfied.
[ equation 1]
VDD＞Vin-Vth···(1)
Next, the operation of the source follower circuit 901 will be described. The output voltage Vout is the source voltage of the transistor M1, so the output voltage Vout is constantly close to the voltage of Vin minus Vth. That is, the output voltage Vout is varied in such a manner as to satisfy equation 2.
[ equation 2]
Figure BDA0003893245820000221
In equation 2,. Mu. n To the mobility, C OX For the gate capacitance, W is the channel width, L is the channel length, vin is the voltage input through the terminal IN (gate voltage of the transistor M1), vth is the threshold voltage of the transistor M1, and R1 is the resistance value of the resistor R1.
In the source follower circuit 901, when the input voltage Vin changes, the output voltage Vout changes with the change in the input voltage Vin.
Next, a case where the input voltage Vin is constant and the input impedance of the load connected to the terminal OUT changes is considered. A current flowing between the source and the drain of the transistor M1 is denoted by Id, a current flowing through the resistor R1 is denoted by Ir, and a voltage (gate voltage) between the gate and the source of the transistor M1 is denoted by Vgs.
Id is equal to Ir when the load is not connected to the terminal OUT. When a load is connected to the terminal OUT, the input impedance of the load decreases, a part of Id is supplied to the load and Ir decreases. At this time, the voltage generated in the resistor R1 becomes small. That is, vout decreases.
On the other hand, the fall of Vout means a fall of the source potential of the transistor M1. Thus, vgs becomes large and Id increases. Id increases until it becomes approximately Vout = Vin-Vth. More specifically, the output voltage Vout continuously increases until equation 2 is satisfied.
In addition, when the input impedance of the load connected to the terminal OUT becomes large, the current supplied to the load side decreases, so Ir flowing through the resistor R1 becomes large. At this time, the voltage generated in the resistor R1 becomes large. That is, vout rises.
On the other hand, the rise of Vout means a rise in the source potential of the transistor M1. Thus, vgs becomes smaller and Id decreases. Id decreases until it becomes approximately Vout = Vin-Vth. More specifically, the output voltage Vout is continuously decreased until equation 2 is satisfied.
In this way, the source follower circuit has a function of always supplying a constant voltage even if the input impedance of the load varies. That is, the source follower circuit has a function of amplifying power (amplifying a current value without changing an output voltage).
As in the source follower circuit 902 shown in fig. 5B, the resistor R1 in the source follower circuit 901 may be replaced with the transistor M2. The transistor M2 is an n-channel transistor. In the source follower circuit 902, the transistor M1 and the transistor M2 are also operated in a saturation region.
IN the source follower circuit 902, the gate of the transistor M1 is electrically connected to the terminal IN1, and the gate of the transistor M2 is electrically connected to the terminal IN 2. The drain of the transistor M2 is electrically connected to the terminal OUT. In addition, the source of the transistor M2 is supplied with the low power supply voltage VSS.
The source follower circuit 902 also has a function of amplifying power. In the source follower circuit 902, a current flowing between the source and the drain of the transistor M1 operating in the saturation region is denoted by Id1, a current flowing between the source and the drain of the transistor M2 operating in the saturation region is denoted by Id2, and Id1 and Id2 can be expressed by equations 3 and 4, respectively.
[ equation 3]
Figure BDA0003893245820000241
In equation 3, μ n To the mobility, C OX For the gate capacitance, W is the channel width, L is the channel length, vin1 is the voltage (gate voltage of the transistor M1) input through the terminal IN1, and Vth1 is the threshold voltage of the transistor M1.
[ equation 4]
Figure BDA0003893245820000242
In equation 4, μ n To the mobility, C OX For the gate capacitance, W is the channel width, L is the channel length, vin2 is the voltage input through the terminal IN2 (gate voltage of the transistor M2), and Vth2 is the threshold voltage of the transistor M2.
In the source follower circuit 902, id1 is equal to Id 2. When the transistor M1 and the transistor M2 have the same structure and the same transistor characteristics, the output voltage Vout of the source follower circuit 902 can be expressed by equation 5.
[ equation 5]
Vout＝Vin1-Vin2···(5)
Returning to the description of the working example of the semiconductor device 100. Fig. 6 is a timing chart for explaining the operation of the semiconductor device 100. Fig. 7 and 8 are diagrams for explaining an operation state of the semiconductor device 100.
In the drawings and the like, a symbol (also referred to as a "potential symbol") indicating a potential such as "VDD" or "VSS" may be attached to a vicinity of a terminal, a wiring, or the like. In order to make it easy to understand the potential change of the terminal, the wiring, and the like, the potential sign of the terminal, the wiring, and the like, in which the potential change has occurred, may be indicated by a box character. In addition, an "x" symbol may be superimposed on the off-state transistor.
[ data write work ]
Before the data write operation is started, the potentials of the terminal WW1 and the terminal WW2 are L potential, and the potentials of the terminal PS1, the terminal PS2, the terminal IN1, the terminal IN2, the node SN1, the node SN2, and the terminal OUT are VSS. In this specification and the like, a potential at which the crystal can be turned off is referred to as an L potential. The L potential may be VSS, for example, but does not mean a specific potential. In this specification and the like, a potential at which the transistor can be turned on is referred to as an H potential. The H potential may be VDD, for example, but does not mean a specific potential.
For example, when it is described that "L potential is supplied" to each of two wirings, the L potentials supplied to the two wirings may not be equal to each other. Similarly, when "supplying H potential" to each of the two wirings, the H potentials supplied to the two wirings may not be equal to each other.
In the period T31, the H potential is supplied to the terminal WW1 and the terminal WW2 to turn on the transistors Tr11 and Tr21 (see fig. 7A). IN addition, a voltage (Vdata + Vref) obtained by adding the data Vdata to the reference voltage Vref (reference potential) is supplied to the node SN1 through the terminal IN1 and the transistor Tr 11.
IN addition, the reference voltage Vref is supplied to the node SN2 through the terminal IN2 and the transistor Tr21 as Vin 2. Since the transistor Tr22 needs to operate in a saturation region when performing a read operation, the reference voltage Vref is preferably equal to or lower than the threshold voltage Vth2 of the transistor Tr22. In addition, when the transistor characteristics of the transistor Tr12 and the transistor Tr22 are the same, vref = Vth1= Vth2.
In the period T32, the L potential is supplied to the terminal WW1 and the terminal WW2, and the transistor Tr11 and the transistor Tr21 are turned off (see fig. 7B). By bringing the transistor Tr11 into the off state, the node SN1 becomes the floating state and the potential (charge) of the node SN1 is held. By turning the transistor Tr21 to the off state, the node SN2 becomes the floating state and the potential (charge) of the node SN2 is held.
[ data reading work ]
During the period T41, VDD is supplied to the terminal PS 1. Thereby, a current flows from the terminal PS1 through the transistor Tr12, and electric charge is supplied to the node BN. Fig. 8A shows a state immediately after the start of the period T41.
The potential of the node BN rises when the node BN is supplied with electric charge. During the period T41, the node SN1 is in a floating state, which is capacitively coupled to the node BN by the capacitor Cb1, so the potential of the node SN1 (also referred to as "Vsn 1") also rises due to the bootstrap effect. Similarly, in the period T41, the node SN2 is in a floating state, and the node SN2 is capacitively coupled to the node BN via the capacitor Cb2, so that the potential of the node SN2 (also referred to as "Vsn 2") also rises due to the bootstrap effect (see fig. 8B).
In this manner, the semiconductor device 100 includes the bootstrap circuit 120a including the transistor Tr12 and the capacitor Cb 1. The bootstrap circuit 120a has a function of boosting the potential of the node SN1. In addition, the semiconductor device 100 includes a bootstrap circuit 120b including a transistor Tr22 and a capacitor Cb2. The bootstrap circuit 120b has a function of boosting the potential of the node SN2.
In the semiconductor device 100, the potential of the node BN may also be referred to as an output voltage Vout. The potential of the node BN (output voltage Vout) is a potential corresponding to the potential difference between the node SN1 and the node SN2. In addition, the potential of the node BN (output voltage Vout) changes until equation 5 described above is satisfied. Specifically, the node BN changes until it becomes Vsn1-Vsn2. Therefore, the potential of the final node BN (output voltage Vout) becomes Vdata.
At this time, it can be said that the transistor Tr22 operates in the saturation region. IN addition, IN order to operate the transistor Tr12 IN the saturation region, the potential Vin1 supplied to the terminal IN1 IN the writing operation needs to satisfy equation 6.
[ equation 6]
Figure BDA0003893245820000271
IN addition, vin1= Vdata can be made by setting the potential supplied to the terminal IN2 to VSS. For example, as shown IN fig. 9, one of the source and the drain of the transistor Tr21 electrically connected to the terminal IN2 may be electrically connected to the terminal PS2 instead of the terminal IN 2. By setting the potential supplied to the terminal IN2 to VSS, it is not necessary to add Vref to Vin1, and thus the driver circuit of the semiconductor device 100 can be reduced IN size. Therefore, the occupied area of the semiconductor device including the semiconductor device 100 can be reduced. In addition, the degree of freedom in designing the semiconductor device is improved. In addition, the reliability of the semiconductor device can be improved.
When the potential supplied to the terminal IN2 is set to VSS, vdata needs to satisfy equation 7.
[ equation 7]
Figure BDA0003893245820000281
As described above, the semiconductor device 100 according to one embodiment of the present invention has a function of holding analog data and a function of amplifying and outputting power of the held analog data. Since the power of the held data is amplified at the time of reading, a power amplifier circuit or the like used after reading the data is not necessary. Alternatively, the number or scale of the power amplification circuits can be reduced.
In addition, the semiconductor device 100 according to one embodiment of the present invention can stably output (read) held data even when the impedance of a load connected to an output terminal (terminal OUT) changes. In addition, the semiconductor device 100 according to one embodiment of the present invention can hold digital data without being limited to analog data.
This embodiment mode can be combined with other embodiment modes and the like described in this specification as appropriate.
(embodiment mode 2)
In this embodiment mode, a semiconductor device 400 including a memory device or a semiconductor device according to one embodiment of the present invention will be described.
Fig. 10A is a block diagram showing a configuration example of the semiconductor device 400. The semiconductor device 400 shown in fig. 10A includes a driver circuit 410 and a memory array 420. The memory array 420 includes a plurality of semiconductor devices 100. The semiconductor device 100 is used as a memory cell. Fig. 10A shows an example in which the memory array 420 includes a plurality of semiconductor devices 100 arranged in a matrix.
The driving circuit 410 includes a PSW241 (power switch), a PSW242, and a peripheral circuit 415. The peripheral Circuit 415 includes a peripheral Circuit 411, a Control Circuit 412 (Control Circuit), and a voltage generation Circuit 428.
In the semiconductor device 400, each circuit, each signal, and each voltage can be appropriately selected and cut off as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.
The signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data and the signal RDA is read data. The signals PON1 and PON2 are power gate control signals. The signals PON1 and PON2 may be generated by the control circuit 412.
The control circuit 412 is a logic circuit having a function of controlling the entire operation of the semiconductor device 400. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine an operation mode (for example, a write operation and a read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates a control signal of the peripheral circuit 411 to execute the above-described operation mode.
The voltage generation circuit 428 has a function of generating a negative voltage. The WAKE has a function of controlling the input CLK to the voltage generation circuit 428. For example, when a signal of H level is applied as WAKE, the signal CLK is input to the voltage generation circuit 428, and the voltage generation circuit 428 generates a negative voltage.
The peripheral circuit 411 is a circuit for writing and reading data to and from the semiconductor device 100. The peripheral circuit 411 includes a Row Decoder 441 (Row Decoder), a Column Decoder 442 (Column Decoder), a Row Driver 423 (Row Driver), a Column Driver 424 (Column Driver), an Input circuit 425 (Input cir.), and an Output circuit 426 (Output cir.). A sense amplifier and the like may be provided as necessary.
The row decoder 441 and the column decoder 442 have a function of decoding a signal ADDR. Row decoder 441 is circuitry used to specify rows to be accessed and column decoder 442 is circuitry used to specify columns to be accessed. The row driver 423 has a function of selecting connection to the wiring designated by the row decoder 441. The column driver 424 has the following functions: a function of writing data to the semiconductor device 100; a function of reading data from the semiconductor device 100; a function of holding the read data, and the like.
The input circuit 425 has a function of holding the signal WDA. The data held in the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is data (Din) written to the semiconductor device 100. The data (Dout) read out from the semiconductor device 100 by the column driver 424 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. Further, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is a signal RDA.
The PSW241 has a function of controlling supply of VDD to the peripheral circuit 415. The PSW242 has a function of controlling supply of VHM to the row driver 423. Here, the high power supply voltage of the semiconductor device 400 is VDD, and the low power supply voltage is GND (ground potential). Further, VHM is a high power supply voltage for bringing the word line to a high level, which is higher than VDD. The PSW241 is turned on/off by the signal PON1, and the PSW242 is turned on/off by the signal PON 2. In fig. 10A, the number of power domains to which VDD is supplied in the peripheral circuit 415 is 1, but a plurality of power domains may be provided. In this case, a power switch may be provided for each power domain.
The driver circuit 410 and the memory array 420 of the semiconductor device 400 are disposed on the same plane. In addition, as shown in fig. 10B, the driving circuit 410 and the memory array 420 may overlap. By overlapping the driving circuit 410 with the memory array 420, the signal transmission distance can be shortened.
In the semiconductor device 400, an arithmetic Processing device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) may be used for the control circuit 412 included in the driver circuit 410. The semiconductor device 400 having an arithmetic processing function can be realized by using a CPU, a GPU, or the like.
This embodiment can be combined with any other embodiment described in this specification, as appropriate.
(embodiment mode 3)
In this embodiment, an example of an arithmetic processing device that can include the semiconductor device described in the above embodiment will be described.
Fig. 11 is a block diagram of the arithmetic processing device 1100. Fig. 11 shows a configuration example of a CPU as a configuration example that can be used for the arithmetic processing device 1100.
The arithmetic processing device 1100 shown in fig. 11 includes, over a substrate 1190: an ALU1191 (Arithmetic circuitry), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface 1198), a cache 1199, and a cache interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. Rewritable ROM and ROM interface may also be included. The cache 1199 and the cache interface 1189 may be provided on different chips.
The cache 1199 is connected to main memory provided on a different chip via a cache interface 1189. The cache interface 1189 has a function of supplying a part of data stored in the main memory to the cache 1199. The cache 1199 has the function of holding the data.
The arithmetic processing device 1100 shown in fig. 11 is only an example shown by simplifying the configuration thereof, and thus the arithmetic processing device 1100 actually has various configurations according to the use thereof. For example, a configuration including the arithmetic processing device 1100 or the arithmetic circuit shown in fig. 11 may be used as a core, and a plurality of the cores may be provided and operated simultaneously, that is, may be operated as a GPU. The number of bits that can be processed by the internal arithmetic circuit and the data bus of the arithmetic processing device 1100 may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
The instruction input to the arithmetic processing device 1100 through the bus interface 1198 is input to the instruction decoder 1193, decoded, and input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.
The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls according to the decoded instructions. Specifically, the ALU controller 1192 generates signals that are used to control the operation of the ALU 1191. When the arithmetic processing device 1100 executes the program, the interrupt controller 1194 determines an interrupt request from an external input/output device or a peripheral circuit based on the priority and the mask state, and performs processing. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 in accordance with the state of the arithmetic processing device 1100.
In addition, the timing controller 1195 generates signals for controlling the operation timings of the ALU1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal from a reference clock signal, and supplies the internal clock signal to the various circuits described above.
In the arithmetic processing device 1100 shown in fig. 11, a register 1196 and a cache 1199 are provided with storage devices. As this memory device, for example, the semiconductor device 100 described in the above embodiment mode can be used.
In the arithmetic processing device 1100 shown in fig. 11, the register controller 1197 selects the holding work in the register 1196 according to the instruction of the ALU 1191. In other words, whether data is held by a flip-flop or a capacitor in a memory cell included in the register 1196 is selected. In the case where data holding by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. In the case where the data holding by the capacitor is selected, rewriting of the data is performed on the capacitor, and the supply of the power supply voltage to the memory cell in the register 1196 may be stopped.
Note that the arithmetic processing device 1100 is not limited to the CPU, and may be a GPU, a DSP (Digital Signal Processor), an FPGA (Field-Programmable gate array), or the like.
The semiconductor device 400 and the arithmetic processing device 1100 according to the above embodiments may overlap each other. Fig. 12A and 12B are perspective views of the semiconductor device 1150A. The semiconductor device 1150A includes the semiconductor device 400 functioning as a memory device over the arithmetic processing device 1100. The arithmetic processing device 1100 and the semiconductor device 400 include regions overlapping each other. In order to make the structure of the semiconductor device 1150A easier to understand, fig. 12B shows the arithmetic processing device 1100 and the semiconductor device 400, respectively.
By overlapping the semiconductor device 400 and the arithmetic processing device 1100, the connection distance between the two can be shortened. This can improve the communication speed between the two. Further, since the connection distance is short, power consumption can be reduced.
Further, a plurality of semiconductor devices 400 may be provided so as to overlap with the arithmetic processing device 1100. Fig. 13A and 13B are perspective views of a semiconductor device 1150B. The semiconductor device 1150B includes the semiconductor device 400a and the semiconductor device 400B in the arithmetic processing unit 1100. The arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b include regions overlapping each other. In order to make the structure of the semiconductor device 1150B easier to understand, fig. 13B shows the arithmetic processing unit 1100, the semiconductor device 400a, and the semiconductor device 400B separately.
The semiconductor device 400a and the semiconductor device 400b are used as memory devices. For example, a NOR-type memory device may be used as one of the semiconductor device 400a and the semiconductor device 400b and a NAND-type memory device may be used as the other. Both the semiconductor device 400a and the semiconductor device 400b may be a NAND type memory device or a NOR type memory device. As the NOR type memory device, DRAM, SRAM, or the like is used. The NOR type memory device operates at a higher speed than the NAND type memory device, and thus, for example, a part of the semiconductor device 400a can be used as a main memory and/or a cache 1199. In addition, the order of overlapping the semiconductor device 400a and the semiconductor device 400b may be reversed.
Fig. 14A and 14B are perspective views of a semiconductor device 1150C. The semiconductor device 1150C has a structure in which the arithmetic processing unit 1100 is interposed between the semiconductor device 400a and the semiconductor device 400b. The arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b include regions overlapping each other. In order to make the structure of the semiconductor device 1150C easier to understand, fig. 14B shows the arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400B, respectively.
By adopting the configuration of the semiconductor device 1150C, both the communication speed between the semiconductor device 400a and the arithmetic processing unit 1100 and the communication speed between the semiconductor device 400b and the arithmetic processing unit 1100 can be increased. Further, power consumption can be further reduced as compared with the semiconductor device 1150B.
A semiconductor device according to one embodiment of the present invention can be used for an artificial neural network. An example of the structure of the artificial neural network is explained below.
Fig. 15A shows a structure example of the neural network NN. The neural network NN may be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL and the intermediate layer HL all comprise one or more neurons (cells). Note that the intermediate layer HL may be one layer or two or more layers. A neural network including two or more intermediate layers HL may be referred to as DNN (deep neural network), and learning using the deep neural network may be referred to as deep learning.
Input data is input to each neuron of the input layer IL, an output signal of a neuron in the previous layer or the next layer is input to each neuron of the intermediate layer HL, and an output signal of a neuron in the previous layer is input to each neuron of the output layer OL. Note that each neuron may be connected to all neurons in the previous layer and the next layer (full connection), or may be connected to a part of neurons.
Fig. 15B shows an example of an operation using neurons. Here, the neuron N and two neurons of the previous layer that output signals to the neuron N are shown. Neuron N is inputted to output x of neuron in the previous layer 1 And the output x of the neuron of the previous layer 2 . In the neuron N, an output x is calculated 1 And a weight w 1 Multiplication result of (x) 1 w 1 ) And output x 2 And a weight w 2 Multiplication result of (x) 2 w 2 ) Sum of x 1 w 1 +x 2 w 2 Then add it as necessaryBias b to obtain a value of a = x 1 w 1 +x 2 w 2 + b. The value a is transformed by the activation function h and the output signal y = h (a) is output from the neuron N.
Thus, the operation using neurons includes an operation of adding the product of the output of the neuron element of the previous layer and the weight, that is, a product-sum operation (x described above) 1 w 1 +x 2 w 2 ). The product-sum operation may be performed in software using a program or in hardware. When the product-sum operation is performed in hardware, a product-sum operation circuit may be used. As the product-sum operation circuit, either a digital circuit or an analog circuit may be used. When an analog circuit is used as the product-sum operation circuit, the circuit scale of the product-sum operation circuit can be reduced, or the number of times of access to the memory can be reduced, thereby improving the processing speed and reducing the power consumption.
When an analog circuit is used as the product-sum operation circuit, analog data is used as the weight information. The semiconductor device 100 according to one embodiment of the present invention can hold analog data without converting it into digital data. Therefore, the conversion circuits such as DAC (Digital to Analog Converter) and/or ADC (Analog to Digital Converter) can be eliminated, thereby reducing power consumption and occupied area.
This embodiment can be combined with any other embodiment described in this specification, as appropriate.
(embodiment mode 4)
In this embodiment, a description will be given of a configuration example of a transistor which can be applied to the semiconductor device described in the above embodiment. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. With the above configuration, the degree of freedom in designing the semiconductor device can be improved. Further, by stacking transistors having different electrical characteristics, the degree of integration of the semiconductor device can be improved.
Fig. 16 shows a partial sectional structure of the semiconductor device. The semiconductor device shown in fig. 16 includes a transistor 550, a transistor 500, and a capacitor 600. Fig. 17A is a top view of the transistor 500. Fig. 17B is a cross-sectional view along a portion L1-L2 indicated by a chain line in fig. 17A, and is also a cross-sectional view in the channel length direction of the transistor 500. Fig. 17C is a cross-sectional view along a portion W1-W2 indicated by a chain line in fig. 17A, and is also a cross-sectional view in the channel width direction of the transistor 500. For example, the transistor 500 corresponds to an OS transistor included in the semiconductor device 100 described in the above embodiment, that is, a transistor including an oxide semiconductor in a channel formation region. The transistor 550 corresponds to a Si transistor included in the driver circuit 410 described in the above embodiment, that is, a transistor including silicon in a channel formation region.
The transistor 500 is an OS transistor. The off-state current of the OS transistor is extremely small. Accordingly, the data voltage or charge written to the storage node through the transistor 500 can be maintained for a long period of time. In other words, since the frequency of the refresh operation of the storage node is reduced or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.
In fig. 16, the transistor 500 is provided above the transistor 550, and the capacitor 600 is provided above the transistor 550 and the transistor 500.
The transistor 550 is provided over a substrate 371. The substrate 371 is, for example, a p-type silicon substrate. The substrate 371 may also be an n-type silicon substrate. The oxide layer 374 is preferably an insulating layer (also referred to as a BOX layer) formed in the substrate 371 by buried oxide (burred oxide), for example, silicon oxide. The transistor 550 is provided over an SOI (Silicon On Insulator) substrate, and the SOI substrate is a substrate in which single crystal Silicon is provided over a substrate 371 with an oxide layer 374 interposed therebetween.
An insulator 373 serving as an element separation layer is provided in the substrate 371 in the SOI substrate. In addition, the substrate 371 includes a well region 372. The well region 372 is a region that is given n-type or p-type conductivity according to the conductivity type of the transistor 550. The semiconductor region 375, the low-resistance region 376a used as a source region or a drain region, and the low-resistance region 376b are provided in single crystal silicon in an SOI substrate. Further, the low-resistance region 376c is provided on the well region 372.
The transistor 550 may be provided so as to overlap with the well region 372 to which the impurity element imparting conductivity is added. The well region 372 can be used as a bottom gate electrode of the transistor 550 by controlling the potential independently by the low-resistance region 376 c. Accordingly, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 372, the threshold voltage of the transistor 550 can be further increased, and the off-state current can be reduced. Therefore, by applying a negative potential to the well region 372, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be reduced. As a result, power consumption due to a through current or the like in an arithmetic circuit including the transistor 550 can be reduced, and arithmetic efficiency can be improved.
The transistor 550 is preferably a so-called Fin type structure in which a conductor 378 covers the top surface and the side surfaces in the channel width direction of a semiconductor layer with an insulator 377 therebetween. In this manner, by providing the transistor 550 with a Fin-type structure, the effective channel width is increased, and the on-state characteristics of the transistor 550 can be improved. In addition, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristic of the transistor 550 can be improved.
Further, the transistor 550 may be either a p-channel transistor or an n-channel transistor.
Here, the conductive body 378 is sometimes used as a first gate (also referred to as top gate) electrode. In addition, the well region 372 is sometimes used as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the well region 372 can be controlled by the low-resistance region 376 c.
The channel formation region of the semiconductor region 375 or a region in the vicinity thereof, the low-resistance region 376a and the low-resistance region 376b which are used as a source region or a drain region, the low-resistance region 376c connected to an electrode which controls the potential of the well region 372, and the like preferably include a semiconductor such as a silicon-based semiconductor, and more preferably include single crystal silicon. In addition, it may be formed using a material containing Ge (germanium), siGe (silicon germanium), gaAs (gallium arsenide), gaAlAs (gallium aluminum arsenide), or the like. Effective quality of silicon can be controlled by applying stress to the crystal lattice and changing the interplanar spacing. Further, the transistor 550 may be a HEMT using GaAs, gaAlAs, or the like.
The well region 372, the low-resistance region 376a, the low-resistance region 376b, and the low-resistance region 376c contain an element imparting n-type conductivity, such as arsenic or phosphorus, or an element imparting p-type conductivity, such as boron, in addition to the semiconductor material applied to the semiconductor region 375.
As the conductor 378 used as a gate electrode, a semiconductor material such as silicon, a metal material, an alloy material, or a conductive material such as a metal oxide material, which contains an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron, can be used. Alternatively, conductor 378 may be made of silicide such as nickel silicide.
Since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, a material such as titanium nitride or tantalum nitride is preferably used as the conductor. In order to achieve both conductivity and embeddability, a stack of metal materials such as tungsten and aluminum is preferably used as the conductor, and tungsten is particularly preferably used in terms of heat resistance.
The low-resistance region 376a, the low-resistance region 376b, and the low-resistance region 376c may be provided by separately laminating a conductor, for example, a silicide such as nickel silicide. By adopting this structure, the conductivity of the region used as the electrode can be improved. At this time, an insulator used as a sidewall spacer (also referred to as a sidewall insulating layer) may be provided on a side surface of the conductor 378 used as a gate electrode and a side surface of an insulator used as a gate insulating film. With this configuration, the conductor 378 can be prevented from being brought into conduction with the low-resistance region 376a and the low-resistance region 376 b.
An insulator 379, an insulator 381, an insulator 383, and an insulator 385 are stacked in this order so as to cover the transistor 550.
As the insulator 379, the insulator 381, the insulator 383, and the insulator 385, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.
Note that in this specification, "silicon oxynitride" refers to a material whose composition contains more oxygen than nitrogen, and "silicon nitride oxide" refers to a material whose composition contains more nitrogen than oxygen. Note that in this specification, "aluminum oxynitride" refers to a material having an oxygen content greater than a nitrogen content, and "aluminum nitride oxide" refers to a material having a nitrogen content greater than an oxygen content.
The insulator 381 may also serve as a planarizing film for planarizing a step due to the transistor 550 or the like provided thereunder. For example, in order to improve the flatness of the top surface of the insulator 381, the planarization may be performed by a planarization process using a Chemical Mechanical Polishing (CMP) method or the like.
As the insulator 383, a film having barrier properties which can prevent diffusion of hydrogen and impurities from the substrate 371, the transistor 550, or the like into a region where the transistor 500 is provided is preferably used.
As an example of the film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as the transistor 500, and the characteristics of the semiconductor element may be degraded. Therefore, a film which suppresses diffusion of hydrogen is preferably provided between the transistor 500 and the transistor 550. Specifically, the membrane that suppresses the diffusion of hydrogen means a membrane in which the amount of hydrogen released is small.
The amount of hydrogen desorbed can be analyzed by Thermal Desorption Spectroscopy (TDS) or the like, for example. For example, in the range of 50 ℃ to 500 ℃ of the film surface temperature in the TDS analysis, when the desorption amount converted into hydrogen atoms is converted into the amount per unit area of the insulator 383, the desorption amount of hydrogen in the insulator 383 is 10 × 10 15 atoms/cm 2 Hereinafter, it is preferably 5 × 10 15 atoms/cm 2 The following may be used.
In addition, the dielectric constant of the insulator 385 is preferably lower than that of the insulator 383. For example, the relative dielectric constant of the insulator 385 is preferably lower than 4, more preferably lower than 3. For example, the relative permittivity of the insulator 385 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative permittivity of the insulator 383. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.
Further, a conductor 328, a conductor 330, and the like connected to the capacitor 600 or the transistor 500 are buried in the insulator 379, the insulator 381, the insulator 383, and the insulator 385. Further, the conductors 328 and 330 function as plugs or wires. Note that the same reference numeral may be used to denote a plurality of conductors having a function of a plug or a wiring. In this specification and the like, a wiring and a plug connected to the wiring may be one component. That is, a part of the conductor is sometimes used as a wiring, and a part of the conductor is sometimes used as a plug.
As a material of each plug and wiring (the conductor 328, the conductor 330, and the like), a single layer or a stacked layer of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. High melting point materials such as tungsten and molybdenum having both heat resistance and conductivity are preferably used, and tungsten is particularly preferably used. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. The wiring resistance can be reduced by using a low-resistance conductive material.
Further, a wiring layer may be formed over the insulator 385 and the conductor 330. For example, in fig. 16, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Further, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring connected to the transistor 550. The conductor 356 can be formed using the same material as the conductor 328 and the conductor 330.
As the insulator 350, an insulator having a barrier property against hydrogen is preferably used, for example, as in the case of the insulator 383. The conductive body 356 preferably contains a conductive body having a barrier property against hydrogen. In particular, a conductor having hydrogen barrier properties is formed in the opening of the insulator 350 having hydrogen barrier properties. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, and thus diffusion of hydrogen from the transistor 550 into the transistor 500 can be suppressed.
Note that as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is preferably used. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining conductivity as a wiring. At this time, the tantalum nitride layer having barrier properties to hydrogen is preferably in contact with the insulator 350 having barrier properties to hydrogen.
Further, a wiring layer may be formed over the insulator 354 and the conductor 356. For example, in fig. 16, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. Conductor 366 functions as a plug or wiring. The conductor 366 can be formed using the same material as the conductor 328 and the conductor 330.
As the insulator 360, an insulator having a barrier property against hydrogen, for example, is preferably used, similarly to the insulator 383. In addition, the conductive body 366 preferably includes a conductive body having barrier properties against hydrogen. In particular, a conductor having hydrogen barrier properties is formed in an opening portion of the insulator 360 having hydrogen barrier properties. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, and thus diffusion of hydrogen from the transistor 550 into the transistor 500 can be suppressed.
Further, a wiring layer may be formed on the insulator 364 and the conductor 366. For example, in fig. 16, an insulator 370, an insulator 369, and an insulator 368 are stacked in this order. Further, a conductor 376 is formed in the insulator 370, the insulator 369, and the insulator 368. The conductor 376 functions as a plug or a wire. The conductor 376 can be formed using the same material as the conductor 328 and the conductor 330.
As the insulator 383, an insulator having a barrier property against hydrogen, for example, is preferably used as the insulator 370. The conductive member 376 preferably includes a conductive member having a barrier property against hydrogen. In particular, a conductor having hydrogen barrier properties is formed in an opening portion of the insulator 370 having hydrogen barrier properties. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, and thus diffusion of hydrogen from the transistor 550 into the transistor 500 can be suppressed.
Further, a wiring layer may be formed on the insulator 368 and the conductor 376. For example, in fig. 16, an insulator 380, an insulator 382, and an insulator 384 are stacked in this order. Further, a conductor 386 is formed in the insulator 380, the insulator 382, and the insulator 384. Conductor 386 functions as a plug or wiring. The conductor 386 may be formed using the same material as the conductor 328 and the conductor 330.
As the insulator 380, an insulator having a barrier property against hydrogen, for example, is preferably used, similarly to the insulator 383. In addition, the electric conductor 386 preferably includes an electric conductor having a barrier property against hydrogen. In particular, a conductor having hydrogen barrier properties is formed in the opening of the insulator 380 having hydrogen barrier properties. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, and thus diffusion of hydrogen from the transistor 550 into the transistor 500 can be suppressed.
The wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described above, but the semiconductor device of the present embodiment is not limited thereto. The same wiring layer as the wiring layer including the conductor 356 may have a structure of three layers or less, or may have a structure of five layers or more.
An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. As any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516, a substance having barrier properties against oxygen and hydrogen is preferably used.
For example, as the insulator 510 and the insulator 514, a film having barrier properties against hydrogen and impurities from the substrate 371, a region where the transistor 550 is provided, or the like to a region where the transistor 500 is provided is preferably used. Therefore, the same material as the insulator 383 can be used.
As an example of the film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as the transistor 500, and the characteristics of the semiconductor element may be degraded. Therefore, a film which suppresses diffusion of hydrogen is preferably provided between the transistor 500 and the transistor 550.
As a film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulators 510 and 514.
In particular, alumina has a high barrier effect against oxygen and impurities such as hydrogen and moisture that cause variations in electrical characteristics of transistors. Therefore, the aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, aluminum oxide can suppress oxygen release from the oxide constituting the transistor 500. Therefore, alumina is suitable as a protective film of the transistor 500.
For example, the same material as the insulator 379 can be used for the insulator 512 and the insulator 516. In addition, by using a material having a low dielectric constant for the insulator, parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 512 and the insulator 516.
A conductor 518, a conductor (e.g., conductor 503) constituting the transistor 500, and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Further, the conductor 518 is used as a plug or a wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using the same material as the conductor 328 and the conductor 330.
In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 550 can be separated from the transistor 500 by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.
A transistor 500 is disposed over the insulator 516.
As shown in fig. 17A to 17C, the transistor 500 includes a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed over the insulator 516 and the conductor 503, an insulator 522 disposed over the insulator 520, an insulator 524 disposed over the insulator 522, an oxide 530a disposed over the insulator 524, an oxide 530b disposed over the oxide 530a, conductors 542a and 542b disposed over the oxide 530b so as to be separated from each other, an insulator 580 disposed over the conductors 542a and 542b and forming an opening so as to overlap between the conductors 542a and 542b, an insulator 545 disposed over the bottom and side surfaces of the opening, and a conductor 560 disposed over the formation surface of the insulator 545.
As shown in fig. 17B and 17C, an insulator 544 is preferably disposed between the oxide 530a, the oxide 530B, the conductor 542a, and the conductor 542B, and the insulator 580. As shown in fig. 17A to 17C, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560 a. As shown in fig. 17B and 17C, an insulator 574 is preferably disposed over the insulator 580, the conductor 560, and the insulator 545.
Note that in this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.
In the transistor 500, two layers of the oxide 530a and the oxide 530b are stacked in a region where a channel is formed and in the vicinity thereof, but the present invention is not limited thereto. For example, the oxide 530b may have a single-layer structure, or may have a stacked-layer structure of three or more layers.
Further, in the transistor 500, the conductive body 560 has a two-layer structure, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a stacked-layer structure of three or more layers. Note that the structure of the transistor 500 shown in fig. 16 and 17A to 17C is merely an example and is not limited to the above structure, and an appropriate transistor can be used depending on a circuit structure and/or a driving method.
Here, the conductor 560 is used as a gate electrode of the transistor 500, and the conductor 542a and the conductor 542b are used as a source electrode or a drain electrode. As described above, the conductor 560 is provided so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductors 560, 542a, and 542b is selected to be self-aligned according to the opening of the insulator 580. In other words, in the transistor 500, a gate electrode can be arranged in self-alignment between a source electrode and a drain electrode. Thus, the conductor 560 can be formed without providing a space for alignment, and therefore, the area occupied by the transistor 500 can be reduced. Thus, miniaturization and high integration of the semiconductor device can be achieved.
Since the conductor 560 is formed in a self-aligned manner in a region between the conductors 542a and 542b, the conductor 560 does not include a region overlapping with the conductor 542a or the conductor 542b. This can reduce the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Accordingly, the switching speed of the transistor 500 can be increased, so that the transistor 500 can have high frequency characteristics.
The conductive body 560 is sometimes used as a first gate (also referred to as a gate or top gate) electrode. The conductive body 503 is sometimes used as a second gate (also referred to as a back gate or bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by independently changing the potential applied to the conductor 503 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductive body 503, the threshold voltage of the transistor 500 can be made larger and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0V can be reduced as compared with the case where a negative potential is not applied to the conductor 503.
The conductor 503 is disposed so as to overlap with the oxide 530 and the conductor 560. Thus, when a potential is applied to the conductor 560 and the conductor 503, an electric field generated from the conductor 560 and an electric field generated from the conductor 503 are connected to each other, and the channel formation region formed in the oxide 530 can be covered.
In this specification and the like, a structure of a transistor in which a channel formation region is electrically surrounded by electric fields of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel structure. The S-channel structure disclosed in this specification and the like is different from a Fin-type structure and a planar structure. By adopting the S-channel structure, resistance to the short channel effect can be improved, in other words, a transistor in which the short channel effect is less likely to occur can be realized.
The conductor 503 has the same configuration as the conductor 518, and a conductor 503a is formed so as to contact the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b is formed inside the conductor. In the transistor 500, the conductor 503a and the conductor 503b are stacked, but the present invention is not limited to this. For example, the conductor 503 may have a single-layer structure or a stacked-layer structure of three or more layers.
Here, as the conductor 503a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (making it difficult for the impurities to permeate therethrough) is preferably used. Further, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (not easily allowing the oxygen to permeate therethrough). In the present specification, the function of suppressing diffusion of an impurity or oxygen means a function of suppressing diffusion of any or all of the impurity and the oxygen.
For example, by providing the conductor 503a with a function of suppressing oxygen diffusion, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.
When the conductor 503 also functions as a wiring, a highly conductive material containing tungsten, copper, or aluminum as a main component is preferably used as the conductor 503b. Although the conductor 503 is shown as being formed by stacking the conductor 503a and the conductor 503b in this embodiment, the conductor 503 may have a single-layer structure.
The insulator 520, the insulator 522, and the insulator 524 are used as the second gate insulating film.
Here, as the insulator 524 in contact with the oxide 530, an insulator containing oxygen in excess of the stoichiometric composition is preferably used. This oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating is sometimes referred to as "excess oxygen". That is, a region containing excess oxygen (also referred to as "excess oxygen region") is preferably formed in the insulator 524. By providing the above insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V) in the oxide 530 can be reduced O : oxygen vacancy) so that the reliability of the transistor 500 may be improved. Further, in the case where hydrogen enters into oxygen vacancies of the oxide 530, the defect is sometimes (to)Hereinafter, it is sometimes referred to as V O H) Is used as a donor to generate electrons as carriers. In addition, a part of hydrogen is bonded to oxygen bonded to a metal atom, and thus electrons as carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen easily has a normally-on characteristic. Further, since hydrogen in the oxide semiconductor is easily moved by heat, an electric field, or the like, when the oxide semiconductor contains a large amount of hydrogen, reliability of the transistor may be lowered. In one embodiment of the present invention, it is preferable to reduce V in the oxide 530 as much as possible O H is intrinsic or substantially intrinsic to high purity. Thus, in order to obtain such a V O An oxide semiconductor in which H is sufficiently reduced, and it is important that: removing impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as dehydration and dehydrogenation treatment); and supplying oxygen to the oxide semiconductor to fill the oxygen vacancy (sometimes also referred to as a plus oxidation process). By mixing V O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, and stable electrical characteristics can be provided.
Specifically, as the insulator having the excess oxygen region, an oxide material in which a part of oxygen is desorbed by heating is preferably used. The oxide in which oxygen is desorbed by heating means that the amount of oxygen desorbed as converted to oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0X 10 18 atoms/cm 3 Above, preferably 1.0X 10 19 atoms/cm 3 Above, more preferably 2.0 × 10 19 atoms/cm 3 Above, or 3.0 × 10 20 atoms/cm 3 The above oxide film. The surface temperature of the film when the TDS analysis is performed is preferably in the range of 100 ℃ to 700 ℃ or more, or 100 ℃ to 400 ℃ or less.
Further, any one or more of heating treatment, microwave treatment, and RF treatment may be performed so that the insulator having the excess oxygen region and the oxide 530 are brought into contact with each other. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction in which VoH bonding is cleaved occurs in the oxide 530, in other words, hairRaw' V O Dehydrogenation can be carried out by the reaction of H → Vo + H'. Part of the hydrogen generated at this time may be bonded to oxygen and removed as H from the oxide 530 or the insulator in the vicinity of the oxide 530 2 And O. In addition, a part of hydrogen may be gettered by the conductors 542a and 542b.
In addition, as the microwave treatment, for example, a device including a power source that generates high-density plasma or a device including a power source that applies RF to the substrate side is preferably used. For example, oxygen radicals can be generated at high density by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. In the microwave treatment, the pressure is 133Pa or more, preferably 200Pa or more, and more preferably 400Pa or more. Further, as the gas introduced into the apparatus for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow rate ratio (O) 2 /(O 2 + Ar)) is 50% or less, preferably 10% or more and 30% or less.
In the manufacturing process of the transistor 500, it is preferable that the surface of the oxide 530 be exposed and heat-treated. The heat treatment may be performed at, for example, 100 ℃ to 450 ℃, more preferably 350 ℃ to 400 ℃. The heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10ppm or more, 1% or more, or 10% or more of oxidizing gas. For example, the heat treatment is preferably performed under an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce oxygen vacancy (V) O ). The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or inert gas, and then the heat treatment may be performed in an atmosphere containing 10ppm or more, 1% or more, or 10% or more of oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or inert gas.
Further, by subjecting the oxide 530 to an oxidation treatment, oxygen vacancies in the oxide 530 can be filled with supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Further, by reacting hydrogen remaining in the oxide 530 with supplied oxygen, the hydrogen can be removed as H 2 O (dehydration). This can suppress the formation of V by recombination of hydrogen remaining in the oxide 530 and oxygen vacancy O H。
When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, or the like) (the oxygen is not easily permeated).
When the insulator 522 has a function of suppressing diffusion of oxygen and impurities, oxygen contained in the oxide 530 is preferably not diffused to the insulator 520 side. Further, the reaction of the conductor 503 with oxygen contained in the insulator 524 and/or the oxide 530 can be suppressed.
As the insulator 522, for example, an insulator containing aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or the like is preferably used 3 ) Or (Ba, sr) TiO 3 A single layer or a stack of insulators of so-called high-k material such as (BST). When miniaturization and high integration of a transistor are performed, a problem of leakage current or the like may occur due to the thinning of a gate insulating film. By using a high-k material as an insulator used as a gate insulating film, a gate potential at the time of operation of the transistor can be reduced while maintaining a physical thickness.
In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material having a function of suppressing diffusion of impurities, oxygen, and the like (the oxygen is not easily permeated). As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer which suppresses release of oxygen from the oxide 530 and entry of impurities such as hydrogen into the oxide 530 from the peripheral portion of the transistor 500.
Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Further, the insulator may be subjected to nitriding treatment. Further, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.
The insulator 520 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferable because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, the insulator 520 having a stacked-layer structure which is thermally stable and has a high relative dielectric constant can be formed.
In the transistor 500 in fig. 17A to 17C, the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a three-layer stacked structure, but the second gate insulating film may have a single-layer structure, a two-layer structure, or a stacked structure of four or more layers. In this case, the laminated structure of the same material is not limited to the laminated structure, and the laminated structure of different materials may be used.
In the transistor 500, a metal oxide functioning as an oxide semiconductor is used as the oxide 530 including a channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used.
The metal oxide used as the oxide semiconductor can be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. In other embodiments, a metal oxide used as an oxide semiconductor is described in detail.
As a metal oxide used as a channel formation region in the oxide 530, a metal oxide having a band gap of preferably 2eV or more, more preferably 2.5eV or more is preferably used. Thus, by using a metal oxide having a wider band gap, the off-state current of the transistor can be reduced.
In the oxide 530, when the oxide 530a is provided under the oxide 530b, diffusion of impurities from a structure formed under the oxide 530a to the oxide 530b can be suppressed.
The oxide 530 preferably has a stacked-layer structure of a plurality of oxide layers having different atomic number ratios of metal atoms. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530a is preferably larger than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530b. Further, the atomic number ratio of the element M with respect to In the metal oxide used for the oxide 530a is preferably larger than the atomic number ratio of the element M with respect to In the metal oxide used for the oxide 530b. Further, the atomic number ratio of In with respect to the element M In the metal oxide used for the oxide 530b is preferably larger than the atomic number ratio of In with respect to the element M In the metal oxide used for the oxide 530 a.
Preferably, the energy of the conduction band bottom of oxide 530a is made higher than the energy of the conduction band bottom of oxide 530b. In other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.
Here, in the junction of the oxide 530a and the oxide 530b, the energy level of the conduction band bottom changes gently. In other words, the above description can be expressed as the case where the energy levels of the conduction band bottoms at the junction of the oxide 530a and the oxide 530b are continuously changed or continuously joined. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.
Specifically, by including a common element (as a main component) in addition to oxygen in the oxide 530a and the oxide 530b, a mixed layer having a low defect state density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like as the oxide 530 a.
At this time, the main path of carriers is oxide 530b. By providing the oxide 530a with the above structure, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of the transistor 500 can be increased.
Conductors 542a and 542b serving as source and drain electrodes are provided over the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal elements as a component, an alloy combining the above metal elements, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity, and thus are preferable. A metal nitride film such as tantalum nitride is more preferable because it has a barrier property against hydrogen or oxygen.
Although fig. 17B shows a single-layer structure of the conductors 542a and 542B, a stacked structure of two or more layers may be employed. For example, a tantalum nitride film and a tungsten film are preferably stacked. Further, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure in which an aluminum film is stacked over a tungsten film, a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked over a titanium film, or a two-layer structure in which a copper film is stacked over a tungsten film may be employed.
Further, it is also possible to use: a three-layer structure in which an aluminum film or a copper film is stacked over a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereover, a three-layer structure in which an aluminum film or a copper film is stacked over a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereover, or the like. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.
As shown in fig. 17B, a region 543a and a region 543B may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542B) and in the vicinity thereof. At this time, the region 543a is used as one of the source region and the drain region, and the region 543b is used as the other of the source region and the drain region. Further, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.
By providing the conductor 542a (conductor 542 b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543 b) may be reduced. In addition, in the region 543a (the region 543 b), a metal compound layer containing a component of the metal and the oxide 530 included in the conductor 542a (the conductor 542 b) may be formed. In this case, the carrier density of the region 543a (the region 543 b) increases, and the region 543a (the region 543 b) becomes a low-resistance region.
The insulator 544 is provided so as to cover the conductors 542a and 542b, and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and be in contact with the insulator 524.
As the insulator 544, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, or the like can be used. Further, silicon oxynitride, silicon nitride, or the like may be used as the insulator 544.
In particular, as the insulator 544, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing an oxide of one or both of aluminum and hafnium, is preferably used. In particular, hafnium aluminate has a higher heat resistance than a hafnium oxide film. Therefore, crystallization is not easily caused in the heat treatment in the subsequent step, and therefore, this is preferable. In the case where the conductors 542a and 542b are made of a material having oxidation resistance or a material that does not significantly reduce the conductivity even when oxygen is absorbed, the insulator 544 does not need to be provided. The transistor can be designed appropriately according to the required transistor characteristics.
By including the insulator 544, diffusion of impurities such as water and hydrogen contained in the insulator 580 into the oxide 530b can be suppressed. Further, the excess oxygen contained in the insulator 580 can be suppressed from oxidizing the conductor 542.
An insulator 545 is used as the first gate insulating film. The insulator 545 is preferably formed using an insulator which contains excessive oxygen and releases oxygen by heating, similarly to the insulator 524 described above.
Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability.
By providing an insulator containing excess oxygen as the insulator 545, oxygen can be efficiently supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water and hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1nm or more and 20nm or less. The microwave treatment may be performed before and/or after the insulator 545 is formed.
In order to efficiently supply the excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductive body 560. By providing a metal oxide that suppresses oxygen diffusion, excessive oxygen diffusion from the insulator 545 to the conductor 560 is suppressed. In other words, the decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Further, oxidation of the conductive body 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.
Further, the insulator 545 may have a stacked structure as in the second gate insulating film. Since miniaturization and high integration of a transistor may cause a problem such as leakage current due to thinning of a gate insulating film, a gate potential during operation of the transistor can be reduced while maintaining a physical thickness by providing an insulator used as the gate insulating film with a stacked structure of a high-k material and a material having thermal stability. In addition, a stacked structure having thermal stability and a high relative dielectric constant can be realized.
In fig. 17B and 17C, the conductor 560 used as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.
The conductor 560a preferably contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N) 2 O、NO、NO 2 Etc.), copper atoms, etc. Further, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like). By providing the conductor 560a with a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 560b by oxygen contained in the insulator 545. As the conductive material having a function of suppressing oxygen diffusion, for example, tantalum nitride, ruthenium oxide, or the like is preferably used. Further, as the conductive body 560a, an oxide semiconductor applicable to the oxide 530 can be used. In this case, by forming the conductor 560b by a sputtering method, the resistance value of the conductor 560a can be reduced to be a conductor. It may be referred to as an OC (Oxide Conductor) electrode.
As the conductor 560b, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. Since the conductor 560b is also used as a wiring, a conductor having high conductivity is preferably used. The conductive body 560b may have a stacked-layer structure, and for example, a stacked-layer structure of titanium or titanium nitride and the above-described conductive material may be employed.
The insulator 580 is preferably provided on the conductors 542a and 542b with the insulator 544 therebetween. Insulator 580 preferably has a region of excess oxygen. For example, the insulator 580 preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having a void, resin, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region is easily formed in a subsequent step.
Insulator 580 preferably has a region of excess oxygen. By providing the insulator 580 that releases oxygen by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Further, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 580.
The opening of the insulator 580 is formed so as to overlap with a region between the conductive body 542a and the conductive body 542b. Thus, the conductor 560 is provided so as to be fitted into the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.
In the miniaturization of a semiconductor device, it is necessary to shorten the gate length, but it is necessary to prevent the decrease in the conductivity of the conductor 560. Therefore, when the thickness of the conductor 560 is increased, the conductor 560 may have a shape with a high aspect ratio. In the present embodiment, since the conductor 560 is provided so as to be fitted into the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 does not collapse in the process.
Insulator 574 is preferably placed in contact with the top surface of insulator 580, the top surface of conductor 560, and the top surface of insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be formed in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.
For example, as the insulator 574, a metal oxide containing one or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.
In particular, alumina has high barrier properties, and even when it is a thin film of 0.5nm or more and 3.0nm or less, diffusion of hydrogen and nitrogen can be suppressed. Thus, the aluminum oxide formed by the sputtering method can function as a barrier film for impurities such as hydrogen while being used as an oxygen supply source.
Further, an insulator 581 used as an interlayer film is preferably provided over the insulator 574. Similarly to the insulator 524 or the like, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 581.
Further, the conductors 540a and 540b are disposed in openings formed in the insulators 581, 574, 580, and 544. The conductors 540a and 540b are provided so as to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same structure as the conductors 546 and 548 to be described later.
An insulator 582 is provided on the insulator 581. The insulator 582 preferably has a barrier property against oxygen and hydrogen. Therefore, the same material as that of the insulator 514 can be used for the insulator 582. For example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used as the insulator 582.
In particular, alumina has a high barrier effect against permeation of impurities such as oxygen and hydrogen and moisture which cause variations in electrical characteristics of a transistor. Therefore, the alumina can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the manufacturing process of the transistor. In addition, aluminum oxide can suppress oxygen release from the oxide constituting the transistor 500. Therefore, alumina is suitable for the protective film of the transistor 500.
Further, an insulator 586 is provided over the insulator 582. The insulator 586 may be made of the same material as the insulator 379. In addition, by applying a material having a low dielectric constant as these insulators, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, or the like can be used.
Further, a conductor 546, a conductor 548, and the like are embedded in the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586.
The conductor 546 and the conductor 548 are used as a plug or a wiring for connecting to the capacitor 600, the transistor 500, or the transistor 550. The conductors 546 and 548 can be formed using the same material as the conductors 328 and 330.
Further, after the transistor 500 is formed, an opening may be formed so as to surround the transistor 500, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By wrapping the transistor 500 with the high-barrier insulator, entry of moisture and hydrogen from the outside can be prevented. Alternatively, the plurality of transistors 500 may be wrapped with an insulator having high barrier properties against hydrogen or water. In the case where an opening is formed around the transistor 500, for example, when an opening reaching the insulator 522 or the insulator 514 is formed and the high-barrier insulator is formed in contact with the insulator 522 or the insulator 514, the opening can be used as part of the manufacturing process of the transistor 500. As the insulator having high barrier properties against hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 may be used.
Next, a capacitor 600 is provided over the transistor 500. Capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.
The conductor 612 may be provided over the conductors 546 and 548. The conductor 612 is used as a plug or a wiring connected to the transistor 500. The conductive body 610 is used as an electrode of the capacitor 600. Further, the conductor 612 and the conductor 610 can be formed at the same time.
As the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, a metal nitride film containing the above element as a component (a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, and a tungsten nitride film), or the like can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.
In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited thereto, and may have a multilayer structure of two or more layers. For example, a conductor having high tightness against a conductor having barrier properties and a conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.
The conductor 620 is provided so as to overlap the conductor 610 with an insulator 630 interposed therebetween. As the conductor 620, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. A high-melting-point material such as tungsten or molybdenum having both heat resistance and conductivity is preferably used, and tungsten is particularly preferably used. When the conductor 620 is formed simultaneously with other components such as a conductor, cu (copper), al (aluminum), or the like, which is a low-resistance metal material, may be used.
An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 may be provided using the same material as the insulator 379. The insulator 640 may also be used as a planarizing film covering the underlying uneven shape.
With this structure, a semiconductor device using a transistor including an oxide semiconductor can be miniaturized or highly integrated.
This embodiment mode can be combined with other embodiment modes and the like described in this specification as appropriate.
(embodiment 5)
In this embodiment, a metal oxide (hereinafter, also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.
The metal oxide preferably contains at least indium or zinc. It is particularly preferable to contain one of indium and zinc. In addition to indium and zinc, aluminum, gallium, yttrium, tin, and the like are preferably contained. Further, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like may be contained.
< Classification of Crystal Structure >
First, classification of crystal structures in an oxide semiconductor will be described with reference to fig. 18A. Fig. 18A is a diagram illustrating classification of a crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, ga, and Zn).
As shown in fig. 18A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". In addition, the complex Amorphous is contained in "Amorphous". The "crystal" includes CAAC (c-axis-Aligned crystal), nc (nanocrystaline) and CAC (Cloud-Aligned Composite). In addition, the classification of "Crystalline" does not include single crystals, multiple crystals and complete Amorphous. In addition, a single Crystal and a poly Crystal are included in "Crystal".
In addition, the structure in the portion of the outline shown in fig. 18A, which is thickened, is an intermediate state between "Amorphous" and "crystalline", and belongs to a New boundary region (New crystalline phase). In other words, the structure is completely different from "Crystal" or "amophorus" which is unstable in energy properties.
The crystalline structure of the film or substrate can be evaluated using X-Ray Diffraction (XRD) spectroscopy. Here, fig. 18B shows an XRD spectrum of the CAAC-IGZO film classified as "Crystalline" obtained by GIXD (Grazing-inclusion XRD) measurement. The GIXD method is also called a thin film method or Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in fig. 18B is simply referred to as XRD spectrum. Further, the composition of the CAAC-IGZO film shown In fig. 18B is In: ga: zn =4:2:3[ atomic number ratio ]. Further, the CAAC-IGZO film shown in FIG. 18B had a thickness of 500nm.
As shown in fig. 18B, a peak indicating clear crystallinity was detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation was detected in the vicinity of 2 θ =31 °. As shown in fig. 18B, the peak values near 2 θ =31 ° are asymmetric to the left and right with respect to the angle at which the peak intensity is detected as the axis.
In addition, the crystal structure of the film or the substrate can be evaluated using a Diffraction pattern (also referred to as a nanobeam Electron Diffraction) observed by a nanobeam Electron Diffraction method (NBED). FIG. 18C shows the diffraction pattern of the CAAC-IGZO film. Fig. 18C is a diffraction pattern observed from an NBED in which an electron beam is incident in a direction parallel to the substrate. Further, the composition of the CAAC-IGZO film shown In fig. 18C is In: ga: zn =4:2:3[ atomic number ratio ]. In the nanobeam electron diffraction method, an electron diffraction method with a beam diameter of 1nm is performed.
As shown in fig. 18C, a plurality of spots indicating C-axis orientation were observed in the diffraction pattern of the CAAC-IGZO film.
< Structure of oxide semiconductor >
Note that when attention is paid to the crystal structure of the oxide semiconductor, the classification of the oxide semiconductor may be different from that in fig. 18A. For example, the oxide semiconductor can be classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. Examples of the non-single crystal oxide semiconductor include the CAAC-OS and nc-OS described above. The non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, an a-like OS (amorphous oxide semiconductor), an amorphous oxide semiconductor, and the like.
The CAAC-OS, nc-OS and a-like OS will be described in detail.
[CAAC-OS]
The CAAC-OS is an oxide semiconductor including a plurality of crystalline regions whose c-axes are oriented in a specific direction. The specific direction is a thickness direction of the CAAC-OS film, a normal direction of a surface of the CAAC-OS film on which the CAAC-OS film is formed, or a normal direction of a surface of the CAAC-OS film. Further, the crystalline region is a region having periodicity of atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region in which the lattice arrangement is uniform. The CAAC-OS has a region where a plurality of crystal regions are connected in the direction of the a-b plane, and this region may have distortion. The distortion is a portion in which the direction of the lattice arrangement changes between a region in which the lattice arrangement is aligned and another region in which the lattice arrangement is aligned, in a region in which a plurality of crystal regions are connected. In other words, CAAC-OS refers to an oxide semiconductor in which the c-axis is oriented and there is no significant orientation in the a-b plane direction.
Each of the plurality of crystal regions is composed of one or more fine crystals (crystals having a maximum diameter of less than 10 nm). When the crystal region is composed of one fine crystal, the maximum diameter of the crystal region is less than 10nm. When the crystal region is composed of a plurality of fine crystals, the size of the crystal region may be about several tens of nm.
In addition, in the In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) including a layer In which indium (In) and oxygen are stacked (hereinafter, in layer), and a layer In which the elements M, zinc (Zn), and oxygen are stacked (hereinafter, M, zn layer). In addition, indium and the element M may be substituted for each other. Therefore, the (M, zn) layer sometimes contains indium. In addition, the In layer may contain the element M. Note that the In layer sometimes contains Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.
For example, when a CAAC-OS film is subjected to structural analysis using an XRD apparatus, in an Out-of-plane XRD measurement using θ/2 θ scanning, a peak indicating c-axis orientation is detected at 2 θ =31 ° or in the vicinity thereof. Note that the position (2 θ value) of the peak indicating the c-axis orientation may vary depending on the kind, composition, and the like of the metal element constituting the CAAC-OS.
In addition, for example, a plurality of bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. When the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) is taken as a center of symmetry, a certain spot and the other spots are observed at positions point-symmetric to each other.
When the crystal region is observed from the above-mentioned specific direction, the lattice arrangement in the crystal region is substantially hexagonal, but the unit lattice is not limited to regular hexagonal, and may be non-regular hexagonal. In addition, the distortion may have a lattice arrangement such as a pentagonal lattice or a heptagonal lattice. In addition, no clear grain boundary (grain boundary) was observed in the vicinity of the CAAC-OS distortion. That is, the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is probably because CAAC-OS can accommodate distortion due to low density of arrangement of oxygen atoms in the a-b plane direction or variation in bonding distance between atoms due to substitution of metal atoms, or the like.
Further, it was confirmed that a crystal structure of a clear grain boundary is called a so-called polycrystal (polycrystall). Since the grain boundary becomes a recombination center and carriers are trapped, there is a possibility that the on-state current of the transistor is reduced, the field-effect mobility is reduced, or the like. Therefore, CAAC-OS, in which no clear grain boundary is found, is one of crystalline oxides that provide a semiconductor layer of a transistor with an excellent crystal structure. Note that Zn is preferably contained to constitute the CAAC-OS. For example, an In-Zn oxide and an In-Ga-Zn oxide are preferable because the occurrence of grain boundaries can be further suppressed as compared with an In oxide.
CAAC-OS is an oxide semiconductor having high crystallinity and no clear grain boundary is observed. Therefore, it can be said that in CAAC-OS, the decrease in electron mobility due to the grain boundary does not easily occur. Further, since crystallinity of an oxide semiconductor may be reduced by mixing of impurities, generation of defects, or the like, CAAC-OS can be said to be an oxide semiconductor with less impurities or defects (oxygen vacancies, or the like). Therefore, the oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS has high heat resistance and good reliability. The CAAC-OS is also stable against high temperature (so-called heat buildup) in the manufacturing process. Thus, the use of the CAAC-OS for the OS transistor can increase the degree of freedom in the manufacturing process.
[nc-OS]
In nc-OS, the atomic arrangement in a minute region (for example, a region of 1nm to 10nm, particularly 1nm to 3 nm) has periodicity. In other words, nc-OS has a minute crystal. The size of the fine crystal is, for example, 1nm or more and 10nm or less, particularly 1nm or more and 3nm or less, and the fine crystal is referred to as a nanocrystal. Furthermore, no regularity in crystallographic orientation was observed for nc-OS between different nanocrystals. Therefore, orientation was not observed in the entire film. Therefore, nc-OS sometimes does not differ from a-like OS or amorphous oxide semiconductor in some analytical methods. For example, when the nc-OS film is subjected to structural analysis using an XRD device, a peak indicating crystallinity is not detected in an Out-of-plane XRD measurement using a theta/2 theta scan. Further, when the nc-OS film is subjected to electron diffraction using an electron beam having a larger beam diameter (for example, 50nm or more) than the nanocrystal (also referred to as selective electron diffraction), a diffraction pattern similar to a halo pattern is observed. On the other hand, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam having a beam diameter close to or smaller than the size of a nanocrystal (for example, 1nm or more and 30nm or less) is performed on an nc-OS film, an electron diffraction pattern in which a plurality of spots are observed in an annular region centered on a direct spot may be obtained.
[a-like OS]
The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS contains holes or low density regions. That is, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. Further, the hydrogen concentration in the film of the a-like OS is higher than that in the films of nc-OS and CAAC-OS.
< construction of oxide semiconductor >
Next, the details of the CAC-OS will be described. Note that CAC-OS is related to material composition.
[CAC-OS]
CAC-OS is, for example, a structure in which elements contained in a metal oxide are unevenly distributed, and the size of a material containing unevenly distributed elements is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size. Note that a state in which one or more metal elements are unevenly distributed in a metal oxide and a region containing the metal elements is mixed is also referred to as a mosaic shape or a patch (patch) shape in the following, and the size of the region is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less, or a size close thereto.
The CAC-OS is a structure in which a material is divided into a first region and a second region to form a mosaic, and the first region is distributed in a film (hereinafter, also referred to as a cloud). That is, CAC-OS refers to a composite metal oxide in which the first region and the second region are mixed.
Here, the atomic number ratios of In, ga and Zn with respect to the metal elements of CAC-OS constituting the In-Ga-Zn oxide are each referred to as [ In ], [ Ga ] and [ Zn ]. For example, in the CAC-OS of the In-Ga-Zn oxide, the first region is a region whose [ In ] is larger than that In the composition of the CAC-OS film. Further, the second region is a region whose [ Ga ] is larger than [ Ga ] in the composition of the CAC-OS film. Further, for example, the first region is a region whose [ In ] is larger than [ In ] In the second region and whose [ Ga ] is smaller than [ Ga ] In the second region. Further, the second region is a region whose [ Ga ] is larger than [ Ga ] In the first region and whose [ In ] is smaller than [ In ] In the first region.
Specifically, the first region is a region containing indium oxide, indium zinc oxide, or the like as a main component. The second region is a region containing gallium oxide, gallium zinc oxide, or the like as a main component. In other words, the first region can be referred to as a region containing In as a main component. The second region may be referred to as a region containing Ga as a main component.
Note that a clear boundary between the first region and the second region may not be observed.
For example, in CAC-OS of an In-Ga-Zn oxide, it was confirmed that a region containing In as a main component (first region) and a region containing Ga as a main component (second region) were unevenly distributed and mixed based on an EDX surface analysis (mapping) image obtained by Energy Dispersive X-ray spectroscopy (EDX: energy Dispersive X-ray spectroscopy).
When the CAC-OS is used for a transistor, the CAC-OS can have a switching function (on/off function) by a complementary action of the conductivity due to the first region and the insulation due to the second region. In other words, the CAC-OS material has a function of conductivity in one part and an insulating function in the other part, and has a function of a semiconductor in the whole material. By separating the conductive function and the insulating function, each function can be improved to the maximum. Therefore, by using the CAC-OS for the transistor, a high on-state current (I) can be realized on ) High field effect mobility (mu) and good switching operation.
Oxide semiconductors have various structures and various characteristics. The oxide semiconductor according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-likeOS, CAC-OS, nc-OS, and CAAC-OS.
< transistor comprising oxide semiconductor >
Next, a case where the above-described oxide semiconductor is used for a transistor will be described.
By using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Further, a transistor with high reliability can be realized.
In addition, an oxide semiconductor having a low carrier concentration is preferably used for the transistor. For example, the carrier concentration of the oxide semiconductor is 1 × 10 17 cm -3 Hereinafter, it is preferably 1 × 10 15 cm -3 Hereinafter, more preferably 1 × 10 13 cm -3 Hereinafter, 1 × 10 is more preferable 11 cm -3 Hereinafter, it is still more preferable that the content is less than 1X 10 10 cm -3 And is 1X 10 -9 cm -3 The above. In the case where the object is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification and the like, a state where the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". In addition, an oxide semiconductor having a low carrier concentration is sometimes referred to as an "intrinsic high purity" or an "intrinsic substantially high purity" oxide semiconductor.
Since the oxide semiconductor film which is intrinsic or substantially intrinsic in high purity has a lower density of defect states, it is possible to have a lower density of trap states.
Further, the electric charges trapped in the trap level of the oxide semiconductor may take a long time to disappear, and may act as fixed electric charges. Therefore, the transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
Therefore, in order to stabilize the electric characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like are mentioned.
< impurities >
Here, the influence of each impurity in the oxide semiconductor is described.
When the oxide semiconductor contains silicon or carbon which is one of the group 14 elements, a defect level is formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor are adjustedThe concentration of silicon and carbon in the vicinity of the interface with the oxide semiconductor (concentration measured by Secondary Ion Mass Spectrometry (SIMS)) is set to 2X 10 18 atoms/cm 3 Hereinafter, 2 × 10 is preferable 17 atoms/cm 3 The following.
Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level may be formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has a normally-on characteristic. Thus, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS analysis was set to 1X 10 18 atoms/cm 3 Hereinafter, 2 × 10 is preferable 16 atoms/cm 3 The following.
In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are easily generated, and the carrier concentration is increased to make the oxide semiconductor n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor is likely to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, a trap level may be formed. As a result, the electrical characteristics of the transistor may be unstable. Therefore, the nitrogen concentration in the oxide semiconductor measured by SIMS is set to be lower than 5 × 10 19 atoms/cm 3 Preferably 5X 10 18 atoms/cm 3 Hereinafter, more preferably 1 × 10 18 atoms/cm 3 Hereinafter, more preferably 5 × 10 17 atoms/cm 3 The following.
Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to the metal atom to generate water, and thus oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, a part of hydrogen is bonded to oxygen bonded to a metal atom, and thus electrons as carriers are generated in some cases. Therefore, a transistor having an oxide semiconductor containing hydrogen easily has a normally-on characteristic. Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by SIMS is set to be lower than 1 × 10 20 atoms/cm 3 Preferably less than 1X 10 19 atoms/cm 3 More preferably less than 5X 10 18 atoms/cm 3 Still more preferably less than 1X 10 18 atoms/cm 3 。
By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.
Note that this embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
(embodiment 6)
This embodiment mode shows an example of a semiconductor wafer on which the semiconductor device and the like described in the above embodiment modes are formed, and an electronic component in which the semiconductor device is mounted.
< semiconductor wafer >
First, an example of a semiconductor wafer on which a semiconductor device and the like are formed will be described with reference to fig. 19A.
A semiconductor wafer 4800 shown in fig. 19A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the top surface of the wafer 4801. A portion of the top surface of the wafer 4801 where the circuit portion 4802 is not provided corresponds to a space 4803 which is a region for dicing.
The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. The wafer 4801 may be thinned by polishing the back surface of the wafer 4801 on which the plurality of circuit portions 4802 are formed. By the above steps, warpage of the wafer 4801 and the like can be reduced, and thus the size of the member can be reduced.
Next, a dicing step is performed. The dicing is performed along the dividing lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) shown by the dotted lines. In order to facilitate the cutting process, the voids 4803 are preferably formed such that the dividing lines SCL1 are parallel to each other, the dividing lines SCL2 are parallel to each other, and the dividing lines SCL1 are perpendicular to the dividing lines SCL 2.
By performing the dicing step, the chip 4800a shown in fig. 19B can be diced from the semiconductor wafer 4800. Chip 4800a includes wafer 4801a, circuit portion 4802, and void 4803a. Further, the void 4803a is preferably as small as possible. In this case, the width of the space 4803 between adjacent circuit portions 4802 may be substantially equal to the dividing portion of the dividing line SCL1 or the dividing portion of the dividing line SCL 2.
The shape of the element substrate according to one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in fig. 19A. For example, it may be a rectangular shaped semiconductor wafer. In addition, the shape of the element substrate can be changed as appropriate depending on the manufacturing process and manufacturing equipment of the element.
< electronic Components >
Fig. 19C illustrates a perspective view of the electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in fig. 19C includes a chip 4800a in a mold 4711. A memory device or the like according to one embodiment of the present invention can be used as the chip 4800a.
In fig. 19C, a part of the electronic component 4700 is omitted to show the inside thereof. The electronic component 4700 includes a land (land) 4712 on the outside of the mold 4711. The land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a via a lead 4714. The electronic component 4700 is mounted on the printed circuit board 4702, for example. The mounting substrate 4704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit boards 4702, respectively.
Fig. 19D illustrates a perspective view of the electronic component 4730. The electronic component 4730 is an example of an SiP (System in package) or an MCM (Multi Chip Module). In the electronic component 4730, an interposer (interposer) 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
The semiconductor device 4710 can be formed using, for example, a chip 4800a, the semiconductor device described in the above embodiment, a High Bandwidth Memory (HBM), or the like. Further, the semiconductor device 4735 may use an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.
The package substrate 4732 may use a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. As the interposer 4731, a silicon interposer, a resin interposer, or the like can be used.
The interposer 4731 has a plurality of wirings and a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are formed of a single layer or a plurality of layers. Furthermore, the interposer 4731 has a function of electrically connecting an integrated circuit provided on the interposer 4731 and an electrode provided on the package substrate 4732. Therefore, the interposer is also sometimes referred to as a "rewiring substrate" or an "intermediate substrate". Further, a through electrode may be provided in the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected to each other through the through electrode. In addition, in the case of using a Silicon interposer, a TSV (Through Silicon Via) may be used as the Through electrode.
As the insertion plate 4731, a silicon insertion plate is preferably used. Since the silicon interposer does not need to be provided with an active element, it can be manufactured at a lower cost than an integrated circuit. The wiring formation of the silicon interposer can be performed in a semiconductor process, and thus a fine wiring which is difficult to form when a resin interposer is used is easily formed.
In HBM, many wires need to be connected in order to realize a wide memory bandwidth. Therefore, it is required that a fine wiring can be formed with high density on an interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer for mounting the HBM.
In addition, in SiP and MCM using a silicon interposer, a decrease in reliability due to a difference in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Further, since the surface flatness of the silicon interposer is high, a connection failure is less likely to occur between the integrated circuit provided in the silicon interposer and the silicon interposer. It is particularly preferred to use a silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged laterally across and on the interposer.
Further, a heat sink (heat radiation plate) may be provided so as to overlap with the electronic component 4730. In the case where a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 4731 uniform. For example, in the electronic component 4730 described in this embodiment, the semiconductor device 4710 and the semiconductor device 4735 are preferably made to have the same height.
In order to mount the electronic component 4730 on another substrate, an electrode 4733 may be provided on the bottom of the package substrate 4732. Fig. 19D shows an example of forming the electrode 4733 with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 4733 may be formed using a conductive needle. PGA (Pin grid array) mounting can be achieved by providing conductive pins in a matrix on the bottom of the package substrate 4732.
The electronic component 4730 may be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, a mounting method such as SPGA (strained Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad J-leaded Package), or QFN (Quad Flat Non-leaded Package) can be used.
This embodiment mode can be combined with other embodiment modes and the like described in this specification as appropriate.
(embodiment 7)
In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention is described.
The semiconductor device according to one embodiment of the present invention can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book reader terminal, a digital camera, a video playback device, a navigation system, a game machine, and the like). In addition, it can be used for image sensors, ioT (Internet of Things), medical treatment, and the like. Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a mainframe computer such as a server system.
An example of an electronic device including a semiconductor device according to one embodiment of the present invention will be described. Fig. 20A to 20J, and 21A to 21E illustrate a case where the electronic component 4700 or the electronic component 4730 having the semiconductor device is included in each electronic apparatus.
[ Mobile telephone ]
An information terminal 5500 shown in fig. 20A is a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511, includes a touch panel in the display portion 5511 as an input interface, and buttons are provided on the housing 5510.
By applying the semiconductor device according to one embodiment of the present invention to the information terminal 5500, a temporary file (e.g., a cache memory when a web browser is used) generated when a program is executed can be held.
[ wearable terminal ]
Fig. 20B shows an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.
Similarly to the information terminal 5500 described above, by applying the semiconductor device according to one embodiment of the present invention to a wearable terminal, a temporary file generated when a program is executed can be held.
[ information terminal ]
Fig. 20C illustrates a desktop information terminal 5300. The desktop information terminal 5300 includes an information terminal main body 5301, a display portion 5302, and a keyboard 5303.
Similarly to the information terminal 5500 described above, by applying the semiconductor device according to one embodiment of the present invention to the desktop information terminal 5300, a temporary file generated when a program is executed can be held.
Note that, in the above example, fig. 20A to 20C each show an example in which a smartphone, a wearable terminal, and a desktop information terminal are used as electronic devices, but information terminals other than a smartphone, a wearable terminal, and a desktop information terminal may be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital assistants), notebook information terminals, and workstations.
[ electric products ]
Fig. 20D shows an electric refrigerator-freezer 5800 as an example of an electric product. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer corresponding to IoT (Internet of Things).
The semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. By using the internet or the like, the electric refrigerator-freezer 5800 can transmit information such as the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food to an information terminal or the like. The electric refrigerator-freezer 5800 can hold a temporary file generated when the information is transmitted in the semiconductor device.
In the above examples, an electric refrigerator-freezer is described as an electric appliance, but examples of other electric appliances include a vacuum cleaner, a microwave oven, an electric rice cooker, a water heater, an IH cooker, a water fountain, a cooling and heating machine including an air conditioner, a washing machine, a clothes dryer, an audio-visual device, and the like.
[ Game machine ]
Fig. 20E shows a portable game machine 5200 as an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
Fig. 20F shows a stationary game machine 7500 as an example of the game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 may be connected to the controller 7522 in a wireless manner or a wired manner. Although not shown in fig. 20F, the controller 7522 may include a display unit for displaying an image of a game, a touch panel and a lever as an input interface other than buttons, a rotary hand grip, a slide hand grip, and the like. Note that the shape of the controller 7522 is not limited to the shape shown in fig. 20F, and the shape of the controller 7522 may be changed depending on the type of game. For example, in a shooting game such as FPS (First Person Shooter), a controller that simulates the shape of a gun may be used as a trigger using a button. Further, for example, in a music game or the like, a controller imitating the shape of a musical instrument, a musical device, or the like may be used. Further, the stationary game machine may be provided with a camera, a depth sensor, a microphone, and the like, and operated by a gesture and/or sound of the player instead of the controller.
The video image of the game machine may be output from a display device such as a television device, a display for a personal computer, a display for a game, or a head mount display.
By using the semiconductor device described in the above embodiment mode for the mobile game machine 5200 or the stationary game machine 7500, the mobile game machine 5200 or the stationary game machine 7500 with low power consumption can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.
By using the semiconductor device described in the above embodiment for the portable game machine 5200 or the stationary game machine 7500, it is possible to hold a temporary file for calculation generated when a game is executed.
In fig. 20E, a portable game machine is shown as an example of the game machine. In addition, fig. 20F shows a home stationary game machine. The electronic device according to one embodiment of the present invention is not limited to this. Examples of the electronic device according to an embodiment of the present invention include a arcade game machine installed in an amusement facility (a game center, an amusement park, and the like), a ball-shooting machine for shooting balls installed in a sports facility, and the like.
[ moving body ]
The semiconductor device described in the above embodiment can be applied to an automobile as a mobile body and the vicinity of a driver seat of the automobile.
Fig. 20G shows an automobile 5700 as an example of the mobile body.
An instrument panel capable of displaying a speedometer, a tachometer, a travel distance, a fuel charge amount, a gear state, a setting of an air conditioner, and the like to provide various information is provided near a driver seat of the automobile 5700. Further, a display device for displaying the above information may be provided near the driver seat.
In particular, by displaying an image captured by an imaging device (not shown) provided in the automobile 5700 on the display device, it is possible to supplement a view blocked by a pillar or the like, a blind spot of a driver's seat, and the like, and to improve safety. That is, by displaying an image captured by an imaging device provided outside the automobile 5700, the field of view can be supplemented to avoid a blind spot, thereby improving safety.
The semiconductor device described in the above embodiment can temporarily store information, and for example, the computer can be applied to an automatic driving system of the automobile 5700, a system for performing navigation, risk prediction, or the like, to temporarily store necessary information. In addition, information such as navigation and risk prediction may be temporarily displayed on the display device. In addition, the video of the drive recorder attached to the automobile 5700 can be retained.
Although an automobile is described as an example of the mobile body in the above example, the mobile body is not limited to an automobile. Examples of the moving body include an electric train, a monorail, a ship, and a flying object (a helicopter, an unmanned plane (drone), an airplane, and a rocket).
[ Camera ]
The semiconductor device described in the above embodiment can be applied to a camera.
Fig. 20H shows a digital camera 6240 as an example of an imaging device. The digital camera 6240 includes a housing 6241, a display portion 6242, an operation switch 6243, a shutter button 6244, and the like, and is mounted with a detachable lens 6246. Here, the digital camera 6240 is configured such that the lens 6246 can be detached from the case 6241, but the lens 6246 and the case 6241 are formed integrally. The digital camera 6240 may further include a flash device, a viewfinder, and the like, which are separately installed.
By using the semiconductor device described in the above embodiment mode for the digital camera 6240, the digital camera 6240 with low power consumption can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.
[ video Camera ]
The semiconductor device described in the above embodiment mode can be applied to a video camera.
Fig. 20I shows a video camera 6300 as an example of an image pickup apparatus. The video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, operation switches 6304, a lens 6305, a connection portion 6306, and the like. An operation switch 6304 and a lens 6305 are provided over the first housing 6301, and a display portion 6303 is provided over the second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connection portion 6306, and an angle between the first housing 6301 and the second housing 6302 can be changed by the connection portion 6306. The image of the display portion 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connecting portion 6306.
When recording an image captured by the video camera 6300, encoding according to the data recording method needs to be performed. With the semiconductor device, the video camera 6300 can hold a temporary file generated when encoding is performed.
[ICD]
The semiconductor device described in the above embodiment can be applied to an Implantable Cardioverter Defibrillator (ICD).
Fig. 20J is a schematic cross-sectional diagram illustrating an example of an ICD. The ICD body 5400 includes at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 for the right atrium, and a wire 5403 for the right ventricle.
The ICD body 5400 is surgically placed in the body with two wires passing through the subclavian vein 5405 and the superior vena cava 5406 of the body, and with the tip of one wire placed in the right ventricle and the tip of the other wire placed in the right atrium.
The ICD body 5400 functions as a cardiac pacemaker and paces the heart when the heart rhythm is outside a prescribed range. In addition, defibrillation therapy is used when the heart rhythm is not improved even during pacing (rapid ventricular frequency or ventricular fibrillation, etc.).
To properly pace and defibrillate, the ICD subject 5400 needs to constantly monitor heart rhythm. Thus, ICD body 5400 includes sensors to detect heart rhythm. Further, the ICD body 5400 may store data of the heart rhythm measured by the sensor, the number of times of treatment with pacing, time, and the like in the electronic component 4700.
Further, since power is received by the antenna 5404, the power is charged to the battery 5401. Further, by including a plurality of batteries in the ICD body 5400, safety can be improved. Specifically, even if some of the batteries in the ICD body 5400 fail, other batteries may function to be used as an auxiliary power source.
In addition to the antenna 5404 capable of receiving power, an antenna capable of transmitting a physiological signal may be included, and a system for monitoring cardiac activity in which a physiological signal such as a pulse rate, a respiration rate, a heart rhythm, or a body temperature can be confirmed by an external monitoring device may be configured.
[ expansion device for PC ]
The semiconductor device described in the above embodiment can be applied to a Computer such as a PC (Personal Computer) or an expansion device for an information terminal.
Fig. 21A shows an expansion device 6100 provided outside a PC, which can be carried and on which a chip capable of storing information is mounted, as an example of the expansion device. The expansion device 6100 is connected to a PC via a USB (Universal Serial Bus), for example, and can store information using the chip. Note that, although fig. 21A shows a portable expansion device 6100, the expansion device according to one embodiment of the present invention is not limited to this, and for example, a large-structure expansion device in which a cooling fan or the like is installed may be employed.
The expansion device 6100 includes a housing 6101, a cover 6102, a USB connector 6103, and a substrate 6104. A substrate 6104 is accommodated in the housing 6101. The substrate 6104 is provided with a circuit which drives the semiconductor device and the like described in the above embodiments. For example, the substrate 6104 is mounted with the electronic component 4700 and the controller chip 6106. The USB connector 6103 is used as an interface for connecting to an external device.
[ SD card ]
The semiconductor device described in the above embodiment can be applied to an SD card that can be mounted on electronic devices such as an information terminal and a digital camera.
Fig. 21B is an external view of the SD card, and fig. 21C is an internal structure of the SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 has a function of an interface to connect to an external device. A substrate 5113 is accommodated in the housing 5111. The substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the substrate 5113 is mounted with the electronic component 4700 and the controller chip 5115. The circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and may be changed as appropriate. For example, a write circuit, a row driver, a read circuit, and the like included in the electronic component may be mounted on the controller chip 5115 without being mounted on the electronic component 4700.
By providing the electronic component 4700 also on the back surface side of the substrate 5113, the capacity of the SD card 5110 can be increased. A wireless chip having a wireless communication function may be provided over the substrate 5113. This enables wireless communication between the external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.
[SSD]
The semiconductor device described in the above embodiment mode can be applied to an SSD (Solid State Drive) which can be mounted on an electronic device such as an information terminal.
Fig. 21D is an external view of the SSD, and fig. 21E is a schematic view of an internal structure of the SSD. The SSD5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 has a function of an interface to connect to an external device. A substrate 5153 is accommodated in the housing 5151. The substrate 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the substrate 5153 is mounted with the electronic component 4700, the memory chip 5155, and the controller chip 5156. By providing the electronic component 4700 also on the back side of the substrate 5153, the capacity of the SSD5150 can be increased. A working memory is mounted in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, and the like are mounted in the controller chip 5156. Note that the circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to the above description, and may be appropriately changed depending on the case. For example, a memory serving as a working memory may be provided in the controller chip 5156.
[ computer ]
The computer 5600 illustrated in fig. 22A is an example of a large computer. In the computer 5600, a plurality of rack-mount computers 5620 are housed in racks 5610.
The computer 5620 may have a structure of a perspective view shown in fig. 22B, for example. In fig. 22B, a computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals and the like. The slot 5631 has a personal computer card 5621 inserted therein. Also, the personal computer card 5621 includes a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, which are connected to the motherboard 5630.
A personal computer card 5621 shown in fig. 22C is an example of a processing board including a CPU, a GPU, a semiconductor device, and the like. The personal computer card 5621 has a board 5622. Further, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that fig. 22C shows a semiconductor device other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, and for description of the semiconductor devices, reference is made to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.
The connection terminal 5629 has a shape of a slot 5631 into which the motherboard 5630 can be inserted, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 to the motherboard 5630. The specification of the connection terminal 5629 includes PCIe and the like.
The connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as interfaces for supplying power to the personal computer card 5621, inputting signals, and the like, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the personal computer card 5621 or the like. Examples of the specifications of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), and the like. When video signals are output from the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625, HDMI (registered trademark) or the like can be used as each specification.
Semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal, and semiconductor device 5626 and plate 5622 can be electrically connected to each other by inserting the terminal into a socket (not shown) included in plate 5622.
Semiconductor device 5627 includes a plurality of terminals, and by soldering the terminals to wirings included in board 5622 by reflow soldering, semiconductor device 5627 and board 5622 can be electrically connected. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. As the semiconductor device 5627, for example, the electronic component 4730 can be used.
Semiconductor device 5628 includes a plurality of terminals, and by solder-reflowing the terminals to wirings included in board 5622, semiconductor device 5628 and board 5622 can be electrically connected. Examples of the semiconductor device 5628 include a semiconductor device and the like. As the semiconductor device 5628, for example, the electronic component 4700 can be used.
The computer 5600 can be used as a parallel computer. By using the computer 5600 as a parallel computer, large-scale calculation necessary for artificial intelligence learning and reasoning, for example, can be performed.
By using the semiconductor device according to one embodiment of the present invention in the various electronic devices, miniaturization, high speed, and low power consumption of the electronic devices can be achieved. Further, the semiconductor device according to one embodiment of the present invention has low power consumption, and thus can reduce heat generation in a circuit. Thus, adverse effects on the circuit itself, peripheral circuits, and modules due to the heat generation can be reduced. Further, by using the semiconductor device according to one embodiment of the present invention, an electronic device which stably operates even in a high-temperature environment can be realized. This can improve the reliability of the electronic device.
This embodiment mode can be combined with other embodiment modes and the like described in this specification as appropriate.
[ examples ]
The operation of the semiconductor device 100 shown in fig. 1A was verified by a circuit simulator. As the circuit simulator, smartSpice manufactured by SILVACO corporation was used.
As a verification condition, it is assumed that an OS transistor having a channel length and a channel width of 60nm is used as the transistor Tr11 and the transistor Tr 21. It is assumed that Si transistors each having a channel length and a channel width of 1 μm are used as the transistors Tr12 and Tr22. The capacitance values of both the capacity Cb1 and the capacity Cb2 are set to 1pF. VSS was set to 0.0V, and VDD was set to 6.0V.
Assuming five references (0.9V, 1.1V, 1.3V, 1.5V, 1.7V) as Vin1 held in the node SN1 and two references (0.0V, 0.7V) as Vref held in the node SN2, the output voltage Vout of all combinations is calculated with a circuit simulator. Note that the five references of Vin1 all satisfy equations 6 and 7 shown in the above embodiment.
Fig. 23A and 23B show the calculation results. The vertical axis of fig. 23A and 23B represents the output voltage Vout and the horizontal axis represents Time (Time). In this example, it is assumed that the write operation described in the above embodiment is ended at time 0.0 μ s. More specifically, the period T32 described in the above embodiment ends, and the potentials of the node SN1 and the node SN2 are held.
Fig. 23A shows the output voltage Vout of each Vin1 reference when Vref is 0.7V. Fig. 23B shows the output voltage Vout of each Vin1 reference when Vref is 0.0V.
In the semiconductor device 100, VSS is supplied to the terminal PS1 and the terminal PS2 until the time 0.5 μ s. The read operation starts at time 0.5 mus. In the readout operation, the terminal PS1 is supplied with VDD and the terminal OUT is supplied with the output voltage Vout.
Fig. 24 shows a calculation result of the source-drain voltage Vds _ Tr12 of the transistor Tr12 after the start of the readout operation. Since the potential of the node BN is VSS (0.0V) until the start of the reading operation, vds _ Tr12 is about 6V after the potential of the terminal PS1 changes from VSS to VDD (6.0V).
Since Vin1 is equal to or higher than the threshold voltage of the transistor Tr12, when the potential of the terminal PS1 becomes VDD, a current flows between the source and the drain of the transistor Tr12, and the potential of the node BN rises. The larger Vin1, the more current flows between the source and the drain of the transistor Tr 12. Therefore, the larger Vin1 is, the more the potential of the node BN rises. That is, the larger Vin1, the smaller Vds _ Tr 12. As a result, when Vref is constant, vout increases as Vin1 increases.
Fig. 23A and 23B show that a voltage corresponding to equation 5 described in the above embodiment can be obtained as the output voltage Vout. In this embodiment, vin2 in equation 5 corresponds to Vref.
Fig. 25 is a graph showing the relationship of Vin1 to Vout calculated by the circuit simulator. The circle (". Smallcircle") in the drawing indicates the relationship between Vin1 and Vout when Vref is 0.0V, and the quadrangle (". □") indicates the relationship between Vin1 and Vout when Vref is 0.7V.
Fig. 25 shows an approximate straight line 851 and an approximate straight line 852. The approximate straight line 851 is an approximate straight line of the circle (". Smallcircle"), and is a relationship between Vin1 and Vout when Vref is 0.0V. The approximate straight line 852 is an approximate straight line of the above-mentioned quadrangle ("□"), and approximates the relationship between Vin1 and Vout when Vref is 0.7V. Coefficient of determination R of approximate straight line 851 2 (contribution ratio) is 0.9966, and the coefficient R of the approximate straight line 852 can be determined 2 (contribution ratio) is 0.9955. Thus, the following steps are carried out: when Vref is constant, the output voltage Vout varies according to the variation of Vin 1.
As a result of verification using a circuit simulator, it is found that the semiconductor device 100 according to one embodiment of the present invention changes the output voltage Vout according to the change in Vin1 when Vref is constant. In addition, it is known that: the semiconductor device 100 according to one embodiment of the present invention can accurately read the held analog data.
[ description of symbols ]
100: semiconductor device, 110a: holding circuit, 110b: holding circuit, 120a: bootstrap circuit, 120b: bootstrap circuit, 130: source follower circuit, tr11: transistor, tr12: transistor, tr21: transistor, tr22: transistor, SN1: node, SN2: node, BN: node, cb1: capacitor, cb2: capacitor, IN1: terminal, IN2: terminal, PS1: terminal, PS2: terminal, WW1: terminal, WW2: and a terminal.

Claims (11)

1. A semiconductor device includes first to fifth circuits,
wherein the first circuit has a function of holding a first potential,
the second circuit has a function of boosting the first potential,
the third circuit has a function of holding the second potential,
the fourth circuit has a function of boosting the second potential,
the fifth circuit has a function of outputting a third potential corresponding to a potential difference between the first potential and the second potential.
2. The semiconductor device according to claim 1, comprising first to fourth transistors, a first capacitor, and a second capacitor,
wherein the first circuit comprises the first transistor and the first capacitor,
the second circuit comprises the second transistor and the first capacitor,
the third circuit includes the third transistor and the second capacitor,
the fourth circuit comprises the fourth transistor and the second capacitor,
and the fifth circuit includes the second transistor and the fourth transistor.
3. The semiconductor device according to claim 1 or 2,
wherein the first transistor and the third transistor include an oxide semiconductor in a semiconductor forming a channel.
4. The semiconductor device according to claim 3, wherein the first and second semiconductor layers are stacked,
wherein the second transistor and the fourth transistor include an oxide semiconductor in a semiconductor forming a channel.
5. The semiconductor device according to claim 3 or 4,
wherein the oxide semiconductor includes at least one of indium and zinc.
6. A semiconductor device includes first to fourth transistors, a first capacitor, and a second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first terminal,
the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor,
a gate of the first transistor is electrically connected to a second terminal,
one of a source and a drain of the third transistor is electrically connected to a third terminal,
the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor,
a gate of the third transistor is electrically connected to a fourth terminal,
one of a source and a drain of the second transistor is electrically connected to a fifth terminal,
the other of the source and the drain of the second transistor is electrically connected to a seventh terminal,
one of a source and a drain of the fourth transistor is electrically connected to a sixth terminal,
the other of the source and the drain of the fourth transistor is electrically connected to the seventh terminal,
one electrode of the first capacitor is electrically connected to the gate of the second transistor,
the other electrode of the first capacitor is electrically connected to the seventh terminal,
one electrode of the second capacitor is electrically connected to a gate of the fourth transistor,
the other electrode of the second capacitor is electrically connected to the seventh terminal.
7. The semiconductor device as set forth in claim 6,
wherein the first terminal is supplied with analog data.
8. The semiconductor device according to claim 6 or 7,
wherein the third terminal is electrically connected to the sixth terminal.
9. The semiconductor device according to any one of claims 6 to 8,
wherein the first transistor and the third transistor include an oxide semiconductor in a semiconductor layer forming a channel.
10. The semiconductor device according to claim 9, wherein the first and second electrodes are formed of a conductive material,
wherein the second transistor and the fourth transistor include an oxide semiconductor in a semiconductor layer in which a channel is formed.
11. The semiconductor device according to claim 9 or 10,
wherein the oxide semiconductor includes at least one of indium and zinc.
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