Nothing Special   »   [go: up one dir, main page]

CN115425019A - Multi-chip bridging integrated structure and assembling method thereof - Google Patents

Multi-chip bridging integrated structure and assembling method thereof Download PDF

Info

Publication number
CN115425019A
CN115425019A CN202211058003.1A CN202211058003A CN115425019A CN 115425019 A CN115425019 A CN 115425019A CN 202211058003 A CN202211058003 A CN 202211058003A CN 115425019 A CN115425019 A CN 115425019A
Authority
CN
China
Prior art keywords
chip
micro
adapter plate
array
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211058003.1A
Other languages
Chinese (zh)
Inventor
李宝霞
赵超
张庆学
何亨洋
张辽辽
张宁
胡佳伟
霍瑞霞
南旭惊
武洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Microelectronics Technology Institute
Original Assignee
Xian Microelectronics Technology Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Microelectronics Technology Institute filed Critical Xian Microelectronics Technology Institute
Priority to CN202211058003.1A priority Critical patent/CN115425019A/en
Publication of CN115425019A publication Critical patent/CN115425019A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The invention discloses a multi-chip bridging integrated structure and an assembling method thereof, wherein the integrated structure comprises a plurality of circuit units, a first chip in the circuit units is bonded on an adapter plate through a first micro-bump array, an outer pin of a connecting part of a second chip adapter plate is bonded on the adapter plate through a second micro-bump array, an outer pin of a connecting part of a second chip packaging substrate is bonded on a packaging substrate through a welding column array, the adapter plate is bonded on the packaging substrate through a welding ball array formed by welding balls, the first chip and the second chip are realized through an electric interconnection path formed by first micro-bumps, metal wires on the adapter plate and second micro-bumps, and a plurality of conductive channels are arranged on the adapter plate. When the chip structure needs array type expansion, the circuit unit can be expanded along the transverse direction and/or the longitudinal direction, the area of the adapter plate does not need to be expanded correspondingly in multiples, the reliability of the adapter plate in the working process can be improved, the yield of the adapter plate is ensured, and the cost is reduced.

Description

Multi-chip bridging integrated structure and assembling method thereof
Technical Field
The invention belongs to the technical field of advanced electronic packaging, and relates to a multi-chip bridging integrated structure and an assembling method thereof.
Background
The existing von Neumann computing system adopts a structure of separating operation and storage, a computing unit reads data from a memory firstly, and then stores the new data back to the memory after the computation is finished. The transmission speed of data between the storage unit and the computing unit cannot keep up with the data computing speed, and the transmission power consumption is far larger than the computing power consumption, so that the problems of a storage wall and a power consumption wall between computing and storing are solved. With the development of image processing and artificial intelligence, the operation complexity is improved, the data amount required to be operated is increased rapidly, a large amount of data needs to be moved frequently between a computing unit and a storage unit, and an appropriate means is urgently needed to improve the data moving efficiency and reduce the data moving overhead. The storage chip and the calculation chip are packaged together in an advanced packaging mode, so that the storage chip and the calculation chip are extremely adjacent to each other, the length of a connecting line between the storage chip and the calculation chip is greatly shortened, the number of the connecting lines is further increased, the number conveying speed is increased, the conveying energy consumption is reduced, and the problems of a storage wall and a power consumption wall can be effectively relieved and weakened. At present, 2D and 2.5D packaging schemes for packaging a processor chip and a memory chip on the same organic carrier plate or the same TSV silicon transfer substrate have been provided, and the distance between a computing chip and a memory chip is reduced to greatly improve computing and storing performance and energy efficiency.
With the increase of the number of processor cores, the size of a processor chip and the number of memory chips to be configured are increased, the conventional 2.5D packaging scheme requires not only a higher interconnection wiring density of a 2.5D TSV silicon interposer substrate but also a larger interposer substrate size, which leads to a reduction in the yield of the interposer substrate and an increase in cost. As shown in fig. 6, in the conventional package integrated structure, all chips are all bonded on an adapter plate, which causes the area of the adapter plate to be at least larger than the sum of the areas of all chips thereon, and the enlargement of the area of the adapter plate directly brings about the improvement of the preparation difficulty, the reduction of the preparation yield, and the increase of the cost; in addition, in the conventional package integrated structure, if the area of the interposer needs to be expanded in an array manner, the area of the interposer needs to be expanded correspondingly in multiples, the area of the interposer may exceed the process preparation capacity of the interposer, and the expansion cannot be realized at all.
Disclosure of Invention
The invention aims to solve the problems that in the prior art, as the size of a processor chip and the number of memory chips to be configured are increased, the area of an adapter plate is required to be at least larger than the sum of the areas of the chips, and the adapter plate has higher wiring density and larger size, but the yield of the adapter plate is reduced, the cost is increased, and the working reliability of the adapter plate is insufficient, and provides a multi-chip bridging integrated structure and an assembling method thereof.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
a multi-chip bridging integrated structure comprises a plurality of circuit units, wherein each circuit unit comprises a first chip, a second chip, an adapter plate, a packaging substrate, a first micro bump, a second micro bump, a welding ball and a welding column;
the first chip is bonded on the upper surface of the adapter plate through a first micro-bump array, the second chip comprises an adapter plate connecting part and a packaging substrate connecting part, an outer pin of the second chip adapter plate connecting part is bonded on the upper surface of the adapter plate through a second micro-bump array, the outer pin of the second chip packaging substrate connecting part is bonded on the packaging substrate through a welding column array, the welding column array is formed by welding columns, the lower surface of the adapter plate is bonded on the packaging substrate through a welding ball array, the electrical interconnection between the first chip and the second chip is realized through a first micro-bump, a metal wiring on the adapter plate and a passage formed by a second micro-bump, and a plurality of conductive channels are formed in the adapter plate.
The invention is further improved in that:
the second chip adapter plate connecting part is positioned at one end of the second chip, and an outer pin at one end of the second chip is bonded on the upper surface of the adapter plate through a second micro bump array; the second chip packaging substrate connecting part is positioned at the other end of the second chip, and the outer pin of the other end of the second chip is bonded on the packaging substrate through the welding column array.
The second chip adapter plate connecting parts are positioned at two corresponding ends of the second chip, and outer pins at two corresponding ends of the second chip are respectively bonded on the upper surfaces of two adjacent adapter plates through a second micro bump array; the second chip packaging substrate connecting part is positioned in the middle of the second chip, and outer pins of the middle of the second chip are bonded on the packaging substrate through the welding column array.
The embedded chip is arranged in the adapter plate, outer pins of the embedded chip are opposite to outer pins of the first chip, the embedded chip and the first chip are electrically interconnected through the first micro-bumps, and the embedded chip and the second chip are electrically interconnected through metal wiring on the connecting plate and the second micro-bumps.
The thickness of the adapter plate is 50-200 μm, the diameters of the first micro-convex point and the second micro-convex point are 10-100 μm, the diameter of the solder ball is 100-300 μm, and the diameter of the solder column is 100-300 μm.
The array pitch of the welding column array is larger than that of the second micro-bump array, and the array pitch of the first micro-bump array and the array pitch of the second micro-bump array are both smaller than that of the solder ball array.
The adapter plate is an inorganic adapter substrate or an organic adapter substrate.
The first chip is a processing chip.
The second chip is a memory chip.
A method of assembling a multi-chip bridging integrated structure, comprising the steps of:
the adapter plate is assembled on the packaging substrate in a micro mode through a reflow process or a hot pressing process, and the electrical interconnection between the adapter plate and the packaging substrate is achieved through a solder ball array formed by solder balls;
assembling the first chip on the upper surface of the adapter plate in a micro-assembling way through a reflow process or a hot pressing process;
and micro-assembling the second chip on the upper surfaces of the adapter plate and the packaging substrate through a reflow process or a hot pressing process.
Compared with the prior art, the invention has the following beneficial effects:
according to the multi-chip bridging integrated structure, a first chip is bonded on an adapter plate through a first micro-bump array formed by first micro-bumps, one part of a second chip is bonded on the adapter plate through a second micro-bump array, the other part of the second chip is bonded on a packaging substrate through welding posts, and the first chip and the second chip are electrically interconnected through the first micro-bumps, metal wiring on the adapter plate and electrical interconnection paths formed by the second micro-bumps to form independent circuit units. When the chip structure needs array type expansion, the circuit unit can be expanded along the transverse direction and/or the longitudinal direction, the communication between chips can be realized without the area of the adapter plate being correspondingly expanded by multiple times, the reliability of the adapter plate in the working process can be improved, the yield of the adapter plate is ensured, and the cost is reduced.
Furthermore, the embedded chip is embedded in the adapter plate, the outer leading-out pins of the embedded chip are arranged opposite to the outer leading-out pins of the first chip, the embedded chip is electrically interconnected with the first chip through the first micro-bumps, and the embedded chip is electrically interconnected with the second chip through the metal wires on the connecting plate and the second micro-bumps, so that the electrical interconnection among the embedded chip, the first chip and the second chip can be ensured to have shorter interconnection paths, shorter interconnection delay and higher interconnection bandwidth.
Furthermore, the multi-chip bridging integrated structure can ensure short-distance, high-density and high-bandwidth interconnection between the first chip and the second chip, and simultaneously reduces the requirement on coplanarity of the bonding pads on the upper surface of the packaging substrate, so that the packaging substrate has lower cost and smaller bonding process difficulty.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a schematic cross-sectional view of an embodiment of a multi-chip bridge integrated structure of the present invention;
FIG. 2 is a schematic view of an embodiment of an expanded structure of the multi-chip bridging integrated structure of the present invention;
FIG. 3 is a cross-sectional view of a multi-chip bridge integrated structure including embedded chips according to the present invention;
FIG. 4 is a schematic cross-sectional view of another embodiment of a multi-chip bridge integrated structure of the present invention;
FIG. 5 is a schematic view of an expanded structure of another embodiment of the multi-chip bridge integrated structure according to the present invention;
fig. 6 shows a chip integration structure in the prior art.
Wherein: 1-a first chip, 2-a second chip, 3-an adapter plate, 4-a packaging substrate, 5-a first micro bump, 6-a second micro bump, 7-a solder ball, 8-a metal column, 9-a solder cap, 10-a solder column, 11-an embedded chip; 12-conductive path.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the embodiments of the present invention, it should be noted that, if the terms "upper", "lower", "horizontal", "inner", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the product of the present invention is used to usually place, it is only for convenience of describing the present invention and simplifying the description, but it is not necessary to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.
Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be broadly construed and interpreted as including, for example, fixed connections, detachable connections, or integral connections; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
The invention is described in further detail below with reference to the accompanying drawings:
the invention discloses a multi-chip bridging integrated structure, which comprises a first chip 1, a second chip 2, an adapter plate 3, a packaging substrate 4, a first micro bump 5, a second micro bump 6, a solder ball 7 and a solder column 10; the first chip 1 is bonded on the upper surface of the adapter plate 3 through a first micro-bump array formed by a first micro-bump 5, the second chip 2 comprises an adapter plate connecting part and a packaging substrate connecting part, an outer pin of the adapter plate connecting part of the second chip 2 is bonded on the upper surface of the adapter plate 3 through a second micro-bump array formed by a second micro-bump 6, an outer pin of the packaging substrate connecting part of the second chip 2 is bonded on the packaging substrate 4 through a welding column array formed by a welding column 10, the lower surface of the adapter plate 3 is bonded on the packaging substrate 4 through a welding ball array formed by a welding ball 7, the first chip 1 and the second chip 2 are connected through the first micro-bump 5, a metal wiring on the adapter plate 3 and an electric interconnection path formed by the second micro-bump 6, and the adapter plate 3 is provided with a plurality of conductive channels 12.
Example 1:
referring to fig. 1, which is a schematic cross-sectional view of an embodiment of the multi-chip bridging integrated structure of the present invention, all outer leads of a first chip 1 are bonded on the upper surface of an interposer 3 through a first micro-bump array formed by first micro-bumps 5, outer leads of one end of a second chip 2 are bonded on the upper surface of the interposer 3 through a second micro-bump array formed by second micro-bumps 6, diameters and heights of the first micro-bumps 5 and the second micro-bumps 6 are the same or similar, and an array pitch of the first micro-bump array formed by the first micro-bumps 5 and a second micro-bump array pitch formed by the second micro-bumps 6 may be the same or similar or different; the outer lead of the other end of the second chip 2 is bonded on the upper surface of the packaging substrate 4 through a welding column array formed by welding columns 10, each welding column 10 is formed by a metal column 8 and a welding cap 9 positioned at the top end of the metal column, the diameter of each welding column 10 is larger than that of each second micro-bump 6, and the array interval of the welding column array formed by the welding columns 10 is larger than that of the second micro-bump array formed by the second micro-bumps 6, so that when the welding column array formed by the welding columns 10 is bonded with the corresponding pad array on the upper surface of the packaging substrate 4, the requirements for the pad density and the pad coplanarity of the corresponding pad on the upper surface of the packaging substrate 4 are lower than the requirements for the pad density and the pad coplanarity of the corresponding lead pad on the upper surface of the connection board 3 by the second micro-bump array formed by the second micro-bumps 6. The lower surface pins of the adapter plate 3 are bonded on the upper surface of the packaging substrate 4 through a solder ball array formed by solder balls 7, the diameter and the height of the solder balls 7 are larger than those of the first micro-bump 5 and the second micro-bump 6, and the array pitch of the solder ball array formed by the solder balls 7 is larger than that of the first micro-bump array and the second micro-bump array respectively formed by the first micro-bump 5 and the second micro-bump 6, so that when the solder ball array formed by the solder balls 7 is bonded with the corresponding pad array on the upper surface of the packaging substrate 4, the requirements on the pad density and the pad coplanarity of the corresponding pad on the upper surface of the packaging substrate 4 are lower than those of the corresponding pad on the upper surface of the butt-joint plate 3 by the first micro-bump array and the second micro-bump array respectively formed by the first micro-bump 5 and the second micro-bump 6. The electrical signals between the first chip 1 and the second chip 2 are mutually communicated through an electrical interconnection path formed by the first micro-bump 5, the metal wiring on the adapter plate 3 and the second micro-bump 6.
The first chip 1 is preferably a processing chip, including but not limited to a CPU, a GPU, a DPU, an NPU, a DSP, an FPGA, or an ASIC chip; the second chip 2 is preferably a memory type chip including DDR and SDRAM, etc., but is not limited thereto.
The adapter plate 3 comprises a metal wiring structure in the XY plane direction, a conductive channel structure in the Z direction, an upper surface pin bonding pad positioned on the upper surface and a lower surface pin bonding pad positioned on the lower surface, and the upper surface pin bonding pad and the lower surface pin bonding pad are electrically interconnected through the metal wiring structure and the conductive channel. The diameter and the interval of the pin bonding pads on the upper surface of the adapter plate 3 are smaller than those of the pin bonding pads on the lower surface, so that the adapter plate 3 has the function of converting a micro-bump array with a micro size and a narrow interval, namely a first micro-bump array and a second micro-bump array which are respectively formed by a first micro-bump 5 and a second micro-bump 6, into a solder ball array with a larger size and a wider interval, namely a solder ball array formed by solder balls 7, so as to reduce the requirements on the density and the coplanarity of the bonding pads in the corresponding area of the packaging substrate 4. The interposer 3 may be an inorganic interposer substrate based on an inorganic material, including but not limited to a silicon interposer, a glass interposer, or a ceramic interposer; the interposer 3 may also be an organic interposer substrate using an organic material as a base material, including a PI interposer, an ABF interposer, an encapsulating resin interposer, or a liquid crystal interposer, but not limited thereto. The adapter plate 3 can also be an active functional chip with the capability of electrically interconnecting pin pads on the upper surface and the lower surface, and the adapter plate 3 can integrate passive devices and passive networks.
The preferred material of the interposer 3 is Silicon, since the Silicon material has excellent electrical, thermal and mechanical properties, the electrical interconnection density is high, the maturity of the Silicon wafer production supply chain is high, and at this time, the Z-direction conductive channel 12 penetrating Through the interposer 3 is a TSV Through hole (Through-Silicon-Via). The package substrate 4 may be an organic package substrate or a ceramic package substrate, but is not limited thereto.
The thickness of the interposer 3 is preferably 50 μm to 200 μm, the diameter of the first and second micro bumps 5 and 6 is preferably 10 μm to 100 μm, the diameter of the solder ball 7 is preferably 100 μm to 300 μm, and the diameter of the solder column 10 is preferably 100 μm to 300 μm.
Referring to fig. 2, a schematic top view of an array structure formed by the multi-chip bridging structure of the embodiment is shown, the structure shown in fig. 1 is regarded as a unit structure, and the structure is expanded along the transverse direction and the longitudinal direction, so as to obtain an array structure, which is 2 × 2 in fig. 2. The first chip 1 is preferably a process chip and the second chip 2 is preferably a memory chip. The first chip 1, the second chip 2 around the first chip, and the interposer 3 below the first chip form a set of relatively independent unit structures, and the unit structures can be expanded into an array structure with different numbers of rows and columns on the package substrate 4 along the transverse direction and the longitudinal direction, that is, the unit structures are reusable. The size of the adapter plate 3 does not need to be expanded along with the expansion of the number of rows and columns of the array, namely, the size does not need to be changed along with the change of the number of rows and columns, and the design, manufacturing and testing cost of the adapter plate 3 is reduced. In each unit structure, 8 storage-class second chips 2 can be configured on a processing-class first chip 1, data reading and writing between the first chip 1 and the second chip 2 is realized through an interconnection line on a patch panel 3 of the unit, and the large storage capacity is realized, meanwhile, a shorter interconnection path can be ensured, and the problem of storage bandwidth is solved.
All the outer pin salient points of the first chip 1 are bonded on the upper surface of the adapter plate 3, so that all the outer pins of the processing chip are electrically connected with the packaging substrate 4 through the first micro salient points 5 on the upper surface of the adapter plate 3, the conductive channels 12 and the solder balls 7 on the lower surface, the size of the first micro salient points 5 is smaller than that of the solder balls 7, the density of the array of the first micro salient points 5 is higher than that of the array of the solder balls 7, on one hand, the development requirement of the high-density narrow-pitch outer pin array of the first chip 1 is better met, and on the other hand, the requirement on the coplanarity of the bonding pads on the upper surface of the packaging substrate 4 is reduced. The second chip 2 has a portion located above the interposer 3 and another portion located outside the interposer 3. The second chip 2 is electrically interconnected with the adapter plate 3 through a pad positioned on the upper part of the adapter plate 3 by a second micro bump 6, and the second chip 2 is electrically interconnected with the packaging substrate 4 through a pad positioned on the outer part of the adapter plate 3 by a welding column 10; the diameter and the length of the solder column 10 are far larger than the diameter and the height of the second micro bump 6, the second chip 2 is close to the first chip 1, and the electrical interconnection between the second chip 2 and the first chip 1 is realized through the series connection path of the second micro bump 6, the wiring on the adapter plate 3 and the first micro bump 5, so that the electrical interconnection between the second chip 2 and the first chip 1 can be ensured to have a shorter interconnection path, shorter interconnection delay and higher interconnection bandwidth, and the data read-write energy efficiency between the second chip 2 and the first chip 1 is improved. The second micro bump 6 may correspond to a pin having an interconnection relationship between the storage type chip 2 and the first chip 1, and particularly to a pin having requirements on an interconnection speed and an interconnection bandwidth, including a data pin, an address pin, a clock pin, but not limited thereto, the stud 10 may correspond to other pins of the second chip 2 that are not directly interconnected with the first chip 1, including a power pin, a ground pin, a pull-up bias pin, a control pin, and the like, but not limited thereto, so that the second chip 2 and the first chip 1 are powered from different paths, interference between the two power supply networks can be avoided, the problem of power integrity is reduced, and meanwhile, the stud 10 having a larger diameter may ensure a larger power supply current and a smaller power supply impedance, so as to provide a better power supply.
Example 2:
referring to fig. 3, which is a cross-sectional view of a multi-chip bridge integrated structure including a buried chip according to the present invention, the interposer 3 may be partially buried in the buried chip 11, and the buried chip 11 may be an active functional chip, a passive chip, such as a capacitor chip, an integrated passive network chip, a sensor chip, etc., but is not limited thereto. The outer pin of the embedded chip 11 is opposite to the outer pin of the first chip 1, and the electrical interconnection between the embedded chip 11 and the first chip 1 and the electrical interconnection between the embedded chip 2 are respectively realized through the first micro bump 5 and the second micro bump 6, so that the electrical interconnection between the embedded chip 11 and the first chip 1 and the electrical interconnection between the embedded chip 2 can be ensured to have a shorter interconnection path, smaller interconnection delay and higher interconnection bandwidth. This embodiment can be combined with other features in embodiment 1 or embodiment 3
Example 3:
referring to fig. 4, which is a schematic cross-sectional view of another embodiment of the multi-chip bridging integrated structure of the present invention, all external leads of a first chip 1 are bonded to the upper surface of an interposer 3 through a first micro-bump array formed by first micro-bumps 5, external leads at opposite ends of a second chip 2 are bonded to two ends of the upper surface of an adjacent interposer 3 through second micro-bump arrays formed by second micro-bumps 6, external leads at the middle of the second chip 2 are bonded to the upper surface of a package substrate 4 through a solder column array formed by solder columns 10, lower surface leads of the interposer 3 are bonded to the upper surface of the package substrate 4 through a solder ball array formed by solder balls 7, and electrical signals between the first chip 1 and the adjacent second chip 2 are implemented by mutually communicating electrical interconnection paths formed by the first micro-bumps 5, metal wires on the interposer 3, and the second micro-bumps 6.
Fig. 5 is a schematic diagram of an array module structure formed by a multi-chip bridge structure according to another embodiment. The illustrated structure is extended in both the lateral and longitudinal directions to provide an array structure as shown in fig. 5, with fig. 5 showing only a partial array structure for simplicity.
The first chip 1 is preferably a process chip and the second chip 2 is preferably a memory chip. Two adjacent first chips 1 share the second chip 2 in the middle, and may share the same memory area by partition. The information interaction between two adjacent first chips 1 can be realized through the second chip 2 shared between the two adjacent first chips, and the structure is more suitable for a calculation and storage integrated structure and a neural network calculation structure so as to meet the requirements of application scenes such as artificial intelligence, unmanned driving and the like on large-scale parallel calculation, high-bandwidth and large-capacity memory and extreme calculation power.
The micro-assembly process of the structure described in each example includes the following steps:
first, the interposer 3 is micro-assembled on the upper surface of the package substrate 4, and the electrical interconnection between the interposer 3 and the package substrate 4 is achieved by an array of solder balls 7. The micro-assembly process may use a reflow process or a hot pressing process, but is not limited thereto.
Then, the micro-assembly of the first chip 1 on the upper surface of the interposer 3 and the micro-assembly of the second chip 2 on the upper surfaces of the interposer 3 and the package substrate 4 can be completed simultaneously; or the micro-assembly of the first chip 1 on the upper surface of the interposer 3 may be completed first, and then the micro-assembly of the second chip 2 on the upper surface of the interposer 3 and the upper surface of the package substrate 4 may be completed. The micro-assembly process may use a reflow process or a hot pressing process, but is not limited thereto.
The multi-chip bridging integrated structure is realized by bonding all outer pins of a first chip 1 on the upper surface of an adapter plate 3 through a first micro-bump array formed by first micro-bumps 5, bonding outer pins at two opposite ends of a second chip 2 on two ends of the upper surface of an adjacent adapter plate 3 respectively through a second micro-bump array formed by second micro-bumps 6, bonding outer pins at the middle part of the second chip 2 on the upper surface of a packaging substrate 4 through a welding column array formed by welding columns 10, bonding lower surface pins of the adapter plate 3 on the upper surface of the packaging substrate 4 through a welding ball array formed by welding balls 7, and mutually communicating electric signals between the first chip 1 and the adjacent second chip 2 with an electric interconnection path formed by the first micro-bumps 5, metal wires on the adapter plate 3 and the second micro-bumps 6. When the chip structure needs array type expansion, the circuit unit can be expanded along the transverse direction and/or the longitudinal direction, the area of the adapter plate can realize communication between the chips without corresponding expansion, two adjacent first chips 1 share the second chip 2 in the middle, information interaction between two adjacent first chips 1 can be realized through the second chip 2 shared in the middle, and the structure can be more suitable for a calculation and storage integrated structure and a neural network calculation structure so as to meet the requirements of application scenes such as artificial intelligence, unmanned driving and the like on large-scale parallel calculation, high-bandwidth and large-capacity memory and extreme calculation power.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A multi-chip bridging integrated structure is characterized by comprising a plurality of circuit units, wherein each circuit unit comprises a first chip (1), a second chip (2), an adapter plate (3), a packaging substrate (4), a first micro bump (5), a second micro bump (6), a welding ball (7) and a welding column (10);
the chip packaging structure is characterized in that a first chip (1) is bonded on the upper surface of an adapter plate (3) through a first micro-bump array formed by a first micro-bump (5), a second chip (2) comprises an adapter plate connecting part and a packaging substrate connecting part, an outer pin of the adapter plate connecting part of the second chip (2) is bonded on the upper surface of the adapter plate (3) through a second micro-bump array formed by a second micro-bump (6), an outer pin of the packaging substrate connecting part of the second chip (2) is bonded on the packaging substrate (4) through a welding column array formed by welding columns (10), the lower surface of the adapter plate (3) is bonded on the packaging substrate (4) through a welding ball array formed by welding balls (7), the electrical interconnection between the first chip (1) and the second chip (2) is realized through a passage formed by the first micro-bump (5), a metal wiring on the adapter plate (3) and the second micro-bump (6), and a plurality of conductive channels (12) are formed on the adapter plate (3).
2. The multi-chip bridging integrated structure of claim 1, wherein the second chip (2) interposer connecting portion is located at one end of the second chip (2), and an outer lead at one end of the second chip (2) is bonded to the upper surface of the interposer (3) through the second micro bump array; the packaging substrate connecting part of the second chip (2) is positioned at the other end of the second chip (2), and the outer pin of the other end of the second chip (2) is bonded on the packaging substrate (4) through a welding column array.
3. The multi-chip bridging integrated structure of claim 1, wherein the second chip (2) interposer connecting portions are located at two corresponding ends of the second chip (2), and outer leads at two corresponding ends of the second chip (2) are respectively bonded to the upper surfaces of two adjacent interposers (3) through the second micro bump array; the packaging substrate connecting part of the second chip (2) is positioned in the middle of the second chip (2), and the outer lead of the middle of the second chip (2) is bonded on the packaging substrate (4) through a welding column array.
4. A multi-chip bridge integrated structure according to claim 1, wherein the interposer (3) is provided with an embedded chip (11), the outer leads of the embedded chip (11) are opposite to the outer leads of the first chip (1), the embedded chip (11) and the first chip (1) are electrically interconnected through the first micro-bumps (5), and the embedded chip (11) and the second chip (2) are electrically interconnected through the metal wires on the connection board (3) and the second micro-bumps (6).
5. The multi-chip bridging integrated structure of claim 1, wherein the interposer (3) has a thickness of 50 μm to 200 μm, the first micro-bump (5) and the second micro-bump (6) have a diameter of 10 μm to 100 μm, the solder ball (7) has a diameter of 100 μm to 300 μm, and the solder post (10) has a diameter of 100 μm to 300 μm.
6. The multi-chip bridging integrated structure of claim 1, wherein the array pitch of the solder pillar array is greater than the array pitch of the second micro-bump array, and the array pitch of the first micro-bump array and the array pitch of the second micro-bump array are both smaller than the array pitch of the solder ball array.
7. The integrated structure of claim 1, wherein the interposer (3) is an inorganic interposer substrate or an organic interposer substrate.
8. A multi-chip bridging integrated structure according to claim 1, wherein the first chip (1) is a process-like chip.
9. A multi-chip bridge integrated structure according to claim 1, wherein the second chip (2) is a memory chip.
10. A method for assembling a multi-chip bridging integrated structure, comprising the steps of:
the adapter plate (3) is assembled on the packaging substrate (4) in a micro mode through a reflow process or a hot pressing process, and the electrical interconnection between the adapter plate (3) and the packaging substrate (4) is achieved through a solder ball array formed by solder balls (7);
the first chip (1) is assembled on the upper surface of the adapter plate (3) in a micro mode through a reflow process or a hot pressing process;
and micro-assembling the second chip (2) on the upper surfaces of the adapter plate (3) and the packaging substrate (4) through a reflow process or a hot pressing process.
CN202211058003.1A 2022-08-30 2022-08-30 Multi-chip bridging integrated structure and assembling method thereof Pending CN115425019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211058003.1A CN115425019A (en) 2022-08-30 2022-08-30 Multi-chip bridging integrated structure and assembling method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211058003.1A CN115425019A (en) 2022-08-30 2022-08-30 Multi-chip bridging integrated structure and assembling method thereof

Publications (1)

Publication Number Publication Date
CN115425019A true CN115425019A (en) 2022-12-02

Family

ID=84200343

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211058003.1A Pending CN115425019A (en) 2022-08-30 2022-08-30 Multi-chip bridging integrated structure and assembling method thereof

Country Status (1)

Country Link
CN (1) CN115425019A (en)

Similar Documents

Publication Publication Date Title
US10468380B2 (en) Stackable microelectronic package structures
US7504717B2 (en) Semiconductor device
KR20040080912A (en) Semiconductor device
TWI425604B (en) Semiconductor device
CN212084946U (en) Fan-out type packaging structure of high-density chip
CN115425019A (en) Multi-chip bridging integrated structure and assembling method thereof
CN101465341B (en) Stacked chip packaging structure
CN116646335A (en) Packaging interconnection structure, manufacturing method and electronic system
CN111508921B (en) Semiconductor chip set with double-sided external contact
CN114823589A (en) Chip set and method for manufacturing the same
CN116528591A (en) Semiconductor packaging structure and manufacturing method thereof
US20160079210A1 (en) Semiconductor packages including through electrodes and methods of manufacturing the same
CN100392849C (en) Package body and package body module
CN111769101B (en) Packaging structure and packaging method based on multiple transfer boards
CN221783207U (en) Chip packaging structure and electronic equipment
CN221632558U (en) Laminated memory chip connection system and equipment
US20240213217A1 (en) Clustering fine pitch micro-bumps for packaging and test
CN118073319A (en) Packaging structure and packaging method
CN116845051A (en) Packaging structure based on active silicon interposer and manufacturing method thereof
TW202406088A (en) Semiconductor devices and methods of manufacturing thereof
CN114446924A (en) Semiconductor structure and chip packaging method
CN115831895A (en) Design method of universal silicon adapter plate for SPI memory integration
CN115377085A (en) Wireless interconnection device and system
CN118335728A (en) Semiconductor packaging structure and forming method thereof
CN118335716A (en) Interconnection structure of three-dimensional chip package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination