CN115361779B

CN115361779B - Hard packaging structure of embedded component and preparation method thereof

Info

Publication number: CN115361779B
Application number: CN202211031334.6A
Authority: CN
Inventors: 王强; 吴婷婷; 朱繁松; 杨金生; 齐学政
Original assignee: NINGBO HUAYUAN ELECTRONIC TECHNOLOGY CO LTD
Current assignee: NINGBO HUAYUAN ELECTRONIC TECHNOLOGY CO LTD
Priority date: 2022-08-26
Filing date: 2022-08-26
Publication date: 2024-09-13
Anticipated expiration: 2042-08-26
Also published as: CN115361779A

Abstract

A hard packaging structure of an embedded component comprises an adhesive layer provided with a first window; the first hard substrate is adhered to the upper surface of the adhesive layer, a second window which forms a containing cavity together with the first window is formed on the first hard substrate, and a circuit is arranged on the upper surface or two sides of the first hard substrate; the second hard substrate is adhered to the lower surface of the adhesive layer, and circuits are arranged on one side or two sides of the second hard substrate; a component bonded to the second hard substrate; the insulating layer is made of flowable resin, is filled in the accommodating cavity and coats the components, and interlayer conductors are filled in the insulating layer, so that the components are not easy to damage by the hard packaging structure and are thinner. The invention also relates to a preparation method of the hard packaging structure of the embedded component.

Description

Hard packaging structure of embedded component and preparation method thereof

Technical Field

The invention relates to a circuit board, in particular to a hard packaging structure of an embedded component and a preparation method of the hard packaging structure of the embedded component.

Background

Semiconductor packaging technology is critical to functioning as a power semiconductor device. Good electrical isolation and thermal management, minimal parasitic capacitance, and minimal distributed inductance are all achieved by careful design of the package structure. A package Substrate is commonly used in the field of semiconductor packaging technology, and the package Substrate is a submount (SUB for short), i.e. a term in a printed wiring board. The substrate can provide the effects of electric connection, protection, support, heat dissipation, assembly and the like for the chip so as to realize the purposes of multi-pin, reduction of the volume of a packaged product, improvement of electric performance and heat dissipation, and ultrahigh density or multi-chip modularization. At present, the packaging substrate is being developed toward higher density, for example, the element is embedded in the multilayer circuit board.

Chinese patent No. ZL201210586713.1 (issued to CN103904062 a) discloses a package structure for embedded electronic components, which includes a core layer, an electronic component, a first dielectric layer, and a second dielectric layer. The core layer is provided with a through accommodating groove, and the electronic element is positioned in the accommodating groove. The first dielectric layer and the second dielectric layer are respectively pressed on the electronic element and the core layer from top to bottom so as to cover the electronic element and the core layer in the first dielectric layer and the second dielectric layer. The material of the first dielectric layer and the second dielectric layer is, for example, semi-cured resin (PP).

The embedded electronic element packaging structure has the following defects: ① Because the conventional semi-cured resin PP is of a structure of resin, glass fiber cloth and filler, the glass fiber cloth can be extruded to the components when the packaging structure is pressed, so that the components are damaged or damaged, gaps are easily formed around the components when the semi-cured resin PP is filled, filling holes are generated, and the reliability of the packaged structure product is invalid; ② The embedded electronic element packaging structure is provided with a layer of curing plate and two layers of semi-curing plates, so that the packaging structure is thicker; ③ Because the semi-cured resin PP is in a molten state before being cured, the packaging structure needs to be firstly pasted with the supporting piece and the strippable film when being assembled, and the supporting piece and the strippable film are removed after the components are fixed on the cured semi-cured resin PP, so that the preparation process flow of the packaging structure is long, and the processing efficiency of the packaging structure is influenced.

Disclosure of Invention

The first technical problem to be solved by the present invention is to provide a hard packaging structure of a thinner embedded component, which is not easy to damage the component.

The second technical problem to be solved by the invention is to provide a preparation method of the hard packaging structure of the embedded component aiming at the state of the art, and the process flow is shorter, so that the processing efficiency is higher.

The third technical problem to be solved by the invention is to provide a preparation method of the hard packaging structure of the embedded component aiming at the state of the art, which can effectively prevent gaps from being formed around the component so as to avoid the reliability failure of the packaging structure product.

The technical scheme adopted by the invention for solving the first technical problem is as follows: a hard packaging structure of an embedded component is characterized in that: comprising

The adhesive layer is provided with a first window;

the first hard substrate is adhered to the upper surface of the adhesive layer and is provided with a second window corresponding to the first window, the second window and the first window form a containing cavity together, and the upper surface of the first hard substrate is provided with a circuit, or both sides of the first hard substrate are provided with circuits;

The second hard substrate is attached to the lower surface of the adhesive layer, one side or two sides of the second hard substrate are provided with circuits, and when the circuits are arranged on the two sides of the first hard substrate and/or the second hard substrate, the circuits on the two sides of the first hard substrate and/or the circuits on the two sides of the second hard substrate are electrically conducted, and in addition, the circuits on the two sides of the first hard substrate and the second hard substrate are electrically conducted;

the component is attached to the upper surface of the second hard substrate and is positioned in the accommodating cavity;

The insulating layer is made of flowable resin, is filled in the accommodating cavity and coats the components, and is filled with interlayer conductors to conduct the components and circuits arranged on the upper surface of the first hard substrate.

In order to make the strength of the hard packaging structure higher, the adhesive layer is semi-cured resin or a sealing material, and the sealing material comprises a main phase and a filler dispersed in the main phase. The material design of the adhesive layer enables the first hard substrate and the second hard substrate to be bonded together through pressing. In order to avoid the damage to components due to lamination deformation, the recommended general lamination structure is as follows: mirror plate/cushioning material/product/cushioning material/mirror plate. Buffer materials with different layers can be matched according to the thickness of products with different packaging structures, so that the buffer materials are prevented from being extruded into the positions of the embedded components, and the components are prevented from being damaged.

In order to further improve the assembly density, the first hard substrate and the second hard substrate jointly form a core board assembly, and the upper surface of the first hard substrate and/or the lower surface of the second hard substrate is/are also overlapped with a layering structure. The build-up structure is referred to the prior art. Through the design of the build-up structure, the components and parts can be embedded in different layers, so that the single-layer embedding can be realized, and the aim of simultaneously embedding multiple layers can be realized.

The invention solves the second technical problem as follows: the preparation method of the hard packaging structure of the embedded component is characterized by comprising the following steps in sequence:

S1, feeding a first hard substrate and a second hard substrate;

S2, performing first processing on the first hard substrate and/or the second hard substrate so as to enable electric conduction between the two-sided routes of the first hard substrate and/or between the two-sided routes of the second hard substrate;

s3, manufacturing a circuit on the lower surface of the first hard substrate and/or the upper surface of the second hard substrate;

S4, respectively windowing on the first hard substrate and the adhesive layer;

S5, mounting the components on the upper surface of the second hard substrate, and bonding the first hard substrate and the second hard substrate together through the adhesive layer;

S6, filling an insulating layer in the accommodating cavity by adopting a printing or coating process;

S7, performing secondary processing on the first hard substrate, the adhesive layer, the second hard substrate and the insulating layer so as to enable electric conduction between the first hard substrate and the second hard substrate and between the component and the circuit on the upper surface of the first hard substrate;

S8, manufacturing a circuit on the upper surface of the first hard substrate only or on the upper surface of the first hard substrate and the lower surface of the second hard substrate.

In the step S4, the size of the window is defined according to the size of the component and the product space, and the unilateral size of the window is generally 0.1mm larger than the embedded space of the component; in step S5, the processes of component mounting and substrate bonding may be interchanged according to the processes of different component mounting, so as to implement multi-process collocation, i.e. component mounting may be performed first and then lamination may be performed; or pressing and then mounting the components.

The invention solves the third technical problem as follows: the material of insulating layer is printing type resin, and the printing technology is vacuum printing technology to can effectively reduce the gap when the insulating layer fills and produce, improve filling cavity phenomenon, make the filling nature better, thereby avoid causing packaging structure product reliability inefficacy.

Further designed, the insulating layer is made of hole plugging resin. The hole plugging resin has the characteristics of good fluidity and proper hardness, the grinding machinability is good, and the surface of the hole plugging resin is favorable for physical or chemical metallization.

In order to prevent the surface of the embedded part of the component from being protruded after the resin material is filled, a grinding process is further arranged between the steps S5 and S6, and the grinding process grinds the upper surface of the insulating layer so that the insulating layer is flush with the upper surface of the first hard substrate, and therefore the surface of the embedded part is free from height difference and flat. The grinding process preferably uses non-woven cloth or ceramic grinding.

The invention solves the second technical problem as follows: the method sequentially comprises the following steps:

S1, feeding a first hard substrate and a second hard substrate;

S4, respectively windowing on the first hard substrate and the adhesive layer;

s8, manufacturing a circuit on the upper surface of the first hard substrate only or on the upper surface of the first hard substrate and the lower surface of the second hard substrate;

S9, laminating a layer-adding structure on the upper surface of the first hard substrate and/or the lower surface of the second hard substrate. And optimizing the number of layers of the laminated structure to obtain the multilayer board. The lamination process of the layer-added structure comprises the following steps: pressing PP, drilling, seed layer, copper plating and line manufacturing.

Further, if in step S3 and step S8, the specific process of circuit fabrication is a subtractive process, the subtractive process is: film pressing, exposure, development, etching and film removal, wherein the specific processes of the first processing in the step S2 and the second processing in the step S7 are as follows: drilling, seed layer and copper plating;

If in step S3 and step S8, the specific process of line manufacturing is an addition process, the addition process is: film pressing, exposure, development, circuit plating, film removing and flash etching, wherein the specific processes of the first processing in the step S2 and the second processing in the step S7 are as follows: drilling- & gt etching- & gt seed layer, or: drilling holes and a seed layer;

The hole type is through holes or blind holes, and in the first hard substrate and the second hard substrate, the drilling mode is mechanical drilling or laser drilling, and in the insulating layer, the drilling mode is laser drilling.

The specific processes of the first processing in the step S2 and the second processing in the step S7 are: drilling- & gt seed layer- & gt copper plating, or: drilling, etching and forming a seed layer, wherein the thickness of the copper layer on the surfaces of the first hard substrate and the second hard substrate is more than 10 mu m; the specific processes of the first processing in the step S2 and the second processing in the step S7 are: and (3) drilling and forming a seed layer, wherein the thickness of the copper layer on the surfaces of the first hard substrate and the second hard substrate is 2-3 mu m. Wherein, the seed layer can be selected from chemical deposition process or vacuum sputtering process, and the thickness of the seed layer is preferably 0.1-0.15 μm.

Compared with the prior art, the invention has the advantages that: the hard packaging structure of the embedded component adopts the flowable resin to fill the periphery of the component without being filled in a pressing manner, so that the damage to the component caused by pressing when the semi-cured resin PP is used for filling can be avoided, the hard packaging structure takes the two-layer structure plate of the first hard substrate and the second hard substrate as a supporting layer, and the adhesive layer only plays a role of adhesion, so that the thickness of the adhesive layer can be reduced, and the hard packaging structure is thinner; according to the preparation method of the hard packaging structure of the embedded component, the insulating layer is made of the flowable resin, so that the hard packaging structure can be filled with the insulating layer through a printing or coating process, a film coating and moving process is not involved, and the interlayer conductor is filled in the insulating layer, so that the process of processing a bonding pad on a second hard substrate can be avoided, and the process flow can be simplified, so that the process flow is shorter, and the processing efficiency is higher; according to the preparation method of the hard packaging structure of the embedded component, the vacuum printing process is adopted, so that vacuum can be pumped when the insulating layer is filled, gaps are effectively avoided from being generated around the component, filling holes are prevented, the filling performance is better, and reliability failure of a packaging structure product is avoided.

Drawings

FIG. 1 is a schematic diagram of a feeding structure of a hard substrate in embodiment 1 of the present invention;

FIG. 2 is a schematic diagram of the structure of an interlayer conductor filled in a hard substrate in embodiment 1 of the present invention;

FIG. 3 is a schematic diagram of the structure of a circuit on the bonding surface of a hard substrate in embodiment 1 of the present invention;

fig. 4 is a schematic diagram of a first hard substrate and an adhesive layer with windows in embodiment 1 of the present invention;

fig. 5 is a schematic structural diagram of component mounting in embodiment 1 of the present invention;

FIG. 6 is a schematic diagram of a hard substrate lamination structure in embodiment 1 of the present invention;

fig. 7 is a schematic diagram of the structure of the insulating layer filling in embodiment 1 of the present invention;

FIG. 8 is a schematic view of the structure of a borehole in embodiment 1 of the present invention;

fig. 9 is a schematic diagram of the structure of the interlayer conductor filled with the insulating layer inside the hard packaging structure in embodiment 1 of the present invention;

FIG. 10 is a schematic structural diagram of embodiment 1 of the present invention;

FIG. 11 is a schematic structural view of embodiment 2 of the present invention;

FIG. 12 is a schematic view showing the structure of embodiment 3 of the present invention;

FIG. 13 is a schematic view showing the structure of embodiment 4 of the present invention;

FIG. 14 is a schematic view showing the structure of embodiment 5 of the present invention;

FIG. 15 is a schematic view showing the structure of embodiment 6 of the present invention;

FIG. 16 is a schematic view showing the structure of embodiment 7 of the present invention;

FIG. 17 is a schematic view showing the structure of embodiment 8 of the present invention;

Fig. 18 is a schematic structural view of embodiment 9 of the present invention;

Detailed Description

Embodiments of the present invention are described in further detail below.

Example 1

As shown in fig. 1 to 10, is a first preferred embodiment of the present invention.

As shown in fig. 10, the hard packaging structure of the embedded component in the present embodiment includes a first hard substrate 1, a second hard substrate 2, an adhesive layer 4, a component 5, and an insulating layer 6.

In this embodiment, the first hard substrate 1 and the second hard substrate 2 are copper clad laminate, and the thickness of copper layer covered on the surfaces of the first hard substrate 1 and the second hard substrate 2 is 15 μm; and both sides of the first hard substrate 1 and both sides of the second hard substrate 2 are provided with circuits (see fig. 3 and 10), so that the hard packaging structure has four layers of circuits. The first hard substrate 1 and the second hard substrate 2 are each filled with an interlayer conductor 3 (see fig. 2), so that both the double-sided wiring of the first hard substrate 1 and the double-sided wiring of the second hard substrate 2 are electrically connected. The adhesive layer 4 is a semi-cured resin PP, and the structure of the semi-cured resin PP is seen in the prior art. The first hard substrate 1 is attached to the upper surface of the adhesive layer 4, and the second hard substrate 2 is attached to the lower surface of the adhesive layer 4 (see fig. 6). The first hard substrate 1, the adhesive layer 4 and the second hard substrate 2 together form a first conductive hole 103 (see fig. 9) for electrically connecting the three.

The adhesive layer 4 is provided with a first window 41, the first hard substrate 1 is provided with a second window 11 (see fig. 4) corresponding to the first window 41, and the second window 11 and the first window 41 together form a containing cavity 101 (see fig. 6). The component 5 is mounted on the upper surface of the second hard substrate 2 and is located in the accommodating cavity 101, and the insulating layer 6 is filled in the accommodating cavity 101 and encapsulates the component 5. The insulating layer 6 is made of hole plugging resin, and is not required to be filled in a pressing manner, so that damage to the component 5 caused by pressing when the semi-cured resin PP is used for filling can be avoided, the hard packaging structure takes two layers of structural plates of the first hard substrate 1 and the second hard substrate 2 as supporting layers, the areas except the accommodating cavity 101 are filled with the adhesive layer 4, the strength of the hard packaging structure can be ensured, and the adhesive layer 4 only plays a role in adhesion, so that the thickness of the adhesive layer 4 can be reduced, and the hard packaging structure is thinner. The insulating layer 6 is also filled with interlayer conductors 3 to conduct the circuit between the component 5 and the upper surface of the first hard substrate 1. The interlayer conductor 3 in this embodiment is through-hole copper plating or hole filling copper plating.

The preparation method of the hard packaging structure of the embedded component in the embodiment sequentially comprises the following steps:

As shown in fig. 1, S1, a first hard substrate 1, and a second hard substrate 2 are fed.

As shown in fig. 2, the interlayer conductors 3 are filled in the first hard substrate 1 and the second hard substrate 2 at S2. Specifically, the first hard substrate 1 and the second hard substrate 2 are respectively drilled with blind holes mechanically or by laser, and then the blind holes are subjected to electroless copper deposition and copper plating to fill the interlayer conductors 3. The optimal copper deposition thickness is 0.10-0.15 mu m. The vacuum sputtering process can also replace the electroless copper plating process, and electroless copper plating is taken as an example for illustration.

As shown in fig. 3, S3, a circuit is formed on the lower surface of the first hard substrate 1 and the upper surface of the second hard substrate 2 by a subtractive process. The subtraction process specifically comprises: film pressing, exposure, development, etching and film removal.

As shown in fig. 4, S4 windows are formed in the first hard substrate 1 and the adhesive layer 4, and the window has a single-side size that is 0.05 to 0.3mm larger than the space in which the component 5 is embedded.

As shown in fig. 5, the component 5 is first mounted on an arbitrary position on the upper surface of the second hard substrate 2 at S5.

As shown in fig. 6, the first hard substrate 1 and the second hard substrate 2 are then bonded together by pressing with the adhesive layer 4. The universal press lamination can be adopted as follows: mirror surface steel plate/buffer material/product/buffer material/mirror surface steel plate, avoid pressfitting deformation damage components and parts 5. Buffer materials with different layers can be matched according to the thickness of products with different packaging structures, so that the buffer materials are prevented from being extruded into the position of the embedded component 5 to damage the component 5.

As shown in fig. 7, S6, the insulating layer 6 is filled in the accommodating cavity 101 by adopting a vacuum printing process, so that the gap generated when the insulating layer 6 is filled can be effectively reduced, the filling cavity phenomenon is improved, the filling performance is better, and the reliability failure of the product of the packaging structure is avoided.

And S7, grinding the upper surface of the insulating layer 6 by using non-woven fabric or ceramic grinding, so that the insulating layer 6 is flush with the upper surface of the first hard substrate 1, and the surface of the position of the embedded component 5 is free from height difference and flat.

S8, processing the first conductive holes 103 on the first hard substrate 1, the adhesive layer 4, and the second hard substrate 2, and filling the interlayer conductors 3 in the insulating layer 6. The first conductive hole 103 is processed in two steps, in which, in the first step, the first hard substrate 1, the adhesive layer 4 and the second hard substrate 2 are mechanically drilled with a first through hole 102 (see fig. 8); in the second step, copper is then chemically deposited into the through hole 102 to fill the interlayer conductor 3 (see fig. 9), so as to realize the conduction of the insulating layer of the through hole 102, thereby realizing the electrical conduction between the first hard substrate 1 and the second hard substrate 2 after being combined. The process of filling the interlayer conductor 3 with the insulating layer 6 is also divided into two steps, wherein in the first step, the insulating layer 6 adopts a laser drilling process to drill a second through hole 61 (see fig. 8) in a pin area of the component 5 corresponding to welding; in the second step, electroless copper plating is further used to fill the interlayer conductor 3 (see fig. 9) in the second via hole 61, and the thickness of the copper plating is 0.10-0.15 μm, so as to metalize the insulating layer of the second via hole 61, thereby realizing electrical conduction between the component 5 and the circuit provided on the upper surface of the first hard substrate 1.

As shown in fig. 10, a line is formed on the upper surface of the first hard substrate 1 and the lower surface of the second hard substrate 2 by a subtractive process at S9. The subtraction process specifically comprises: film pressing, exposure, development, etching and film removal.

S10, performing conventional post-treatment procedures of the hard packaging structure: and (3) performing processes such as solder resist, surface treatment, electrical property test, appearance manufacturing, appearance inspection and the like, so as to realize a finished product of the hard packaging structure.

Example 2

As shown in fig. 11, a second preferred embodiment of the present invention.

This embodiment differs from embodiment 1 in that: between steps S9 and S10, the method further comprises the following steps: the rigid package structure of the present embodiment has 6 layers of wires by stacking a build-up layer 7 on each of the upper surface of the first rigid substrate 1 and the lower surface of the second rigid substrate 2 using the rigid package structure of the embodiment 1 as the core board assembly 100. The lamination process of the build-up structure 7 is as follows: pressing PP, drilling, electroless copper deposition, copper plating and line manufacturing. The build-up structure 7 may be a copper foil commonly used in the art, which is laminated to the surface of the core assembly 100 by the semi-cured resin PP.

The adhesive layer 4 is a sealing material, which comprises a main phase and a filler dispersed in the main phase, wherein the main phase is glass fiber epoxy resin, and the filler is usually silicon dioxide.

Example 3

As shown in fig. 12, a third preferred embodiment of the present invention.

This embodiment differs from embodiment 1 in that: between steps S9 and S10, the method further comprises the following steps: the rigid package structure of the present embodiment has 8 layers of wires by laminating two layers of build-up structures 7 on the upper surface of the first rigid substrate 1 and the lower surface of the second rigid substrate 2, respectively, using the rigid package structure of the embodiment 1 as the core board assembly 100. The lamination process of the build-up structure 7 is as follows: pressing PP, drilling, electroless copper deposition, copper plating and line manufacturing. The build-up structure 7 may be a copper foil commonly used in the art, which is laminated to the surface of the core assembly 100 by the semi-cured resin PP.

Example 4

As shown in fig. 13, a fourth preferred embodiment of the present invention.

This embodiment differs from embodiment 1 in that: the second hard substrate 2 is provided with a circuit on the lower surface only, so that the hard packaging structure of the embodiment has 3 layers of circuits.

Example 5

As shown in fig. 14, a fifth preferred embodiment of the present invention is shown.

This embodiment differs from embodiment 4 in that: between steps S9 and S10, the method further comprises the following steps: the rigid package structure of this embodiment has 5 layers of wires by stacking a build-up layer 7 on each of the upper surface of the first rigid substrate 1 and the lower surface of the second rigid substrate 2 using the rigid package structure of embodiment 4 as the core board assembly 100. The build-up structure 7 may be a copper foil commonly used in the art, which is laminated to the surface of the core assembly 100 by the semi-cured resin PP.

Example 6

As shown in fig. 15, a sixth preferred embodiment of the present invention is shown.

This embodiment differs from embodiment 4 in that: between steps S9 and S10, the method further comprises the following steps: the rigid package structure of the present embodiment has 7 layers of wires by laminating two layers of build-up structures 7 on the upper surface of the first rigid substrate 1 and the lower surface of the second rigid substrate 2, respectively, using the rigid package structure of the embodiment 4 as the core board assembly 100. The lamination process of the build-up structure 7 is as follows: pressing PP, drilling, electroless copper deposition, copper plating and line manufacturing. The build-up structure 7 may be a copper foil commonly used in the art, which is laminated to the surface of the core assembly 100 by the semi-cured resin PP.

Example 7

As shown in fig. 16, a seventh preferred embodiment of the present invention.

This embodiment differs from embodiment 1 in that: the first hard substrate 1 is only provided with a circuit on its upper surface, so that the hard packaging structure of the present embodiment has 3 layers of circuits.

Example 9

As shown in fig. 17, an eighth preferred embodiment of the present invention.

This embodiment differs from embodiment 7 in that: between steps S9 and S10, the method further comprises the following steps: the rigid package structure of this embodiment has 5 layers of wires by stacking a build-up layer 7 on each of the upper surface of the first rigid substrate 1 and the lower surface of the second rigid substrate 2 using the rigid package structure of embodiment 7 as the core board assembly 100. The build-up structure 7 may be a copper foil commonly used in the art, which is laminated to the surface of the core assembly 100 by the semi-cured resin PP.

Example 9

As shown in fig. 18, a ninth preferred embodiment of the present invention is shown.

This embodiment differs from embodiment 7 in that: between steps S9 and S10, the method further comprises the following steps: the rigid package structure of the present embodiment has 7 layers of wires by laminating two layers of build-up structures 7 on the upper surface of the first rigid substrate 1 and the lower surface of the second rigid substrate 2, respectively, using the rigid package structure of the embodiment 7 as the core board assembly 100. The lamination process of the build-up structure 7 is as follows: pressing PP, drilling, electroless copper deposition, copper plating and line manufacturing. The build-up structure 7 may be a copper foil commonly used in the art, which is laminated to the surface of the core assembly 100 by the semi-cured resin PP.

Example 10

This embodiment differs from embodiment 1 in that: in step S5, the first hard substrate 1 and the second hard substrate 2 are pressed together, and then the component 5 is mounted on the upper surface of the second hard substrate.

Example 11

This embodiment differs from embodiment 1 in that:

The specific processes of the first processing in the step S2 and the second processing in the step S7 are: drilling, etching and seed layer, wherein the seed layer is copper deposition, namely a chemical deposition process, and the thickness of the copper deposition is 0.1-0.15 mu m.

In step S3 and step S8, the specific process of line manufacturing is an addition process, and the addition process is: film pressing, exposure, development, circuit plating, film removing and flash etching.

Example 12

This embodiment differs from embodiment 11 in that:

The thickness of the copper layer covered on the surfaces of the first hard substrate 1 and the second hard substrate 2 is 2-3 mu m; the specific processes of the first processing in the step S2 and the second processing in the step S7 are: drilling, and forming a seed layer, wherein the seed layer is formed by adopting a chemical vacuum sputtering process, and the thickness of the seed layer is 0.10-0.15 mu m.

Claims

1. A hard packaging structure of an embedded component is characterized in that: comprising

An adhesive layer (4) on which a first window (41) is formed;

The first hard substrate (1) is adhered to the upper surface of the adhesive layer (4) and is provided with a second window (11) corresponding to the first window (41), the second window (11) and the first window (41) jointly form a containing cavity (101), and the upper surface of the first hard substrate (1) is provided with a circuit, or both sides of the first hard substrate (1) are provided with circuits;

the second hard substrate (2) is attached to the lower surface of the adhesive layer (4), one side or two sides of the second hard substrate (2) are provided with circuits, and when the two sides of the first hard substrate (1) and/or the second hard substrate (2) are provided with circuits, the circuits on the two sides of the first hard substrate (1) and/or the circuits on the two sides of the second hard substrate (2) are electrically conducted, and in addition, the circuits on the two sides of the first hard substrate and the second hard substrate are electrically conducted;

The component (5) is attached to the upper surface of the second hard substrate (2) and is positioned in the accommodating cavity (101);

The insulating layer (6) is made of flowable resin, the insulating layer (6) is filled in the accommodating cavity (101) and coats the components (5), and the insulating layer (6) is filled with an interlayer conductor (3) so as to conduct the components (5) and a circuit arranged on the upper surface of the first hard substrate (1).

2. The hard pack structure of embedded components of claim 1, wherein: the adhesive layer (4) is a semi-cured resin or a sealing material, and the sealing material comprises a main phase and a filler dispersed in the main phase.

3. The hard packaging structure of an embedded component according to claim 1 or 2, wherein: the first hard substrate (1) and the second hard substrate (2) jointly form a core board assembly (100), and a layer-adding structure (7) is further overlapped on the upper surface of the first hard substrate (1) and/or the lower surface of the second hard substrate (2).

4. A method for manufacturing a hard encapsulation structure of an embedded component as claimed in claim 1 or 2, comprising the steps of, in order:

s1, feeding a first hard substrate (1) and a second hard substrate (2);

S2, performing first processing on the first hard substrate (1) and/or the second hard substrate (2) so as to enable the double-sided route of the first hard substrate (1) and/or the double-sided route of the second hard substrate (2) to be electrically communicated;

s3, manufacturing a circuit on the lower surface of the first hard substrate (1) and/or the upper surface of the second hard substrate (2);

s4, windowing is carried out on the first hard substrate (1) and the adhesive layer (4) respectively;

S5, mounting the component (5) on the upper surface of the second hard substrate (2), and bonding the first hard substrate (1) and the second hard substrate (2) together through the adhesive layer (4);

S6, filling the insulating layer (6) in the accommodating cavity (101) by adopting a printing or coating process;

S7, performing secondary processing on the first hard substrate (1), the adhesive layer (4), the second hard substrate (2) and the insulating layer (6) so as to enable electric conduction between the first hard substrate (1) and the second hard substrate (2) and between the component (5) and the circuit on the upper surface of the first hard substrate (1);

s8, manufacturing a circuit on the upper surface of the first hard substrate (1) or on the upper surface of the first hard substrate (1) and the lower surface of the second hard substrate (2).

5. The method for manufacturing a hard encapsulation structure for embedded components as claimed in claim 4, wherein: the material of the insulating layer (6) is printing resin, and the printing process is a vacuum printing process.

6. The method for manufacturing a hard encapsulation structure of an embedded component according to claim 5, wherein: the insulating layer (6) is made of hole plugging resin.

7. The method for manufacturing a hard encapsulation structure for embedded components as claimed in claim 4, wherein: between the steps S6 and S7, a polishing process is further provided, which polishes the upper surface of the insulating layer (6) so that the insulating layer (6) is flush with the upper surface of the first hard substrate (1).

8. A method for manufacturing a hard encapsulation structure of an embedded component as claimed in claim 3, comprising the steps of, in order:

s1, feeding a first hard substrate (1) and a second hard substrate (2);

S8, manufacturing a circuit on the upper surface of the first hard substrate (1) or on the upper surface of the first hard substrate (1) and the lower surface of the second hard substrate (2);

s9, laminating a layer-adding structure (7) on the upper surface of the first hard substrate (1) and/or the lower surface of the second hard substrate (2).

9. A method for manufacturing a hard packaging structure of an embedded component according to any one of claims 4 to 8, characterized in that,

If in step S3 and step S8, the specific process of line manufacturing is a subtraction process, the subtraction process is: film pressing, exposure, development, etching and film removal, wherein the specific processes of the first processing in the step S2 and the second processing in the step S7 are as follows: drilling, seed layer and copper plating;

Wherein the hole type is a through hole or a blind hole, and in the first hard substrate (1) and the second hard substrate (2), the drilling mode is mechanical drilling or laser drilling, and in the insulating layer (6), the drilling mode is laser drilling.